LXR linux/drivers/gpu/drm/amd/include/cgs

   1/*
   2 * Copyright 2015 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 *
  23 */
  24#ifndef _CGS_COMMON_H
  25#define _CGS_COMMON_H
  26
  27#include "amd_shared.h"
  28
  29struct cgs_device;
  30
  31/**
  32 * enum cgs_ind_reg - Indirect register spaces
  33 */
  34enum cgs_ind_reg {
  35        CGS_IND_REG__MMIO,
  36        CGS_IND_REG__PCIE,
  37        CGS_IND_REG__SMC,
  38        CGS_IND_REG__UVD_CTX,
  39        CGS_IND_REG__DIDT,
  40        CGS_IND_REG_GC_CAC,
  41        CGS_IND_REG_SE_CAC,
  42        CGS_IND_REG__AUDIO_ENDPT
  43};
  44
  45/**
  46 * enum cgs_engine - Engines that can be statically power-gated
  47 */
  48enum cgs_engine {
  49        CGS_ENGINE__UVD,
  50        CGS_ENGINE__VCE,
  51        CGS_ENGINE__VP8,
  52        CGS_ENGINE__ACP_DMA,
  53        CGS_ENGINE__ACP_DSP0,
  54        CGS_ENGINE__ACP_DSP1,
  55        CGS_ENGINE__ISP,
  56        /* ... */
  57};
  58
  59/*
  60 * enum cgs_ucode_id - Firmware types for different IPs
  61 */
  62enum cgs_ucode_id {
  63        CGS_UCODE_ID_SMU = 0,
  64        CGS_UCODE_ID_SMU_SK,
  65        CGS_UCODE_ID_SDMA0,
  66        CGS_UCODE_ID_SDMA1,
  67        CGS_UCODE_ID_CP_CE,
  68        CGS_UCODE_ID_CP_PFP,
  69        CGS_UCODE_ID_CP_ME,
  70        CGS_UCODE_ID_CP_MEC,
  71        CGS_UCODE_ID_CP_MEC_JT1,
  72        CGS_UCODE_ID_CP_MEC_JT2,
  73        CGS_UCODE_ID_GMCON_RENG,
  74        CGS_UCODE_ID_RLC_G,
  75        CGS_UCODE_ID_STORAGE,
  76        CGS_UCODE_ID_MAXIMUM,
  77};
  78
  79/*
  80 * enum cgs_resource_type - GPU resource type
  81 */
  82enum cgs_resource_type {
  83        CGS_RESOURCE_TYPE_MMIO = 0,
  84        CGS_RESOURCE_TYPE_FB,
  85        CGS_RESOURCE_TYPE_IO,
  86        CGS_RESOURCE_TYPE_DOORBELL,
  87        CGS_RESOURCE_TYPE_ROM,
  88};
  89
  90/**
  91 * struct cgs_firmware_info - Firmware information
  92 */
  93struct cgs_firmware_info {
  94        uint16_t                version;
  95        uint16_t                fw_version;
  96        uint16_t                feature_version;
  97        uint32_t                image_size;
  98        uint64_t                mc_addr;
  99
 100        /* only for smc firmware */
 101        uint32_t                ucode_start_address;
 102
 103        void                    *kptr;
 104        bool                    is_kicker;
 105};
 106
 107struct cgs_mode_info {
 108        uint32_t                refresh_rate;
 109        uint32_t                vblank_time_us;
 110};
 111
 112struct cgs_display_info {
 113        uint32_t                display_count;
 114        uint32_t                active_display_mask;
 115        struct cgs_mode_info *mode_info;
 116};
 117
 118typedef unsigned long cgs_handle_t;
 119
 120/**
 121 * cgs_read_register() - Read an MMIO register
 122 * @cgs_device: opaque device handle
 123 * @offset:     register offset
 124 *
 125 * Return:  register value
 126 */
 127typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
 128
 129/**
 130 * cgs_write_register() - Write an MMIO register
 131 * @cgs_device: opaque device handle
 132 * @offset:     register offset
 133 * @value:      register value
 134 */
 135typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,
 136                                     uint32_t value);
 137
 138/**
 139 * cgs_read_ind_register() - Read an indirect register
 140 * @cgs_device: opaque device handle
 141 * @offset:     register offset
 142 *
 143 * Return:  register value
 144 */
 145typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
 146                                            unsigned index);
 147
 148/**
 149 * cgs_write_ind_register() - Write an indirect register
 150 * @cgs_device: opaque device handle
 151 * @offset:     register offset
 152 * @value:      register value
 153 */
 154typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
 155                                         unsigned index, uint32_t value);
 156
 157#define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
 158#define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK
 159
 160#define CGS_REG_SET_FIELD(orig_val, reg, field, field_val)                      \
 161        (((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) |                       \
 162         (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field))))
 163
 164#define CGS_REG_GET_FIELD(value, reg, field)                            \
 165        (((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field))
 166
 167#define CGS_WREG32_FIELD(device, reg, field, val)       \
 168        cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
 169
 170#define CGS_WREG32_FIELD_IND(device, space, reg, field, val)    \
 171        cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
 172
 173/**
 174 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
 175 * @cgs_device: opaque device handle
 176 * @resource_type:      Type of Resource (MMIO, IO, ROM, FB, DOORBELL)
 177 * @size:       size of the region
 178 * @offset:     offset from the start of the region
 179 * @resource_base:      base address (not including offset) returned
 180 *
 181 * Return: 0 on success, -errno otherwise
 182 */
 183typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device,
 184                                      enum cgs_resource_type resource_type,
 185                                      uint64_t size,
 186                                      uint64_t offset,
 187                                      uint64_t *resource_base);
 188
 189/**
 190 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
 191 * @cgs_device: opaque device handle
 192 * @table:      data table index
 193 * @size:       size of the table (output, may be NULL)
 194 * @frev:       table format revision (output, may be NULL)
 195 * @crev:       table content revision (output, may be NULL)
 196 *
 197 * Return: Pointer to start of the table, or NULL on failure
 198 */
 199typedef const void *(*cgs_atom_get_data_table_t)(
 200        struct cgs_device *cgs_device, unsigned table,
 201        uint16_t *size, uint8_t *frev, uint8_t *crev);
 202
 203/**
 204 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
 205 * @cgs_device: opaque device handle
 206 * @table:      data table index
 207 * @frev:       table format revision (output, may be NULL)
 208 * @crev:       table content revision (output, may be NULL)
 209 *
 210 * Return: 0 on success, -errno otherwise
 211 */
 212typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table,
 213                                             uint8_t *frev, uint8_t *crev);
 214
 215/**
 216 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
 217 * @cgs_device: opaque device handle
 218 * @table:      command table index
 219 * @args:       arguments
 220 *
 221 * Return: 0 on success, -errno otherwise
 222 */
 223typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device,
 224                                         unsigned table, void *args);
 225
 226/**
 227 * cgs_get_firmware_info - Get the firmware information from core driver
 228 * @cgs_device: opaque device handle
 229 * @type: the firmware type
 230 * @info: returend firmware information
 231 *
 232 * Return: 0 on success, -errno otherwise
 233 */
 234typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
 235                                     enum cgs_ucode_id type,
 236                                     struct cgs_firmware_info *info);
 237
 238typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device,
 239                                         enum cgs_ucode_id type);
 240
 241typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,
 242                                  enum amd_ip_block_type block_type,
 243                                  enum amd_powergating_state state);
 244
 245typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device,
 246                                  enum amd_ip_block_type block_type,
 247                                  enum amd_clockgating_state state);
 248
 249typedef int(*cgs_get_active_displays_info)(
 250                                        struct cgs_device *cgs_device,
 251                                        struct cgs_display_info *info);
 252
 253typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);
 254
 255typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device);
 256
 257typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en);
 258
 259typedef void (*cgs_lock_grbm_idx)(struct cgs_device *cgs_device, bool lock);
 260
 261struct cgs_ops {
 262        /* MMIO access */
 263        cgs_read_register_t read_register;
 264        cgs_write_register_t write_register;
 265        cgs_read_ind_register_t read_ind_register;
 266        cgs_write_ind_register_t write_ind_register;
 267        /* PCI resources */
 268        cgs_get_pci_resource_t get_pci_resource;
 269        /* ATOM BIOS */
 270        cgs_atom_get_data_table_t atom_get_data_table;
 271        cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
 272        cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
 273        /* Firmware Info */
 274        cgs_get_firmware_info get_firmware_info;
 275        cgs_rel_firmware rel_firmware;
 276        /* cg pg interface*/
 277        cgs_set_powergating_state set_powergating_state;
 278        cgs_set_clockgating_state set_clockgating_state;
 279        /* display manager */
 280        cgs_get_active_displays_info get_active_displays_info;
 281        /* notify dpm enabled */
 282        cgs_notify_dpm_enabled notify_dpm_enabled;
 283        cgs_is_virtualization_enabled_t is_virtualization_enabled;
 284        cgs_enter_safe_mode enter_safe_mode;
 285        cgs_lock_grbm_idx lock_grbm_idx;
 286};
 287
 288struct cgs_os_ops; /* To be define in OS-specific CGS header */
 289
 290struct cgs_device
 291{
 292        const struct cgs_ops *ops;
 293        /* to be embedded at the start of driver private structure */
 294};
 295
 296/* Convenience macros that make CGS indirect function calls look like
 297 * normal function calls */
 298#define CGS_CALL(func,dev,...) \
 299        (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
 300#define CGS_OS_CALL(func,dev,...) \
 301        (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
 302
 303#define cgs_read_register(dev,offset)           \
 304        CGS_CALL(read_register,dev,offset)
 305#define cgs_write_register(dev,offset,value)            \
 306        CGS_CALL(write_register,dev,offset,value)
 307#define cgs_read_ind_register(dev,space,index)          \
 308        CGS_CALL(read_ind_register,dev,space,index)
 309#define cgs_write_ind_register(dev,space,index,value)           \
 310        CGS_CALL(write_ind_register,dev,space,index,value)
 311
 312#define cgs_atom_get_data_table(dev,table,size,frev,crev)       \
 313        CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
 314#define cgs_atom_get_cmd_table_revs(dev,table,frev,crev)        \
 315        CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
 316#define cgs_atom_exec_cmd_table(dev,table,args)         \
 317        CGS_CALL(atom_exec_cmd_table,dev,table,args)
 318
 319#define cgs_get_firmware_info(dev, type, info)  \
 320        CGS_CALL(get_firmware_info, dev, type, info)
 321#define cgs_rel_firmware(dev, type)     \
 322        CGS_CALL(rel_firmware, dev, type)
 323#define cgs_set_powergating_state(dev, block_type, state)       \
 324        CGS_CALL(set_powergating_state, dev, block_type, state)
 325#define cgs_set_clockgating_state(dev, block_type, state)       \
 326        CGS_CALL(set_clockgating_state, dev, block_type, state)
 327#define cgs_notify_dpm_enabled(dev, enabled)    \
 328        CGS_CALL(notify_dpm_enabled, dev, enabled)
 329
 330#define cgs_get_active_displays_info(dev, info) \
 331        CGS_CALL(get_active_displays_info, dev, info)
 332
 333#define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \
 334        resource_base) \
 335        CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
 336        resource_base)
 337
 338#define cgs_is_virtualization_enabled(cgs_device) \
 339                CGS_CALL(is_virtualization_enabled, cgs_device)
 340
 341#define cgs_enter_safe_mode(cgs_device, en) \
 342                CGS_CALL(enter_safe_mode, cgs_device, en)
 343
 344#define cgs_lock_grbm_idx(cgs_device, lock) \
 345                CGS_CALL(lock_grbm_idx, cgs_device, lock)
 346
 347
 348#endif /* _CGS_COMMON_H */
 349