1#ifndef BCM63XX_ENET_H_ 2#define BCM63XX_ENET_H_ 3 4#include <linux/types.h> 5#include <linux/mii.h> 6#include <linux/mutex.h> 7#include <linux/phy.h> 8#include <linux/platform_device.h> 9 10#include <bcm63xx_regs.h> 11#include <bcm63xx_irq.h> 12#include <bcm63xx_io.h> 13#include <bcm63xx_iudma.h> 14 15/* default number of descriptor */ 16#define BCMENET_DEF_RX_DESC 64 17#define BCMENET_DEF_TX_DESC 32 18 19/* maximum burst len for dma (4 bytes unit) */ 20#define BCMENET_DMA_MAXBURST 16 21 22/* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value 23 * must be low enough so that a DMA transfer of above burst length can 24 * not overflow the fifo */ 25#define BCMENET_TX_FIFO_TRESH 32 26 27/* 28 * hardware maximum rx/tx packet size including FCS, max mtu is 29 * actually 2047, but if we set max rx size register to 2047 we won't 30 * get overflow information if packet size is 2048 or above 31 */ 32#define BCMENET_MAX_MTU 2046 33 34/* 35 * MIB Counters register definitions 36*/ 37#define ETH_MIB_TX_GD_OCTETS 0 38#define ETH_MIB_TX_GD_PKTS 1 39#define ETH_MIB_TX_ALL_OCTETS 2 40#define ETH_MIB_TX_ALL_PKTS 3 41#define ETH_MIB_TX_BRDCAST 4 42#define ETH_MIB_TX_MULT 5 43#define ETH_MIB_TX_64 6 44#define ETH_MIB_TX_65_127 7 45#define ETH_MIB_TX_128_255 8 46#define ETH_MIB_TX_256_511 9 47#define ETH_MIB_TX_512_1023 10 48#define ETH_MIB_TX_1024_MAX 11 49#define ETH_MIB_TX_JAB 12 50#define ETH_MIB_TX_OVR 13 51#define ETH_MIB_TX_FRAG 14 52#define ETH_MIB_TX_UNDERRUN 15 53#define ETH_MIB_TX_COL 16 54#define ETH_MIB_TX_1_COL 17 55#define ETH_MIB_TX_M_COL 18 56#define ETH_MIB_TX_EX_COL 19 57#define ETH_MIB_TX_LATE 20 58#define ETH_MIB_TX_DEF 21 59#define ETH_MIB_TX_CRS 22 60#define ETH_MIB_TX_PAUSE 23 61 62#define ETH_MIB_RX_GD_OCTETS 32 63#define ETH_MIB_RX_GD_PKTS 33 64#define ETH_MIB_RX_ALL_OCTETS 34 65#define ETH_MIB_RX_ALL_PKTS 35 66#define ETH_MIB_RX_BRDCAST 36 67#define ETH_MIB_RX_MULT 37 68#define ETH_MIB_RX_64 38 69#define ETH_MIB_RX_65_127 39 70#define ETH_MIB_RX_128_255 40 71#define ETH_MIB_RX_256_511 41 72#define ETH_MIB_RX_512_1023 42 73#define ETH_MIB_RX_1024_MAX 43 74#define ETH_MIB_RX_JAB 44 75#define ETH_MIB_RX_OVR 45 76#define ETH_MIB_RX_FRAG 46 77#define ETH_MIB_RX_DROP 47 78#define ETH_MIB_RX_CRC_ALIGN 48 79#define ETH_MIB_RX_UND 49 80#define ETH_MIB_RX_CRC 50 81#define ETH_MIB_RX_ALIGN 51 82#define ETH_MIB_RX_SYM 52 83#define ETH_MIB_RX_PAUSE 53 84#define ETH_MIB_RX_CNTRL 54 85 86 87struct bcm_enet_mib_counters { 88 u64 tx_gd_octets; 89 u32 tx_gd_pkts; 90 u32 tx_all_octets; 91 u32 tx_all_pkts; 92 u32 tx_brdcast; 93 u32 tx_mult; 94 u32 tx_64; 95 u32 tx_65_127; 96 u32 tx_128_255; 97 u32 tx_256_511; 98 u32 tx_512_1023; 99 u32 tx_1024_max; 100 u32 tx_jab; 101 u32 tx_ovr; 102 u32 tx_frag; 103 u32 tx_underrun; 104 u32 tx_col; 105 u32 tx_1_col; 106 u32 tx_m_col; 107 u32 tx_ex_col; 108 u32 tx_late; 109 u32 tx_def; 110 u32 tx_crs; 111 u32 tx_pause; 112 u64 rx_gd_octets; 113 u32 rx_gd_pkts; 114 u32 rx_all_octets; 115 u32 rx_all_pkts; 116 u32 rx_brdcast; 117 u32 rx_mult; 118 u32 rx_64; 119 u32 rx_65_127; 120 u32 rx_128_255; 121 u32 rx_256_511; 122 u32 rx_512_1023; 123 u32 rx_1024_max; 124 u32 rx_jab; 125 u32 rx_ovr; 126 u32 rx_frag; 127 u32 rx_drop; 128 u32 rx_crc_align; 129 u32 rx_und; 130 u32 rx_crc; 131 u32 rx_align; 132 u32 rx_sym; 133 u32 rx_pause; 134 u32 rx_cntrl; 135}; 136 137 138struct bcm_enet_priv { 139 140 /* mac id (from platform device id) */ 141 int mac_id; 142 143 /* base remapped address of device */ 144 void __iomem *base; 145 146 /* mac irq, rx_dma irq, tx_dma irq */ 147 int irq; 148 int irq_rx; 149 int irq_tx; 150 151 /* hw view of rx & tx dma ring */ 152 dma_addr_t rx_desc_dma; 153 dma_addr_t tx_desc_dma; 154 155 /* allocated size (in bytes) for rx & tx dma ring */ 156 unsigned int rx_desc_alloc_size; 157 unsigned int tx_desc_alloc_size; 158 159 160 struct napi_struct napi; 161 162 /* dma channel id for rx */ 163 int rx_chan; 164 165 /* number of dma desc in rx ring */ 166 int rx_ring_size; 167 168 /* cpu view of rx dma ring */ 169 struct bcm_enet_desc *rx_desc_cpu; 170 171 /* current number of armed descriptor given to hardware for rx */ 172 int rx_desc_count; 173 174 /* next rx descriptor to fetch from hardware */ 175 int rx_curr_desc; 176 177 /* next dirty rx descriptor to refill */ 178 int rx_dirty_desc; 179 180 /* size of allocated rx skbs */ 181 unsigned int rx_skb_size; 182 183 /* list of skb given to hw for rx */ 184 struct sk_buff **rx_skb; 185 186 /* used when rx skb allocation failed, so we defer rx queue 187 * refill */ 188 struct timer_list rx_timeout; 189 190 /* lock rx_timeout against rx normal operation */ 191 spinlock_t rx_lock; 192 193 194 /* dma channel id for tx */ 195 int tx_chan; 196 197 /* number of dma desc in tx ring */ 198 int tx_ring_size; 199 200 /* cpu view of rx dma ring */ 201 struct bcm_enet_desc *tx_desc_cpu; 202 203 /* number of available descriptor for tx */ 204 int tx_desc_count; 205 206 /* next tx descriptor avaiable */ 207 int tx_curr_desc; 208 209 /* next dirty tx descriptor to reclaim */ 210 int tx_dirty_desc; 211 212 /* list of skb given to hw for tx */ 213 struct sk_buff **tx_skb; 214 215 /* lock used by tx reclaim and xmit */ 216 spinlock_t tx_lock; 217 218 219 /* set if internal phy is ignored and external mii interface 220 * is selected */ 221 int use_external_mii; 222 223 /* set if a phy is connected, phy address must be known, 224 * probing is not possible */ 225 int has_phy; 226 int phy_id; 227 228 /* set if connected phy has an associated irq */ 229 int has_phy_interrupt; 230 int phy_interrupt; 231 232 /* used when a phy is connected (phylib used) */ 233 struct mii_bus *mii_bus; 234 struct phy_device *phydev; 235 int old_link; 236 int old_duplex; 237 int old_pause; 238 239 /* used when no phy is connected */ 240 int force_speed_100; 241 int force_duplex_full; 242 243 /* pause parameters */ 244 int pause_auto; 245 int pause_rx; 246 int pause_tx; 247 248 /* stats */ 249 struct bcm_enet_mib_counters mib; 250 251 /* after mib interrupt, mib registers update is done in this 252 * work queue */ 253 struct work_struct mib_update_task; 254 255 /* lock mib update between userspace request and workqueue */ 256 struct mutex mib_update_lock; 257 258 /* mac clock */ 259 struct clk *mac_clk; 260 261 /* phy clock if internal phy is used */ 262 struct clk *phy_clk; 263 264 /* network device reference */ 265 struct net_device *net_dev; 266 267 /* platform device reference */ 268 struct platform_device *pdev; 269 270 /* maximum hardware transmit/receive size */ 271 unsigned int hw_mtu; 272}; 273 274#endif /* ! BCM63XX_ENET_H_ */ 275