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9#include "bgmac.h"
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
16#include <linux/phy.h>
17#include <linux/interrupt.h>
18#include <linux/dma-mapping.h>
19#include <bcm47xx_nvram.h>
20
21static const struct bcma_device_id bgmac_bcma_tbl[] = {
22 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
24 BCMA_CORETABLE_END
25};
26MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl);
27
28static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask,
29 u32 value, int timeout)
30{
31 u32 val;
32 int i;
33
34 for (i = 0; i < timeout / 10; i++) {
35 val = bcma_read32(core, reg);
36 if ((val & mask) == value)
37 return true;
38 udelay(10);
39 }
40 pr_err("Timeout waiting for reg 0x%X\n", reg);
41 return false;
42}
43
44
45
46
47
48static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
49{
50 u32 val;
51 int i;
52
53 if (!ring->mmio_base)
54 return;
55
56
57
58
59
60 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
61 BGMAC_DMA_TX_SUSPEND);
62 for (i = 0; i < 10000 / 10; i++) {
63 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
64 val &= BGMAC_DMA_TX_STAT;
65 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
66 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
67 val == BGMAC_DMA_TX_STAT_STOPPED) {
68 i = 0;
69 break;
70 }
71 udelay(10);
72 }
73 if (i)
74 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
75 ring->mmio_base, val);
76
77
78 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
79 if (!bgmac_wait_value(bgmac->core,
80 ring->mmio_base + BGMAC_DMA_TX_STATUS,
81 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
82 10000)) {
83 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
84 ring->mmio_base);
85 udelay(300);
86 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
87 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
88 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n",
89 ring->mmio_base);
90 }
91}
92
93static void bgmac_dma_tx_enable(struct bgmac *bgmac,
94 struct bgmac_dma_ring *ring)
95{
96 u32 ctl;
97
98 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
99 ctl |= BGMAC_DMA_TX_ENABLE;
100 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
101 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
102}
103
104static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
105 struct bgmac_dma_ring *ring,
106 struct sk_buff *skb)
107{
108 struct device *dma_dev = bgmac->core->dma_dev;
109 struct net_device *net_dev = bgmac->net_dev;
110 struct bgmac_dma_desc *dma_desc;
111 struct bgmac_slot_info *slot;
112 u32 ctl0, ctl1;
113 int free_slots;
114
115 if (skb->len > BGMAC_DESC_CTL1_LEN) {
116 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len);
117 goto err_stop_drop;
118 }
119
120 if (ring->start <= ring->end)
121 free_slots = ring->start - ring->end + BGMAC_TX_RING_SLOTS;
122 else
123 free_slots = ring->start - ring->end;
124 if (free_slots == 1) {
125 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n");
126 netif_stop_queue(net_dev);
127 return NETDEV_TX_BUSY;
128 }
129
130 slot = &ring->slots[ring->end];
131 slot->skb = skb;
132 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb->len,
133 DMA_TO_DEVICE);
134 if (dma_mapping_error(dma_dev, slot->dma_addr)) {
135 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n",
136 ring->mmio_base);
137 goto err_stop_drop;
138 }
139
140 ctl0 = BGMAC_DESC_CTL0_IOC | BGMAC_DESC_CTL0_SOF | BGMAC_DESC_CTL0_EOF;
141 if (ring->end == ring->num_slots - 1)
142 ctl0 |= BGMAC_DESC_CTL0_EOT;
143 ctl1 = skb->len & BGMAC_DESC_CTL1_LEN;
144
145 dma_desc = ring->cpu_base;
146 dma_desc += ring->end;
147 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
148 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
149 dma_desc->ctl0 = cpu_to_le32(ctl0);
150 dma_desc->ctl1 = cpu_to_le32(ctl1);
151
152 wmb();
153
154
155
156
157 if (++ring->end >= BGMAC_TX_RING_SLOTS)
158 ring->end = 0;
159 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
160 ring->end * sizeof(struct bgmac_dma_desc));
161
162
163 if (--free_slots == 1)
164 netif_stop_queue(net_dev);
165
166 return NETDEV_TX_OK;
167
168err_stop_drop:
169 netif_stop_queue(net_dev);
170 dev_kfree_skb(skb);
171 return NETDEV_TX_OK;
172}
173
174
175static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
176{
177 struct device *dma_dev = bgmac->core->dma_dev;
178 int empty_slot;
179 bool freed = false;
180
181
182 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
183 empty_slot &= BGMAC_DMA_TX_STATDPTR;
184 empty_slot /= sizeof(struct bgmac_dma_desc);
185
186 while (ring->start != empty_slot) {
187 struct bgmac_slot_info *slot = &ring->slots[ring->start];
188
189 if (slot->skb) {
190
191 dma_unmap_single(dma_dev, slot->dma_addr,
192 slot->skb->len, DMA_TO_DEVICE);
193 slot->dma_addr = 0;
194
195
196 dev_kfree_skb(slot->skb);
197 slot->skb = NULL;
198 } else {
199 bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n",
200 ring->start, ring->end);
201 }
202
203 if (++ring->start >= BGMAC_TX_RING_SLOTS)
204 ring->start = 0;
205 freed = true;
206 }
207
208 if (freed && netif_queue_stopped(bgmac->net_dev))
209 netif_wake_queue(bgmac->net_dev);
210}
211
212static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
213{
214 if (!ring->mmio_base)
215 return;
216
217 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
218 if (!bgmac_wait_value(bgmac->core,
219 ring->mmio_base + BGMAC_DMA_RX_STATUS,
220 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
221 10000))
222 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n",
223 ring->mmio_base);
224}
225
226static void bgmac_dma_rx_enable(struct bgmac *bgmac,
227 struct bgmac_dma_ring *ring)
228{
229 u32 ctl;
230
231 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
232 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
233 ctl |= BGMAC_DMA_RX_ENABLE;
234 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
235 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
236 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
237 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
238}
239
240static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
241 struct bgmac_slot_info *slot)
242{
243 struct device *dma_dev = bgmac->core->dma_dev;
244 struct bgmac_rx_header *rx;
245
246
247 slot->skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE);
248 if (!slot->skb)
249 return -ENOMEM;
250
251
252 rx = (struct bgmac_rx_header *)slot->skb->data;
253 rx->len = cpu_to_le16(0xdead);
254 rx->flags = cpu_to_le16(0xbeef);
255
256
257 slot->dma_addr = dma_map_single(dma_dev, slot->skb->data,
258 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
259 if (dma_mapping_error(dma_dev, slot->dma_addr)) {
260 bgmac_err(bgmac, "DMA mapping error\n");
261 return -ENOMEM;
262 }
263 if (slot->dma_addr & 0xC0000000)
264 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
265
266 return 0;
267}
268
269static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
270 int weight)
271{
272 u32 end_slot;
273 int handled = 0;
274
275 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
276 end_slot &= BGMAC_DMA_RX_STATDPTR;
277 end_slot /= sizeof(struct bgmac_dma_desc);
278
279 ring->end = end_slot;
280
281 while (ring->start != ring->end) {
282 struct device *dma_dev = bgmac->core->dma_dev;
283 struct bgmac_slot_info *slot = &ring->slots[ring->start];
284 struct sk_buff *skb = slot->skb;
285 struct sk_buff *new_skb;
286 struct bgmac_rx_header *rx;
287 u16 len, flags;
288
289
290 dma_sync_single_for_cpu(dma_dev, slot->dma_addr,
291 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
292
293
294 rx = (struct bgmac_rx_header *)skb->data;
295 len = le16_to_cpu(rx->len);
296 flags = le16_to_cpu(rx->flags);
297
298
299 if (len == 0xdead && flags == 0xbeef) {
300 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n",
301 ring->start);
302 } else {
303
304 len -= ETH_FCS_LEN;
305
306 new_skb = netdev_alloc_skb_ip_align(bgmac->net_dev, len);
307 if (new_skb) {
308 skb_put(new_skb, len);
309 skb_copy_from_linear_data_offset(skb, BGMAC_RX_FRAME_OFFSET,
310 new_skb->data,
311 len);
312 skb_checksum_none_assert(skb);
313 new_skb->protocol =
314 eth_type_trans(new_skb, bgmac->net_dev);
315 netif_receive_skb(new_skb);
316 handled++;
317 } else {
318 bgmac->net_dev->stats.rx_dropped++;
319 bgmac_err(bgmac, "Allocation of skb for copying packet failed!\n");
320 }
321
322
323 rx->len = cpu_to_le16(0xdead);
324 rx->flags = cpu_to_le16(0xbeef);
325 }
326
327
328 dma_sync_single_for_device(dma_dev, slot->dma_addr,
329 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
330
331 if (++ring->start >= BGMAC_RX_RING_SLOTS)
332 ring->start = 0;
333
334 if (handled >= weight)
335 break;
336 }
337
338 return handled;
339}
340
341
342static bool bgmac_dma_unaligned(struct bgmac *bgmac,
343 struct bgmac_dma_ring *ring,
344 enum bgmac_dma_ring_type ring_type)
345{
346 switch (ring_type) {
347 case BGMAC_DMA_RING_TX:
348 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
349 0xff0);
350 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
351 return true;
352 break;
353 case BGMAC_DMA_RING_RX:
354 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
355 0xff0);
356 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
357 return true;
358 break;
359 }
360 return false;
361}
362
363static void bgmac_dma_ring_free(struct bgmac *bgmac,
364 struct bgmac_dma_ring *ring)
365{
366 struct device *dma_dev = bgmac->core->dma_dev;
367 struct bgmac_slot_info *slot;
368 int size;
369 int i;
370
371 for (i = 0; i < ring->num_slots; i++) {
372 slot = &ring->slots[i];
373 if (slot->skb) {
374 if (slot->dma_addr)
375 dma_unmap_single(dma_dev, slot->dma_addr,
376 slot->skb->len, DMA_TO_DEVICE);
377 dev_kfree_skb(slot->skb);
378 }
379 }
380
381 if (ring->cpu_base) {
382
383 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
384 dma_free_coherent(dma_dev, size, ring->cpu_base,
385 ring->dma_base);
386 }
387}
388
389static void bgmac_dma_free(struct bgmac *bgmac)
390{
391 int i;
392
393 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
394 bgmac_dma_ring_free(bgmac, &bgmac->tx_ring[i]);
395 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
396 bgmac_dma_ring_free(bgmac, &bgmac->rx_ring[i]);
397}
398
399static int bgmac_dma_alloc(struct bgmac *bgmac)
400{
401 struct device *dma_dev = bgmac->core->dma_dev;
402 struct bgmac_dma_ring *ring;
403 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
404 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
405 int size;
406 int err;
407 int i;
408
409 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
410 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
411
412 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) {
413 bgmac_err(bgmac, "Core does not report 64-bit DMA\n");
414 return -ENOTSUPP;
415 }
416
417 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
418 ring = &bgmac->tx_ring[i];
419 ring->num_slots = BGMAC_TX_RING_SLOTS;
420 ring->mmio_base = ring_base[i];
421 if (bgmac_dma_unaligned(bgmac, ring, BGMAC_DMA_RING_TX))
422 bgmac_warn(bgmac, "TX on ring 0x%X supports unaligned addressing but this feature is not implemented\n",
423 ring->mmio_base);
424
425
426 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
427 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
428 &ring->dma_base,
429 GFP_KERNEL);
430 if (!ring->cpu_base) {
431 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n",
432 ring->mmio_base);
433 goto err_dma_free;
434 }
435 if (ring->dma_base & 0xC0000000)
436 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
437
438
439 }
440
441 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
442 int j;
443
444 ring = &bgmac->rx_ring[i];
445 ring->num_slots = BGMAC_RX_RING_SLOTS;
446 ring->mmio_base = ring_base[i];
447 if (bgmac_dma_unaligned(bgmac, ring, BGMAC_DMA_RING_RX))
448 bgmac_warn(bgmac, "RX on ring 0x%X supports unaligned addressing but this feature is not implemented\n",
449 ring->mmio_base);
450
451
452 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
453 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
454 &ring->dma_base,
455 GFP_KERNEL);
456 if (!ring->cpu_base) {
457 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n",
458 ring->mmio_base);
459 err = -ENOMEM;
460 goto err_dma_free;
461 }
462 if (ring->dma_base & 0xC0000000)
463 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
464
465
466 for (j = 0; j < ring->num_slots; j++) {
467 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
468 if (err) {
469 bgmac_err(bgmac, "Can't allocate skb for slot in RX ring\n");
470 goto err_dma_free;
471 }
472 }
473 }
474
475 return 0;
476
477err_dma_free:
478 bgmac_dma_free(bgmac);
479 return -ENOMEM;
480}
481
482static void bgmac_dma_init(struct bgmac *bgmac)
483{
484 struct bgmac_dma_ring *ring;
485 struct bgmac_dma_desc *dma_desc;
486 u32 ctl0, ctl1;
487 int i;
488
489 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
490 ring = &bgmac->tx_ring[i];
491
492
493 bgmac_dma_tx_enable(bgmac, ring);
494 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
495 lower_32_bits(ring->dma_base));
496 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
497 upper_32_bits(ring->dma_base));
498
499 ring->start = 0;
500 ring->end = 0;
501 }
502
503 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
504 int j;
505
506 ring = &bgmac->rx_ring[i];
507
508
509 bgmac_dma_rx_enable(bgmac, ring);
510 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
511 lower_32_bits(ring->dma_base));
512 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
513 upper_32_bits(ring->dma_base));
514
515 for (j = 0, dma_desc = ring->cpu_base; j < ring->num_slots;
516 j++, dma_desc++) {
517 ctl0 = ctl1 = 0;
518
519 if (j == ring->num_slots - 1)
520 ctl0 |= BGMAC_DESC_CTL0_EOT;
521 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
522
523
524
525
526
527 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[j].dma_addr));
528 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[j].dma_addr));
529 dma_desc->ctl0 = cpu_to_le32(ctl0);
530 dma_desc->ctl1 = cpu_to_le32(ctl1);
531 }
532
533 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
534 ring->num_slots * sizeof(struct bgmac_dma_desc));
535
536 ring->start = 0;
537 ring->end = 0;
538 }
539}
540
541
542
543
544
545static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
546{
547 struct bcma_device *core;
548 u16 phy_access_addr;
549 u16 phy_ctl_addr;
550 u32 tmp;
551
552 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
553 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
554 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
555 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
556 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
557 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
558 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
559 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
560 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
561 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
562 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
563
564 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
565 core = bgmac->core->bus->drv_gmac_cmn.core;
566 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
567 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
568 } else {
569 core = bgmac->core;
570 phy_access_addr = BGMAC_PHY_ACCESS;
571 phy_ctl_addr = BGMAC_PHY_CNTL;
572 }
573
574 tmp = bcma_read32(core, phy_ctl_addr);
575 tmp &= ~BGMAC_PC_EPA_MASK;
576 tmp |= phyaddr;
577 bcma_write32(core, phy_ctl_addr, tmp);
578
579 tmp = BGMAC_PA_START;
580 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
581 tmp |= reg << BGMAC_PA_REG_SHIFT;
582 bcma_write32(core, phy_access_addr, tmp);
583
584 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
585 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n",
586 phyaddr, reg);
587 return 0xffff;
588 }
589
590 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
591}
592
593
594static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value)
595{
596 struct bcma_device *core;
597 u16 phy_access_addr;
598 u16 phy_ctl_addr;
599 u32 tmp;
600
601 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
602 core = bgmac->core->bus->drv_gmac_cmn.core;
603 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
604 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
605 } else {
606 core = bgmac->core;
607 phy_access_addr = BGMAC_PHY_ACCESS;
608 phy_ctl_addr = BGMAC_PHY_CNTL;
609 }
610
611 tmp = bcma_read32(core, phy_ctl_addr);
612 tmp &= ~BGMAC_PC_EPA_MASK;
613 tmp |= phyaddr;
614 bcma_write32(core, phy_ctl_addr, tmp);
615
616 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
617 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
618 bgmac_warn(bgmac, "Error setting MDIO int\n");
619
620 tmp = BGMAC_PA_START;
621 tmp |= BGMAC_PA_WRITE;
622 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
623 tmp |= reg << BGMAC_PA_REG_SHIFT;
624 tmp |= value;
625 bcma_write32(core, phy_access_addr, tmp);
626
627 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
628 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n",
629 phyaddr, reg);
630 return -ETIMEDOUT;
631 }
632
633 return 0;
634}
635
636
637static void bgmac_phy_force(struct bgmac *bgmac)
638{
639 u16 ctl;
640 u16 mask = ~(BGMAC_PHY_CTL_SPEED | BGMAC_PHY_CTL_SPEED_MSB |
641 BGMAC_PHY_CTL_ANENAB | BGMAC_PHY_CTL_DUPLEX);
642
643 if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
644 return;
645
646 if (bgmac->autoneg)
647 return;
648
649 ctl = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL);
650 ctl &= mask;
651 if (bgmac->full_duplex)
652 ctl |= BGMAC_PHY_CTL_DUPLEX;
653 if (bgmac->speed == BGMAC_SPEED_100)
654 ctl |= BGMAC_PHY_CTL_SPEED_100;
655 else if (bgmac->speed == BGMAC_SPEED_1000)
656 ctl |= BGMAC_PHY_CTL_SPEED_1000;
657 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL, ctl);
658}
659
660
661static void bgmac_phy_advertise(struct bgmac *bgmac)
662{
663 u16 adv;
664
665 if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
666 return;
667
668 if (!bgmac->autoneg)
669 return;
670
671
672 adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV);
673 adv &= ~(BGMAC_PHY_ADV_10HALF | BGMAC_PHY_ADV_10FULL |
674 BGMAC_PHY_ADV_100HALF | BGMAC_PHY_ADV_100FULL);
675 if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10)
676 adv |= BGMAC_PHY_ADV_10HALF;
677 if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100)
678 adv |= BGMAC_PHY_ADV_100HALF;
679 if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10)
680 adv |= BGMAC_PHY_ADV_10FULL;
681 if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100)
682 adv |= BGMAC_PHY_ADV_100FULL;
683 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV, adv);
684
685
686 adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2);
687 adv &= ~(BGMAC_PHY_ADV2_1000HALF | BGMAC_PHY_ADV2_1000FULL);
688 if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000)
689 adv |= BGMAC_PHY_ADV2_1000HALF;
690 if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000)
691 adv |= BGMAC_PHY_ADV2_1000FULL;
692 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2, adv);
693
694
695 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
696 bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) |
697 BGMAC_PHY_CTL_RESTART);
698}
699
700
701static void bgmac_phy_init(struct bgmac *bgmac)
702{
703 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
704 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
705 u8 i;
706
707 if (ci->id == BCMA_CHIP_ID_BCM5356) {
708 for (i = 0; i < 5; i++) {
709 bgmac_phy_write(bgmac, i, 0x1f, 0x008b);
710 bgmac_phy_write(bgmac, i, 0x15, 0x0100);
711 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
712 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa);
713 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
714 }
715 }
716 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
717 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
718 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
719 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
720 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
721 for (i = 0; i < 5; i++) {
722 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
723 bgmac_phy_write(bgmac, i, 0x16, 0x5284);
724 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
725 bgmac_phy_write(bgmac, i, 0x17, 0x0010);
726 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
727 bgmac_phy_write(bgmac, i, 0x16, 0x5296);
728 bgmac_phy_write(bgmac, i, 0x17, 0x1073);
729 bgmac_phy_write(bgmac, i, 0x17, 0x9073);
730 bgmac_phy_write(bgmac, i, 0x16, 0x52b6);
731 bgmac_phy_write(bgmac, i, 0x17, 0x9273);
732 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
733 }
734 }
735}
736
737
738static void bgmac_phy_reset(struct bgmac *bgmac)
739{
740 if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
741 return;
742
743 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
744 BGMAC_PHY_CTL_RESET);
745 udelay(100);
746 if (bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) &
747 BGMAC_PHY_CTL_RESET)
748 bgmac_err(bgmac, "PHY reset failed\n");
749 bgmac_phy_init(bgmac);
750}
751
752
753
754
755
756
757
758
759static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
760 bool force)
761{
762 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
763 u32 new_val = (cmdcfg & mask) | set;
764
765 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
766 udelay(2);
767
768 if (new_val != cmdcfg || force)
769 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
770
771 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
772 udelay(2);
773}
774
775static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
776{
777 u32 tmp;
778
779 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
780 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
781 tmp = (addr[4] << 8) | addr[5];
782 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
783}
784
785static void bgmac_set_rx_mode(struct net_device *net_dev)
786{
787 struct bgmac *bgmac = netdev_priv(net_dev);
788
789 if (net_dev->flags & IFF_PROMISC)
790 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
791 else
792 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
793}
794
795#if 0
796static void bgmac_chip_stats_update(struct bgmac *bgmac)
797{
798 int i;
799
800 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) {
801 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
802 bgmac->mib_tx_regs[i] =
803 bgmac_read(bgmac,
804 BGMAC_TX_GOOD_OCTETS + (i * 4));
805 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
806 bgmac->mib_rx_regs[i] =
807 bgmac_read(bgmac,
808 BGMAC_RX_GOOD_OCTETS + (i * 4));
809 }
810
811
812}
813#endif
814
815static void bgmac_clear_mib(struct bgmac *bgmac)
816{
817 int i;
818
819 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT)
820 return;
821
822 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
823 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
824 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
825 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
826 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
827}
828
829
830static void bgmac_speed(struct bgmac *bgmac, int speed)
831{
832 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
833 u32 set = 0;
834
835 if (speed & BGMAC_SPEED_10)
836 set |= BGMAC_CMDCFG_ES_10;
837 if (speed & BGMAC_SPEED_100)
838 set |= BGMAC_CMDCFG_ES_100;
839 if (speed & BGMAC_SPEED_1000)
840 set |= BGMAC_CMDCFG_ES_1000;
841 if (!bgmac->full_duplex)
842 set |= BGMAC_CMDCFG_HD;
843 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
844}
845
846static void bgmac_miiconfig(struct bgmac *bgmac)
847{
848 u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
849 BGMAC_DS_MM_SHIFT;
850 if (imode == 0 || imode == 1) {
851 if (bgmac->autoneg)
852 bgmac_speed(bgmac, BGMAC_SPEED_100);
853 else
854 bgmac_speed(bgmac, bgmac->speed);
855 }
856}
857
858
859static void bgmac_chip_reset(struct bgmac *bgmac)
860{
861 struct bcma_device *core = bgmac->core;
862 struct bcma_bus *bus = core->bus;
863 struct bcma_chipinfo *ci = &bus->chipinfo;
864 u32 flags = 0;
865 u32 iost;
866 int i;
867
868 if (bcma_core_is_enabled(core)) {
869 if (!bgmac->stats_grabbed) {
870
871 bgmac->stats_grabbed = true;
872 }
873
874 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
875 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
876
877 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
878 udelay(1);
879
880 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
881 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
882
883
884 }
885
886 iost = bcma_aread32(core, BCMA_IOST);
887 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 10) ||
888 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
889 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9))
890 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
891
892 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
893 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
894 if (!bgmac->has_robosw)
895 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
896 }
897
898 bcma_core_enable(core, flags);
899
900 if (core->id.rev > 2) {
901 bgmac_set(bgmac, BCMA_CLKCTLST, 1 << 8);
902 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1 << 24, 1 << 24,
903 1000);
904 }
905
906 if (ci->id == BCMA_CHIP_ID_BCM5357 || ci->id == BCMA_CHIP_ID_BCM4749 ||
907 ci->id == BCMA_CHIP_ID_BCM53572) {
908 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
909 u8 et_swtype = 0;
910 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
911 BGMAC_CHIPCTL_1_IF_TYPE_MII;
912 char buf[2];
913
914 if (bcm47xx_nvram_getenv("et_swtype", buf, 1) > 0) {
915 if (kstrtou8(buf, 0, &et_swtype))
916 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n",
917 buf);
918 et_swtype &= 0x0f;
919 et_swtype <<= 4;
920 sw_type = et_swtype;
921 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 9) {
922 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
923 } else if ((ci->id != BCMA_CHIP_ID_BCM53572 && ci->pkg == 10) ||
924 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9)) {
925 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
926 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
927 }
928 bcma_chipco_chipctl_maskset(cc, 1,
929 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
930 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
931 sw_type);
932 }
933
934 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
935 bcma_awrite32(core, BCMA_IOCTL,
936 bcma_aread32(core, BCMA_IOCTL) &
937 ~BGMAC_BCMA_IOCTL_SW_RESET);
938
939
940
941
942
943
944 bgmac_cmdcfg_maskset(bgmac,
945 ~(BGMAC_CMDCFG_TE |
946 BGMAC_CMDCFG_RE |
947 BGMAC_CMDCFG_RPI |
948 BGMAC_CMDCFG_TAI |
949 BGMAC_CMDCFG_HD |
950 BGMAC_CMDCFG_ML |
951 BGMAC_CMDCFG_CFE |
952 BGMAC_CMDCFG_RL |
953 BGMAC_CMDCFG_RED |
954 BGMAC_CMDCFG_PE |
955 BGMAC_CMDCFG_TPI |
956 BGMAC_CMDCFG_PAD_EN |
957 BGMAC_CMDCFG_PF),
958 BGMAC_CMDCFG_PROM |
959 BGMAC_CMDCFG_NLC |
960 BGMAC_CMDCFG_CFE |
961 BGMAC_CMDCFG_SR,
962 false);
963
964 bgmac_clear_mib(bgmac);
965 if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
966 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0,
967 BCMA_GMAC_CMN_PC_MTE);
968 else
969 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
970 bgmac_miiconfig(bgmac);
971 bgmac_phy_init(bgmac);
972}
973
974static void bgmac_chip_intrs_on(struct bgmac *bgmac)
975{
976 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
977}
978
979static void bgmac_chip_intrs_off(struct bgmac *bgmac)
980{
981 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
982 bgmac_read(bgmac, BGMAC_INT_MASK);
983}
984
985
986static void bgmac_enable(struct bgmac *bgmac)
987{
988 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
989 u32 cmdcfg;
990 u32 mode;
991 u32 rxq_ctl;
992 u32 fl_ctl;
993 u16 bp_clk;
994 u8 mdp;
995
996 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
997 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
998 BGMAC_CMDCFG_SR, true);
999 udelay(2);
1000 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1001 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1002
1003 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1004 BGMAC_DS_MM_SHIFT;
1005 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0)
1006 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1007 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2)
1008 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0,
1009 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1010
1011 switch (ci->id) {
1012 case BCMA_CHIP_ID_BCM5357:
1013 case BCMA_CHIP_ID_BCM4749:
1014 case BCMA_CHIP_ID_BCM53572:
1015 case BCMA_CHIP_ID_BCM4716:
1016 case BCMA_CHIP_ID_BCM47162:
1017 fl_ctl = 0x03cb04cb;
1018 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1019 ci->id == BCMA_CHIP_ID_BCM4749 ||
1020 ci->id == BCMA_CHIP_ID_BCM53572)
1021 fl_ctl = 0x2300e1;
1022 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1023 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1024 break;
1025 }
1026
1027 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1028 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1029 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
1030 mdp = (bp_clk * 128 / 1000) - 3;
1031 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1032 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1033}
1034
1035
1036static void bgmac_chip_init(struct bgmac *bgmac, bool full_init)
1037{
1038 struct bgmac_dma_ring *ring;
1039 int i;
1040
1041
1042 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1043
1044
1045 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1046
1047 bgmac_set_rx_mode(bgmac->net_dev);
1048
1049 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
1050
1051 if (bgmac->loopback)
1052 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1053 else
1054 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
1055
1056 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1057
1058 if (!bgmac->autoneg) {
1059 bgmac_speed(bgmac, bgmac->speed);
1060 bgmac_phy_force(bgmac);
1061 } else if (bgmac->speed) {
1062 bgmac_phy_advertise(bgmac);
1063 }
1064
1065 if (full_init) {
1066 bgmac_dma_init(bgmac);
1067 if (1)
1068 bgmac_chip_intrs_on(bgmac);
1069 } else {
1070 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
1071 ring = &bgmac->rx_ring[i];
1072 bgmac_dma_rx_enable(bgmac, ring);
1073 }
1074 }
1075
1076 bgmac_enable(bgmac);
1077}
1078
1079static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1080{
1081 struct bgmac *bgmac = netdev_priv(dev_id);
1082
1083 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1084 int_status &= bgmac->int_mask;
1085
1086 if (!int_status)
1087 return IRQ_NONE;
1088
1089 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX);
1090 if (int_status)
1091 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", int_status);
1092
1093
1094 bgmac_chip_intrs_off(bgmac);
1095
1096 napi_schedule(&bgmac->napi);
1097
1098 return IRQ_HANDLED;
1099}
1100
1101static int bgmac_poll(struct napi_struct *napi, int weight)
1102{
1103 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1104 int handled = 0;
1105
1106
1107 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1108
1109 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]);
1110 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight);
1111
1112
1113 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
1114 return weight;
1115
1116 if (handled < weight)
1117 napi_complete(napi);
1118
1119 bgmac_chip_intrs_on(bgmac);
1120
1121 return handled;
1122}
1123
1124
1125
1126
1127
1128static int bgmac_open(struct net_device *net_dev)
1129{
1130 struct bgmac *bgmac = netdev_priv(net_dev);
1131 int err = 0;
1132
1133 bgmac_chip_reset(bgmac);
1134
1135 bgmac_chip_init(bgmac, true);
1136
1137 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED,
1138 KBUILD_MODNAME, net_dev);
1139 if (err < 0) {
1140 bgmac_err(bgmac, "IRQ request error: %d!\n", err);
1141 goto err_out;
1142 }
1143 napi_enable(&bgmac->napi);
1144
1145 netif_carrier_on(net_dev);
1146
1147err_out:
1148 return err;
1149}
1150
1151static int bgmac_stop(struct net_device *net_dev)
1152{
1153 struct bgmac *bgmac = netdev_priv(net_dev);
1154
1155 netif_carrier_off(net_dev);
1156
1157 napi_disable(&bgmac->napi);
1158 bgmac_chip_intrs_off(bgmac);
1159 free_irq(bgmac->core->irq, net_dev);
1160
1161 bgmac_chip_reset(bgmac);
1162
1163 return 0;
1164}
1165
1166static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1167 struct net_device *net_dev)
1168{
1169 struct bgmac *bgmac = netdev_priv(net_dev);
1170 struct bgmac_dma_ring *ring;
1171
1172
1173 ring = &bgmac->tx_ring[0];
1174 return bgmac_dma_tx_add(bgmac, ring, skb);
1175}
1176
1177static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1178{
1179 struct bgmac *bgmac = netdev_priv(net_dev);
1180 int ret;
1181
1182 ret = eth_prepare_mac_addr_change(net_dev, addr);
1183 if (ret < 0)
1184 return ret;
1185 bgmac_write_mac_address(bgmac, (u8 *)addr);
1186 eth_commit_mac_addr_change(net_dev, addr);
1187 return 0;
1188}
1189
1190static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1191{
1192 struct bgmac *bgmac = netdev_priv(net_dev);
1193 struct mii_ioctl_data *data = if_mii(ifr);
1194
1195 switch (cmd) {
1196 case SIOCGMIIPHY:
1197 data->phy_id = bgmac->phyaddr;
1198
1199 case SIOCGMIIREG:
1200 if (!netif_running(net_dev))
1201 return -EAGAIN;
1202 data->val_out = bgmac_phy_read(bgmac, data->phy_id,
1203 data->reg_num & 0x1f);
1204 return 0;
1205 case SIOCSMIIREG:
1206 if (!netif_running(net_dev))
1207 return -EAGAIN;
1208 bgmac_phy_write(bgmac, data->phy_id, data->reg_num & 0x1f,
1209 data->val_in);
1210 return 0;
1211 default:
1212 return -EOPNOTSUPP;
1213 }
1214}
1215
1216static const struct net_device_ops bgmac_netdev_ops = {
1217 .ndo_open = bgmac_open,
1218 .ndo_stop = bgmac_stop,
1219 .ndo_start_xmit = bgmac_start_xmit,
1220 .ndo_set_rx_mode = bgmac_set_rx_mode,
1221 .ndo_set_mac_address = bgmac_set_mac_address,
1222 .ndo_validate_addr = eth_validate_addr,
1223 .ndo_do_ioctl = bgmac_ioctl,
1224};
1225
1226
1227
1228
1229
1230static int bgmac_get_settings(struct net_device *net_dev,
1231 struct ethtool_cmd *cmd)
1232{
1233 struct bgmac *bgmac = netdev_priv(net_dev);
1234
1235 cmd->supported = SUPPORTED_10baseT_Half |
1236 SUPPORTED_10baseT_Full |
1237 SUPPORTED_100baseT_Half |
1238 SUPPORTED_100baseT_Full |
1239 SUPPORTED_1000baseT_Half |
1240 SUPPORTED_1000baseT_Full |
1241 SUPPORTED_Autoneg;
1242
1243 if (bgmac->autoneg) {
1244 WARN_ON(cmd->advertising);
1245 if (bgmac->full_duplex) {
1246 if (bgmac->speed & BGMAC_SPEED_10)
1247 cmd->advertising |= ADVERTISED_10baseT_Full;
1248 if (bgmac->speed & BGMAC_SPEED_100)
1249 cmd->advertising |= ADVERTISED_100baseT_Full;
1250 if (bgmac->speed & BGMAC_SPEED_1000)
1251 cmd->advertising |= ADVERTISED_1000baseT_Full;
1252 } else {
1253 if (bgmac->speed & BGMAC_SPEED_10)
1254 cmd->advertising |= ADVERTISED_10baseT_Half;
1255 if (bgmac->speed & BGMAC_SPEED_100)
1256 cmd->advertising |= ADVERTISED_100baseT_Half;
1257 if (bgmac->speed & BGMAC_SPEED_1000)
1258 cmd->advertising |= ADVERTISED_1000baseT_Half;
1259 }
1260 } else {
1261 switch (bgmac->speed) {
1262 case BGMAC_SPEED_10:
1263 ethtool_cmd_speed_set(cmd, SPEED_10);
1264 break;
1265 case BGMAC_SPEED_100:
1266 ethtool_cmd_speed_set(cmd, SPEED_100);
1267 break;
1268 case BGMAC_SPEED_1000:
1269 ethtool_cmd_speed_set(cmd, SPEED_1000);
1270 break;
1271 }
1272 }
1273
1274 cmd->duplex = bgmac->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1275
1276 cmd->autoneg = bgmac->autoneg;
1277
1278 return 0;
1279}
1280
1281#if 0
1282static int bgmac_set_settings(struct net_device *net_dev,
1283 struct ethtool_cmd *cmd)
1284{
1285 struct bgmac *bgmac = netdev_priv(net_dev);
1286
1287 return -1;
1288}
1289#endif
1290
1291static void bgmac_get_drvinfo(struct net_device *net_dev,
1292 struct ethtool_drvinfo *info)
1293{
1294 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1295 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info));
1296}
1297
1298static const struct ethtool_ops bgmac_ethtool_ops = {
1299 .get_settings = bgmac_get_settings,
1300 .get_drvinfo = bgmac_get_drvinfo,
1301};
1302
1303
1304
1305
1306
1307static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum)
1308{
1309 return bgmac_phy_read(bus->priv, mii_id, regnum);
1310}
1311
1312static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum,
1313 u16 value)
1314{
1315 return bgmac_phy_write(bus->priv, mii_id, regnum, value);
1316}
1317
1318static int bgmac_mii_register(struct bgmac *bgmac)
1319{
1320 struct mii_bus *mii_bus;
1321 int i, err = 0;
1322
1323 mii_bus = mdiobus_alloc();
1324 if (!mii_bus)
1325 return -ENOMEM;
1326
1327 mii_bus->name = "bgmac mii bus";
1328 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num,
1329 bgmac->core->core_unit);
1330 mii_bus->priv = bgmac;
1331 mii_bus->read = bgmac_mii_read;
1332 mii_bus->write = bgmac_mii_write;
1333 mii_bus->parent = &bgmac->core->dev;
1334 mii_bus->phy_mask = ~(1 << bgmac->phyaddr);
1335
1336 mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1337 if (!mii_bus->irq) {
1338 err = -ENOMEM;
1339 goto err_free_bus;
1340 }
1341 for (i = 0; i < PHY_MAX_ADDR; i++)
1342 mii_bus->irq[i] = PHY_POLL;
1343
1344 err = mdiobus_register(mii_bus);
1345 if (err) {
1346 bgmac_err(bgmac, "Registration of mii bus failed\n");
1347 goto err_free_irq;
1348 }
1349
1350 bgmac->mii_bus = mii_bus;
1351
1352 return err;
1353
1354err_free_irq:
1355 kfree(mii_bus->irq);
1356err_free_bus:
1357 mdiobus_free(mii_bus);
1358 return err;
1359}
1360
1361static void bgmac_mii_unregister(struct bgmac *bgmac)
1362{
1363 struct mii_bus *mii_bus = bgmac->mii_bus;
1364
1365 mdiobus_unregister(mii_bus);
1366 kfree(mii_bus->irq);
1367 mdiobus_free(mii_bus);
1368}
1369
1370
1371
1372
1373
1374
1375static int bgmac_probe(struct bcma_device *core)
1376{
1377 struct net_device *net_dev;
1378 struct bgmac *bgmac;
1379 struct ssb_sprom *sprom = &core->bus->sprom;
1380 u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac;
1381 int err;
1382
1383
1384 if (core->core_unit > 1) {
1385 pr_err("Unsupported core_unit %d\n", core->core_unit);
1386 return -ENOTSUPP;
1387 }
1388
1389 if (!is_valid_ether_addr(mac)) {
1390 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac);
1391 eth_random_addr(mac);
1392 dev_warn(&core->dev, "Using random MAC: %pM\n", mac);
1393 }
1394
1395
1396 net_dev = alloc_etherdev(sizeof(*bgmac));
1397 if (!net_dev)
1398 return -ENOMEM;
1399 net_dev->netdev_ops = &bgmac_netdev_ops;
1400 net_dev->irq = core->irq;
1401 SET_ETHTOOL_OPS(net_dev, &bgmac_ethtool_ops);
1402 bgmac = netdev_priv(net_dev);
1403 bgmac->net_dev = net_dev;
1404 bgmac->core = core;
1405 bcma_set_drvdata(core, bgmac);
1406
1407
1408 bgmac->autoneg = true;
1409 bgmac->full_duplex = true;
1410 bgmac->speed = BGMAC_SPEED_10 | BGMAC_SPEED_100 | BGMAC_SPEED_1000;
1411 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
1412
1413
1414 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1415 !core->bus->drv_gmac_cmn.core) {
1416 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n");
1417 err = -ENODEV;
1418 goto err_netdev_free;
1419 }
1420 bgmac->cmn = core->bus->drv_gmac_cmn.core;
1421
1422 bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr :
1423 sprom->et0phyaddr;
1424 bgmac->phyaddr &= BGMAC_PHY_MASK;
1425 if (bgmac->phyaddr == BGMAC_PHY_MASK) {
1426 bgmac_err(bgmac, "No PHY found\n");
1427 err = -ENODEV;
1428 goto err_netdev_free;
1429 }
1430 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr,
1431 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : "");
1432
1433 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
1434 bgmac_err(bgmac, "PCI setup not implemented\n");
1435 err = -ENOTSUPP;
1436 goto err_netdev_free;
1437 }
1438
1439 bgmac_chip_reset(bgmac);
1440
1441 err = bgmac_dma_alloc(bgmac);
1442 if (err) {
1443 bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
1444 goto err_netdev_free;
1445 }
1446
1447 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
1448 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
1449 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1450
1451
1452 bgmac_phy_reset(bgmac);
1453
1454 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo &
1455 BGMAC_BFL_ENETROBO);
1456 if (bgmac->has_robosw)
1457 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n");
1458
1459 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM)
1460 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n");
1461
1462 err = bgmac_mii_register(bgmac);
1463 if (err) {
1464 bgmac_err(bgmac, "Cannot register MDIO\n");
1465 err = -ENOTSUPP;
1466 goto err_dma_free;
1467 }
1468
1469 err = register_netdev(bgmac->net_dev);
1470 if (err) {
1471 bgmac_err(bgmac, "Cannot register net device\n");
1472 err = -ENOTSUPP;
1473 goto err_mii_unregister;
1474 }
1475
1476 netif_carrier_off(net_dev);
1477
1478 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1479
1480 return 0;
1481
1482err_mii_unregister:
1483 bgmac_mii_unregister(bgmac);
1484err_dma_free:
1485 bgmac_dma_free(bgmac);
1486
1487err_netdev_free:
1488 bcma_set_drvdata(core, NULL);
1489 free_netdev(net_dev);
1490
1491 return err;
1492}
1493
1494static void bgmac_remove(struct bcma_device *core)
1495{
1496 struct bgmac *bgmac = bcma_get_drvdata(core);
1497
1498 netif_napi_del(&bgmac->napi);
1499 unregister_netdev(bgmac->net_dev);
1500 bgmac_mii_unregister(bgmac);
1501 bgmac_dma_free(bgmac);
1502 bcma_set_drvdata(core, NULL);
1503 free_netdev(bgmac->net_dev);
1504}
1505
1506static struct bcma_driver bgmac_bcma_driver = {
1507 .name = KBUILD_MODNAME,
1508 .id_table = bgmac_bcma_tbl,
1509 .probe = bgmac_probe,
1510 .remove = bgmac_remove,
1511};
1512
1513static int __init bgmac_init(void)
1514{
1515 int err;
1516
1517 err = bcma_driver_register(&bgmac_bcma_driver);
1518 if (err)
1519 return err;
1520 pr_info("Broadcom 47xx GBit MAC driver loaded\n");
1521
1522 return 0;
1523}
1524
1525static void __exit bgmac_exit(void)
1526{
1527 bcma_driver_unregister(&bgmac_bcma_driver);
1528}
1529
1530module_init(bgmac_init)
1531module_exit(bgmac_exit)
1532
1533MODULE_AUTHOR("Rafał Miłecki");
1534MODULE_LICENSE("GPL");
1535
