1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
38#include "t4_hw.h"
39
40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
48#include <linux/vmalloc.h>
49#include <linux/etherdevice.h>
50#include <linux/net_tstamp.h>
51#include <linux/ptp_clock_kernel.h>
52#include <linux/ptp_classify.h>
53#include <asm/io.h>
54#include "t4_chip_type.h"
55#include "cxgb4_uld.h"
56
57#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
58extern struct list_head adapter_list;
59extern struct mutex uld_mutex;
60
61
62
63
64
65#define ETHTXQ_STOP_THRES \
66 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8))
67
68enum {
69 MAX_NPORTS = 4,
70 SERNUM_LEN = 24,
71 EC_LEN = 16,
72 ID_LEN = 16,
73 PN_LEN = 16,
74 MACADDR_LEN = 12,
75};
76
77enum {
78 T4_REGMAP_SIZE = (160 * 1024),
79 T5_REGMAP_SIZE = (332 * 1024),
80};
81
82enum {
83 MEM_EDC0,
84 MEM_EDC1,
85 MEM_MC,
86 MEM_MC0 = MEM_MC,
87 MEM_MC1,
88 MEM_HMA,
89};
90
91enum {
92 MEMWIN0_APERTURE = 2048,
93 MEMWIN0_BASE = 0x1b800,
94 MEMWIN1_APERTURE = 32768,
95 MEMWIN1_BASE = 0x28000,
96 MEMWIN1_BASE_T5 = 0x52000,
97 MEMWIN2_APERTURE = 65536,
98 MEMWIN2_BASE = 0x30000,
99 MEMWIN2_APERTURE_T5 = 131072,
100 MEMWIN2_BASE_T5 = 0x60000,
101};
102
103enum dev_master {
104 MASTER_CANT,
105 MASTER_MAY,
106 MASTER_MUST
107};
108
109enum dev_state {
110 DEV_STATE_UNINIT,
111 DEV_STATE_INIT,
112 DEV_STATE_ERR
113};
114
115enum cc_pause {
116 PAUSE_RX = 1 << 0,
117 PAUSE_TX = 1 << 1,
118 PAUSE_AUTONEG = 1 << 2
119};
120
121enum cc_fec {
122 FEC_AUTO = 1 << 0,
123 FEC_RS = 1 << 1,
124 FEC_BASER_RS = 1 << 2
125};
126
127struct port_stats {
128 u64 tx_octets;
129 u64 tx_frames;
130 u64 tx_bcast_frames;
131 u64 tx_mcast_frames;
132 u64 tx_ucast_frames;
133 u64 tx_error_frames;
134
135 u64 tx_frames_64;
136 u64 tx_frames_65_127;
137 u64 tx_frames_128_255;
138 u64 tx_frames_256_511;
139 u64 tx_frames_512_1023;
140 u64 tx_frames_1024_1518;
141 u64 tx_frames_1519_max;
142
143 u64 tx_drop;
144 u64 tx_pause;
145 u64 tx_ppp0;
146 u64 tx_ppp1;
147 u64 tx_ppp2;
148 u64 tx_ppp3;
149 u64 tx_ppp4;
150 u64 tx_ppp5;
151 u64 tx_ppp6;
152 u64 tx_ppp7;
153
154 u64 rx_octets;
155 u64 rx_frames;
156 u64 rx_bcast_frames;
157 u64 rx_mcast_frames;
158 u64 rx_ucast_frames;
159 u64 rx_too_long;
160 u64 rx_jabber;
161 u64 rx_fcs_err;
162 u64 rx_len_err;
163 u64 rx_symbol_err;
164 u64 rx_runt;
165
166 u64 rx_frames_64;
167 u64 rx_frames_65_127;
168 u64 rx_frames_128_255;
169 u64 rx_frames_256_511;
170 u64 rx_frames_512_1023;
171 u64 rx_frames_1024_1518;
172 u64 rx_frames_1519_max;
173
174 u64 rx_pause;
175 u64 rx_ppp0;
176 u64 rx_ppp1;
177 u64 rx_ppp2;
178 u64 rx_ppp3;
179 u64 rx_ppp4;
180 u64 rx_ppp5;
181 u64 rx_ppp6;
182 u64 rx_ppp7;
183
184 u64 rx_ovflow0;
185 u64 rx_ovflow1;
186 u64 rx_ovflow2;
187 u64 rx_ovflow3;
188 u64 rx_trunc0;
189 u64 rx_trunc1;
190 u64 rx_trunc2;
191 u64 rx_trunc3;
192};
193
194struct lb_port_stats {
195 u64 octets;
196 u64 frames;
197 u64 bcast_frames;
198 u64 mcast_frames;
199 u64 ucast_frames;
200 u64 error_frames;
201
202 u64 frames_64;
203 u64 frames_65_127;
204 u64 frames_128_255;
205 u64 frames_256_511;
206 u64 frames_512_1023;
207 u64 frames_1024_1518;
208 u64 frames_1519_max;
209
210 u64 drop;
211
212 u64 ovflow0;
213 u64 ovflow1;
214 u64 ovflow2;
215 u64 ovflow3;
216 u64 trunc0;
217 u64 trunc1;
218 u64 trunc2;
219 u64 trunc3;
220};
221
222struct tp_tcp_stats {
223 u32 tcp_out_rsts;
224 u64 tcp_in_segs;
225 u64 tcp_out_segs;
226 u64 tcp_retrans_segs;
227};
228
229struct tp_usm_stats {
230 u32 frames;
231 u32 drops;
232 u64 octets;
233};
234
235struct tp_fcoe_stats {
236 u32 frames_ddp;
237 u32 frames_drop;
238 u64 octets_ddp;
239};
240
241struct tp_err_stats {
242 u32 mac_in_errs[4];
243 u32 hdr_in_errs[4];
244 u32 tcp_in_errs[4];
245 u32 tnl_cong_drops[4];
246 u32 ofld_chan_drops[4];
247 u32 tnl_tx_drops[4];
248 u32 ofld_vlan_drops[4];
249 u32 tcp6_in_errs[4];
250 u32 ofld_no_neigh;
251 u32 ofld_cong_defer;
252};
253
254struct tp_cpl_stats {
255 u32 req[4];
256 u32 rsp[4];
257};
258
259struct tp_rdma_stats {
260 u32 rqe_dfr_pkt;
261 u32 rqe_dfr_mod;
262};
263
264struct sge_params {
265 u32 hps;
266 u32 eq_qpp;
267 u32 iq_qpp;
268};
269
270struct tp_params {
271 unsigned int tre;
272 unsigned int la_mask;
273 unsigned short tx_modq_map;
274
275
276 uint32_t dack_re;
277 unsigned short tx_modq[NCHAN];
278
279 u32 vlan_pri_map;
280 u32 ingress_config;
281
282
283
284
285 int rx_pkt_encap;
286
287
288
289
290
291
292
293
294
295
296
297
298 int fcoe_shift;
299 int port_shift;
300 int vnic_shift;
301 int vlan_shift;
302 int tos_shift;
303 int protocol_shift;
304 int ethertype_shift;
305 int macmatch_shift;
306 int matchtype_shift;
307 int frag_shift;
308
309 u64 hash_filter_mask;
310};
311
312struct vpd_params {
313 unsigned int cclk;
314 u8 ec[EC_LEN + 1];
315 u8 sn[SERNUM_LEN + 1];
316 u8 id[ID_LEN + 1];
317 u8 pn[PN_LEN + 1];
318 u8 na[MACADDR_LEN + 1];
319};
320
321struct pci_params {
322 unsigned int vpd_cap_addr;
323 unsigned char speed;
324 unsigned char width;
325};
326
327struct devlog_params {
328 u32 memtype;
329 u32 start;
330 u32 size;
331};
332
333
334struct arch_specific_params {
335 u8 nchan;
336 u8 pm_stats_cnt;
337 u8 cng_ch_bits_log;
338 u16 mps_rplc_size;
339 u16 vfcount;
340 u32 sge_fl_db;
341 u16 mps_tcam_size;
342};
343
344struct adapter_params {
345 struct sge_params sge;
346 struct tp_params tp;
347 struct vpd_params vpd;
348 struct pci_params pci;
349 struct devlog_params devlog;
350 enum pcie_memwin drv_memwin;
351
352 unsigned int cim_la_size;
353
354 unsigned int sf_size;
355 unsigned int sf_nsec;
356
357 unsigned int fw_vers;
358 unsigned int bs_vers;
359 unsigned int tp_vers;
360 unsigned int er_vers;
361 unsigned int scfg_vers;
362 unsigned int vpd_vers;
363 u8 api_vers[7];
364
365 unsigned short mtus[NMTUS];
366 unsigned short a_wnd[NCCTRL_WIN];
367 unsigned short b_wnd[NCCTRL_WIN];
368
369 unsigned char nports;
370 unsigned char portvec;
371 enum chip_type chip;
372 struct arch_specific_params arch;
373 unsigned char offload;
374 unsigned char crypto;
375
376 unsigned char bypass;
377 unsigned char hash_filter;
378
379 unsigned int ofldq_wr_cred;
380 bool ulptx_memwrite_dsgl;
381
382 unsigned int nsched_cls;
383 unsigned int max_ordird_qp;
384 unsigned int max_ird_adapter;
385 bool fr_nsmr_tpte_wr_support;
386 u8 fw_caps_support;
387 bool filter2_wr_support;
388
389
390
391
392 u8 mps_bg_map[MAX_NPORTS];
393 bool write_w_imm_support;
394 bool write_cmpl_support;
395};
396
397
398
399
400struct sge_idma_monitor_state {
401 unsigned int idma_1s_thresh;
402 unsigned int idma_stalled[2];
403 unsigned int idma_state[2];
404 unsigned int idma_qid[2];
405 unsigned int idma_warn[2];
406};
407
408
409
410
411
412struct mbox_cmd {
413 u64 cmd[MBOX_LEN / 8];
414 u64 timestamp;
415 u32 seqno;
416 s16 access;
417 s16 execute;
418};
419
420struct mbox_cmd_log {
421 unsigned int size;
422 unsigned int cursor;
423 u32 seqno;
424
425};
426
427
428
429
430static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
431 unsigned int entry_idx)
432{
433 return &((struct mbox_cmd *)&(log)[1])[entry_idx];
434}
435
436#include "t4fw_api.h"
437
438#define FW_VERSION(chip) ( \
439 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
440 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
441 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
442 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
443#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
444
445struct fw_info {
446 u8 chip;
447 char *fs_name;
448 char *fw_mod_name;
449 struct fw_hdr fw_hdr;
450};
451
452struct trace_params {
453 u32 data[TRACE_LEN / 4];
454 u32 mask[TRACE_LEN / 4];
455 unsigned short snap_len;
456 unsigned short min_len;
457 unsigned char skip_ofst;
458 unsigned char skip_len;
459 unsigned char invert;
460 unsigned char port;
461};
462
463
464
465typedef u16 fw_port_cap16_t;
466typedef u32 fw_port_cap32_t;
467
468enum fw_caps {
469 FW_CAPS_UNKNOWN = 0,
470 FW_CAPS16 = 1,
471 FW_CAPS32 = 2,
472};
473
474struct link_config {
475 fw_port_cap32_t pcaps;
476 fw_port_cap32_t def_acaps;
477 fw_port_cap32_t acaps;
478 fw_port_cap32_t lpacaps;
479
480 fw_port_cap32_t speed_caps;
481 unsigned int speed;
482
483 enum cc_pause requested_fc;
484 enum cc_pause fc;
485
486 enum cc_fec requested_fec;
487 enum cc_fec fec;
488
489 unsigned char autoneg;
490
491 unsigned char link_ok;
492 unsigned char link_down_rc;
493
494 bool new_module;
495 bool redo_l1cfg;
496};
497
498#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
499
500enum {
501 MAX_ETH_QSETS = 32,
502 MAX_OFLD_QSETS = 16,
503 MAX_CTRL_QUEUES = NCHAN,
504};
505
506enum {
507 MAX_TXQ_ENTRIES = 16384,
508 MAX_CTRL_TXQ_ENTRIES = 1024,
509 MAX_RSPQ_ENTRIES = 16384,
510 MAX_RX_BUFFERS = 16384,
511 MIN_TXQ_ENTRIES = 32,
512 MIN_CTRL_TXQ_ENTRIES = 32,
513 MIN_RSPQ_ENTRIES = 128,
514 MIN_FL_ENTRIES = 16
515};
516
517enum {
518 INGQ_EXTRAS = 2,
519
520 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS,
521};
522
523enum {
524 PRIV_FLAG_PORT_TX_VM_BIT,
525};
526
527#define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT)
528
529#define PRIV_FLAGS_ADAP 0
530#define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM
531
532struct adapter;
533struct sge_rspq;
534
535#include "cxgb4_dcb.h"
536
537struct port_info {
538 struct adapter *adapter;
539 u16 viid;
540 s16 xact_addr_filt;
541 u16 rss_size;
542 s8 mdio_addr;
543 enum fw_port_type port_type;
544 u8 mod_type;
545 u8 port_id;
546 u8 tx_chan;
547 u8 lport;
548 u8 nqsets;
549 u8 first_qset;
550 u8 rss_mode;
551 struct link_config link_cfg;
552 u16 *rss;
553 struct port_stats stats_base;
554#ifdef CONFIG_CHELSIO_T4_DCB
555 struct port_dcb_info dcb;
556#endif
557 bool rxtstamp;
558 struct hwtstamp_config tstamp_config;
559 bool ptp_enable;
560 struct sched_table *sched_tbl;
561 u32 eth_flags;
562};
563
564struct dentry;
565struct work_struct;
566
567enum {
568 FULL_INIT_DONE = (1 << 0),
569 DEV_ENABLED = (1 << 1),
570 USING_MSI = (1 << 2),
571 USING_MSIX = (1 << 3),
572 FW_OK = (1 << 4),
573 RSS_TNLALLLOOKUP = (1 << 5),
574 USING_SOFT_PARAMS = (1 << 6),
575 MASTER_PF = (1 << 7),
576 FW_OFLD_CONN = (1 << 9),
577 ROOT_NO_RELAXED_ORDERING = (1 << 10),
578 SHUTTING_DOWN = (1 << 11),
579};
580
581enum {
582 ULP_CRYPTO_LOOKASIDE = 1 << 0,
583 ULP_CRYPTO_IPSEC_INLINE = 1 << 1,
584};
585
586struct rx_sw_desc;
587
588struct sge_fl {
589 unsigned int avail;
590 unsigned int pend_cred;
591 unsigned int cidx;
592 unsigned int pidx;
593 unsigned long alloc_failed;
594 unsigned long large_alloc_failed;
595 unsigned long mapping_err;
596 unsigned long low;
597 unsigned long starving;
598
599 unsigned int cntxt_id;
600 unsigned int size;
601 struct rx_sw_desc *sdesc;
602 __be64 *desc;
603 dma_addr_t addr;
604 void __iomem *bar2_addr;
605 unsigned int bar2_qid;
606};
607
608
609struct pkt_gl {
610 u64 sgetstamp;
611 struct page_frag frags[MAX_SKB_FRAGS];
612 void *va;
613 unsigned int nfrags;
614 unsigned int tot_len;
615};
616
617typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
618 const struct pkt_gl *gl);
619typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
620
621struct t4_lro_mgr {
622#define MAX_LRO_SESSIONS 64
623 u8 lro_session_cnt;
624 unsigned long lro_pkts;
625 unsigned long lro_merged;
626 struct sk_buff_head lroq;
627};
628
629struct sge_rspq {
630 struct napi_struct napi;
631 const __be64 *cur_desc;
632 unsigned int cidx;
633 u8 gen;
634 u8 intr_params;
635 u8 next_intr_params;
636 u8 adaptive_rx;
637 u8 pktcnt_idx;
638 u8 uld;
639 u8 idx;
640 int offset;
641 u16 cntxt_id;
642 u16 abs_id;
643 __be64 *desc;
644 dma_addr_t phys_addr;
645 void __iomem *bar2_addr;
646 unsigned int bar2_qid;
647 unsigned int iqe_len;
648 unsigned int size;
649 struct adapter *adap;
650 struct net_device *netdev;
651 rspq_handler_t handler;
652 rspq_flush_handler_t flush_handler;
653 struct t4_lro_mgr lro_mgr;
654};
655
656struct sge_eth_stats {
657 unsigned long pkts;
658 unsigned long lro_pkts;
659 unsigned long lro_merged;
660 unsigned long rx_cso;
661 unsigned long vlan_ex;
662 unsigned long rx_drops;
663};
664
665struct sge_eth_rxq {
666 struct sge_rspq rspq;
667 struct sge_fl fl;
668 struct sge_eth_stats stats;
669} ____cacheline_aligned_in_smp;
670
671struct sge_ofld_stats {
672 unsigned long pkts;
673 unsigned long imm;
674 unsigned long an;
675 unsigned long nomem;
676};
677
678struct sge_ofld_rxq {
679 struct sge_rspq rspq;
680 struct sge_fl fl;
681 struct sge_ofld_stats stats;
682} ____cacheline_aligned_in_smp;
683
684struct tx_desc {
685 __be64 flit[8];
686};
687
688struct tx_sw_desc;
689
690struct sge_txq {
691 unsigned int in_use;
692 unsigned int q_type;
693 unsigned int size;
694 unsigned int cidx;
695 unsigned int pidx;
696 unsigned long stops;
697 unsigned long restarts;
698 unsigned int cntxt_id;
699 struct tx_desc *desc;
700 struct tx_sw_desc *sdesc;
701 struct sge_qstat *stat;
702 dma_addr_t phys_addr;
703 spinlock_t db_lock;
704 int db_disabled;
705 unsigned short db_pidx;
706 unsigned short db_pidx_inc;
707 void __iomem *bar2_addr;
708 unsigned int bar2_qid;
709};
710
711struct sge_eth_txq {
712 struct sge_txq q;
713 struct netdev_queue *txq;
714#ifdef CONFIG_CHELSIO_T4_DCB
715 u8 dcb_prio;
716#endif
717 unsigned long tso;
718 unsigned long tx_cso;
719 unsigned long vlan_ins;
720 unsigned long mapping_err;
721} ____cacheline_aligned_in_smp;
722
723struct sge_uld_txq {
724 struct sge_txq q;
725 struct adapter *adap;
726 struct sk_buff_head sendq;
727 struct tasklet_struct qresume_tsk;
728 bool service_ofldq_running;
729 u8 full;
730 unsigned long mapping_err;
731} ____cacheline_aligned_in_smp;
732
733struct sge_ctrl_txq {
734 struct sge_txq q;
735 struct adapter *adap;
736 struct sk_buff_head sendq;
737 struct tasklet_struct qresume_tsk;
738 u8 full;
739} ____cacheline_aligned_in_smp;
740
741struct sge_uld_rxq_info {
742 char name[IFNAMSIZ];
743 struct sge_ofld_rxq *uldrxq;
744 u16 *msix_tbl;
745 u16 *rspq_id;
746 u16 nrxq;
747 u16 nciq;
748 u8 uld;
749};
750
751struct sge_uld_txq_info {
752 struct sge_uld_txq *uldtxq;
753 atomic_t users;
754 u16 ntxq;
755};
756
757struct sge {
758 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
759 struct sge_eth_txq ptptxq;
760 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
761
762 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
763 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
764 struct sge_uld_rxq_info **uld_rxq_info;
765 struct sge_uld_txq_info **uld_txq_info;
766
767 struct sge_rspq intrq ____cacheline_aligned_in_smp;
768 spinlock_t intrq_lock;
769
770 u16 max_ethqsets;
771 u16 ethqsets;
772 u16 ethtxq_rover;
773 u16 ofldqsets;
774 u16 nqs_per_uld;
775 u16 timer_val[SGE_NTIMERS];
776 u8 counter_val[SGE_NCOUNTERS];
777 u32 fl_pg_order;
778 u32 stat_len;
779 u32 pktshift;
780 u32 fl_align;
781 u32 fl_starve_thres;
782
783 struct sge_idma_monitor_state idma_monitor;
784 unsigned int egr_start;
785 unsigned int egr_sz;
786 unsigned int ingr_start;
787 unsigned int ingr_sz;
788 void **egr_map;
789 struct sge_rspq **ingr_map;
790 unsigned long *starving_fl;
791 unsigned long *txq_maperr;
792 unsigned long *blocked_fl;
793 struct timer_list rx_timer;
794 struct timer_list tx_timer;
795};
796
797#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
798#define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
799
800struct l2t_data;
801
802#ifdef CONFIG_PCI_IOV
803
804
805
806
807
808#define NUM_OF_PF_WITH_SRIOV 4
809
810#endif
811
812struct doorbell_stats {
813 u32 db_drop;
814 u32 db_empty;
815 u32 db_full;
816};
817
818struct hash_mac_addr {
819 struct list_head list;
820 u8 addr[ETH_ALEN];
821};
822
823struct uld_msix_bmap {
824 unsigned long *msix_bmap;
825 unsigned int mapsize;
826 spinlock_t lock;
827};
828
829struct uld_msix_info {
830 unsigned short vec;
831 char desc[IFNAMSIZ + 10];
832 unsigned int idx;
833};
834
835struct vf_info {
836 unsigned char vf_mac_addr[ETH_ALEN];
837 unsigned int tx_rate;
838 bool pf_set_mac;
839 u16 vlan;
840};
841
842enum {
843 HMA_DMA_MAPPED_FLAG = 1
844};
845
846struct hma_data {
847 unsigned char flags;
848 struct sg_table *sgt;
849 dma_addr_t *phy_addr;
850};
851
852struct mbox_list {
853 struct list_head list;
854};
855
856struct mps_encap_entry {
857 atomic_t refcnt;
858};
859
860struct adapter {
861 void __iomem *regs;
862 void __iomem *bar2;
863 u32 t4_bar0;
864 struct pci_dev *pdev;
865 struct device *pdev_dev;
866 const char *name;
867 unsigned int mbox;
868 unsigned int pf;
869 unsigned int flags;
870 unsigned int adap_idx;
871 enum chip_type chip;
872 u32 eth_flags;
873
874 int msg_enable;
875 __be16 vxlan_port;
876 u8 vxlan_port_cnt;
877 __be16 geneve_port;
878 u8 geneve_port_cnt;
879
880 struct adapter_params params;
881 struct cxgb4_virt_res vres;
882 unsigned int swintr;
883
884 struct {
885 unsigned short vec;
886 char desc[IFNAMSIZ + 10];
887 } msix_info[MAX_INGQ + 1];
888 struct uld_msix_info *msix_info_ulds;
889 struct uld_msix_bmap msix_bmap_ulds;
890 int msi_idx;
891
892 struct doorbell_stats db_stats;
893 struct sge sge;
894
895 struct net_device *port[MAX_NPORTS];
896 u8 chan_map[NCHAN];
897
898 struct vf_info *vfinfo;
899 u8 num_vfs;
900
901 u32 filter_mode;
902 unsigned int l2t_start;
903 unsigned int l2t_end;
904 struct l2t_data *l2t;
905 unsigned int clipt_start;
906 unsigned int clipt_end;
907 struct clip_tbl *clipt;
908 unsigned int rawf_start;
909 unsigned int rawf_cnt;
910 struct smt_data *smt;
911 struct mps_encap_entry *mps_encap;
912 struct cxgb4_uld_info *uld;
913 void *uld_handle[CXGB4_ULD_MAX];
914 unsigned int num_uld;
915 unsigned int num_ofld_uld;
916 struct list_head list_node;
917 struct list_head rcu_node;
918 struct list_head mac_hlist;
919
920 void *iscsi_ppm;
921
922 struct tid_info tids;
923 void **tid_release_head;
924 spinlock_t tid_release_lock;
925 struct workqueue_struct *workq;
926 struct work_struct tid_release_task;
927 struct work_struct db_full_task;
928 struct work_struct db_drop_task;
929 struct work_struct fatal_err_notify_task;
930 bool tid_release_task_busy;
931
932
933 spinlock_t mbox_lock;
934 struct mbox_list mlist;
935
936
937#define T4_OS_LOG_MBOX_CMDS 256
938 struct mbox_cmd_log *mbox_log;
939
940 struct mutex uld_mutex;
941
942 struct dentry *debugfs_root;
943 u32 use_bd;
944 u32 trace_rss;
945
946
947
948
949 struct ptp_clock *ptp_clock;
950 struct ptp_clock_info ptp_clock_info;
951 struct sk_buff *ptp_tx_skb;
952
953 spinlock_t ptp_lock;
954 spinlock_t stats_lock;
955 spinlock_t win0_lock ____cacheline_aligned_in_smp;
956
957
958 struct cxgb4_tc_u32_table *tc_u32;
959 struct chcr_stats_debug chcr_stats;
960
961
962 DECLARE_HASHTABLE(flower_anymatch_tbl, 9);
963 struct timer_list flower_stats_timer;
964
965
966 struct ethtool_dump eth_dump;
967
968
969 struct hma_data hma;
970
971 struct srq_data *srq;
972};
973
974
975
976
977struct ch_sched_params {
978 s8 type;
979 union {
980 struct {
981 s8 level;
982 s8 mode;
983 s8 rateunit;
984 s8 ratemode;
985 s8 channel;
986 s8 class;
987 s32 minrate;
988 s32 maxrate;
989 s16 weight;
990 s16 pktsize;
991 } params;
992 } u;
993};
994
995enum {
996 SCHED_CLASS_TYPE_PACKET = 0,
997};
998
999enum {
1000 SCHED_CLASS_LEVEL_CL_RL = 0,
1001};
1002
1003enum {
1004 SCHED_CLASS_MODE_CLASS = 0,
1005};
1006
1007enum {
1008 SCHED_CLASS_RATEUNIT_BITS = 0,
1009};
1010
1011enum {
1012 SCHED_CLASS_RATEMODE_ABS = 1,
1013};
1014
1015struct tx_sw_desc {
1016 struct sk_buff *skb;
1017 struct ulptx_sgl *sgl;
1018};
1019
1020
1021
1022
1023struct ch_sched_queue {
1024 s8 queue;
1025 s8 class;
1026};
1027
1028
1029
1030#define ETHTYPE_BITWIDTH 16
1031#define FRAG_BITWIDTH 1
1032#define MACIDX_BITWIDTH 9
1033#define FCOE_BITWIDTH 1
1034#define IPORT_BITWIDTH 3
1035#define MATCHTYPE_BITWIDTH 3
1036#define PROTO_BITWIDTH 8
1037#define TOS_BITWIDTH 8
1038#define PF_BITWIDTH 8
1039#define VF_BITWIDTH 8
1040#define IVLAN_BITWIDTH 16
1041#define OVLAN_BITWIDTH 16
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060struct ch_filter_tuple {
1061
1062
1063
1064
1065
1066
1067 uint32_t ethtype:ETHTYPE_BITWIDTH;
1068 uint32_t frag:FRAG_BITWIDTH;
1069 uint32_t ivlan_vld:1;
1070 uint32_t ovlan_vld:1;
1071 uint32_t pfvf_vld:1;
1072 uint32_t macidx:MACIDX_BITWIDTH;
1073 uint32_t fcoe:FCOE_BITWIDTH;
1074 uint32_t iport:IPORT_BITWIDTH;
1075 uint32_t matchtype:MATCHTYPE_BITWIDTH;
1076 uint32_t proto:PROTO_BITWIDTH;
1077 uint32_t tos:TOS_BITWIDTH;
1078 uint32_t pf:PF_BITWIDTH;
1079 uint32_t vf:VF_BITWIDTH;
1080 uint32_t ivlan:IVLAN_BITWIDTH;
1081 uint32_t ovlan:OVLAN_BITWIDTH;
1082
1083
1084
1085
1086 uint8_t lip[16];
1087 uint8_t fip[16];
1088 uint16_t lport;
1089 uint16_t fport;
1090};
1091
1092
1093
1094struct ch_filter_specification {
1095
1096
1097 uint32_t hitcnts:1;
1098 uint32_t prio:1;
1099
1100
1101
1102
1103 uint32_t type:1;
1104 u32 hash:1;
1105
1106
1107
1108
1109
1110 uint32_t action:2;
1111
1112 uint32_t rpttid:1;
1113
1114 uint32_t dirsteer:1;
1115 uint32_t iq:10;
1116
1117 uint32_t maskhash:1;
1118 uint32_t dirsteerhash:1;
1119
1120
1121
1122
1123
1124
1125 uint32_t eport:2;
1126 uint32_t newdmac:1;
1127 uint32_t newsmac:1;
1128 uint32_t newvlan:2;
1129 uint32_t nat_mode:3;
1130 uint8_t dmac[ETH_ALEN];
1131 uint8_t smac[ETH_ALEN];
1132 uint16_t vlan;
1133
1134 u8 nat_lip[16];
1135 u8 nat_fip[16];
1136 u16 nat_lport;
1137 u16 nat_fport;
1138
1139
1140 u8 rsvd[24];
1141
1142
1143
1144 struct ch_filter_tuple val;
1145 struct ch_filter_tuple mask;
1146};
1147
1148enum {
1149 FILTER_PASS = 0,
1150 FILTER_DROP,
1151 FILTER_SWITCH
1152};
1153
1154enum {
1155 VLAN_NOCHANGE = 0,
1156 VLAN_REMOVE,
1157 VLAN_INSERT,
1158 VLAN_REWRITE
1159};
1160
1161enum {
1162 NAT_MODE_NONE = 0,
1163 NAT_MODE_DIP,
1164 NAT_MODE_DIP_DP,
1165 NAT_MODE_DIP_DP_SIP,
1166 NAT_MODE_DIP_DP_SP,
1167 NAT_MODE_SIP_SP,
1168 NAT_MODE_DIP_SIP_SP,
1169 NAT_MODE_ALL
1170};
1171
1172
1173
1174
1175
1176
1177
1178struct filter_entry {
1179
1180 u32 valid:1;
1181 u32 locked:1;
1182
1183 u32 pending:1;
1184 struct filter_ctx *ctx;
1185 struct l2t_entry *l2t;
1186 struct smt_entry *smt;
1187 struct net_device *dev;
1188 u32 tid;
1189
1190
1191
1192
1193
1194
1195 struct ch_filter_specification fs;
1196};
1197
1198static inline int is_offload(const struct adapter *adap)
1199{
1200 return adap->params.offload;
1201}
1202
1203static inline int is_hashfilter(const struct adapter *adap)
1204{
1205 return adap->params.hash_filter;
1206}
1207
1208static inline int is_pci_uld(const struct adapter *adap)
1209{
1210 return adap->params.crypto;
1211}
1212
1213static inline int is_uld(const struct adapter *adap)
1214{
1215 return (adap->params.offload || adap->params.crypto);
1216}
1217
1218static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1219{
1220 return readl(adap->regs + reg_addr);
1221}
1222
1223static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1224{
1225 writel(val, adap->regs + reg_addr);
1226}
1227
1228#ifndef readq
1229static inline u64 readq(const volatile void __iomem *addr)
1230{
1231 return readl(addr) + ((u64)readl(addr + 4) << 32);
1232}
1233
1234static inline void writeq(u64 val, volatile void __iomem *addr)
1235{
1236 writel(val, addr);
1237 writel(val >> 32, addr + 4);
1238}
1239#endif
1240
1241static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1242{
1243 return readq(adap->regs + reg_addr);
1244}
1245
1246static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1247{
1248 writeq(val, adap->regs + reg_addr);
1249}
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1261 u8 hw_addr[])
1262{
1263 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1264 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1265}
1266
1267
1268
1269
1270
1271
1272
1273static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1274{
1275 return netdev_priv(dev);
1276}
1277
1278
1279
1280
1281
1282
1283
1284
1285static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1286{
1287 return netdev_priv(adap->port[idx]);
1288}
1289
1290
1291
1292
1293
1294
1295
1296static inline struct adapter *netdev2adap(const struct net_device *dev)
1297{
1298 return netdev2pinfo(dev)->adapter;
1299}
1300
1301
1302
1303
1304
1305
1306static inline unsigned int mk_adap_vers(struct adapter *ap)
1307{
1308 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1309 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1310}
1311
1312
1313static inline unsigned int qtimer_val(const struct adapter *adap,
1314 const struct sge_rspq *q)
1315{
1316 unsigned int idx = q->intr_params >> 1;
1317
1318 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1319}
1320
1321
1322extern char cxgb4_driver_name[];
1323extern const char cxgb4_driver_version[];
1324
1325void t4_os_portmod_changed(struct adapter *adap, int port_id);
1326void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1327
1328void t4_free_sge_resources(struct adapter *adap);
1329void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1330irq_handler_t t4_intr_handler(struct adapter *adap);
1331netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev);
1332int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1333 const struct pkt_gl *gl);
1334int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1335int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1336int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1337 struct net_device *dev, int intr_idx,
1338 struct sge_fl *fl, rspq_handler_t hnd,
1339 rspq_flush_handler_t flush_handler, int cong);
1340int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1341 struct net_device *dev, struct netdev_queue *netdevq,
1342 unsigned int iqid);
1343int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1344 struct net_device *dev, unsigned int iqid,
1345 unsigned int cmplqid);
1346int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
1347 unsigned int cmplqid);
1348int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
1349 struct net_device *dev, unsigned int iqid,
1350 unsigned int uld_type);
1351irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1352int t4_sge_init(struct adapter *adap);
1353void t4_sge_start(struct adapter *adap);
1354void t4_sge_stop(struct adapter *adap);
1355void cxgb4_set_ethtool_ops(struct net_device *netdev);
1356int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1357enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb);
1358extern int dbfifo_int_thresh;
1359
1360#define for_each_port(adapter, iter) \
1361 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1362
1363static inline int is_bypass(struct adapter *adap)
1364{
1365 return adap->params.bypass;
1366}
1367
1368static inline int is_bypass_device(int device)
1369{
1370
1371 switch (device) {
1372 case 0x440b:
1373 case 0x440c:
1374 return 1;
1375 default:
1376 return 0;
1377 }
1378}
1379
1380static inline int is_10gbt_device(int device)
1381{
1382
1383 switch (device) {
1384 case 0x4409:
1385 case 0x4486:
1386 return 1;
1387
1388 default:
1389 return 0;
1390 }
1391}
1392
1393static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1394{
1395 return adap->params.vpd.cclk / 1000;
1396}
1397
1398static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1399 unsigned int us)
1400{
1401 return (us * adap->params.vpd.cclk) / 1000;
1402}
1403
1404static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1405 unsigned int ticks)
1406{
1407
1408 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1409 adapter->params.vpd.cclk);
1410}
1411
1412static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
1413 unsigned int ticks)
1414{
1415 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
1416}
1417
1418void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1419 u32 val);
1420
1421int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1422 int size, void *rpl, bool sleep_ok, int timeout);
1423int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1424 void *rpl, bool sleep_ok);
1425
1426static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1427 const void *cmd, int size, void *rpl,
1428 int timeout)
1429{
1430 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1431 timeout);
1432}
1433
1434static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1435 int size, void *rpl)
1436{
1437 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1438}
1439
1440static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1441 int size, void *rpl)
1442{
1443 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1444}
1445
1446
1447
1448
1449
1450
1451
1452
1453static inline int hash_mac_addr(const u8 *addr)
1454{
1455 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1456 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1457
1458 a ^= b;
1459 a ^= (a >> 12);
1460 a ^= (a >> 6);
1461 return a & 0x3f;
1462}
1463
1464int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1465 unsigned int cnt);
1466static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1467 unsigned int us, unsigned int cnt,
1468 unsigned int size, unsigned int iqe_size)
1469{
1470 q->adap = adap;
1471 cxgb4_set_rspq_intr_params(q, us, cnt);
1472 q->iqe_len = iqe_size;
1473 q->size = size;
1474}
1475
1476
1477
1478
1479
1480
1481
1482
1483static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type)
1484{
1485 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE &&
1486 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED &&
1487 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN &&
1488 fw_mod_type != FW_PORT_MOD_TYPE_ERROR);
1489}
1490
1491void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1492 unsigned int data_reg, const u32 *vals,
1493 unsigned int nregs, unsigned int start_idx);
1494void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1495 unsigned int data_reg, u32 *vals, unsigned int nregs,
1496 unsigned int start_idx);
1497void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1498
1499struct fw_filter_wr;
1500
1501void t4_intr_enable(struct adapter *adapter);
1502void t4_intr_disable(struct adapter *adapter);
1503int t4_slow_intr_handler(struct adapter *adapter);
1504
1505int t4_wait_dev_ready(void __iomem *regs);
1506
1507int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox,
1508 unsigned int port, struct link_config *lc,
1509 bool sleep_ok, int timeout);
1510
1511static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
1512 unsigned int port, struct link_config *lc)
1513{
1514 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1515 true, FW_CMD_MAX_TIMEOUT);
1516}
1517
1518static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox,
1519 unsigned int port, struct link_config *lc)
1520{
1521 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1522 false, FW_CMD_MAX_TIMEOUT);
1523}
1524
1525int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1526
1527u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1528u32 t4_get_util_window(struct adapter *adap);
1529void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1530
1531int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
1532 u32 *mem_base, u32 *mem_aperture);
1533void t4_memory_update_win(struct adapter *adap, int win, u32 addr);
1534void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
1535 int dir);
1536#define T4_MEMORY_WRITE 0
1537#define T4_MEMORY_READ 1
1538int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1539 void *buf, int dir);
1540static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1541 u32 len, __be32 *buf)
1542{
1543 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1544}
1545
1546unsigned int t4_get_regs_len(struct adapter *adapter);
1547void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1548
1549int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
1550int t4_seeprom_wp(struct adapter *adapter, bool enable);
1551int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1552int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1553int t4_read_flash(struct adapter *adapter, unsigned int addr,
1554 unsigned int nwords, u32 *data, int byte_oriented);
1555int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1556int t4_load_phy_fw(struct adapter *adap,
1557 int win, spinlock_t *lock,
1558 int (*phy_fw_version)(const u8 *, size_t),
1559 const u8 *phy_fw_data, size_t phy_fw_size);
1560int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1561int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1562int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1563 const u8 *fw_data, unsigned int size, int force);
1564int t4_fl_pkt_align(struct adapter *adap);
1565unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1566int t4_check_fw_version(struct adapter *adap);
1567int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
1568int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1569int t4_get_bs_version(struct adapter *adapter, u32 *vers);
1570int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1571int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1572int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
1573int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
1574int t4_get_version_info(struct adapter *adapter);
1575void t4_dump_version_info(struct adapter *adapter);
1576int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1577 const u8 *fw_data, unsigned int fw_size,
1578 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1579int t4_prep_adapter(struct adapter *adapter);
1580int t4_shutdown_adapter(struct adapter *adapter);
1581
1582enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1583int t4_bar2_sge_qregs(struct adapter *adapter,
1584 unsigned int qid,
1585 enum t4_bar2_qtype qtype,
1586 int user,
1587 u64 *pbar2_qoffset,
1588 unsigned int *pbar2_qid);
1589
1590unsigned int qtimer_val(const struct adapter *adap,
1591 const struct sge_rspq *q);
1592
1593int t4_init_devlog_params(struct adapter *adapter);
1594int t4_init_sge_params(struct adapter *adapter);
1595int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
1596int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1597int t4_init_rss_mode(struct adapter *adap, int mbox);
1598int t4_init_portinfo(struct port_info *pi, int mbox,
1599 int port, int pf, int vf, u8 mac[]);
1600int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1601void t4_fatal_err(struct adapter *adapter);
1602unsigned int t4_chip_rss_size(struct adapter *adapter);
1603int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1604 int start, int n, const u16 *rspq, unsigned int nrspq);
1605int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1606 unsigned int flags);
1607int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1608 unsigned int flags, unsigned int defq);
1609int t4_read_rss(struct adapter *adapter, u16 *entries);
1610void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
1611void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
1612 bool sleep_ok);
1613void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1614 u32 *valp, bool sleep_ok);
1615void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1616 u32 *vfl, u32 *vfh, bool sleep_ok);
1617u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
1618u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
1619
1620unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
1621unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
1622void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1623void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1624int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1625 size_t n);
1626int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1627 size_t n);
1628int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1629 unsigned int *valp);
1630int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1631 const unsigned int *valp);
1632int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1633void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1634 unsigned int *pif_req_wrptr,
1635 unsigned int *pif_rsp_wrptr);
1636void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1637void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1638const char *t4_get_port_type_description(enum fw_port_type port_type);
1639void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1640void t4_get_port_stats_offset(struct adapter *adap, int idx,
1641 struct port_stats *stats,
1642 struct port_stats *offset);
1643void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1644void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1645void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1646void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1647 unsigned int mask, unsigned int val);
1648void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1649void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
1650 bool sleep_ok);
1651void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
1652 bool sleep_ok);
1653void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
1654 bool sleep_ok);
1655void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
1656 bool sleep_ok);
1657void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1658 struct tp_tcp_stats *v6, bool sleep_ok);
1659void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1660 struct tp_fcoe_stats *st, bool sleep_ok);
1661void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1662 const unsigned short *alpha, const unsigned short *beta);
1663
1664void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1665
1666void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1667void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1668
1669void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1670 const u8 *addr);
1671int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1672 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1673
1674int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1675 enum dev_master master, enum dev_state *state);
1676int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1677int t4_early_init(struct adapter *adap, unsigned int mbox);
1678int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1679int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1680 unsigned int cache_line_size);
1681int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1682int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1683 unsigned int vf, unsigned int nparams, const u32 *params,
1684 u32 *val);
1685int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
1686 unsigned int vf, unsigned int nparams, const u32 *params,
1687 u32 *val);
1688int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1689 unsigned int vf, unsigned int nparams, const u32 *params,
1690 u32 *val, int rw, bool sleep_ok);
1691int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1692 unsigned int pf, unsigned int vf,
1693 unsigned int nparams, const u32 *params,
1694 const u32 *val, int timeout);
1695int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1696 unsigned int vf, unsigned int nparams, const u32 *params,
1697 const u32 *val);
1698int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1699 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1700 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1701 unsigned int vi, unsigned int cmask, unsigned int pmask,
1702 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1703int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1704 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1705 unsigned int *rss_size);
1706int t4_free_vi(struct adapter *adap, unsigned int mbox,
1707 unsigned int pf, unsigned int vf,
1708 unsigned int viid);
1709int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1710 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1711 bool sleep_ok);
1712int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
1713 const u8 *addr, const u8 *mask, unsigned int idx,
1714 u8 lookup_type, u8 port_id, bool sleep_ok);
1715int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
1716 const u8 *addr, const u8 *mask, unsigned int idx,
1717 u8 lookup_type, u8 port_id, bool sleep_ok);
1718int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1719 unsigned int viid, bool free, unsigned int naddr,
1720 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1721int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
1722 unsigned int viid, unsigned int naddr,
1723 const u8 **addr, bool sleep_ok);
1724int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1725 int idx, const u8 *addr, bool persist, bool add_smt);
1726int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1727 bool ucast, u64 vec, bool sleep_ok);
1728int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1729 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1730int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
1731 struct port_info *pi,
1732 bool rx_en, bool tx_en, bool dcb_en);
1733int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1734 bool rx_en, bool tx_en);
1735int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1736 unsigned int nblinks);
1737int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1738 unsigned int mmd, unsigned int reg, u16 *valp);
1739int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1740 unsigned int mmd, unsigned int reg, u16 val);
1741int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
1742 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1743 unsigned int fl0id, unsigned int fl1id);
1744int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1745 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1746 unsigned int fl0id, unsigned int fl1id);
1747int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1748 unsigned int vf, unsigned int eqid);
1749int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1750 unsigned int vf, unsigned int eqid);
1751int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1752 unsigned int vf, unsigned int eqid);
1753int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type);
1754void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
1755int t4_update_port_info(struct port_info *pi);
1756int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
1757 unsigned int *speedp, unsigned int *mtup);
1758int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1759void t4_db_full(struct adapter *adapter);
1760void t4_db_dropped(struct adapter *adapter);
1761int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1762 int filter_index, int enable);
1763void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1764 int filter_index, int *enabled);
1765int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1766 u32 addr, u32 val);
1767void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
1768void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
1769 unsigned int *kbps, unsigned int *ipg, bool sleep_ok);
1770int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
1771 enum ctxt_type ctype, u32 *data);
1772int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
1773 enum ctxt_type ctype, u32 *data);
1774int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
1775 int rateunit, int ratemode, int channel, int class,
1776 int minrate, int maxrate, int weight, int pktsize);
1777void t4_sge_decode_idma_state(struct adapter *adapter, int state);
1778void t4_idma_monitor_init(struct adapter *adapter,
1779 struct sge_idma_monitor_state *idma);
1780void t4_idma_monitor(struct adapter *adapter,
1781 struct sge_idma_monitor_state *idma,
1782 int hz, int ticks);
1783int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
1784 unsigned int naddr, u8 *addr);
1785void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1786 u32 start_index, bool sleep_ok);
1787void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1788 u32 start_index, bool sleep_ok);
1789void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
1790 u32 start_index, bool sleep_ok);
1791
1792void t4_uld_mem_free(struct adapter *adap);
1793int t4_uld_mem_alloc(struct adapter *adap);
1794void t4_uld_clean_up(struct adapter *adap);
1795void t4_register_netevent_notifier(void);
1796int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
1797 unsigned int devid, unsigned int offset,
1798 unsigned int len, u8 *buf);
1799void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
1800void free_tx_desc(struct adapter *adap, struct sge_txq *q,
1801 unsigned int n, bool unmap);
1802void free_txq(struct adapter *adap, struct sge_txq *q);
1803void cxgb4_reclaim_completed_tx(struct adapter *adap,
1804 struct sge_txq *q, bool unmap);
1805int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb,
1806 dma_addr_t *addr);
1807void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
1808 void *pos);
1809void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q,
1810 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
1811 const dma_addr_t *addr);
1812void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n);
1813int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
1814 u16 vlan);
1815#endif
1816