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34#include <linux/kernel.h>
35#include <linux/ethtool.h>
36#include <linux/netdevice.h>
37#include <linux/mlx4/driver.h>
38#include <linux/mlx4/device.h>
39#include <linux/in.h>
40#include <net/ip.h>
41#include <linux/bitmap.h>
42
43#include "mlx4_en.h"
44#include "en_port.h"
45
46#define EN_ETHTOOL_QP_ATTACH (1ull << 63)
47#define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff)
48#define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff)
49
50static int mlx4_en_moderation_update(struct mlx4_en_priv *priv)
51{
52 int i, t;
53 int err = 0;
54
55 for (t = 0 ; t < MLX4_EN_NUM_TX_TYPES; t++) {
56 for (i = 0; i < priv->tx_ring_num[t]; i++) {
57 priv->tx_cq[t][i]->moder_cnt = priv->tx_frames;
58 priv->tx_cq[t][i]->moder_time = priv->tx_usecs;
59 if (priv->port_up) {
60 err = mlx4_en_set_cq_moder(priv,
61 priv->tx_cq[t][i]);
62 if (err)
63 return err;
64 }
65 }
66 }
67
68 if (priv->adaptive_rx_coal)
69 return 0;
70
71 for (i = 0; i < priv->rx_ring_num; i++) {
72 priv->rx_cq[i]->moder_cnt = priv->rx_frames;
73 priv->rx_cq[i]->moder_time = priv->rx_usecs;
74 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
75 if (priv->port_up) {
76 err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]);
77 if (err)
78 return err;
79 }
80 }
81
82 return err;
83}
84
85static void
86mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
87{
88 struct mlx4_en_priv *priv = netdev_priv(dev);
89 struct mlx4_en_dev *mdev = priv->mdev;
90
91 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
92 strlcpy(drvinfo->version, DRV_VERSION,
93 sizeof(drvinfo->version));
94 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
95 "%d.%d.%d",
96 (u16) (mdev->dev->caps.fw_ver >> 32),
97 (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff),
98 (u16) (mdev->dev->caps.fw_ver & 0xffff));
99 strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev),
100 sizeof(drvinfo->bus_info));
101}
102
103static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = {
104 "blueflame",
105 "phv-bit"
106};
107
108static const char main_strings[][ETH_GSTRING_LEN] = {
109
110 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
111 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
112 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
113 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
114 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
115 "tx_heartbeat_errors", "tx_window_errors",
116
117
118 "tso_packets",
119 "xmit_more",
120 "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_pages",
121 "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload",
122
123
124 "pf_rx_packets",
125 "pf_rx_bytes",
126 "pf_tx_packets",
127 "pf_tx_bytes",
128
129
130 "rx_pause_prio_0", "rx_pause_duration_prio_0",
131 "rx_pause_transition_prio_0",
132 "rx_pause_prio_1", "rx_pause_duration_prio_1",
133 "rx_pause_transition_prio_1",
134 "rx_pause_prio_2", "rx_pause_duration_prio_2",
135 "rx_pause_transition_prio_2",
136 "rx_pause_prio_3", "rx_pause_duration_prio_3",
137 "rx_pause_transition_prio_3",
138 "rx_pause_prio_4", "rx_pause_duration_prio_4",
139 "rx_pause_transition_prio_4",
140 "rx_pause_prio_5", "rx_pause_duration_prio_5",
141 "rx_pause_transition_prio_5",
142 "rx_pause_prio_6", "rx_pause_duration_prio_6",
143 "rx_pause_transition_prio_6",
144 "rx_pause_prio_7", "rx_pause_duration_prio_7",
145 "rx_pause_transition_prio_7",
146
147
148 "rx_pause", "rx_pause_duration", "rx_pause_transition",
149
150
151 "tx_pause_prio_0", "tx_pause_duration_prio_0",
152 "tx_pause_transition_prio_0",
153 "tx_pause_prio_1", "tx_pause_duration_prio_1",
154 "tx_pause_transition_prio_1",
155 "tx_pause_prio_2", "tx_pause_duration_prio_2",
156 "tx_pause_transition_prio_2",
157 "tx_pause_prio_3", "tx_pause_duration_prio_3",
158 "tx_pause_transition_prio_3",
159 "tx_pause_prio_4", "tx_pause_duration_prio_4",
160 "tx_pause_transition_prio_4",
161 "tx_pause_prio_5", "tx_pause_duration_prio_5",
162 "tx_pause_transition_prio_5",
163 "tx_pause_prio_6", "tx_pause_duration_prio_6",
164 "tx_pause_transition_prio_6",
165 "tx_pause_prio_7", "tx_pause_duration_prio_7",
166 "tx_pause_transition_prio_7",
167
168
169 "tx_pause", "tx_pause_duration", "tx_pause_transition",
170
171
172 "rx_multicast_packets",
173 "rx_broadcast_packets",
174 "rx_jabbers",
175 "rx_in_range_length_error",
176 "rx_out_range_length_error",
177 "tx_multicast_packets",
178 "tx_broadcast_packets",
179 "rx_prio_0_packets", "rx_prio_0_bytes",
180 "rx_prio_1_packets", "rx_prio_1_bytes",
181 "rx_prio_2_packets", "rx_prio_2_bytes",
182 "rx_prio_3_packets", "rx_prio_3_bytes",
183 "rx_prio_4_packets", "rx_prio_4_bytes",
184 "rx_prio_5_packets", "rx_prio_5_bytes",
185 "rx_prio_6_packets", "rx_prio_6_bytes",
186 "rx_prio_7_packets", "rx_prio_7_bytes",
187 "rx_novlan_packets", "rx_novlan_bytes",
188 "tx_prio_0_packets", "tx_prio_0_bytes",
189 "tx_prio_1_packets", "tx_prio_1_bytes",
190 "tx_prio_2_packets", "tx_prio_2_bytes",
191 "tx_prio_3_packets", "tx_prio_3_bytes",
192 "tx_prio_4_packets", "tx_prio_4_bytes",
193 "tx_prio_5_packets", "tx_prio_5_bytes",
194 "tx_prio_6_packets", "tx_prio_6_bytes",
195 "tx_prio_7_packets", "tx_prio_7_bytes",
196 "tx_novlan_packets", "tx_novlan_bytes",
197
198
199 "rx_xdp_drop",
200 "rx_xdp_tx",
201 "rx_xdp_tx_full",
202};
203
204static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= {
205 "Interrupt Test",
206 "Link Test",
207 "Speed Test",
208 "Register Test",
209 "Loopback Test",
210};
211
212static u32 mlx4_en_get_msglevel(struct net_device *dev)
213{
214 return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable;
215}
216
217static void mlx4_en_set_msglevel(struct net_device *dev, u32 val)
218{
219 ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val;
220}
221
222static void mlx4_en_get_wol(struct net_device *netdev,
223 struct ethtool_wolinfo *wol)
224{
225 struct mlx4_en_priv *priv = netdev_priv(netdev);
226 struct mlx4_caps *caps = &priv->mdev->dev->caps;
227 int err = 0;
228 u64 config = 0;
229 u64 mask;
230
231 if ((priv->port < 1) || (priv->port > 2)) {
232 en_err(priv, "Failed to get WoL information\n");
233 return;
234 }
235
236 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
237 MLX4_DEV_CAP_FLAG_WOL_PORT2;
238
239 if (!(caps->flags & mask)) {
240 wol->supported = 0;
241 wol->wolopts = 0;
242 return;
243 }
244
245 if (caps->wol_port[priv->port])
246 wol->supported = WAKE_MAGIC;
247 else
248 wol->supported = 0;
249
250 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
251 if (err) {
252 en_err(priv, "Failed to get WoL information\n");
253 return;
254 }
255
256 if ((config & MLX4_EN_WOL_ENABLED) && (config & MLX4_EN_WOL_MAGIC))
257 wol->wolopts = WAKE_MAGIC;
258 else
259 wol->wolopts = 0;
260}
261
262static int mlx4_en_set_wol(struct net_device *netdev,
263 struct ethtool_wolinfo *wol)
264{
265 struct mlx4_en_priv *priv = netdev_priv(netdev);
266 u64 config = 0;
267 int err = 0;
268 u64 mask;
269
270 if ((priv->port < 1) || (priv->port > 2))
271 return -EOPNOTSUPP;
272
273 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
274 MLX4_DEV_CAP_FLAG_WOL_PORT2;
275
276 if (!(priv->mdev->dev->caps.flags & mask))
277 return -EOPNOTSUPP;
278
279 if (wol->supported & ~WAKE_MAGIC)
280 return -EINVAL;
281
282 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
283 if (err) {
284 en_err(priv, "Failed to get WoL info, unable to modify\n");
285 return err;
286 }
287
288 if (wol->wolopts & WAKE_MAGIC) {
289 config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED |
290 MLX4_EN_WOL_MAGIC;
291 } else {
292 config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC);
293 config |= MLX4_EN_WOL_DO_MODIFY;
294 }
295
296 err = mlx4_wol_write(priv->mdev->dev, config, priv->port);
297 if (err)
298 en_err(priv, "Failed to set WoL information\n");
299
300 return err;
301}
302
303struct bitmap_iterator {
304 unsigned long *stats_bitmap;
305 unsigned int count;
306 unsigned int iterator;
307 bool advance_array;
308};
309
310static inline void bitmap_iterator_init(struct bitmap_iterator *h,
311 unsigned long *stats_bitmap,
312 int count)
313{
314 h->iterator = 0;
315 h->advance_array = !bitmap_empty(stats_bitmap, count);
316 h->count = h->advance_array ? bitmap_weight(stats_bitmap, count)
317 : count;
318 h->stats_bitmap = stats_bitmap;
319}
320
321static inline int bitmap_iterator_test(struct bitmap_iterator *h)
322{
323 return !h->advance_array ? 1 : test_bit(h->iterator, h->stats_bitmap);
324}
325
326static inline int bitmap_iterator_inc(struct bitmap_iterator *h)
327{
328 return h->iterator++;
329}
330
331static inline unsigned int
332bitmap_iterator_count(struct bitmap_iterator *h)
333{
334 return h->count;
335}
336
337static int mlx4_en_get_sset_count(struct net_device *dev, int sset)
338{
339 struct mlx4_en_priv *priv = netdev_priv(dev);
340 struct bitmap_iterator it;
341
342 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
343
344 switch (sset) {
345 case ETH_SS_STATS:
346 return bitmap_iterator_count(&it) +
347 (priv->tx_ring_num[TX] * 2) +
348 (priv->rx_ring_num * (3 + NUM_XDP_STATS));
349 case ETH_SS_TEST:
350 return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags
351 & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2;
352 case ETH_SS_PRIV_FLAGS:
353 return ARRAY_SIZE(mlx4_en_priv_flags);
354 default:
355 return -EOPNOTSUPP;
356 }
357}
358
359static void mlx4_en_get_ethtool_stats(struct net_device *dev,
360 struct ethtool_stats *stats, uint64_t *data)
361{
362 struct mlx4_en_priv *priv = netdev_priv(dev);
363 int index = 0;
364 int i;
365 struct bitmap_iterator it;
366
367 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
368
369 spin_lock_bh(&priv->stats_lock);
370
371 mlx4_en_fold_software_stats(dev);
372
373 for (i = 0; i < NUM_MAIN_STATS; i++, bitmap_iterator_inc(&it))
374 if (bitmap_iterator_test(&it))
375 data[index++] = ((unsigned long *)&dev->stats)[i];
376
377 for (i = 0; i < NUM_PORT_STATS; i++, bitmap_iterator_inc(&it))
378 if (bitmap_iterator_test(&it))
379 data[index++] = ((unsigned long *)&priv->port_stats)[i];
380
381 for (i = 0; i < NUM_PF_STATS; i++, bitmap_iterator_inc(&it))
382 if (bitmap_iterator_test(&it))
383 data[index++] =
384 ((unsigned long *)&priv->pf_stats)[i];
385
386 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_RX;
387 i++, bitmap_iterator_inc(&it))
388 if (bitmap_iterator_test(&it))
389 data[index++] =
390 ((u64 *)&priv->rx_priority_flowstats)[i];
391
392 for (i = 0; i < NUM_FLOW_STATS_RX; i++, bitmap_iterator_inc(&it))
393 if (bitmap_iterator_test(&it))
394 data[index++] = ((u64 *)&priv->rx_flowstats)[i];
395
396 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_TX;
397 i++, bitmap_iterator_inc(&it))
398 if (bitmap_iterator_test(&it))
399 data[index++] =
400 ((u64 *)&priv->tx_priority_flowstats)[i];
401
402 for (i = 0; i < NUM_FLOW_STATS_TX; i++, bitmap_iterator_inc(&it))
403 if (bitmap_iterator_test(&it))
404 data[index++] = ((u64 *)&priv->tx_flowstats)[i];
405
406 for (i = 0; i < NUM_PKT_STATS; i++, bitmap_iterator_inc(&it))
407 if (bitmap_iterator_test(&it))
408 data[index++] = ((unsigned long *)&priv->pkstats)[i];
409
410 for (i = 0; i < NUM_XDP_STATS; i++, bitmap_iterator_inc(&it))
411 if (bitmap_iterator_test(&it))
412 data[index++] = ((unsigned long *)&priv->xdp_stats)[i];
413
414 for (i = 0; i < priv->tx_ring_num[TX]; i++) {
415 data[index++] = priv->tx_ring[TX][i]->packets;
416 data[index++] = priv->tx_ring[TX][i]->bytes;
417 }
418 for (i = 0; i < priv->rx_ring_num; i++) {
419 data[index++] = priv->rx_ring[i]->packets;
420 data[index++] = priv->rx_ring[i]->bytes;
421 data[index++] = priv->rx_ring[i]->dropped;
422 data[index++] = priv->rx_ring[i]->xdp_drop;
423 data[index++] = priv->rx_ring[i]->xdp_tx;
424 data[index++] = priv->rx_ring[i]->xdp_tx_full;
425 }
426 spin_unlock_bh(&priv->stats_lock);
427
428}
429
430static void mlx4_en_self_test(struct net_device *dev,
431 struct ethtool_test *etest, u64 *buf)
432{
433 mlx4_en_ex_selftest(dev, &etest->flags, buf);
434}
435
436static void mlx4_en_get_strings(struct net_device *dev,
437 uint32_t stringset, uint8_t *data)
438{
439 struct mlx4_en_priv *priv = netdev_priv(dev);
440 int index = 0;
441 int i, strings = 0;
442 struct bitmap_iterator it;
443
444 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
445
446 switch (stringset) {
447 case ETH_SS_TEST:
448 for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++)
449 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
450 if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK)
451 for (; i < MLX4_EN_NUM_SELF_TEST; i++)
452 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
453 break;
454
455 case ETH_SS_STATS:
456
457 for (i = 0; i < NUM_MAIN_STATS; i++, strings++,
458 bitmap_iterator_inc(&it))
459 if (bitmap_iterator_test(&it))
460 strcpy(data + (index++) * ETH_GSTRING_LEN,
461 main_strings[strings]);
462
463 for (i = 0; i < NUM_PORT_STATS; i++, strings++,
464 bitmap_iterator_inc(&it))
465 if (bitmap_iterator_test(&it))
466 strcpy(data + (index++) * ETH_GSTRING_LEN,
467 main_strings[strings]);
468
469 for (i = 0; i < NUM_PF_STATS; i++, strings++,
470 bitmap_iterator_inc(&it))
471 if (bitmap_iterator_test(&it))
472 strcpy(data + (index++) * ETH_GSTRING_LEN,
473 main_strings[strings]);
474
475 for (i = 0; i < NUM_FLOW_STATS; i++, strings++,
476 bitmap_iterator_inc(&it))
477 if (bitmap_iterator_test(&it))
478 strcpy(data + (index++) * ETH_GSTRING_LEN,
479 main_strings[strings]);
480
481 for (i = 0; i < NUM_PKT_STATS; i++, strings++,
482 bitmap_iterator_inc(&it))
483 if (bitmap_iterator_test(&it))
484 strcpy(data + (index++) * ETH_GSTRING_LEN,
485 main_strings[strings]);
486
487 for (i = 0; i < NUM_XDP_STATS; i++, strings++,
488 bitmap_iterator_inc(&it))
489 if (bitmap_iterator_test(&it))
490 strcpy(data + (index++) * ETH_GSTRING_LEN,
491 main_strings[strings]);
492
493 for (i = 0; i < priv->tx_ring_num[TX]; i++) {
494 sprintf(data + (index++) * ETH_GSTRING_LEN,
495 "tx%d_packets", i);
496 sprintf(data + (index++) * ETH_GSTRING_LEN,
497 "tx%d_bytes", i);
498 }
499 for (i = 0; i < priv->rx_ring_num; i++) {
500 sprintf(data + (index++) * ETH_GSTRING_LEN,
501 "rx%d_packets", i);
502 sprintf(data + (index++) * ETH_GSTRING_LEN,
503 "rx%d_bytes", i);
504 sprintf(data + (index++) * ETH_GSTRING_LEN,
505 "rx%d_dropped", i);
506 sprintf(data + (index++) * ETH_GSTRING_LEN,
507 "rx%d_xdp_drop", i);
508 sprintf(data + (index++) * ETH_GSTRING_LEN,
509 "rx%d_xdp_tx", i);
510 sprintf(data + (index++) * ETH_GSTRING_LEN,
511 "rx%d_xdp_tx_full", i);
512 }
513 break;
514 case ETH_SS_PRIV_FLAGS:
515 for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++)
516 strcpy(data + i * ETH_GSTRING_LEN,
517 mlx4_en_priv_flags[i]);
518 break;
519
520 }
521}
522
523static u32 mlx4_en_autoneg_get(struct net_device *dev)
524{
525 struct mlx4_en_priv *priv = netdev_priv(dev);
526 struct mlx4_en_dev *mdev = priv->mdev;
527 u32 autoneg = AUTONEG_DISABLE;
528
529 if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) &&
530 (priv->port_state.flags & MLX4_EN_PORT_ANE))
531 autoneg = AUTONEG_ENABLE;
532
533 return autoneg;
534}
535
536static void ptys2ethtool_update_supported_port(unsigned long *mask,
537 struct mlx4_ptys_reg *ptys_reg)
538{
539 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
540
541 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
542 | MLX4_PROT_MASK(MLX4_1000BASE_T)
543 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
544 __set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask);
545 } else if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
546 | MLX4_PROT_MASK(MLX4_10GBASE_SR)
547 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
548 | MLX4_PROT_MASK(MLX4_40GBASE_CR4)
549 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
550 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
551 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mask);
552 } else if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
553 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
554 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
555 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
556 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
557 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
558 __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mask);
559 }
560}
561
562static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg)
563{
564 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper);
565
566 if (!eth_proto)
567 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
568
569 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
570 | MLX4_PROT_MASK(MLX4_1000BASE_T)
571 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
572 return PORT_TP;
573 }
574
575 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR)
576 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
577 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
578 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
579 return PORT_FIBRE;
580 }
581
582 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
583 | MLX4_PROT_MASK(MLX4_56GBASE_CR4)
584 | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) {
585 return PORT_DA;
586 }
587
588 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
589 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
590 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
591 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
592 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
593 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
594 return PORT_NONE;
595 }
596 return PORT_OTHER;
597}
598
599#define MLX4_LINK_MODES_SZ \
600 (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8)
601
602enum ethtool_report {
603 SUPPORTED = 0,
604 ADVERTISED = 1,
605};
606
607struct ptys2ethtool_config {
608 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
609 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
610 u32 speed;
611};
612
613static unsigned long *ptys2ethtool_link_mode(struct ptys2ethtool_config *cfg,
614 enum ethtool_report report)
615{
616 switch (report) {
617 case SUPPORTED:
618 return cfg->supported;
619 case ADVERTISED:
620 return cfg->advertised;
621 }
622 return NULL;
623}
624
625#define MLX4_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
626 ({ \
627 struct ptys2ethtool_config *cfg; \
628 const unsigned int modes[] = { __VA_ARGS__ }; \
629 unsigned int i; \
630 cfg = &ptys2ethtool_map[reg_]; \
631 cfg->speed = speed_; \
632 bitmap_zero(cfg->supported, \
633 __ETHTOOL_LINK_MODE_MASK_NBITS); \
634 bitmap_zero(cfg->advertised, \
635 __ETHTOOL_LINK_MODE_MASK_NBITS); \
636 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
637 __set_bit(modes[i], cfg->supported); \
638 __set_bit(modes[i], cfg->advertised); \
639 } \
640 })
641
642
643static struct ptys2ethtool_config ptys2ethtool_map[MLX4_LINK_MODES_SZ];
644
645void __init mlx4_en_init_ptys2ethtool_map(void)
646{
647 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_100BASE_TX, SPEED_100,
648 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
649 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_T, SPEED_1000,
650 ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
651 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_CX_SGMII, SPEED_1000,
652 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
653 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_KX, SPEED_1000,
654 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
655 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_T, SPEED_10000,
656 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
657 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CX4, SPEED_10000,
658 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
659 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KX4, SPEED_10000,
660 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
661 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KR, SPEED_10000,
662 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
663 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CR, SPEED_10000,
664 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
665 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_SR, SPEED_10000,
666 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
667 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_20GBASE_KR2, SPEED_20000,
668 ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT,
669 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
670 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_CR4, SPEED_40000,
671 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
672 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_KR4, SPEED_40000,
673 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
674 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_SR4, SPEED_40000,
675 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
676 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_KR4, SPEED_56000,
677 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
678 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_CR4, SPEED_56000,
679 ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT);
680 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_SR4, SPEED_56000,
681 ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT);
682};
683
684static void ptys2ethtool_update_link_modes(unsigned long *link_modes,
685 u32 eth_proto,
686 enum ethtool_report report)
687{
688 int i;
689 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
690 if (eth_proto & MLX4_PROT_MASK(i))
691 bitmap_or(link_modes, link_modes,
692 ptys2ethtool_link_mode(&ptys2ethtool_map[i],
693 report),
694 __ETHTOOL_LINK_MODE_MASK_NBITS);
695 }
696}
697
698static u32 ethtool2ptys_link_modes(const unsigned long *link_modes,
699 enum ethtool_report report)
700{
701 int i;
702 u32 ptys_modes = 0;
703
704 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
705 if (bitmap_intersects(
706 ptys2ethtool_link_mode(&ptys2ethtool_map[i],
707 report),
708 link_modes,
709 __ETHTOOL_LINK_MODE_MASK_NBITS))
710 ptys_modes |= 1 << i;
711 }
712 return ptys_modes;
713}
714
715
716static u32 speed2ptys_link_modes(u32 speed)
717{
718 int i;
719 u32 ptys_modes = 0;
720
721 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
722 if (ptys2ethtool_map[i].speed == speed)
723 ptys_modes |= 1 << i;
724 }
725 return ptys_modes;
726}
727
728static int
729ethtool_get_ptys_link_ksettings(struct net_device *dev,
730 struct ethtool_link_ksettings *link_ksettings)
731{
732 struct mlx4_en_priv *priv = netdev_priv(dev);
733 struct mlx4_ptys_reg ptys_reg;
734 u32 eth_proto;
735 int ret;
736
737 memset(&ptys_reg, 0, sizeof(ptys_reg));
738 ptys_reg.local_port = priv->port;
739 ptys_reg.proto_mask = MLX4_PTYS_EN;
740 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
741 MLX4_ACCESS_REG_QUERY, &ptys_reg);
742 if (ret) {
743 en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)",
744 ret);
745 return ret;
746 }
747 en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n",
748 ptys_reg.proto_mask);
749 en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n",
750 be32_to_cpu(ptys_reg.eth_proto_cap));
751 en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n",
752 be32_to_cpu(ptys_reg.eth_proto_admin));
753 en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n",
754 be32_to_cpu(ptys_reg.eth_proto_oper));
755 en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n",
756 be32_to_cpu(ptys_reg.eth_proto_lp_adv));
757
758
759 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
760 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
761
762 ptys2ethtool_update_supported_port(link_ksettings->link_modes.supported,
763 &ptys_reg);
764
765 eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap);
766 ptys2ethtool_update_link_modes(link_ksettings->link_modes.supported,
767 eth_proto, SUPPORTED);
768
769 eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin);
770 ptys2ethtool_update_link_modes(link_ksettings->link_modes.advertising,
771 eth_proto, ADVERTISED);
772
773 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
774 Pause);
775 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
776 Asym_Pause);
777
778 if (priv->prof->tx_pause)
779 ethtool_link_ksettings_add_link_mode(link_ksettings,
780 advertising, Pause);
781 if (priv->prof->tx_pause ^ priv->prof->rx_pause)
782 ethtool_link_ksettings_add_link_mode(link_ksettings,
783 advertising, Asym_Pause);
784
785 link_ksettings->base.port = ptys_get_active_port(&ptys_reg);
786
787 if (mlx4_en_autoneg_get(dev)) {
788 ethtool_link_ksettings_add_link_mode(link_ksettings,
789 supported, Autoneg);
790 ethtool_link_ksettings_add_link_mode(link_ksettings,
791 advertising, Autoneg);
792 }
793
794 link_ksettings->base.autoneg
795 = (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
796 AUTONEG_ENABLE : AUTONEG_DISABLE;
797
798 eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv);
799
800 ethtool_link_ksettings_zero_link_mode(link_ksettings, lp_advertising);
801 ptys2ethtool_update_link_modes(
802 link_ksettings->link_modes.lp_advertising,
803 eth_proto, ADVERTISED);
804 if (priv->port_state.flags & MLX4_EN_PORT_ANC)
805 ethtool_link_ksettings_add_link_mode(link_ksettings,
806 lp_advertising, Autoneg);
807
808 link_ksettings->base.phy_address = 0;
809 link_ksettings->base.mdio_support = 0;
810 link_ksettings->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
811 link_ksettings->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
812
813 return ret;
814}
815
816static void
817ethtool_get_default_link_ksettings(
818 struct net_device *dev, struct ethtool_link_ksettings *link_ksettings)
819{
820 struct mlx4_en_priv *priv = netdev_priv(dev);
821 int trans_type;
822
823 link_ksettings->base.autoneg = AUTONEG_DISABLE;
824
825 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
826 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
827 10000baseT_Full);
828
829 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
830 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising,
831 10000baseT_Full);
832
833 trans_type = priv->port_state.transceiver;
834 if (trans_type > 0 && trans_type <= 0xC) {
835 link_ksettings->base.port = PORT_FIBRE;
836 ethtool_link_ksettings_add_link_mode(link_ksettings,
837 supported, FIBRE);
838 ethtool_link_ksettings_add_link_mode(link_ksettings,
839 advertising, FIBRE);
840 } else if (trans_type == 0x80 || trans_type == 0) {
841 link_ksettings->base.port = PORT_TP;
842 ethtool_link_ksettings_add_link_mode(link_ksettings,
843 supported, TP);
844 ethtool_link_ksettings_add_link_mode(link_ksettings,
845 advertising, TP);
846 } else {
847 link_ksettings->base.port = -1;
848 }
849}
850
851static int
852mlx4_en_get_link_ksettings(struct net_device *dev,
853 struct ethtool_link_ksettings *link_ksettings)
854{
855 struct mlx4_en_priv *priv = netdev_priv(dev);
856 int ret = -EINVAL;
857
858 if (mlx4_en_QUERY_PORT(priv->mdev, priv->port))
859 return -ENOMEM;
860
861 en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n",
862 priv->port_state.flags & MLX4_EN_PORT_ANC,
863 priv->port_state.flags & MLX4_EN_PORT_ANE);
864
865 if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL)
866 ret = ethtool_get_ptys_link_ksettings(dev, link_ksettings);
867 if (ret)
868 ethtool_get_default_link_ksettings(dev, link_ksettings);
869
870 if (netif_carrier_ok(dev)) {
871 link_ksettings->base.speed = priv->port_state.link_speed;
872 link_ksettings->base.duplex = DUPLEX_FULL;
873 } else {
874 link_ksettings->base.speed = SPEED_UNKNOWN;
875 link_ksettings->base.duplex = DUPLEX_UNKNOWN;
876 }
877 return 0;
878}
879
880
881static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed,
882 __be32 proto_cap)
883{
884 __be32 proto_admin = 0;
885
886 if (!speed) {
887 proto_admin = proto_cap;
888 en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n",
889 be32_to_cpu(proto_cap));
890 } else {
891 u32 ptys_link_modes = speed2ptys_link_modes(speed);
892
893 proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap;
894 en_info(priv, "Setting Speed to %d\n", speed);
895 }
896 return proto_admin;
897}
898
899static int
900mlx4_en_set_link_ksettings(struct net_device *dev,
901 const struct ethtool_link_ksettings *link_ksettings)
902{
903 struct mlx4_en_priv *priv = netdev_priv(dev);
904 struct mlx4_ptys_reg ptys_reg;
905 __be32 proto_admin;
906 u8 cur_autoneg;
907 int ret;
908
909 u32 ptys_adv = ethtool2ptys_link_modes(
910 link_ksettings->link_modes.advertising, ADVERTISED);
911 const int speed = link_ksettings->base.speed;
912
913 en_dbg(DRV, priv,
914 "Set Speed=%d adv={%*pbl} autoneg=%d duplex=%d\n",
915 speed, __ETHTOOL_LINK_MODE_MASK_NBITS,
916 link_ksettings->link_modes.advertising,
917 link_ksettings->base.autoneg,
918 link_ksettings->base.duplex);
919
920 if (!(priv->mdev->dev->caps.flags2 &
921 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) ||
922 (link_ksettings->base.duplex == DUPLEX_HALF))
923 return -EINVAL;
924
925 memset(&ptys_reg, 0, sizeof(ptys_reg));
926 ptys_reg.local_port = priv->port;
927 ptys_reg.proto_mask = MLX4_PTYS_EN;
928 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
929 MLX4_ACCESS_REG_QUERY, &ptys_reg);
930 if (ret) {
931 en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n",
932 ret);
933 return 0;
934 }
935
936 cur_autoneg = ptys_reg.flags & MLX4_PTYS_AN_DISABLE_ADMIN ?
937 AUTONEG_DISABLE : AUTONEG_ENABLE;
938
939 if (link_ksettings->base.autoneg == AUTONEG_DISABLE) {
940 proto_admin = speed_set_ptys_admin(priv, speed,
941 ptys_reg.eth_proto_cap);
942 if ((be32_to_cpu(proto_admin) &
943 (MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII) |
944 MLX4_PROT_MASK(MLX4_1000BASE_KX))) &&
945 (ptys_reg.flags & MLX4_PTYS_AN_DISABLE_CAP))
946 ptys_reg.flags |= MLX4_PTYS_AN_DISABLE_ADMIN;
947 } else {
948 proto_admin = cpu_to_be32(ptys_adv);
949 ptys_reg.flags &= ~MLX4_PTYS_AN_DISABLE_ADMIN;
950 }
951
952 proto_admin &= ptys_reg.eth_proto_cap;
953 if (!proto_admin) {
954 en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n");
955 return -EINVAL;
956 }
957
958 if ((proto_admin == ptys_reg.eth_proto_admin) &&
959 ((ptys_reg.flags & MLX4_PTYS_AN_DISABLE_CAP) &&
960 (link_ksettings->base.autoneg == cur_autoneg)))
961 return 0;
962
963 en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n",
964 be32_to_cpu(proto_admin));
965
966 ptys_reg.eth_proto_admin = proto_admin;
967 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE,
968 &ptys_reg);
969 if (ret) {
970 en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)",
971 be32_to_cpu(ptys_reg.eth_proto_admin), ret);
972 return ret;
973 }
974
975 mutex_lock(&priv->mdev->state_lock);
976 if (priv->port_up) {
977 en_warn(priv, "Port link mode changed, restarting port...\n");
978 mlx4_en_stop_port(dev, 1);
979 if (mlx4_en_start_port(dev))
980 en_err(priv, "Failed restarting port %d\n", priv->port);
981 }
982 mutex_unlock(&priv->mdev->state_lock);
983 return 0;
984}
985
986static int mlx4_en_get_coalesce(struct net_device *dev,
987 struct ethtool_coalesce *coal)
988{
989 struct mlx4_en_priv *priv = netdev_priv(dev);
990
991 coal->tx_coalesce_usecs = priv->tx_usecs;
992 coal->tx_max_coalesced_frames = priv->tx_frames;
993 coal->tx_max_coalesced_frames_irq = priv->tx_work_limit;
994
995 coal->rx_coalesce_usecs = priv->rx_usecs;
996 coal->rx_max_coalesced_frames = priv->rx_frames;
997
998 coal->pkt_rate_low = priv->pkt_rate_low;
999 coal->rx_coalesce_usecs_low = priv->rx_usecs_low;
1000 coal->pkt_rate_high = priv->pkt_rate_high;
1001 coal->rx_coalesce_usecs_high = priv->rx_usecs_high;
1002 coal->rate_sample_interval = priv->sample_interval;
1003 coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal;
1004
1005 return 0;
1006}
1007
1008static int mlx4_en_set_coalesce(struct net_device *dev,
1009 struct ethtool_coalesce *coal)
1010{
1011 struct mlx4_en_priv *priv = netdev_priv(dev);
1012
1013 if (!coal->tx_max_coalesced_frames_irq)
1014 return -EINVAL;
1015
1016 priv->rx_frames = (coal->rx_max_coalesced_frames ==
1017 MLX4_EN_AUTO_CONF) ?
1018 MLX4_EN_RX_COAL_TARGET :
1019 coal->rx_max_coalesced_frames;
1020 priv->rx_usecs = (coal->rx_coalesce_usecs ==
1021 MLX4_EN_AUTO_CONF) ?
1022 MLX4_EN_RX_COAL_TIME :
1023 coal->rx_coalesce_usecs;
1024
1025
1026 if (coal->tx_coalesce_usecs != priv->tx_usecs ||
1027 coal->tx_max_coalesced_frames != priv->tx_frames) {
1028 priv->tx_usecs = coal->tx_coalesce_usecs;
1029 priv->tx_frames = coal->tx_max_coalesced_frames;
1030 }
1031
1032
1033 priv->pkt_rate_low = coal->pkt_rate_low;
1034 priv->rx_usecs_low = coal->rx_coalesce_usecs_low;
1035 priv->pkt_rate_high = coal->pkt_rate_high;
1036 priv->rx_usecs_high = coal->rx_coalesce_usecs_high;
1037 priv->sample_interval = coal->rate_sample_interval;
1038 priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce;
1039 priv->tx_work_limit = coal->tx_max_coalesced_frames_irq;
1040
1041 return mlx4_en_moderation_update(priv);
1042}
1043
1044static int mlx4_en_set_pauseparam(struct net_device *dev,
1045 struct ethtool_pauseparam *pause)
1046{
1047 struct mlx4_en_priv *priv = netdev_priv(dev);
1048 struct mlx4_en_dev *mdev = priv->mdev;
1049 u8 tx_pause, tx_ppp, rx_pause, rx_ppp;
1050 int err;
1051
1052 if (pause->autoneg)
1053 return -EINVAL;
1054
1055 tx_pause = !!(pause->tx_pause);
1056 rx_pause = !!(pause->rx_pause);
1057 rx_ppp = priv->prof->rx_ppp && !(tx_pause || rx_pause);
1058 tx_ppp = priv->prof->tx_ppp && !(tx_pause || rx_pause);
1059
1060 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1061 priv->rx_skb_size + ETH_FCS_LEN,
1062 tx_pause, tx_ppp, rx_pause, rx_ppp);
1063 if (err) {
1064 en_err(priv, "Failed setting pause params, err = %d\n", err);
1065 return err;
1066 }
1067
1068 mlx4_en_update_pfc_stats_bitmap(mdev->dev, &priv->stats_bitmap,
1069 rx_ppp, rx_pause, tx_ppp, tx_pause);
1070
1071 priv->prof->tx_pause = tx_pause;
1072 priv->prof->rx_pause = rx_pause;
1073 priv->prof->tx_ppp = tx_ppp;
1074 priv->prof->rx_ppp = rx_ppp;
1075
1076 return err;
1077}
1078
1079static void mlx4_en_get_pauseparam(struct net_device *dev,
1080 struct ethtool_pauseparam *pause)
1081{
1082 struct mlx4_en_priv *priv = netdev_priv(dev);
1083
1084 pause->tx_pause = priv->prof->tx_pause;
1085 pause->rx_pause = priv->prof->rx_pause;
1086}
1087
1088static int mlx4_en_set_ringparam(struct net_device *dev,
1089 struct ethtool_ringparam *param)
1090{
1091 struct mlx4_en_priv *priv = netdev_priv(dev);
1092 struct mlx4_en_dev *mdev = priv->mdev;
1093 struct mlx4_en_port_profile new_prof;
1094 struct mlx4_en_priv *tmp;
1095 u32 rx_size, tx_size;
1096 int port_up = 0;
1097 int err = 0;
1098
1099 if (param->rx_jumbo_pending || param->rx_mini_pending)
1100 return -EINVAL;
1101
1102 if (param->rx_pending < MLX4_EN_MIN_RX_SIZE) {
1103 en_warn(priv, "%s: rx_pending (%d) < min (%d)\n",
1104 __func__, param->rx_pending,
1105 MLX4_EN_MIN_RX_SIZE);
1106 return -EINVAL;
1107 }
1108 if (param->tx_pending < MLX4_EN_MIN_TX_SIZE) {
1109 en_warn(priv, "%s: tx_pending (%d) < min (%lu)\n",
1110 __func__, param->tx_pending,
1111 MLX4_EN_MIN_TX_SIZE);
1112 return -EINVAL;
1113 }
1114
1115 rx_size = roundup_pow_of_two(param->rx_pending);
1116 tx_size = roundup_pow_of_two(param->tx_pending);
1117
1118 if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size :
1119 priv->rx_ring[0]->size) &&
1120 tx_size == priv->tx_ring[TX][0]->size)
1121 return 0;
1122
1123 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
1124 if (!tmp)
1125 return -ENOMEM;
1126
1127 mutex_lock(&mdev->state_lock);
1128 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
1129 new_prof.tx_ring_size = tx_size;
1130 new_prof.rx_ring_size = rx_size;
1131 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true);
1132 if (err)
1133 goto out;
1134
1135 if (priv->port_up) {
1136 port_up = 1;
1137 mlx4_en_stop_port(dev, 1);
1138 }
1139
1140 mlx4_en_safe_replace_resources(priv, tmp);
1141
1142 if (port_up) {
1143 err = mlx4_en_start_port(dev);
1144 if (err)
1145 en_err(priv, "Failed starting port\n");
1146 }
1147
1148 err = mlx4_en_moderation_update(priv);
1149out:
1150 kfree(tmp);
1151 mutex_unlock(&mdev->state_lock);
1152 return err;
1153}
1154
1155static void mlx4_en_get_ringparam(struct net_device *dev,
1156 struct ethtool_ringparam *param)
1157{
1158 struct mlx4_en_priv *priv = netdev_priv(dev);
1159
1160 memset(param, 0, sizeof(*param));
1161 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE;
1162 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE;
1163 param->rx_pending = priv->port_up ?
1164 priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size;
1165 param->tx_pending = priv->tx_ring[TX][0]->size;
1166}
1167
1168static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev)
1169{
1170 struct mlx4_en_priv *priv = netdev_priv(dev);
1171
1172 return rounddown_pow_of_two(priv->rx_ring_num);
1173}
1174
1175static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev)
1176{
1177 return MLX4_EN_RSS_KEY_SIZE;
1178}
1179
1180static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc)
1181{
1182 struct mlx4_en_priv *priv = netdev_priv(dev);
1183
1184
1185 if (hfunc == ETH_RSS_HASH_TOP) {
1186 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP))
1187 return -EINVAL;
1188 if (!(dev->features & NETIF_F_RXHASH))
1189 en_warn(priv, "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n");
1190 return 0;
1191 } else if (hfunc == ETH_RSS_HASH_XOR) {
1192 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR))
1193 return -EINVAL;
1194 if (dev->features & NETIF_F_RXHASH)
1195 en_warn(priv, "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n");
1196 return 0;
1197 }
1198
1199 return -EINVAL;
1200}
1201
1202static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key,
1203 u8 *hfunc)
1204{
1205 struct mlx4_en_priv *priv = netdev_priv(dev);
1206 u32 n = mlx4_en_get_rxfh_indir_size(dev);
1207 u32 i, rss_rings;
1208 int err = 0;
1209
1210 rss_rings = priv->prof->rss_rings ?: n;
1211 rss_rings = rounddown_pow_of_two(rss_rings);
1212
1213 for (i = 0; i < n; i++) {
1214 if (!ring_index)
1215 break;
1216 ring_index[i] = i % rss_rings;
1217 }
1218 if (key)
1219 memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE);
1220 if (hfunc)
1221 *hfunc = priv->rss_hash_fn;
1222 return err;
1223}
1224
1225static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index,
1226 const u8 *key, const u8 hfunc)
1227{
1228 struct mlx4_en_priv *priv = netdev_priv(dev);
1229 u32 n = mlx4_en_get_rxfh_indir_size(dev);
1230 struct mlx4_en_dev *mdev = priv->mdev;
1231 int port_up = 0;
1232 int err = 0;
1233 int i;
1234 int rss_rings = 0;
1235
1236
1237
1238
1239 for (i = 0; i < n; i++) {
1240 if (!ring_index)
1241 break;
1242 if (i > 0 && !ring_index[i] && !rss_rings)
1243 rss_rings = i;
1244
1245 if (ring_index[i] != (i % (rss_rings ?: n)))
1246 return -EINVAL;
1247 }
1248
1249 if (!rss_rings)
1250 rss_rings = n;
1251
1252
1253 if (!is_power_of_2(rss_rings))
1254 return -EINVAL;
1255
1256 if (hfunc != ETH_RSS_HASH_NO_CHANGE) {
1257 err = mlx4_en_check_rxfh_func(dev, hfunc);
1258 if (err)
1259 return err;
1260 }
1261
1262 mutex_lock(&mdev->state_lock);
1263 if (priv->port_up) {
1264 port_up = 1;
1265 mlx4_en_stop_port(dev, 1);
1266 }
1267
1268 if (ring_index)
1269 priv->prof->rss_rings = rss_rings;
1270 if (key)
1271 memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE);
1272 if (hfunc != ETH_RSS_HASH_NO_CHANGE)
1273 priv->rss_hash_fn = hfunc;
1274
1275 if (port_up) {
1276 err = mlx4_en_start_port(dev);
1277 if (err)
1278 en_err(priv, "Failed starting port\n");
1279 }
1280
1281 mutex_unlock(&mdev->state_lock);
1282 return err;
1283}
1284
1285#define all_zeros_or_all_ones(field) \
1286 ((field) == 0 || (field) == (__force typeof(field))-1)
1287
1288static int mlx4_en_validate_flow(struct net_device *dev,
1289 struct ethtool_rxnfc *cmd)
1290{
1291 struct ethtool_usrip4_spec *l3_mask;
1292 struct ethtool_tcpip4_spec *l4_mask;
1293 struct ethhdr *eth_mask;
1294
1295 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1296 return -EINVAL;
1297
1298 if (cmd->fs.flow_type & FLOW_MAC_EXT) {
1299
1300 if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest))
1301 return -EINVAL;
1302 }
1303
1304 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1305 case TCP_V4_FLOW:
1306 case UDP_V4_FLOW:
1307 if (cmd->fs.m_u.tcp_ip4_spec.tos)
1308 return -EINVAL;
1309 l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1310
1311 if (!all_zeros_or_all_ones(l4_mask->ip4src) ||
1312 !all_zeros_or_all_ones(l4_mask->ip4dst) ||
1313 !all_zeros_or_all_ones(l4_mask->psrc) ||
1314 !all_zeros_or_all_ones(l4_mask->pdst))
1315 return -EINVAL;
1316 break;
1317 case IP_USER_FLOW:
1318 l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1319 if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto ||
1320 cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 ||
1321 (!l3_mask->ip4src && !l3_mask->ip4dst) ||
1322 !all_zeros_or_all_ones(l3_mask->ip4src) ||
1323 !all_zeros_or_all_ones(l3_mask->ip4dst))
1324 return -EINVAL;
1325 break;
1326 case ETHER_FLOW:
1327 eth_mask = &cmd->fs.m_u.ether_spec;
1328
1329 if (!is_zero_ether_addr(eth_mask->h_source))
1330 return -EINVAL;
1331
1332
1333 if (!is_broadcast_ether_addr(eth_mask->h_dest))
1334 return -EINVAL;
1335
1336 if (!all_zeros_or_all_ones(eth_mask->h_proto))
1337 return -EINVAL;
1338 break;
1339 default:
1340 return -EINVAL;
1341 }
1342
1343 if ((cmd->fs.flow_type & FLOW_EXT)) {
1344 if (cmd->fs.m_ext.vlan_etype ||
1345 !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1346 0 ||
1347 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1348 cpu_to_be16(VLAN_VID_MASK)))
1349 return -EINVAL;
1350
1351 if (cmd->fs.m_ext.vlan_tci) {
1352 if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID)
1353 return -EINVAL;
1354
1355 }
1356 }
1357
1358 return 0;
1359}
1360
1361static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd,
1362 struct list_head *rule_list_h,
1363 struct mlx4_spec_list *spec_l2,
1364 unsigned char *mac)
1365{
1366 int err = 0;
1367 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
1368
1369 spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH;
1370 memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN);
1371 memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN);
1372
1373 if ((cmd->fs.flow_type & FLOW_EXT) &&
1374 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) {
1375 spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci;
1376 spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK);
1377 }
1378
1379 list_add_tail(&spec_l2->list, rule_list_h);
1380
1381 return err;
1382}
1383
1384static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv,
1385 struct ethtool_rxnfc *cmd,
1386 struct list_head *rule_list_h,
1387 struct mlx4_spec_list *spec_l2,
1388 __be32 ipv4_dst)
1389{
1390#ifdef CONFIG_INET
1391 unsigned char mac[ETH_ALEN];
1392
1393 if (!ipv4_is_multicast(ipv4_dst)) {
1394 if (cmd->fs.flow_type & FLOW_MAC_EXT)
1395 memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN);
1396 else
1397 memcpy(&mac, priv->dev->dev_addr, ETH_ALEN);
1398 } else {
1399 ip_eth_mc_map(ipv4_dst, mac);
1400 }
1401
1402 return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]);
1403#else
1404 return -EINVAL;
1405#endif
1406}
1407
1408static int add_ip_rule(struct mlx4_en_priv *priv,
1409 struct ethtool_rxnfc *cmd,
1410 struct list_head *list_h)
1411{
1412 int err;
1413 struct mlx4_spec_list *spec_l2 = NULL;
1414 struct mlx4_spec_list *spec_l3 = NULL;
1415 struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1416
1417 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1418 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1419 if (!spec_l2 || !spec_l3) {
1420 err = -ENOMEM;
1421 goto free_spec;
1422 }
1423
1424 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2,
1425 cmd->fs.h_u.
1426 usr_ip4_spec.ip4dst);
1427 if (err)
1428 goto free_spec;
1429 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1430 spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src;
1431 if (l3_mask->ip4src)
1432 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1433 spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst;
1434 if (l3_mask->ip4dst)
1435 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1436 list_add_tail(&spec_l3->list, list_h);
1437
1438 return 0;
1439
1440free_spec:
1441 kfree(spec_l2);
1442 kfree(spec_l3);
1443 return err;
1444}
1445
1446static int add_tcp_udp_rule(struct mlx4_en_priv *priv,
1447 struct ethtool_rxnfc *cmd,
1448 struct list_head *list_h, int proto)
1449{
1450 int err;
1451 struct mlx4_spec_list *spec_l2 = NULL;
1452 struct mlx4_spec_list *spec_l3 = NULL;
1453 struct mlx4_spec_list *spec_l4 = NULL;
1454 struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1455
1456 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1457 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1458 spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL);
1459 if (!spec_l2 || !spec_l3 || !spec_l4) {
1460 err = -ENOMEM;
1461 goto free_spec;
1462 }
1463
1464 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1465
1466 if (proto == TCP_V4_FLOW) {
1467 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1468 spec_l2,
1469 cmd->fs.h_u.
1470 tcp_ip4_spec.ip4dst);
1471 if (err)
1472 goto free_spec;
1473 spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP;
1474 spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src;
1475 spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst;
1476 spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc;
1477 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst;
1478 } else {
1479 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1480 spec_l2,
1481 cmd->fs.h_u.
1482 udp_ip4_spec.ip4dst);
1483 if (err)
1484 goto free_spec;
1485 spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP;
1486 spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src;
1487 spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst;
1488 spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc;
1489 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst;
1490 }
1491
1492 if (l4_mask->ip4src)
1493 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1494 if (l4_mask->ip4dst)
1495 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1496
1497 if (l4_mask->psrc)
1498 spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK;
1499 if (l4_mask->pdst)
1500 spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK;
1501
1502 list_add_tail(&spec_l3->list, list_h);
1503 list_add_tail(&spec_l4->list, list_h);
1504
1505 return 0;
1506
1507free_spec:
1508 kfree(spec_l2);
1509 kfree(spec_l3);
1510 kfree(spec_l4);
1511 return err;
1512}
1513
1514static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev,
1515 struct ethtool_rxnfc *cmd,
1516 struct list_head *rule_list_h)
1517{
1518 int err;
1519 struct ethhdr *eth_spec;
1520 struct mlx4_spec_list *spec_l2;
1521 struct mlx4_en_priv *priv = netdev_priv(dev);
1522
1523 err = mlx4_en_validate_flow(dev, cmd);
1524 if (err)
1525 return err;
1526
1527 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1528 case ETHER_FLOW:
1529 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1530 if (!spec_l2)
1531 return -ENOMEM;
1532
1533 eth_spec = &cmd->fs.h_u.ether_spec;
1534 mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2,
1535 ð_spec->h_dest[0]);
1536 spec_l2->eth.ether_type = eth_spec->h_proto;
1537 if (eth_spec->h_proto)
1538 spec_l2->eth.ether_type_enable = 1;
1539 break;
1540 case IP_USER_FLOW:
1541 err = add_ip_rule(priv, cmd, rule_list_h);
1542 break;
1543 case TCP_V4_FLOW:
1544 err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW);
1545 break;
1546 case UDP_V4_FLOW:
1547 err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW);
1548 break;
1549 }
1550
1551 return err;
1552}
1553
1554static int mlx4_en_flow_replace(struct net_device *dev,
1555 struct ethtool_rxnfc *cmd)
1556{
1557 int err;
1558 struct mlx4_en_priv *priv = netdev_priv(dev);
1559 struct ethtool_flow_id *loc_rule;
1560 struct mlx4_spec_list *spec, *tmp_spec;
1561 u32 qpn;
1562 u64 reg_id;
1563
1564 struct mlx4_net_trans_rule rule = {
1565 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1566 .exclusive = 0,
1567 .allow_loopback = 1,
1568 .promisc_mode = MLX4_FS_REGULAR,
1569 };
1570
1571 rule.port = priv->port;
1572 rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location;
1573 INIT_LIST_HEAD(&rule.list);
1574
1575
1576 if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC)
1577 qpn = priv->drop_qp.qpn;
1578 else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) {
1579 qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1);
1580 } else {
1581 if (cmd->fs.ring_cookie >= priv->rx_ring_num) {
1582 en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n",
1583 cmd->fs.ring_cookie);
1584 return -EINVAL;
1585 }
1586 qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn;
1587 if (!qpn) {
1588 en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n",
1589 cmd->fs.ring_cookie);
1590 return -EINVAL;
1591 }
1592 }
1593 rule.qpn = qpn;
1594 err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list);
1595 if (err)
1596 goto out_free_list;
1597
1598 loc_rule = &priv->ethtool_rules[cmd->fs.location];
1599 if (loc_rule->id) {
1600 err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id);
1601 if (err) {
1602 en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n",
1603 cmd->fs.location, loc_rule->id);
1604 goto out_free_list;
1605 }
1606 loc_rule->id = 0;
1607 memset(&loc_rule->flow_spec, 0,
1608 sizeof(struct ethtool_rx_flow_spec));
1609 list_del(&loc_rule->list);
1610 }
1611 err = mlx4_flow_attach(priv->mdev->dev, &rule, ®_id);
1612 if (err) {
1613 en_err(priv, "Fail to attach network rule at location %d\n",
1614 cmd->fs.location);
1615 goto out_free_list;
1616 }
1617 loc_rule->id = reg_id;
1618 memcpy(&loc_rule->flow_spec, &cmd->fs,
1619 sizeof(struct ethtool_rx_flow_spec));
1620 list_add_tail(&loc_rule->list, &priv->ethtool_list);
1621
1622out_free_list:
1623 list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) {
1624 list_del(&spec->list);
1625 kfree(spec);
1626 }
1627 return err;
1628}
1629
1630static int mlx4_en_flow_detach(struct net_device *dev,
1631 struct ethtool_rxnfc *cmd)
1632{
1633 int err = 0;
1634 struct ethtool_flow_id *rule;
1635 struct mlx4_en_priv *priv = netdev_priv(dev);
1636
1637 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1638 return -EINVAL;
1639
1640 rule = &priv->ethtool_rules[cmd->fs.location];
1641 if (!rule->id) {
1642 err = -ENOENT;
1643 goto out;
1644 }
1645
1646 err = mlx4_flow_detach(priv->mdev->dev, rule->id);
1647 if (err) {
1648 en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n",
1649 cmd->fs.location, rule->id);
1650 goto out;
1651 }
1652 rule->id = 0;
1653 memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec));
1654 list_del(&rule->list);
1655out:
1656 return err;
1657
1658}
1659
1660static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1661 int loc)
1662{
1663 int err = 0;
1664 struct ethtool_flow_id *rule;
1665 struct mlx4_en_priv *priv = netdev_priv(dev);
1666
1667 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1668 return -EINVAL;
1669
1670 rule = &priv->ethtool_rules[loc];
1671 if (rule->id)
1672 memcpy(&cmd->fs, &rule->flow_spec,
1673 sizeof(struct ethtool_rx_flow_spec));
1674 else
1675 err = -ENOENT;
1676
1677 return err;
1678}
1679
1680static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv)
1681{
1682
1683 int i, res = 0;
1684 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
1685 if (priv->ethtool_rules[i].id)
1686 res++;
1687 }
1688 return res;
1689
1690}
1691
1692static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1693 u32 *rule_locs)
1694{
1695 struct mlx4_en_priv *priv = netdev_priv(dev);
1696 struct mlx4_en_dev *mdev = priv->mdev;
1697 int err = 0;
1698 int i = 0, priority = 0;
1699
1700 if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT ||
1701 cmd->cmd == ETHTOOL_GRXCLSRULE ||
1702 cmd->cmd == ETHTOOL_GRXCLSRLALL) &&
1703 (mdev->dev->caps.steering_mode !=
1704 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up))
1705 return -EINVAL;
1706
1707 switch (cmd->cmd) {
1708 case ETHTOOL_GRXRINGS:
1709 cmd->data = priv->rx_ring_num;
1710 break;
1711 case ETHTOOL_GRXCLSRLCNT:
1712 cmd->rule_cnt = mlx4_en_get_num_flows(priv);
1713 break;
1714 case ETHTOOL_GRXCLSRULE:
1715 err = mlx4_en_get_flow(dev, cmd, cmd->fs.location);
1716 break;
1717 case ETHTOOL_GRXCLSRLALL:
1718 while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) {
1719 err = mlx4_en_get_flow(dev, cmd, i);
1720 if (!err)
1721 rule_locs[priority++] = i;
1722 i++;
1723 }
1724 err = 0;
1725 break;
1726 default:
1727 err = -EOPNOTSUPP;
1728 break;
1729 }
1730
1731 return err;
1732}
1733
1734static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1735{
1736 int err = 0;
1737 struct mlx4_en_priv *priv = netdev_priv(dev);
1738 struct mlx4_en_dev *mdev = priv->mdev;
1739
1740 if (mdev->dev->caps.steering_mode !=
1741 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)
1742 return -EINVAL;
1743
1744 switch (cmd->cmd) {
1745 case ETHTOOL_SRXCLSRLINS:
1746 err = mlx4_en_flow_replace(dev, cmd);
1747 break;
1748 case ETHTOOL_SRXCLSRLDEL:
1749 err = mlx4_en_flow_detach(dev, cmd);
1750 break;
1751 default:
1752 en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd);
1753 return -EINVAL;
1754 }
1755
1756 return err;
1757}
1758
1759static int mlx4_en_get_max_num_rx_rings(struct net_device *dev)
1760{
1761 return min_t(int, num_online_cpus(), MAX_RX_RINGS);
1762}
1763
1764static void mlx4_en_get_channels(struct net_device *dev,
1765 struct ethtool_channels *channel)
1766{
1767 struct mlx4_en_priv *priv = netdev_priv(dev);
1768
1769 channel->max_rx = mlx4_en_get_max_num_rx_rings(dev);
1770 channel->max_tx = priv->mdev->profile.max_num_tx_rings_p_up;
1771
1772 channel->rx_count = priv->rx_ring_num;
1773 channel->tx_count = priv->tx_ring_num[TX] /
1774 priv->prof->num_up;
1775}
1776
1777static int mlx4_en_set_channels(struct net_device *dev,
1778 struct ethtool_channels *channel)
1779{
1780 struct mlx4_en_priv *priv = netdev_priv(dev);
1781 struct mlx4_en_dev *mdev = priv->mdev;
1782 struct mlx4_en_port_profile new_prof;
1783 struct mlx4_en_priv *tmp;
1784 int port_up = 0;
1785 int xdp_count;
1786 int err = 0;
1787 u8 up;
1788
1789 if (!channel->tx_count || !channel->rx_count)
1790 return -EINVAL;
1791
1792 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
1793 if (!tmp)
1794 return -ENOMEM;
1795
1796 mutex_lock(&mdev->state_lock);
1797 xdp_count = priv->tx_ring_num[TX_XDP] ? channel->rx_count : 0;
1798 if (channel->tx_count * priv->prof->num_up + xdp_count >
1799 priv->mdev->profile.max_num_tx_rings_p_up * priv->prof->num_up) {
1800 err = -EINVAL;
1801 en_err(priv,
1802 "Total number of TX and XDP rings (%d) exceeds the maximum supported (%d)\n",
1803 channel->tx_count * priv->prof->num_up + xdp_count,
1804 MAX_TX_RINGS);
1805 goto out;
1806 }
1807
1808 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
1809 new_prof.num_tx_rings_p_up = channel->tx_count;
1810 new_prof.tx_ring_num[TX] = channel->tx_count * priv->prof->num_up;
1811 new_prof.tx_ring_num[TX_XDP] = xdp_count;
1812 new_prof.rx_ring_num = channel->rx_count;
1813
1814 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true);
1815 if (err)
1816 goto out;
1817
1818 if (priv->port_up) {
1819 port_up = 1;
1820 mlx4_en_stop_port(dev, 1);
1821 }
1822
1823 mlx4_en_safe_replace_resources(priv, tmp);
1824
1825 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
1826
1827 up = (priv->prof->num_up == MLX4_EN_NUM_UP_LOW) ?
1828 0 : priv->prof->num_up;
1829 mlx4_en_setup_tc(dev, up);
1830
1831 en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num[TX]);
1832 en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num);
1833
1834 if (port_up) {
1835 err = mlx4_en_start_port(dev);
1836 if (err)
1837 en_err(priv, "Failed starting port\n");
1838 }
1839
1840 err = mlx4_en_moderation_update(priv);
1841out:
1842 mutex_unlock(&mdev->state_lock);
1843 kfree(tmp);
1844 return err;
1845}
1846
1847static int mlx4_en_get_ts_info(struct net_device *dev,
1848 struct ethtool_ts_info *info)
1849{
1850 struct mlx4_en_priv *priv = netdev_priv(dev);
1851 struct mlx4_en_dev *mdev = priv->mdev;
1852 int ret;
1853
1854 ret = ethtool_op_get_ts_info(dev, info);
1855 if (ret)
1856 return ret;
1857
1858 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1859 info->so_timestamping |=
1860 SOF_TIMESTAMPING_TX_HARDWARE |
1861 SOF_TIMESTAMPING_RX_HARDWARE |
1862 SOF_TIMESTAMPING_RAW_HARDWARE;
1863
1864 info->tx_types =
1865 (1 << HWTSTAMP_TX_OFF) |
1866 (1 << HWTSTAMP_TX_ON);
1867
1868 info->rx_filters =
1869 (1 << HWTSTAMP_FILTER_NONE) |
1870 (1 << HWTSTAMP_FILTER_ALL);
1871
1872 if (mdev->ptp_clock)
1873 info->phc_index = ptp_clock_index(mdev->ptp_clock);
1874 }
1875
1876 return ret;
1877}
1878
1879static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags)
1880{
1881 struct mlx4_en_priv *priv = netdev_priv(dev);
1882 struct mlx4_en_dev *mdev = priv->mdev;
1883 bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1884 bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1885 bool phv_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_PHV);
1886 bool phv_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_PHV);
1887 int i;
1888 int ret = 0;
1889
1890 if (bf_enabled_new != bf_enabled_old) {
1891 int t;
1892
1893 if (bf_enabled_new) {
1894 bool bf_supported = true;
1895
1896 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++)
1897 for (i = 0; i < priv->tx_ring_num[t]; i++)
1898 bf_supported &=
1899 priv->tx_ring[t][i]->bf_alloced;
1900
1901 if (!bf_supported) {
1902 en_err(priv, "BlueFlame is not supported\n");
1903 return -EINVAL;
1904 }
1905
1906 priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1907 } else {
1908 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1909 }
1910
1911 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++)
1912 for (i = 0; i < priv->tx_ring_num[t]; i++)
1913 priv->tx_ring[t][i]->bf_enabled =
1914 bf_enabled_new;
1915
1916 en_info(priv, "BlueFlame %s\n",
1917 bf_enabled_new ? "Enabled" : "Disabled");
1918 }
1919
1920 if (phv_enabled_new != phv_enabled_old) {
1921 ret = set_phv_bit(mdev->dev, priv->port, (int)phv_enabled_new);
1922 if (ret)
1923 return ret;
1924 else if (phv_enabled_new)
1925 priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV;
1926 else
1927 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_PHV;
1928 en_info(priv, "PHV bit %s\n",
1929 phv_enabled_new ? "Enabled" : "Disabled");
1930 }
1931 return 0;
1932}
1933
1934static u32 mlx4_en_get_priv_flags(struct net_device *dev)
1935{
1936 struct mlx4_en_priv *priv = netdev_priv(dev);
1937
1938 return priv->pflags;
1939}
1940
1941static int mlx4_en_get_tunable(struct net_device *dev,
1942 const struct ethtool_tunable *tuna,
1943 void *data)
1944{
1945 const struct mlx4_en_priv *priv = netdev_priv(dev);
1946 int ret = 0;
1947
1948 switch (tuna->id) {
1949 case ETHTOOL_TX_COPYBREAK:
1950 *(u32 *)data = priv->prof->inline_thold;
1951 break;
1952 default:
1953 ret = -EINVAL;
1954 break;
1955 }
1956
1957 return ret;
1958}
1959
1960static int mlx4_en_set_tunable(struct net_device *dev,
1961 const struct ethtool_tunable *tuna,
1962 const void *data)
1963{
1964 struct mlx4_en_priv *priv = netdev_priv(dev);
1965 int val, ret = 0;
1966
1967 switch (tuna->id) {
1968 case ETHTOOL_TX_COPYBREAK:
1969 val = *(u32 *)data;
1970 if (val < MIN_PKT_LEN || val > MAX_INLINE)
1971 ret = -EINVAL;
1972 else
1973 priv->prof->inline_thold = val;
1974 break;
1975 default:
1976 ret = -EINVAL;
1977 break;
1978 }
1979
1980 return ret;
1981}
1982
1983static int mlx4_en_get_module_info(struct net_device *dev,
1984 struct ethtool_modinfo *modinfo)
1985{
1986 struct mlx4_en_priv *priv = netdev_priv(dev);
1987 struct mlx4_en_dev *mdev = priv->mdev;
1988 int ret;
1989 u8 data[4];
1990
1991
1992 ret = mlx4_get_module_info(mdev->dev, priv->port,
1993 0, 2, data);
1994 if (ret < 2)
1995 return -EIO;
1996
1997 switch (data[0] ) {
1998 case MLX4_MODULE_ID_QSFP:
1999 modinfo->type = ETH_MODULE_SFF_8436;
2000 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2001 break;
2002 case MLX4_MODULE_ID_QSFP_PLUS:
2003 if (data[1] >= 0x3) {
2004 modinfo->type = ETH_MODULE_SFF_8636;
2005 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2006 } else {
2007 modinfo->type = ETH_MODULE_SFF_8436;
2008 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2009 }
2010 break;
2011 case MLX4_MODULE_ID_QSFP28:
2012 modinfo->type = ETH_MODULE_SFF_8636;
2013 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2014 break;
2015 case MLX4_MODULE_ID_SFP:
2016 modinfo->type = ETH_MODULE_SFF_8472;
2017 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2018 break;
2019 default:
2020 return -EINVAL;
2021 }
2022
2023 return 0;
2024}
2025
2026static int mlx4_en_get_module_eeprom(struct net_device *dev,
2027 struct ethtool_eeprom *ee,
2028 u8 *data)
2029{
2030 struct mlx4_en_priv *priv = netdev_priv(dev);
2031 struct mlx4_en_dev *mdev = priv->mdev;
2032 int offset = ee->offset;
2033 int i = 0, ret;
2034
2035 if (ee->len == 0)
2036 return -EINVAL;
2037
2038 memset(data, 0, ee->len);
2039
2040 while (i < ee->len) {
2041 en_dbg(DRV, priv,
2042 "mlx4_get_module_info i(%d) offset(%d) len(%d)\n",
2043 i, offset, ee->len - i);
2044
2045 ret = mlx4_get_module_info(mdev->dev, priv->port,
2046 offset, ee->len - i, data + i);
2047
2048 if (!ret)
2049 return 0;
2050
2051 if (ret < 0) {
2052 en_err(priv,
2053 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n",
2054 i, offset, ee->len - i, ret);
2055 return 0;
2056 }
2057
2058 i += ret;
2059 offset += ret;
2060 }
2061 return 0;
2062}
2063
2064static int mlx4_en_set_phys_id(struct net_device *dev,
2065 enum ethtool_phys_id_state state)
2066{
2067 int err;
2068 u16 beacon_duration;
2069 struct mlx4_en_priv *priv = netdev_priv(dev);
2070 struct mlx4_en_dev *mdev = priv->mdev;
2071
2072 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_BEACON))
2073 return -EOPNOTSUPP;
2074
2075 switch (state) {
2076 case ETHTOOL_ID_ACTIVE:
2077 beacon_duration = PORT_BEACON_MAX_LIMIT;
2078 break;
2079 case ETHTOOL_ID_INACTIVE:
2080 beacon_duration = 0;
2081 break;
2082 default:
2083 return -EOPNOTSUPP;
2084 }
2085
2086 err = mlx4_SET_PORT_BEACON(mdev->dev, priv->port, beacon_duration);
2087 return err;
2088}
2089
2090const struct ethtool_ops mlx4_en_ethtool_ops = {
2091 .get_drvinfo = mlx4_en_get_drvinfo,
2092 .get_link_ksettings = mlx4_en_get_link_ksettings,
2093 .set_link_ksettings = mlx4_en_set_link_ksettings,
2094 .get_link = ethtool_op_get_link,
2095 .get_strings = mlx4_en_get_strings,
2096 .get_sset_count = mlx4_en_get_sset_count,
2097 .get_ethtool_stats = mlx4_en_get_ethtool_stats,
2098 .self_test = mlx4_en_self_test,
2099 .set_phys_id = mlx4_en_set_phys_id,
2100 .get_wol = mlx4_en_get_wol,
2101 .set_wol = mlx4_en_set_wol,
2102 .get_msglevel = mlx4_en_get_msglevel,
2103 .set_msglevel = mlx4_en_set_msglevel,
2104 .get_coalesce = mlx4_en_get_coalesce,
2105 .set_coalesce = mlx4_en_set_coalesce,
2106 .get_pauseparam = mlx4_en_get_pauseparam,
2107 .set_pauseparam = mlx4_en_set_pauseparam,
2108 .get_ringparam = mlx4_en_get_ringparam,
2109 .set_ringparam = mlx4_en_set_ringparam,
2110 .get_rxnfc = mlx4_en_get_rxnfc,
2111 .set_rxnfc = mlx4_en_set_rxnfc,
2112 .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size,
2113 .get_rxfh_key_size = mlx4_en_get_rxfh_key_size,
2114 .get_rxfh = mlx4_en_get_rxfh,
2115 .set_rxfh = mlx4_en_set_rxfh,
2116 .get_channels = mlx4_en_get_channels,
2117 .set_channels = mlx4_en_set_channels,
2118 .get_ts_info = mlx4_en_get_ts_info,
2119 .set_priv_flags = mlx4_en_set_priv_flags,
2120 .get_priv_flags = mlx4_en_get_priv_flags,
2121 .get_tunable = mlx4_en_get_tunable,
2122 .set_tunable = mlx4_en_set_tunable,
2123 .get_module_info = mlx4_en_get_module_info,
2124 .get_module_eeprom = mlx4_en_get_module_eeprom
2125};
2126
2127
2128
2129
2130
2131
