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37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
40#include <linux/pci.h>
41#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
52#include <linux/list.h>
53#include <linux/notifier.h>
54#include <linux/dcbnl.h>
55#include <linux/inetdevice.h>
56#include <linux/netlink.h>
57#include <net/switchdev.h>
58#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
60#include <net/netevent.h>
61#include <net/tc_act/tc_sample.h>
62#include <net/addrconf.h>
63
64#include "l3mdev.h"
65#include "spectrum.h"
66#include "pci.h"
67#include "core.h"
68#include "reg.h"
69#include "port.h"
70#include "trap.h"
71#include "txheader.h"
72#include "spectrum_cnt.h"
73#include "spectrum_dpipe.h"
74#include "spectrum_acl_flex_actions.h"
75#include "spectrum_span.h"
76#include "../mlxfw/mlxfw.h"
77
78#define MLXSW_FWREV_MAJOR 13
79#define MLXSW_FWREV_MINOR 1620
80#define MLXSW_FWREV_SUBMINOR 192
81#define MLXSW_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
82
83#define MLXSW_SP_FW_FILENAME \
84 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
85 "." __stringify(MLXSW_FWREV_MINOR) \
86 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
87
88static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
89static const char mlxsw_sp_driver_version[] = "1.0";
90
91
92
93
94
95MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
96
97
98
99
100
101
102MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
103
104
105
106
107MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
108
109
110
111
112MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
113
114
115
116
117
118MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
119
120
121
122
123MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
124
125
126
127
128
129MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
130
131
132
133
134MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
135
136
137
138
139
140
141
142
143
144MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
145
146
147
148
149
150
151MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
152
153
154
155
156
157MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
158
159struct mlxsw_sp_mlxfw_dev {
160 struct mlxfw_dev mlxfw_dev;
161 struct mlxsw_sp *mlxsw_sp;
162};
163
164static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
165 u16 component_index, u32 *p_max_size,
166 u8 *p_align_bits, u16 *p_max_write_size)
167{
168 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
169 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
170 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
171 char mcqi_pl[MLXSW_REG_MCQI_LEN];
172 int err;
173
174 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
175 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
176 if (err)
177 return err;
178 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
179 p_max_write_size);
180
181 *p_align_bits = max_t(u8, *p_align_bits, 2);
182 *p_max_write_size = min_t(u16, *p_max_write_size,
183 MLXSW_REG_MCDA_MAX_DATA_LEN);
184 return 0;
185}
186
187static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
188{
189 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
190 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
191 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
192 char mcc_pl[MLXSW_REG_MCC_LEN];
193 u8 control_state;
194 int err;
195
196 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
197 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
198 if (err)
199 return err;
200
201 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
202 if (control_state != MLXFW_FSM_STATE_IDLE)
203 return -EBUSY;
204
205 mlxsw_reg_mcc_pack(mcc_pl,
206 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
207 0, *fwhandle, 0);
208 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
209}
210
211static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
212 u32 fwhandle, u16 component_index,
213 u32 component_size)
214{
215 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
216 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
217 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
218 char mcc_pl[MLXSW_REG_MCC_LEN];
219
220 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
221 component_index, fwhandle, component_size);
222 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
223}
224
225static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
226 u32 fwhandle, u8 *data, u16 size,
227 u32 offset)
228{
229 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
230 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
231 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
232 char mcda_pl[MLXSW_REG_MCDA_LEN];
233
234 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
235 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
236}
237
238static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
239 u32 fwhandle, u16 component_index)
240{
241 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
242 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
243 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
244 char mcc_pl[MLXSW_REG_MCC_LEN];
245
246 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
247 component_index, fwhandle, 0);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
249}
250
251static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
252{
253 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
254 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
255 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
256 char mcc_pl[MLXSW_REG_MCC_LEN];
257
258 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
259 fwhandle, 0);
260 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
261}
262
263static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
264 enum mlxfw_fsm_state *fsm_state,
265 enum mlxfw_fsm_state_err *fsm_state_err)
266{
267 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
268 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
269 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
270 char mcc_pl[MLXSW_REG_MCC_LEN];
271 u8 control_state;
272 u8 error_code;
273 int err;
274
275 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
276 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
277 if (err)
278 return err;
279
280 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
281 *fsm_state = control_state;
282 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
283 MLXFW_FSM_STATE_ERR_MAX);
284 return 0;
285}
286
287static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
288{
289 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
290 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
291 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
292 char mcc_pl[MLXSW_REG_MCC_LEN];
293
294 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
295 fwhandle, 0);
296 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
297}
298
299static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
300{
301 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
302 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
303 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
304 char mcc_pl[MLXSW_REG_MCC_LEN];
305
306 mlxsw_reg_mcc_pack(mcc_pl,
307 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
308 fwhandle, 0);
309 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
310}
311
312static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
313 .component_query = mlxsw_sp_component_query,
314 .fsm_lock = mlxsw_sp_fsm_lock,
315 .fsm_component_update = mlxsw_sp_fsm_component_update,
316 .fsm_block_download = mlxsw_sp_fsm_block_download,
317 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
318 .fsm_activate = mlxsw_sp_fsm_activate,
319 .fsm_query_state = mlxsw_sp_fsm_query_state,
320 .fsm_cancel = mlxsw_sp_fsm_cancel,
321 .fsm_release = mlxsw_sp_fsm_release
322};
323
324static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
325 const struct firmware *firmware)
326{
327 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
328 .mlxfw_dev = {
329 .ops = &mlxsw_sp_mlxfw_dev_ops,
330 .psid = mlxsw_sp->bus_info->psid,
331 .psid_size = strlen(mlxsw_sp->bus_info->psid),
332 },
333 .mlxsw_sp = mlxsw_sp
334 };
335
336 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
337}
338
339static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
340{
341 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
342 const struct firmware *firmware;
343 int err;
344
345
346 if (rev->major != MLXSW_FWREV_MAJOR) {
347 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
348 rev->major, MLXSW_FWREV_MAJOR);
349 return -EINVAL;
350 }
351 if (MLXSW_FWREV_MINOR_TO_BRANCH(rev->minor) ==
352 MLXSW_FWREV_MINOR_TO_BRANCH(MLXSW_FWREV_MINOR))
353 return 0;
354
355 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
356 rev->major, rev->minor, rev->subminor);
357 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
358 MLXSW_SP_FW_FILENAME);
359
360 err = request_firmware(&firmware, MLXSW_SP_FW_FILENAME,
361 mlxsw_sp->bus_info->dev);
362 if (err) {
363 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
364 MLXSW_SP_FW_FILENAME);
365 return err;
366 }
367
368 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
369 release_firmware(firmware);
370 return err;
371}
372
373int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
374 unsigned int counter_index, u64 *packets,
375 u64 *bytes)
376{
377 char mgpc_pl[MLXSW_REG_MGPC_LEN];
378 int err;
379
380 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
381 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
382 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
383 if (err)
384 return err;
385 if (packets)
386 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
387 if (bytes)
388 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
389 return 0;
390}
391
392static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
393 unsigned int counter_index)
394{
395 char mgpc_pl[MLXSW_REG_MGPC_LEN];
396
397 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
398 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
399 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
400}
401
402int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
403 unsigned int *p_counter_index)
404{
405 int err;
406
407 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
408 p_counter_index);
409 if (err)
410 return err;
411 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
412 if (err)
413 goto err_counter_clear;
414 return 0;
415
416err_counter_clear:
417 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
418 *p_counter_index);
419 return err;
420}
421
422void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
423 unsigned int counter_index)
424{
425 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
426 counter_index);
427}
428
429static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
430 const struct mlxsw_tx_info *tx_info)
431{
432 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
433
434 memset(txhdr, 0, MLXSW_TXHDR_LEN);
435
436 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
437 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
438 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
439 mlxsw_tx_hdr_swid_set(txhdr, 0);
440 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
441 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
442 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
443}
444
445int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
446 u8 state)
447{
448 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
449 enum mlxsw_reg_spms_state spms_state;
450 char *spms_pl;
451 int err;
452
453 switch (state) {
454 case BR_STATE_FORWARDING:
455 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
456 break;
457 case BR_STATE_LEARNING:
458 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
459 break;
460 case BR_STATE_LISTENING:
461 case BR_STATE_DISABLED:
462 case BR_STATE_BLOCKING:
463 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
464 break;
465 default:
466 BUG();
467 }
468
469 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
470 if (!spms_pl)
471 return -ENOMEM;
472 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
473 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
474
475 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
476 kfree(spms_pl);
477 return err;
478}
479
480static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
481{
482 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
483 int err;
484
485 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
486 if (err)
487 return err;
488 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
489 return 0;
490}
491
492static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
493 bool enable, u32 rate)
494{
495 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
496 char mpsc_pl[MLXSW_REG_MPSC_LEN];
497
498 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
499 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
500}
501
502static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
503 bool is_up)
504{
505 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
506 char paos_pl[MLXSW_REG_PAOS_LEN];
507
508 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
509 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
510 MLXSW_PORT_ADMIN_STATUS_DOWN);
511 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
512}
513
514static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
515 unsigned char *addr)
516{
517 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
518 char ppad_pl[MLXSW_REG_PPAD_LEN];
519
520 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
521 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
522 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
523}
524
525static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
526{
527 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
528 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
529
530 ether_addr_copy(addr, mlxsw_sp->base_mac);
531 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
532 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
533}
534
535static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
536{
537 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
538 char pmtu_pl[MLXSW_REG_PMTU_LEN];
539 int max_mtu;
540 int err;
541
542 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
543 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
544 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
545 if (err)
546 return err;
547 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
548
549 if (mtu > max_mtu)
550 return -EINVAL;
551
552 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
553 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
554}
555
556static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
557{
558 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
559 char pspa_pl[MLXSW_REG_PSPA_LEN];
560
561 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
562 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
563}
564
565int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
566{
567 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
568 char svpe_pl[MLXSW_REG_SVPE_LEN];
569
570 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
571 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
572}
573
574int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
575 bool learn_enable)
576{
577 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
578 char *spvmlr_pl;
579 int err;
580
581 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
582 if (!spvmlr_pl)
583 return -ENOMEM;
584 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
585 learn_enable);
586 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
587 kfree(spvmlr_pl);
588 return err;
589}
590
591static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
592 u16 vid)
593{
594 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
595 char spvid_pl[MLXSW_REG_SPVID_LEN];
596
597 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
598 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
599}
600
601static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
602 bool allow)
603{
604 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
605 char spaft_pl[MLXSW_REG_SPAFT_LEN];
606
607 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
608 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
609}
610
611int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
612{
613 int err;
614
615 if (!vid) {
616 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
617 if (err)
618 return err;
619 } else {
620 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
621 if (err)
622 return err;
623 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
624 if (err)
625 goto err_port_allow_untagged_set;
626 }
627
628 mlxsw_sp_port->pvid = vid;
629 return 0;
630
631err_port_allow_untagged_set:
632 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
633 return err;
634}
635
636static int
637mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
638{
639 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
640 char sspr_pl[MLXSW_REG_SSPR_LEN];
641
642 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
643 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
644}
645
646static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
647 u8 local_port, u8 *p_module,
648 u8 *p_width, u8 *p_lane)
649{
650 char pmlp_pl[MLXSW_REG_PMLP_LEN];
651 int err;
652
653 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
654 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
655 if (err)
656 return err;
657 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
658 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
659 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
660 return 0;
661}
662
663static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
664 u8 module, u8 width, u8 lane)
665{
666 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
667 char pmlp_pl[MLXSW_REG_PMLP_LEN];
668 int i;
669
670 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
671 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
672 for (i = 0; i < width; i++) {
673 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
674 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i);
675 }
676
677 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
678}
679
680static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
681{
682 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
683 char pmlp_pl[MLXSW_REG_PMLP_LEN];
684
685 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
686 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
687 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
688}
689
690static int mlxsw_sp_port_open(struct net_device *dev)
691{
692 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
693 int err;
694
695 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
696 if (err)
697 return err;
698 netif_start_queue(dev);
699 return 0;
700}
701
702static int mlxsw_sp_port_stop(struct net_device *dev)
703{
704 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
705
706 netif_stop_queue(dev);
707 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
708}
709
710static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
711 struct net_device *dev)
712{
713 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
714 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
715 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
716 const struct mlxsw_tx_info tx_info = {
717 .local_port = mlxsw_sp_port->local_port,
718 .is_emad = false,
719 };
720 u64 len;
721 int err;
722
723 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
724 return NETDEV_TX_BUSY;
725
726 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
727 struct sk_buff *skb_orig = skb;
728
729 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
730 if (!skb) {
731 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
732 dev_kfree_skb_any(skb_orig);
733 return NETDEV_TX_OK;
734 }
735 dev_consume_skb_any(skb_orig);
736 }
737
738 if (eth_skb_pad(skb)) {
739 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
740 return NETDEV_TX_OK;
741 }
742
743 mlxsw_sp_txhdr_construct(skb, &tx_info);
744
745
746
747 len = skb->len - MLXSW_TXHDR_LEN;
748
749
750
751
752 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
753
754 if (!err) {
755 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
756 u64_stats_update_begin(&pcpu_stats->syncp);
757 pcpu_stats->tx_packets++;
758 pcpu_stats->tx_bytes += len;
759 u64_stats_update_end(&pcpu_stats->syncp);
760 } else {
761 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
762 dev_kfree_skb_any(skb);
763 }
764 return NETDEV_TX_OK;
765}
766
767static void mlxsw_sp_set_rx_mode(struct net_device *dev)
768{
769}
770
771static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
772{
773 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
774 struct sockaddr *addr = p;
775 int err;
776
777 if (!is_valid_ether_addr(addr->sa_data))
778 return -EADDRNOTAVAIL;
779
780 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
781 if (err)
782 return err;
783 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
784 return 0;
785}
786
787static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
788 int mtu)
789{
790 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
791}
792
793#define MLXSW_SP_CELL_FACTOR 2
794
795static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
796 u16 delay)
797{
798 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
799 BITS_PER_BYTE));
800 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
801 mtu);
802}
803
804
805
806
807#define MLXSW_SP_PAUSE_DELAY 58752
808
809static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
810 u16 delay, bool pfc, bool pause)
811{
812 if (pfc)
813 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
814 else if (pause)
815 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
816 else
817 return 0;
818}
819
820static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
821 bool lossy)
822{
823 if (lossy)
824 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
825 else
826 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
827 thres);
828}
829
830int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
831 u8 *prio_tc, bool pause_en,
832 struct ieee_pfc *my_pfc)
833{
834 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
835 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
836 u16 delay = !!my_pfc ? my_pfc->delay : 0;
837 char pbmc_pl[MLXSW_REG_PBMC_LEN];
838 int i, j, err;
839
840 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
841 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
842 if (err)
843 return err;
844
845 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
846 bool configure = false;
847 bool pfc = false;
848 bool lossy;
849 u16 thres;
850
851 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
852 if (prio_tc[j] == i) {
853 pfc = pfc_en & BIT(j);
854 configure = true;
855 break;
856 }
857 }
858
859 if (!configure)
860 continue;
861
862 lossy = !(pfc || pause_en);
863 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
864 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
865 pause_en);
866 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
867 }
868
869 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
870}
871
872static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
873 int mtu, bool pause_en)
874{
875 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
876 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
877 struct ieee_pfc *my_pfc;
878 u8 *prio_tc;
879
880 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
881 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
882
883 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
884 pause_en, my_pfc);
885}
886
887static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
888{
889 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
890 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
891 int err;
892
893 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
894 if (err)
895 return err;
896 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
897 if (err)
898 goto err_span_port_mtu_update;
899 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
900 if (err)
901 goto err_port_mtu_set;
902 dev->mtu = mtu;
903 return 0;
904
905err_port_mtu_set:
906 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
907err_span_port_mtu_update:
908 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
909 return err;
910}
911
912static int
913mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
914 struct rtnl_link_stats64 *stats)
915{
916 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
917 struct mlxsw_sp_port_pcpu_stats *p;
918 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
919 u32 tx_dropped = 0;
920 unsigned int start;
921 int i;
922
923 for_each_possible_cpu(i) {
924 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
925 do {
926 start = u64_stats_fetch_begin_irq(&p->syncp);
927 rx_packets = p->rx_packets;
928 rx_bytes = p->rx_bytes;
929 tx_packets = p->tx_packets;
930 tx_bytes = p->tx_bytes;
931 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
932
933 stats->rx_packets += rx_packets;
934 stats->rx_bytes += rx_bytes;
935 stats->tx_packets += tx_packets;
936 stats->tx_bytes += tx_bytes;
937
938 tx_dropped += p->tx_dropped;
939 }
940 stats->tx_dropped = tx_dropped;
941 return 0;
942}
943
944static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
945{
946 switch (attr_id) {
947 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
948 return true;
949 }
950
951 return false;
952}
953
954static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
955 void *sp)
956{
957 switch (attr_id) {
958 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
959 return mlxsw_sp_port_get_sw_stats64(dev, sp);
960 }
961
962 return -EINVAL;
963}
964
965static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
966 int prio, char *ppcnt_pl)
967{
968 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
969 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
970
971 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
972 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
973}
974
975static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
976 struct rtnl_link_stats64 *stats)
977{
978 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
979 int err;
980
981 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
982 0, ppcnt_pl);
983 if (err)
984 goto out;
985
986 stats->tx_packets =
987 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
988 stats->rx_packets =
989 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
990 stats->tx_bytes =
991 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
992 stats->rx_bytes =
993 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
994 stats->multicast =
995 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
996
997 stats->rx_crc_errors =
998 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
999 stats->rx_frame_errors =
1000 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1001
1002 stats->rx_length_errors = (
1003 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1004 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1005 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1006
1007 stats->rx_errors = (stats->rx_crc_errors +
1008 stats->rx_frame_errors + stats->rx_length_errors);
1009
1010out:
1011 return err;
1012}
1013
1014static void
1015mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1016 struct mlxsw_sp_port_xstats *xstats)
1017{
1018 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1019 int err, i;
1020
1021 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1022 ppcnt_pl);
1023 if (!err)
1024 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1025
1026 for (i = 0; i < TC_MAX_QUEUE; i++) {
1027 err = mlxsw_sp_port_get_stats_raw(dev,
1028 MLXSW_REG_PPCNT_TC_CONG_TC,
1029 i, ppcnt_pl);
1030 if (!err)
1031 xstats->wred_drop[i] =
1032 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1033
1034 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1035 i, ppcnt_pl);
1036 if (err)
1037 continue;
1038
1039 xstats->backlog[i] =
1040 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1041 xstats->tail_drop[i] =
1042 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1043 }
1044
1045 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1046 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1047 i, ppcnt_pl);
1048 if (err)
1049 continue;
1050
1051 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1052 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1053 }
1054}
1055
1056static void update_stats_cache(struct work_struct *work)
1057{
1058 struct mlxsw_sp_port *mlxsw_sp_port =
1059 container_of(work, struct mlxsw_sp_port,
1060 periodic_hw_stats.update_dw.work);
1061
1062 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1063 goto out;
1064
1065 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1066 &mlxsw_sp_port->periodic_hw_stats.stats);
1067 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1068 &mlxsw_sp_port->periodic_hw_stats.xstats);
1069
1070out:
1071 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1072 MLXSW_HW_STATS_UPDATE_TIME);
1073}
1074
1075
1076
1077
1078static void
1079mlxsw_sp_port_get_stats64(struct net_device *dev,
1080 struct rtnl_link_stats64 *stats)
1081{
1082 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1083
1084 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
1085}
1086
1087static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1088 u16 vid_begin, u16 vid_end,
1089 bool is_member, bool untagged)
1090{
1091 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1092 char *spvm_pl;
1093 int err;
1094
1095 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1096 if (!spvm_pl)
1097 return -ENOMEM;
1098
1099 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1100 vid_end, is_member, untagged);
1101 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1102 kfree(spvm_pl);
1103 return err;
1104}
1105
1106int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1107 u16 vid_end, bool is_member, bool untagged)
1108{
1109 u16 vid, vid_e;
1110 int err;
1111
1112 for (vid = vid_begin; vid <= vid_end;
1113 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1114 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1115 vid_end);
1116
1117 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1118 is_member, untagged);
1119 if (err)
1120 return err;
1121 }
1122
1123 return 0;
1124}
1125
1126static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
1127{
1128 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
1129
1130 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1131 &mlxsw_sp_port->vlans_list, list)
1132 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
1133}
1134
1135static struct mlxsw_sp_port_vlan *
1136mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1137{
1138 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1139 bool untagged = vid == 1;
1140 int err;
1141
1142 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1143 if (err)
1144 return ERR_PTR(err);
1145
1146 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1147 if (!mlxsw_sp_port_vlan) {
1148 err = -ENOMEM;
1149 goto err_port_vlan_alloc;
1150 }
1151
1152 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1153 mlxsw_sp_port_vlan->ref_count = 1;
1154 mlxsw_sp_port_vlan->vid = vid;
1155 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1156
1157 return mlxsw_sp_port_vlan;
1158
1159err_port_vlan_alloc:
1160 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1161 return ERR_PTR(err);
1162}
1163
1164static void
1165mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1166{
1167 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1168 u16 vid = mlxsw_sp_port_vlan->vid;
1169
1170 list_del(&mlxsw_sp_port_vlan->list);
1171 kfree(mlxsw_sp_port_vlan);
1172 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1173}
1174
1175struct mlxsw_sp_port_vlan *
1176mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1177{
1178 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1179
1180 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1181 if (mlxsw_sp_port_vlan) {
1182 mlxsw_sp_port_vlan->ref_count++;
1183 return mlxsw_sp_port_vlan;
1184 }
1185
1186 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1187}
1188
1189void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1190{
1191 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1192
1193 if (--mlxsw_sp_port_vlan->ref_count != 0)
1194 return;
1195
1196 if (mlxsw_sp_port_vlan->bridge_port)
1197 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
1198 else if (fid)
1199 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
1200
1201 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1202}
1203
1204static int mlxsw_sp_port_add_vid(struct net_device *dev,
1205 __be16 __always_unused proto, u16 vid)
1206{
1207 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1208
1209
1210
1211
1212 if (!vid)
1213 return 0;
1214
1215 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
1216}
1217
1218static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1219 __be16 __always_unused proto, u16 vid)
1220{
1221 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1222 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1223
1224
1225
1226
1227 if (!vid)
1228 return 0;
1229
1230 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1231 if (!mlxsw_sp_port_vlan)
1232 return 0;
1233 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
1234
1235 return 0;
1236}
1237
1238static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1239 size_t len)
1240{
1241 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1242 u8 module = mlxsw_sp_port->mapping.module;
1243 u8 width = mlxsw_sp_port->mapping.width;
1244 u8 lane = mlxsw_sp_port->mapping.lane;
1245 int err;
1246
1247 if (!mlxsw_sp_port->split)
1248 err = snprintf(name, len, "p%d", module + 1);
1249 else
1250 err = snprintf(name, len, "p%ds%d", module + 1,
1251 lane / width);
1252
1253 if (err >= len)
1254 return -EINVAL;
1255
1256 return 0;
1257}
1258
1259static struct mlxsw_sp_port_mall_tc_entry *
1260mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1261 unsigned long cookie) {
1262 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1263
1264 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1265 if (mall_tc_entry->cookie == cookie)
1266 return mall_tc_entry;
1267
1268 return NULL;
1269}
1270
1271static int
1272mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1273 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
1274 const struct tc_action *a,
1275 bool ingress)
1276{
1277 enum mlxsw_sp_span_type span_type;
1278 struct net_device *to_dev;
1279
1280 to_dev = tcf_mirred_dev(a);
1281 if (!to_dev) {
1282 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1283 return -EINVAL;
1284 }
1285
1286 mirror->ingress = ingress;
1287 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1288 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type,
1289 true, &mirror->span_id);
1290}
1291
1292static void
1293mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1294 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1295{
1296 enum mlxsw_sp_span_type span_type;
1297
1298 span_type = mirror->ingress ?
1299 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1300 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
1301 span_type, true);
1302}
1303
1304static int
1305mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1306 struct tc_cls_matchall_offload *cls,
1307 const struct tc_action *a,
1308 bool ingress)
1309{
1310 int err;
1311
1312 if (!mlxsw_sp_port->sample)
1313 return -EOPNOTSUPP;
1314 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1315 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1316 return -EEXIST;
1317 }
1318 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1319 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1320 return -EOPNOTSUPP;
1321 }
1322
1323 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1324 tcf_sample_psample_group(a));
1325 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1326 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1327 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1328
1329 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1330 if (err)
1331 goto err_port_sample_set;
1332 return 0;
1333
1334err_port_sample_set:
1335 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1336 return err;
1337}
1338
1339static void
1340mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1341{
1342 if (!mlxsw_sp_port->sample)
1343 return;
1344
1345 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1346 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1347}
1348
1349static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1350 struct tc_cls_matchall_offload *f,
1351 bool ingress)
1352{
1353 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1354 __be16 protocol = f->common.protocol;
1355 const struct tc_action *a;
1356 LIST_HEAD(actions);
1357 int err;
1358
1359 if (!tcf_exts_has_one_action(f->exts)) {
1360 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1361 return -EOPNOTSUPP;
1362 }
1363
1364 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1365 if (!mall_tc_entry)
1366 return -ENOMEM;
1367 mall_tc_entry->cookie = f->cookie;
1368
1369 tcf_exts_to_list(f->exts, &actions);
1370 a = list_first_entry(&actions, struct tc_action, list);
1371
1372 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1373 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1374
1375 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1376 mirror = &mall_tc_entry->mirror;
1377 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1378 mirror, a, ingress);
1379 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1380 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1381 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
1382 a, ingress);
1383 } else {
1384 err = -EOPNOTSUPP;
1385 }
1386
1387 if (err)
1388 goto err_add_action;
1389
1390 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1391 return 0;
1392
1393err_add_action:
1394 kfree(mall_tc_entry);
1395 return err;
1396}
1397
1398static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1399 struct tc_cls_matchall_offload *f)
1400{
1401 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1402
1403 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1404 f->cookie);
1405 if (!mall_tc_entry) {
1406 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1407 return;
1408 }
1409 list_del(&mall_tc_entry->list);
1410
1411 switch (mall_tc_entry->type) {
1412 case MLXSW_SP_PORT_MALL_MIRROR:
1413 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1414 &mall_tc_entry->mirror);
1415 break;
1416 case MLXSW_SP_PORT_MALL_SAMPLE:
1417 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1418 break;
1419 default:
1420 WARN_ON(1);
1421 }
1422
1423 kfree(mall_tc_entry);
1424}
1425
1426static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1427 struct tc_cls_matchall_offload *f,
1428 bool ingress)
1429{
1430 switch (f->command) {
1431 case TC_CLSMATCHALL_REPLACE:
1432 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
1433 ingress);
1434 case TC_CLSMATCHALL_DESTROY:
1435 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1436 return 0;
1437 default:
1438 return -EOPNOTSUPP;
1439 }
1440}
1441
1442static int
1443mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1444 struct tc_cls_flower_offload *f)
1445{
1446 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1447
1448 switch (f->command) {
1449 case TC_CLSFLOWER_REPLACE:
1450 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
1451 case TC_CLSFLOWER_DESTROY:
1452 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
1453 return 0;
1454 case TC_CLSFLOWER_STATS:
1455 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
1456 default:
1457 return -EOPNOTSUPP;
1458 }
1459}
1460
1461static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1462 void *type_data,
1463 void *cb_priv, bool ingress)
1464{
1465 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1466
1467 switch (type) {
1468 case TC_SETUP_CLSMATCHALL:
1469 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1470 type_data))
1471 return -EOPNOTSUPP;
1472
1473 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1474 ingress);
1475 case TC_SETUP_CLSFLOWER:
1476 return 0;
1477 default:
1478 return -EOPNOTSUPP;
1479 }
1480}
1481
1482static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1483 void *type_data,
1484 void *cb_priv)
1485{
1486 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1487 cb_priv, true);
1488}
1489
1490static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1491 void *type_data,
1492 void *cb_priv)
1493{
1494 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1495 cb_priv, false);
1496}
1497
1498static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1499 void *type_data, void *cb_priv)
1500{
1501 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1502
1503 switch (type) {
1504 case TC_SETUP_CLSMATCHALL:
1505 return 0;
1506 case TC_SETUP_CLSFLOWER:
1507 if (mlxsw_sp_acl_block_disabled(acl_block))
1508 return -EOPNOTSUPP;
1509
1510 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1511 default:
1512 return -EOPNOTSUPP;
1513 }
1514}
1515
1516static int
1517mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1518 struct tcf_block *block, bool ingress)
1519{
1520 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1521 struct mlxsw_sp_acl_block *acl_block;
1522 struct tcf_block_cb *block_cb;
1523 int err;
1524
1525 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1526 mlxsw_sp);
1527 if (!block_cb) {
1528 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1529 if (!acl_block)
1530 return -ENOMEM;
1531 block_cb = __tcf_block_cb_register(block,
1532 mlxsw_sp_setup_tc_block_cb_flower,
1533 mlxsw_sp, acl_block);
1534 if (IS_ERR(block_cb)) {
1535 err = PTR_ERR(block_cb);
1536 goto err_cb_register;
1537 }
1538 } else {
1539 acl_block = tcf_block_cb_priv(block_cb);
1540 }
1541 tcf_block_cb_incref(block_cb);
1542 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1543 mlxsw_sp_port, ingress);
1544 if (err)
1545 goto err_block_bind;
1546
1547 if (ingress)
1548 mlxsw_sp_port->ing_acl_block = acl_block;
1549 else
1550 mlxsw_sp_port->eg_acl_block = acl_block;
1551
1552 return 0;
1553
1554err_block_bind:
1555 if (!tcf_block_cb_decref(block_cb)) {
1556 __tcf_block_cb_unregister(block_cb);
1557err_cb_register:
1558 mlxsw_sp_acl_block_destroy(acl_block);
1559 }
1560 return err;
1561}
1562
1563static void
1564mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1565 struct tcf_block *block, bool ingress)
1566{
1567 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1568 struct mlxsw_sp_acl_block *acl_block;
1569 struct tcf_block_cb *block_cb;
1570 int err;
1571
1572 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1573 mlxsw_sp);
1574 if (!block_cb)
1575 return;
1576
1577 if (ingress)
1578 mlxsw_sp_port->ing_acl_block = NULL;
1579 else
1580 mlxsw_sp_port->eg_acl_block = NULL;
1581
1582 acl_block = tcf_block_cb_priv(block_cb);
1583 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1584 mlxsw_sp_port, ingress);
1585 if (!err && !tcf_block_cb_decref(block_cb)) {
1586 __tcf_block_cb_unregister(block_cb);
1587 mlxsw_sp_acl_block_destroy(acl_block);
1588 }
1589}
1590
1591static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1592 struct tc_block_offload *f)
1593{
1594 tc_setup_cb_t *cb;
1595 bool ingress;
1596 int err;
1597
1598 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1599 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1600 ingress = true;
1601 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1602 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1603 ingress = false;
1604 } else {
1605 return -EOPNOTSUPP;
1606 }
1607
1608 switch (f->command) {
1609 case TC_BLOCK_BIND:
1610 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1611 mlxsw_sp_port);
1612 if (err)
1613 return err;
1614 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1615 f->block, ingress);
1616 if (err) {
1617 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1618 return err;
1619 }
1620 return 0;
1621 case TC_BLOCK_UNBIND:
1622 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1623 f->block, ingress);
1624 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1625 return 0;
1626 default:
1627 return -EOPNOTSUPP;
1628 }
1629}
1630
1631static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
1632 void *type_data)
1633{
1634 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1635
1636 switch (type) {
1637 case TC_SETUP_BLOCK:
1638 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
1639 case TC_SETUP_QDISC_RED:
1640 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
1641 case TC_SETUP_QDISC_PRIO:
1642 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
1643 default:
1644 return -EOPNOTSUPP;
1645 }
1646}
1647
1648
1649static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1650{
1651 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1652
1653 if (!enable) {
1654 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1655 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1656 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1657 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1658 return -EINVAL;
1659 }
1660 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1661 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1662 } else {
1663 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1664 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
1665 }
1666 return 0;
1667}
1668
1669typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1670
1671static int mlxsw_sp_handle_feature(struct net_device *dev,
1672 netdev_features_t wanted_features,
1673 netdev_features_t feature,
1674 mlxsw_sp_feature_handler feature_handler)
1675{
1676 netdev_features_t changes = wanted_features ^ dev->features;
1677 bool enable = !!(wanted_features & feature);
1678 int err;
1679
1680 if (!(changes & feature))
1681 return 0;
1682
1683 err = feature_handler(dev, enable);
1684 if (err) {
1685 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1686 enable ? "Enable" : "Disable", &feature, err);
1687 return err;
1688 }
1689
1690 if (enable)
1691 dev->features |= feature;
1692 else
1693 dev->features &= ~feature;
1694
1695 return 0;
1696}
1697static int mlxsw_sp_set_features(struct net_device *dev,
1698 netdev_features_t features)
1699{
1700 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1701 mlxsw_sp_feature_hw_tc);
1702}
1703
1704static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1705 .ndo_size = sizeof(struct net_device_ops),
1706 .ndo_open = mlxsw_sp_port_open,
1707 .ndo_stop = mlxsw_sp_port_stop,
1708 .ndo_start_xmit = mlxsw_sp_port_xmit,
1709 .extended.ndo_setup_tc_rh = mlxsw_sp_setup_tc,
1710 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
1711 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1712 .extended.ndo_change_mtu = mlxsw_sp_port_change_mtu,
1713 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
1714 .extended.ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1715 .extended.ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
1716 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1717 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1718 .extended.ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
1719 .ndo_set_features = mlxsw_sp_set_features,
1720};
1721
1722static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1723 struct ethtool_drvinfo *drvinfo)
1724{
1725 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1726 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1727
1728 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1729 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1730 sizeof(drvinfo->version));
1731 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1732 "%d.%d.%d",
1733 mlxsw_sp->bus_info->fw_rev.major,
1734 mlxsw_sp->bus_info->fw_rev.minor,
1735 mlxsw_sp->bus_info->fw_rev.subminor);
1736 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1737 sizeof(drvinfo->bus_info));
1738}
1739
1740static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1741 struct ethtool_pauseparam *pause)
1742{
1743 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1744
1745 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1746 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1747}
1748
1749static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1750 struct ethtool_pauseparam *pause)
1751{
1752 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1753
1754 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1755 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1756 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1757
1758 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1759 pfcc_pl);
1760}
1761
1762static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1763 struct ethtool_pauseparam *pause)
1764{
1765 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1766 bool pause_en = pause->tx_pause || pause->rx_pause;
1767 int err;
1768
1769 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1770 netdev_err(dev, "PFC already enabled on port\n");
1771 return -EINVAL;
1772 }
1773
1774 if (pause->autoneg) {
1775 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1776 return -EINVAL;
1777 }
1778
1779 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1780 if (err) {
1781 netdev_err(dev, "Failed to configure port's headroom\n");
1782 return err;
1783 }
1784
1785 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1786 if (err) {
1787 netdev_err(dev, "Failed to set PAUSE parameters\n");
1788 goto err_port_pause_configure;
1789 }
1790
1791 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1792 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1793
1794 return 0;
1795
1796err_port_pause_configure:
1797 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1798 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1799 return err;
1800}
1801
1802struct mlxsw_sp_port_hw_stats {
1803 char str[ETH_GSTRING_LEN];
1804 u64 (*getter)(const char *payload);
1805 bool cells_bytes;
1806};
1807
1808static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1809 {
1810 .str = "a_frames_transmitted_ok",
1811 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1812 },
1813 {
1814 .str = "a_frames_received_ok",
1815 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1816 },
1817 {
1818 .str = "a_frame_check_sequence_errors",
1819 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1820 },
1821 {
1822 .str = "a_alignment_errors",
1823 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1824 },
1825 {
1826 .str = "a_octets_transmitted_ok",
1827 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1828 },
1829 {
1830 .str = "a_octets_received_ok",
1831 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1832 },
1833 {
1834 .str = "a_multicast_frames_xmitted_ok",
1835 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1836 },
1837 {
1838 .str = "a_broadcast_frames_xmitted_ok",
1839 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1840 },
1841 {
1842 .str = "a_multicast_frames_received_ok",
1843 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1844 },
1845 {
1846 .str = "a_broadcast_frames_received_ok",
1847 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1848 },
1849 {
1850 .str = "a_in_range_length_errors",
1851 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1852 },
1853 {
1854 .str = "a_out_of_range_length_field",
1855 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1856 },
1857 {
1858 .str = "a_frame_too_long_errors",
1859 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1860 },
1861 {
1862 .str = "a_symbol_error_during_carrier",
1863 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1864 },
1865 {
1866 .str = "a_mac_control_frames_transmitted",
1867 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1868 },
1869 {
1870 .str = "a_mac_control_frames_received",
1871 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1872 },
1873 {
1874 .str = "a_unsupported_opcodes_received",
1875 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1876 },
1877 {
1878 .str = "a_pause_mac_ctrl_frames_received",
1879 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1880 },
1881 {
1882 .str = "a_pause_mac_ctrl_frames_xmitted",
1883 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1884 },
1885};
1886
1887#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1888
1889static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1890 {
1891 .str = "rx_octets_prio",
1892 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1893 },
1894 {
1895 .str = "rx_frames_prio",
1896 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1897 },
1898 {
1899 .str = "tx_octets_prio",
1900 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1901 },
1902 {
1903 .str = "tx_frames_prio",
1904 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1905 },
1906 {
1907 .str = "rx_pause_prio",
1908 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1909 },
1910 {
1911 .str = "rx_pause_duration_prio",
1912 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1913 },
1914 {
1915 .str = "tx_pause_prio",
1916 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1917 },
1918 {
1919 .str = "tx_pause_duration_prio",
1920 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1921 },
1922};
1923
1924#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1925
1926static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1927 {
1928 .str = "tc_transmit_queue_tc",
1929 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1930 .cells_bytes = true,
1931 },
1932 {
1933 .str = "tc_no_buffer_discard_uc_tc",
1934 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1935 },
1936};
1937
1938#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1939
1940#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
1941 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1942 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
1943 IEEE_8021QAZ_MAX_TCS)
1944
1945static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1946{
1947 int i;
1948
1949 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1950 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1951 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1952 *p += ETH_GSTRING_LEN;
1953 }
1954}
1955
1956static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1957{
1958 int i;
1959
1960 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1961 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1962 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1963 *p += ETH_GSTRING_LEN;
1964 }
1965}
1966
1967static void mlxsw_sp_port_get_strings(struct net_device *dev,
1968 u32 stringset, u8 *data)
1969{
1970 u8 *p = data;
1971 int i;
1972
1973 switch (stringset) {
1974 case ETH_SS_STATS:
1975 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1976 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1977 ETH_GSTRING_LEN);
1978 p += ETH_GSTRING_LEN;
1979 }
1980
1981 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1982 mlxsw_sp_port_get_prio_strings(&p, i);
1983
1984 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1985 mlxsw_sp_port_get_tc_strings(&p, i);
1986
1987 break;
1988 }
1989}
1990
1991static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1992 enum ethtool_phys_id_state state)
1993{
1994 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1995 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1996 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1997 bool active;
1998
1999 switch (state) {
2000 case ETHTOOL_ID_ACTIVE:
2001 active = true;
2002 break;
2003 case ETHTOOL_ID_INACTIVE:
2004 active = false;
2005 break;
2006 default:
2007 return -EOPNOTSUPP;
2008 }
2009
2010 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2011 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2012}
2013
2014static int
2015mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2016 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2017{
2018 switch (grp) {
2019 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2020 *p_hw_stats = mlxsw_sp_port_hw_stats;
2021 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2022 break;
2023 case MLXSW_REG_PPCNT_PRIO_CNT:
2024 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2025 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2026 break;
2027 case MLXSW_REG_PPCNT_TC_CNT:
2028 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2029 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2030 break;
2031 default:
2032 WARN_ON(1);
2033 return -EOPNOTSUPP;
2034 }
2035 return 0;
2036}
2037
2038static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2039 enum mlxsw_reg_ppcnt_grp grp, int prio,
2040 u64 *data, int data_index)
2041{
2042 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2043 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2044 struct mlxsw_sp_port_hw_stats *hw_stats;
2045 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
2046 int i, len;
2047 int err;
2048
2049 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2050 if (err)
2051 return;
2052 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
2053 for (i = 0; i < len; i++) {
2054 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
2055 if (!hw_stats[i].cells_bytes)
2056 continue;
2057 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2058 data[data_index + i]);
2059 }
2060}
2061
2062static void mlxsw_sp_port_get_stats(struct net_device *dev,
2063 struct ethtool_stats *stats, u64 *data)
2064{
2065 int i, data_index = 0;
2066
2067
2068 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2069 data, data_index);
2070 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2071
2072
2073 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2074 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2075 data, data_index);
2076 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2077 }
2078
2079
2080 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2081 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2082 data, data_index);
2083 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2084 }
2085}
2086
2087static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2088{
2089 switch (sset) {
2090 case ETH_SS_STATS:
2091 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
2092 default:
2093 return -EOPNOTSUPP;
2094 }
2095}
2096
2097struct mlxsw_sp_port_link_mode {
2098 enum ethtool_link_mode_bit_indices mask_ethtool;
2099 u32 mask;
2100 u32 speed;
2101};
2102
2103static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2104 {
2105 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
2106 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2107 .speed = SPEED_100,
2108 },
2109 {
2110 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2111 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
2112 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2113 .speed = SPEED_1000,
2114 },
2115 {
2116 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
2117 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2118 .speed = SPEED_10000,
2119 },
2120 {
2121 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2122 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
2123 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2124 .speed = SPEED_10000,
2125 },
2126 {
2127 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2128 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2129 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2130 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
2131 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2132 .speed = SPEED_10000,
2133 },
2134 {
2135 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
2136 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2137 .speed = SPEED_20000,
2138 },
2139 {
2140 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
2141 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2142 .speed = SPEED_40000,
2143 },
2144 {
2145 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
2146 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2147 .speed = SPEED_40000,
2148 },
2149 {
2150 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
2151 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2152 .speed = SPEED_40000,
2153 },
2154 {
2155 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
2156 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2157 .speed = SPEED_40000,
2158 },
2159 {
2160 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2161 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2162 .speed = SPEED_25000,
2163 },
2164 {
2165 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2166 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2167 .speed = SPEED_25000,
2168 },
2169 {
2170 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2171 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2172 .speed = SPEED_25000,
2173 },
2174 {
2175 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2176 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2177 .speed = SPEED_25000,
2178 },
2179 {
2180 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2181 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2182 .speed = SPEED_50000,
2183 },
2184 {
2185 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2186 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2187 .speed = SPEED_50000,
2188 },
2189 {
2190 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2191 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2192 .speed = SPEED_50000,
2193 },
2194 {
2195 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2196 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2197 .speed = SPEED_56000,
2198 },
2199 {
2200 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2201 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2202 .speed = SPEED_56000,
2203 },
2204 {
2205 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2206 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2207 .speed = SPEED_56000,
2208 },
2209 {
2210 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2211 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2212 .speed = SPEED_56000,
2213 },
2214 {
2215 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2216 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2217 .speed = SPEED_100000,
2218 },
2219 {
2220 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2221 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2222 .speed = SPEED_100000,
2223 },
2224 {
2225 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2226 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2227 .speed = SPEED_100000,
2228 },
2229 {
2230 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2231 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2232 .speed = SPEED_100000,
2233 },
2234};
2235
2236#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2237
2238static void
2239mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2240 struct ethtool_link_ksettings *cmd)
2241{
2242 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2243 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2244 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2245 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2246 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2247 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2248 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
2249
2250 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2251 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2252 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2253 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2254 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
2255 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
2256}
2257
2258static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
2259{
2260 int i;
2261
2262 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2263 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
2264 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2265 mode);
2266 }
2267}
2268
2269static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
2270 struct ethtool_link_ksettings *cmd)
2271{
2272 u32 speed = SPEED_UNKNOWN;
2273 u8 duplex = DUPLEX_UNKNOWN;
2274 int i;
2275
2276 if (!carrier_ok)
2277 goto out;
2278
2279 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2280 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2281 speed = mlxsw_sp_port_link_mode[i].speed;
2282 duplex = DUPLEX_FULL;
2283 break;
2284 }
2285 }
2286out:
2287 cmd->base.speed = speed;
2288 cmd->base.duplex = duplex;
2289}
2290
2291static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2292{
2293 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2294 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2295 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2296 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2297 return PORT_FIBRE;
2298
2299 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2300 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2301 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2302 return PORT_DA;
2303
2304 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2305 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2306 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2307 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2308 return PORT_NONE;
2309
2310 return PORT_OTHER;
2311}
2312
2313static u32
2314mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
2315{
2316 u32 ptys_proto = 0;
2317 int i;
2318
2319 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2320 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2321 cmd->link_modes.advertising))
2322 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2323 }
2324 return ptys_proto;
2325}
2326
2327static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2328{
2329 u32 ptys_proto = 0;
2330 int i;
2331
2332 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2333 if (speed == mlxsw_sp_port_link_mode[i].speed)
2334 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2335 }
2336 return ptys_proto;
2337}
2338
2339static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2340{
2341 u32 ptys_proto = 0;
2342 int i;
2343
2344 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2345 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2346 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2347 }
2348 return ptys_proto;
2349}
2350
2351static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2352 struct ethtool_link_ksettings *cmd)
2353{
2354 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2355 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2356 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2357
2358 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2359 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2360}
2361
2362static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2363 struct ethtool_link_ksettings *cmd)
2364{
2365 if (!autoneg)
2366 return;
2367
2368 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2369 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2370}
2371
2372static void
2373mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2374 struct ethtool_link_ksettings *cmd)
2375{
2376 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2377 return;
2378
2379 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2380 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2381}
2382
2383static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2384 struct ethtool_link_ksettings *cmd)
2385{
2386 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2387 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2388 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2389 char ptys_pl[MLXSW_REG_PTYS_LEN];
2390 u8 autoneg_status;
2391 bool autoneg;
2392 int err;
2393
2394 autoneg = mlxsw_sp_port->link.autoneg;
2395 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
2396 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2397 if (err)
2398 return err;
2399 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, ð_proto_admin,
2400 ð_proto_oper);
2401
2402 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2403
2404 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2405
2406 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2407 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2408 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2409
2410 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2411 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2412 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2413 cmd);
2414
2415 return 0;
2416}
2417
2418static int
2419mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2420 const struct ethtool_link_ksettings *cmd)
2421{
2422 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2423 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2424 char ptys_pl[MLXSW_REG_PTYS_LEN];
2425 u32 eth_proto_cap, eth_proto_new;
2426 bool autoneg;
2427 int err;
2428
2429 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
2430 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2431 if (err)
2432 return err;
2433 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, NULL, NULL);
2434
2435 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2436 eth_proto_new = autoneg ?
2437 mlxsw_sp_to_ptys_advert_link(cmd) :
2438 mlxsw_sp_to_ptys_speed(cmd->base.speed);
2439
2440 eth_proto_new = eth_proto_new & eth_proto_cap;
2441 if (!eth_proto_new) {
2442 netdev_err(dev, "No supported speed requested\n");
2443 return -EINVAL;
2444 }
2445
2446 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2447 eth_proto_new, autoneg);
2448 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2449 if (err)
2450 return err;
2451
2452 if (!netif_running(dev))
2453 return 0;
2454
2455 mlxsw_sp_port->link.autoneg = autoneg;
2456
2457 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2458 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
2459
2460 return 0;
2461}
2462
2463static int mlxsw_sp_flash_device(struct net_device *dev,
2464 struct ethtool_flash *flash)
2465{
2466 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2467 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2468 const struct firmware *firmware;
2469 int err;
2470
2471 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2472 return -EOPNOTSUPP;
2473
2474 dev_hold(dev);
2475 rtnl_unlock();
2476
2477 err = request_firmware(&firmware, flash->data, &dev->dev);
2478 if (err)
2479 goto out;
2480 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2481 release_firmware(firmware);
2482out:
2483 rtnl_lock();
2484 dev_put(dev);
2485 return err;
2486}
2487
2488#define MLXSW_SP_I2C_ADDR_LOW 0x50
2489#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2490#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
2491
2492static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2493 u16 offset, u16 size, void *data,
2494 unsigned int *p_read_size)
2495{
2496 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2497 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2498 char mcia_pl[MLXSW_REG_MCIA_LEN];
2499 u16 i2c_addr;
2500 int status;
2501 int err;
2502
2503 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
2504
2505 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2506 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2507
2508 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2509
2510 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2511 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2512 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2513 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2514 }
2515
2516 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
2517 0, 0, offset, size, i2c_addr);
2518
2519 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2520 if (err)
2521 return err;
2522
2523 status = mlxsw_reg_mcia_status_get(mcia_pl);
2524 if (status)
2525 return -EIO;
2526
2527 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2528 memcpy(data, eeprom_tmp, size);
2529 *p_read_size = size;
2530
2531 return 0;
2532}
2533
2534enum mlxsw_sp_eeprom_module_info_rev_id {
2535 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2536 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2537 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2538};
2539
2540enum mlxsw_sp_eeprom_module_info_id {
2541 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2542 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2543 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2544 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2545};
2546
2547enum mlxsw_sp_eeprom_module_info {
2548 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2549 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2550 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2551};
2552
2553static int mlxsw_sp_get_module_info(struct net_device *netdev,
2554 struct ethtool_modinfo *modinfo)
2555{
2556 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2557 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2558 u8 module_rev_id, module_id;
2559 unsigned int read_size;
2560 int err;
2561
2562 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2563 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2564 module_info, &read_size);
2565 if (err)
2566 return err;
2567
2568 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2569 return -EIO;
2570
2571 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2572 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2573
2574 switch (module_id) {
2575 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2576 modinfo->type = ETH_MODULE_SFF_8436;
2577 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2578 break;
2579 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2580 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2581 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2582 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2583 modinfo->type = ETH_MODULE_SFF_8636;
2584 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2585 } else {
2586 modinfo->type = ETH_MODULE_SFF_8436;
2587 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2588 }
2589 break;
2590 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2591 modinfo->type = ETH_MODULE_SFF_8472;
2592 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2593 break;
2594 default:
2595 return -EINVAL;
2596 }
2597
2598 return 0;
2599}
2600
2601static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2602 struct ethtool_eeprom *ee,
2603 u8 *data)
2604{
2605 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2606 int offset = ee->offset;
2607 unsigned int read_size;
2608 int i = 0;
2609 int err;
2610
2611 if (!ee->len)
2612 return -EINVAL;
2613
2614 memset(data, 0, ee->len);
2615
2616 while (i < ee->len) {
2617 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2618 ee->len - i, data + i,
2619 &read_size);
2620 if (err) {
2621 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2622 return err;
2623 }
2624
2625 i += read_size;
2626 offset += read_size;
2627 }
2628
2629 return 0;
2630}
2631
2632static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2633 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2634 .get_link = ethtool_op_get_link,
2635 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2636 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
2637 .get_strings = mlxsw_sp_port_get_strings,
2638 .set_phys_id = mlxsw_sp_port_set_phys_id,
2639 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2640 .get_sset_count = mlxsw_sp_port_get_sset_count,
2641 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2642 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
2643 .flash_device = mlxsw_sp_flash_device,
2644 .get_module_info = mlxsw_sp_get_module_info,
2645 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
2646};
2647
2648static int
2649mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2650{
2651 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2652 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2653 char ptys_pl[MLXSW_REG_PTYS_LEN];
2654 u32 eth_proto_admin;
2655
2656 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
2657 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2658 eth_proto_admin, mlxsw_sp_port->link.autoneg);
2659 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2660}
2661
2662int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2663 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2664 bool dwrr, u8 dwrr_weight)
2665{
2666 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2667 char qeec_pl[MLXSW_REG_QEEC_LEN];
2668
2669 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2670 next_index);
2671 mlxsw_reg_qeec_de_set(qeec_pl, true);
2672 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2673 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2674 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2675}
2676
2677int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2678 enum mlxsw_reg_qeec_hr hr, u8 index,
2679 u8 next_index, u32 maxrate)
2680{
2681 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2682 char qeec_pl[MLXSW_REG_QEEC_LEN];
2683
2684 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2685 next_index);
2686 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2687 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2688 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2689}
2690
2691int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2692 u8 switch_prio, u8 tclass)
2693{
2694 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2695 char qtct_pl[MLXSW_REG_QTCT_LEN];
2696
2697 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2698 tclass);
2699 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2700}
2701
2702static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2703{
2704 int err, i;
2705
2706
2707
2708
2709 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2710 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2711 0);
2712 if (err)
2713 return err;
2714 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2715 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2716 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2717 0, false, 0);
2718 if (err)
2719 return err;
2720 }
2721 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2722 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2723 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2724 false, 0);
2725 if (err)
2726 return err;
2727 }
2728
2729
2730
2731
2732 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2733 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2734 MLXSW_REG_QEEC_MAS_DIS);
2735 if (err)
2736 return err;
2737 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2738 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2739 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2740 i, 0,
2741 MLXSW_REG_QEEC_MAS_DIS);
2742 if (err)
2743 return err;
2744 }
2745 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2746 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2747 MLXSW_REG_QEEC_HIERARCY_TC,
2748 i, i,
2749 MLXSW_REG_QEEC_MAS_DIS);
2750 if (err)
2751 return err;
2752 }
2753
2754
2755 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2756 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2757 if (err)
2758 return err;
2759 }
2760
2761 return 0;
2762}
2763
2764static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2765 bool split, u8 module, u8 width, u8 lane)
2766{
2767 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
2768 struct mlxsw_sp_port *mlxsw_sp_port;
2769 struct net_device *dev;
2770 int err;
2771
2772 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2773 if (err) {
2774 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2775 local_port);
2776 return err;
2777 }
2778
2779 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2780 if (!dev) {
2781 err = -ENOMEM;
2782 goto err_alloc_etherdev;
2783 }
2784 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
2785 mlxsw_sp_port = netdev_priv(dev);
2786 mlxsw_sp_port->dev = dev;
2787 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2788 mlxsw_sp_port->local_port = local_port;
2789 mlxsw_sp_port->pvid = 1;
2790 mlxsw_sp_port->split = split;
2791 mlxsw_sp_port->mapping.module = module;
2792 mlxsw_sp_port->mapping.width = width;
2793 mlxsw_sp_port->mapping.lane = lane;
2794 mlxsw_sp_port->link.autoneg = 1;
2795 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
2796 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
2797
2798 mlxsw_sp_port->pcpu_stats =
2799 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2800 if (!mlxsw_sp_port->pcpu_stats) {
2801 err = -ENOMEM;
2802 goto err_alloc_stats;
2803 }
2804
2805 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2806 GFP_KERNEL);
2807 if (!mlxsw_sp_port->sample) {
2808 err = -ENOMEM;
2809 goto err_alloc_sample;
2810 }
2811
2812 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
2813 &update_stats_cache);
2814
2815 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2816 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2817
2818 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
2819 if (err) {
2820 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2821 mlxsw_sp_port->local_port);
2822 goto err_port_module_map;
2823 }
2824
2825 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2826 if (err) {
2827 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2828 mlxsw_sp_port->local_port);
2829 goto err_port_swid_set;
2830 }
2831
2832 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2833 if (err) {
2834 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2835 mlxsw_sp_port->local_port);
2836 goto err_dev_addr_init;
2837 }
2838
2839 netif_carrier_off(dev);
2840
2841 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
2842 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2843 dev->hw_features |= NETIF_F_HW_TC;
2844
2845 dev->extended->min_mtu = 0;
2846 dev->extended->max_mtu = ETH_MAX_MTU;
2847
2848
2849
2850
2851 dev->needed_headroom = MLXSW_TXHDR_LEN;
2852
2853 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2854 if (err) {
2855 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2856 mlxsw_sp_port->local_port);
2857 goto err_port_system_port_mapping_set;
2858 }
2859
2860 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2861 if (err) {
2862 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2863 mlxsw_sp_port->local_port);
2864 goto err_port_speed_by_width_set;
2865 }
2866
2867 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2868 if (err) {
2869 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2870 mlxsw_sp_port->local_port);
2871 goto err_port_mtu_set;
2872 }
2873
2874 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2875 if (err)
2876 goto err_port_admin_status_set;
2877
2878 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2879 if (err) {
2880 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2881 mlxsw_sp_port->local_port);
2882 goto err_port_buffers_init;
2883 }
2884
2885 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2886 if (err) {
2887 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2888 mlxsw_sp_port->local_port);
2889 goto err_port_ets_init;
2890 }
2891
2892
2893 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2894 if (err) {
2895 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2896 mlxsw_sp_port->local_port);
2897 goto err_port_dcb_init;
2898 }
2899
2900 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
2901 if (err) {
2902 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
2903 mlxsw_sp_port->local_port);
2904 goto err_port_fids_init;
2905 }
2906
2907 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
2908 if (err) {
2909 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
2910 mlxsw_sp_port->local_port);
2911 goto err_port_qdiscs_init;
2912 }
2913
2914 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
2915 if (IS_ERR(mlxsw_sp_port_vlan)) {
2916 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
2917 mlxsw_sp_port->local_port);
2918 err = PTR_ERR(mlxsw_sp_port_vlan);
2919 goto err_port_vlan_get;
2920 }
2921
2922 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
2923 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
2924 err = register_netdev(dev);
2925 if (err) {
2926 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2927 mlxsw_sp_port->local_port);
2928 goto err_register_netdev;
2929 }
2930
2931 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2932 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2933 module);
2934 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
2935 return 0;
2936
2937err_register_netdev:
2938 mlxsw_sp->ports[local_port] = NULL;
2939 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
2940 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
2941err_port_vlan_get:
2942 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
2943err_port_qdiscs_init:
2944 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
2945err_port_fids_init:
2946 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
2947err_port_dcb_init:
2948err_port_ets_init:
2949err_port_buffers_init:
2950err_port_admin_status_set:
2951err_port_mtu_set:
2952err_port_speed_by_width_set:
2953err_port_system_port_mapping_set:
2954err_dev_addr_init:
2955 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2956err_port_swid_set:
2957 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
2958err_port_module_map:
2959 kfree(mlxsw_sp_port->sample);
2960err_alloc_sample:
2961 free_percpu(mlxsw_sp_port->pcpu_stats);
2962err_alloc_stats:
2963 free_netdev(dev);
2964err_alloc_etherdev:
2965 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2966 return err;
2967}
2968
2969static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2970{
2971 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2972
2973 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
2974 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
2975 unregister_netdev(mlxsw_sp_port->dev);
2976 mlxsw_sp->ports[local_port] = NULL;
2977 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
2978 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
2979 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
2980 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
2981 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
2982 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2983 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
2984 kfree(mlxsw_sp_port->sample);
2985 free_percpu(mlxsw_sp_port->pcpu_stats);
2986 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
2987 free_netdev(mlxsw_sp_port->dev);
2988 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2989}
2990
2991static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2992{
2993 return mlxsw_sp->ports[local_port] != NULL;
2994}
2995
2996static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2997{
2998 int i;
2999
3000 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
3001 if (mlxsw_sp_port_created(mlxsw_sp, i))
3002 mlxsw_sp_port_remove(mlxsw_sp, i);
3003 kfree(mlxsw_sp->port_to_module);
3004 kfree(mlxsw_sp->ports);
3005}
3006
3007static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3008{
3009 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
3010 u8 module, width, lane;
3011 size_t alloc_size;
3012 int i;
3013 int err;
3014
3015 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
3016 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3017 if (!mlxsw_sp->ports)
3018 return -ENOMEM;
3019
3020 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3021 GFP_KERNEL);
3022 if (!mlxsw_sp->port_to_module) {
3023 err = -ENOMEM;
3024 goto err_port_to_module_alloc;
3025 }
3026
3027 for (i = 1; i < max_ports; i++) {
3028
3029 mlxsw_sp->port_to_module[i] = -1;
3030
3031 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
3032 &width, &lane);
3033 if (err)
3034 goto err_port_module_info_get;
3035 if (!width)
3036 continue;
3037 mlxsw_sp->port_to_module[i] = module;
3038 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3039 module, width, lane);
3040 if (err)
3041 goto err_port_create;
3042 }
3043 return 0;
3044
3045err_port_create:
3046err_port_module_info_get:
3047 for (i--; i >= 1; i--)
3048 if (mlxsw_sp_port_created(mlxsw_sp, i))
3049 mlxsw_sp_port_remove(mlxsw_sp, i);
3050 kfree(mlxsw_sp->port_to_module);
3051err_port_to_module_alloc:
3052 kfree(mlxsw_sp->ports);
3053 return err;
3054}
3055
3056static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3057{
3058 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3059
3060 return local_port - offset;
3061}
3062
3063static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3064 u8 module, unsigned int count)
3065{
3066 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3067 int err, i;
3068
3069 for (i = 0; i < count; i++) {
3070 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
3071 module, width, i * width);
3072 if (err)
3073 goto err_port_create;
3074 }
3075
3076 return 0;
3077
3078err_port_create:
3079 for (i--; i >= 0; i--)
3080 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3081 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3082 return err;
3083}
3084
3085static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3086 u8 base_port, unsigned int count)
3087{
3088 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3089 int i;
3090
3091
3092
3093
3094 count = count / 2;
3095
3096 for (i = 0; i < count; i++) {
3097 local_port = base_port + i * 2;
3098 if (mlxsw_sp->port_to_module[local_port] < 0)
3099 continue;
3100 module = mlxsw_sp->port_to_module[local_port];
3101
3102 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
3103 width, 0);
3104 }
3105}
3106
3107static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3108 unsigned int count)
3109{
3110 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3111 struct mlxsw_sp_port *mlxsw_sp_port;
3112 u8 module, cur_width, base_port;
3113 int i;
3114 int err;
3115
3116 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3117 if (!mlxsw_sp_port) {
3118 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3119 local_port);
3120 return -EINVAL;
3121 }
3122
3123 module = mlxsw_sp_port->mapping.module;
3124 cur_width = mlxsw_sp_port->mapping.width;
3125
3126 if (count != 2 && count != 4) {
3127 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3128 return -EINVAL;
3129 }
3130
3131 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3132 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3133 return -EINVAL;
3134 }
3135
3136
3137 if (count == 2) {
3138 base_port = local_port;
3139 if (mlxsw_sp->ports[base_port + 1]) {
3140 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3141 return -EINVAL;
3142 }
3143 } else {
3144 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3145 if (mlxsw_sp->ports[base_port + 1] ||
3146 mlxsw_sp->ports[base_port + 3]) {
3147 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3148 return -EINVAL;
3149 }
3150 }
3151
3152 for (i = 0; i < count; i++)
3153 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3154 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3155
3156 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3157 if (err) {
3158 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3159 goto err_port_split_create;
3160 }
3161
3162 return 0;
3163
3164err_port_split_create:
3165 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
3166 return err;
3167}
3168
3169static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
3170{
3171 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3172 struct mlxsw_sp_port *mlxsw_sp_port;
3173 u8 cur_width, base_port;
3174 unsigned int count;
3175 int i;
3176
3177 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3178 if (!mlxsw_sp_port) {
3179 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3180 local_port);
3181 return -EINVAL;
3182 }
3183
3184 if (!mlxsw_sp_port->split) {
3185 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3186 return -EINVAL;
3187 }
3188
3189 cur_width = mlxsw_sp_port->mapping.width;
3190 count = cur_width == 1 ? 4 : 2;
3191
3192 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3193
3194
3195 if (count == 2 && local_port >= base_port + 2)
3196 base_port = base_port + 2;
3197
3198 for (i = 0; i < count; i++)
3199 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3200 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3201
3202 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
3203
3204 return 0;
3205}
3206
3207static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3208 char *pude_pl, void *priv)
3209{
3210 struct mlxsw_sp *mlxsw_sp = priv;
3211 struct mlxsw_sp_port *mlxsw_sp_port;
3212 enum mlxsw_reg_pude_oper_status status;
3213 u8 local_port;
3214
3215 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3216 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3217 if (!mlxsw_sp_port)
3218 return;
3219
3220 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3221 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3222 netdev_info(mlxsw_sp_port->dev, "link up\n");
3223 netif_carrier_on(mlxsw_sp_port->dev);
3224 } else {
3225 netdev_info(mlxsw_sp_port->dev, "link down\n");
3226 netif_carrier_off(mlxsw_sp_port->dev);
3227 }
3228}
3229
3230static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3231 u8 local_port, void *priv)
3232{
3233 struct mlxsw_sp *mlxsw_sp = priv;
3234 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3235 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3236
3237 if (unlikely(!mlxsw_sp_port)) {
3238 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3239 local_port);
3240 return;
3241 }
3242
3243 skb->dev = mlxsw_sp_port->dev;
3244
3245 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3246 u64_stats_update_begin(&pcpu_stats->syncp);
3247 pcpu_stats->rx_packets++;
3248 pcpu_stats->rx_bytes += skb->len;
3249 u64_stats_update_end(&pcpu_stats->syncp);
3250
3251 skb->protocol = eth_type_trans(skb, skb->dev);
3252 netif_receive_skb(skb);
3253}
3254
3255static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3256 void *priv)
3257{
3258 skb->offload_fwd_mark = 1;
3259 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3260}
3261
3262static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3263 u8 local_port, void *priv)
3264{
3265 skb->offload_mr_fwd_mark = 1;
3266 skb->offload_fwd_mark = 1;
3267 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3268}
3269
3270static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3271 void *priv)
3272{
3273 struct mlxsw_sp *mlxsw_sp = priv;
3274 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3275 struct psample_group *psample_group;
3276 u32 size;
3277
3278 if (unlikely(!mlxsw_sp_port)) {
3279 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3280 local_port);
3281 goto out;
3282 }
3283 if (unlikely(!mlxsw_sp_port->sample)) {
3284 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3285 local_port);
3286 goto out;
3287 }
3288
3289 size = mlxsw_sp_port->sample->truncate ?
3290 mlxsw_sp_port->sample->trunc_size : skb->len;
3291
3292 rcu_read_lock();
3293 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3294 if (!psample_group)
3295 goto out_unlock;
3296 psample_sample_packet(psample_group, skb, size,
3297 mlxsw_sp_port->dev->ifindex, 0,
3298 mlxsw_sp_port->sample->rate);
3299out_unlock:
3300 rcu_read_unlock();
3301out:
3302 consume_skb(skb);
3303}
3304
3305#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3306 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
3307 _is_ctrl, SP_##_trap_group, DISCARD)
3308
3309#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3310 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
3311 _is_ctrl, SP_##_trap_group, DISCARD)
3312
3313#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3314 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3315 _is_ctrl, SP_##_trap_group, DISCARD)
3316
3317#define MLXSW_SP_EVENTL(_func, _trap_id) \
3318 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
3319
3320static const struct mlxsw_listener mlxsw_sp_listener[] = {
3321
3322 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
3323
3324 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3325 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3326 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3327 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3328 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3329 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3330 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3331 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3332 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3333 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3334 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
3335 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
3336 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3337 false),
3338 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3339 false),
3340 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3341 false),
3342 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3343 false),
3344
3345 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3346 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3347 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3348 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
3349 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3350 false),
3351 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3352 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3353 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3354 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3355 false),
3356 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3357 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3358 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
3359 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
3360 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3361 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3362 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3363 false),
3364 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3365 false),
3366 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3367 false),
3368 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3369 false),
3370 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3371 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3372 false),
3373 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3374 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
3375 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
3376 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
3377 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3378
3379 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
3380 false, SP_IP2ME, DISCARD),
3381
3382 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
3383
3384 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3385 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3386 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
3387 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
3388};
3389
3390static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3391{
3392 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3393 enum mlxsw_reg_qpcr_ir_units ir_units;
3394 int max_cpu_policers;
3395 bool is_bytes;
3396 u8 burst_size;
3397 u32 rate;
3398 int i, err;
3399
3400 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3401 return -EIO;
3402
3403 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3404
3405 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3406 for (i = 0; i < max_cpu_policers; i++) {
3407 is_bytes = false;
3408 switch (i) {
3409 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3410 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3411 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3412 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3413 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3414 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
3415 rate = 128;
3416 burst_size = 7;
3417 break;
3418 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3419 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
3420 rate = 16 * 1024;
3421 burst_size = 10;
3422 break;
3423 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
3424 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3425 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3426 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
3427 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3428 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3429 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
3430 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
3431 rate = 1024;
3432 burst_size = 7;
3433 break;
3434 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3435 is_bytes = true;
3436 rate = 4 * 1024;
3437 burst_size = 4;
3438 break;
3439 default:
3440 continue;
3441 }
3442
3443 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3444 burst_size);
3445 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3446 if (err)
3447 return err;
3448 }
3449
3450 return 0;
3451}
3452
3453static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
3454{
3455 char htgt_pl[MLXSW_REG_HTGT_LEN];
3456 enum mlxsw_reg_htgt_trap_group i;
3457 int max_cpu_policers;
3458 int max_trap_groups;
3459 u8 priority, tc;
3460 u16 policer_id;
3461 int err;
3462
3463 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3464 return -EIO;
3465
3466 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
3467 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3468
3469 for (i = 0; i < max_trap_groups; i++) {
3470 policer_id = i;
3471 switch (i) {
3472 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3473 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3474 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3475 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3476 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3477 priority = 5;
3478 tc = 5;
3479 break;
3480 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
3481 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3482 priority = 4;
3483 tc = 4;
3484 break;
3485 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3486 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3487 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
3488 priority = 3;
3489 tc = 3;
3490 break;
3491 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3492 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
3493 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
3494 priority = 2;
3495 tc = 2;
3496 break;
3497 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
3498 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3499 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3500 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
3501 priority = 1;
3502 tc = 1;
3503 break;
3504 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
3505 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3506 tc = MLXSW_REG_HTGT_DEFAULT_TC;
3507 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
3508 break;
3509 default:
3510 continue;
3511 }
3512
3513 if (max_cpu_policers <= policer_id &&
3514 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3515 return -EIO;
3516
3517 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
3518 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3519 if (err)
3520 return err;
3521 }
3522
3523 return 0;
3524}
3525
3526static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3527{
3528 int i;
3529 int err;
3530
3531 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3532 if (err)
3533 return err;
3534
3535 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
3536 if (err)
3537 return err;
3538
3539 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
3540 err = mlxsw_core_trap_register(mlxsw_sp->core,
3541 &mlxsw_sp_listener[i],
3542 mlxsw_sp);
3543 if (err)
3544 goto err_listener_register;
3545
3546 }
3547 return 0;
3548
3549err_listener_register:
3550 for (i--; i >= 0; i--) {
3551 mlxsw_core_trap_unregister(mlxsw_sp->core,
3552 &mlxsw_sp_listener[i],
3553 mlxsw_sp);
3554 }
3555 return err;
3556}
3557
3558static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3559{
3560 int i;
3561
3562 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
3563 mlxsw_core_trap_unregister(mlxsw_sp->core,
3564 &mlxsw_sp_listener[i],
3565 mlxsw_sp);
3566 }
3567}
3568
3569static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3570{
3571 char slcr_pl[MLXSW_REG_SLCR_LEN];
3572 int err;
3573
3574 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3575 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3576 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3577 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3578 MLXSW_REG_SLCR_LAG_HASH_SIP |
3579 MLXSW_REG_SLCR_LAG_HASH_DIP |
3580 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3581 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3582 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
3583 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3584 if (err)
3585 return err;
3586
3587 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3588 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
3589 return -EIO;
3590
3591 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
3592 sizeof(struct mlxsw_sp_upper),
3593 GFP_KERNEL);
3594 if (!mlxsw_sp->lags)
3595 return -ENOMEM;
3596
3597 return 0;
3598}
3599
3600static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3601{
3602 kfree(mlxsw_sp->lags);
3603}
3604
3605static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3606{
3607 char htgt_pl[MLXSW_REG_HTGT_LEN];
3608
3609 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3610 MLXSW_REG_HTGT_INVALID_POLICER,
3611 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3612 MLXSW_REG_HTGT_DEFAULT_TC);
3613 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3614}
3615
3616static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3617 unsigned long event, void *ptr);
3618
3619static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
3620 const struct mlxsw_bus_info *mlxsw_bus_info)
3621{
3622 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3623 int err;
3624
3625 mlxsw_sp->core = mlxsw_core;
3626 mlxsw_sp->bus_info = mlxsw_bus_info;
3627
3628 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3629 if (err) {
3630 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3631 return err;
3632 }
3633
3634 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3635 if (err) {
3636 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3637 return err;
3638 }
3639
3640 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3641 if (err) {
3642 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3643 return err;
3644 }
3645
3646 err = mlxsw_sp_fids_init(mlxsw_sp);
3647 if (err) {
3648 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
3649 goto err_fids_init;
3650 }
3651
3652 err = mlxsw_sp_traps_init(mlxsw_sp);
3653 if (err) {
3654 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3655 goto err_traps_init;
3656 }
3657
3658 err = mlxsw_sp_buffers_init(mlxsw_sp);
3659 if (err) {
3660 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3661 goto err_buffers_init;
3662 }
3663
3664 err = mlxsw_sp_lag_init(mlxsw_sp);
3665 if (err) {
3666 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3667 goto err_lag_init;
3668 }
3669
3670 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3671 if (err) {
3672 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3673 goto err_switchdev_init;
3674 }
3675
3676 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3677 if (err) {
3678 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3679 goto err_counter_pool_init;
3680 }
3681
3682 err = mlxsw_sp_afa_init(mlxsw_sp);
3683 if (err) {
3684 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3685 goto err_afa_init;
3686 }
3687
3688 err = mlxsw_sp_span_init(mlxsw_sp);
3689 if (err) {
3690 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3691 goto err_span_init;
3692 }
3693
3694
3695
3696
3697 err = mlxsw_sp_router_init(mlxsw_sp);
3698 if (err) {
3699 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3700 goto err_router_init;
3701 }
3702
3703
3704
3705
3706
3707 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3708 err = register_netdevice_notifier_rh(&mlxsw_sp->netdevice_nb);
3709 if (err) {
3710 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3711 goto err_netdev_notifier;
3712 }
3713
3714 err = mlxsw_sp_acl_init(mlxsw_sp);
3715 if (err) {
3716 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3717 goto err_acl_init;
3718 }
3719
3720 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3721 if (err) {
3722 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3723 goto err_dpipe_init;
3724 }
3725
3726 err = mlxsw_sp_ports_create(mlxsw_sp);
3727 if (err) {
3728 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3729 goto err_ports_create;
3730 }
3731
3732 return 0;
3733
3734err_ports_create:
3735 mlxsw_sp_dpipe_fini(mlxsw_sp);
3736err_dpipe_init:
3737 mlxsw_sp_acl_fini(mlxsw_sp);
3738err_acl_init:
3739 unregister_netdevice_notifier_rh(&mlxsw_sp->netdevice_nb);
3740err_netdev_notifier:
3741 mlxsw_sp_router_fini(mlxsw_sp);
3742err_router_init:
3743 mlxsw_sp_span_fini(mlxsw_sp);
3744err_span_init:
3745 mlxsw_sp_afa_fini(mlxsw_sp);
3746err_afa_init:
3747 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3748err_counter_pool_init:
3749 mlxsw_sp_switchdev_fini(mlxsw_sp);
3750err_switchdev_init:
3751 mlxsw_sp_lag_fini(mlxsw_sp);
3752err_lag_init:
3753 mlxsw_sp_buffers_fini(mlxsw_sp);
3754err_buffers_init:
3755 mlxsw_sp_traps_fini(mlxsw_sp);
3756err_traps_init:
3757 mlxsw_sp_fids_fini(mlxsw_sp);
3758err_fids_init:
3759 mlxsw_sp_kvdl_fini(mlxsw_sp);
3760 return err;
3761}
3762
3763static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
3764{
3765 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3766
3767 mlxsw_sp_ports_remove(mlxsw_sp);
3768 mlxsw_sp_dpipe_fini(mlxsw_sp);
3769 mlxsw_sp_acl_fini(mlxsw_sp);
3770 unregister_netdevice_notifier_rh(&mlxsw_sp->netdevice_nb);
3771 mlxsw_sp_router_fini(mlxsw_sp);
3772 mlxsw_sp_span_fini(mlxsw_sp);
3773 mlxsw_sp_afa_fini(mlxsw_sp);
3774 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3775 mlxsw_sp_switchdev_fini(mlxsw_sp);
3776 mlxsw_sp_lag_fini(mlxsw_sp);
3777 mlxsw_sp_buffers_fini(mlxsw_sp);
3778 mlxsw_sp_traps_fini(mlxsw_sp);
3779 mlxsw_sp_fids_fini(mlxsw_sp);
3780 mlxsw_sp_kvdl_fini(mlxsw_sp);
3781}
3782
3783static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
3784 .used_max_mid = 1,
3785 .max_mid = MLXSW_SP_MID_MAX,
3786 .used_flood_tables = 1,
3787 .used_flood_mode = 1,
3788 .flood_mode = 3,
3789 .max_fid_offset_flood_tables = 3,
3790 .fid_offset_flood_table_size = VLAN_N_VID - 1,
3791 .max_fid_flood_tables = 3,
3792 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
3793 .used_max_ib_mc = 1,
3794 .max_ib_mc = 0,
3795 .used_max_pkey = 1,
3796 .max_pkey = 0,
3797 .used_kvd_sizes = 1,
3798 .kvd_hash_single_parts = 59,
3799 .kvd_hash_double_parts = 41,
3800 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
3801 .swid_config = {
3802 {
3803 .used_type = 1,
3804 .type = MLXSW_PORT_SWID_TYPE_ETH,
3805 }
3806 },
3807};
3808
3809static void
3810mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
3811 struct devlink_resource_size_params *kvd_size_params,
3812 struct devlink_resource_size_params *linear_size_params,
3813 struct devlink_resource_size_params *hash_double_size_params,
3814 struct devlink_resource_size_params *hash_single_size_params)
3815{
3816 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3817 KVD_SINGLE_MIN_SIZE);
3818 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3819 KVD_DOUBLE_MIN_SIZE);
3820 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3821 u32 linear_size_min = 0;
3822
3823 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
3824 MLXSW_SP_KVD_GRANULARITY,
3825 DEVLINK_RESOURCE_UNIT_ENTRY);
3826 devlink_resource_size_params_init(linear_size_params, linear_size_min,
3827 kvd_size - single_size_min -
3828 double_size_min,
3829 MLXSW_SP_KVD_GRANULARITY,
3830 DEVLINK_RESOURCE_UNIT_ENTRY);
3831 devlink_resource_size_params_init(hash_double_size_params,
3832 double_size_min,
3833 kvd_size - single_size_min -
3834 linear_size_min,
3835 MLXSW_SP_KVD_GRANULARITY,
3836 DEVLINK_RESOURCE_UNIT_ENTRY);
3837 devlink_resource_size_params_init(hash_single_size_params,
3838 single_size_min,
3839 kvd_size - double_size_min -
3840 linear_size_min,
3841 MLXSW_SP_KVD_GRANULARITY,
3842 DEVLINK_RESOURCE_UNIT_ENTRY);
3843}
3844
3845static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core)
3846{
3847 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3848 struct devlink_resource_size_params hash_single_size_params;
3849 struct devlink_resource_size_params hash_double_size_params;
3850 struct devlink_resource_size_params linear_size_params;
3851 struct devlink_resource_size_params kvd_size_params;
3852 u32 kvd_size, single_size, double_size, linear_size;
3853 const struct mlxsw_config_profile *profile;
3854 int err;
3855
3856 profile = &mlxsw_sp_config_profile;
3857 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3858 return -EIO;
3859
3860 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
3861 &linear_size_params,
3862 &hash_double_size_params,
3863 &hash_single_size_params);
3864
3865 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3866 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
3867 kvd_size, MLXSW_SP_RESOURCE_KVD,
3868 DEVLINK_RESOURCE_ID_PARENT_TOP,
3869 &kvd_size_params);
3870 if (err)
3871 return err;
3872
3873 linear_size = profile->kvd_linear_size;
3874 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
3875 linear_size,
3876 MLXSW_SP_RESOURCE_KVD_LINEAR,
3877 MLXSW_SP_RESOURCE_KVD,
3878 &linear_size_params);
3879 if (err)
3880 return err;
3881
3882 err = mlxsw_sp_kvdl_resources_register(mlxsw_core);
3883 if (err)
3884 return err;
3885
3886 double_size = kvd_size - linear_size;
3887 double_size *= profile->kvd_hash_double_parts;
3888 double_size /= profile->kvd_hash_double_parts +
3889 profile->kvd_hash_single_parts;
3890 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
3891 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
3892 double_size,
3893 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3894 MLXSW_SP_RESOURCE_KVD,
3895 &hash_double_size_params);
3896 if (err)
3897 return err;
3898
3899 single_size = kvd_size - double_size - linear_size;
3900 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
3901 single_size,
3902 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3903 MLXSW_SP_RESOURCE_KVD,
3904 &hash_single_size_params);
3905 if (err)
3906 return err;
3907
3908 return 0;
3909}
3910
3911static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
3912 const struct mlxsw_config_profile *profile,
3913 u64 *p_single_size, u64 *p_double_size,
3914 u64 *p_linear_size)
3915{
3916 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3917 u32 double_size;
3918 int err;
3919
3920 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3921 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
3922 return -EIO;
3923
3924
3925
3926
3927
3928
3929
3930
3931 err = devlink_resource_size_get(devlink,
3932 MLXSW_SP_RESOURCE_KVD_LINEAR,
3933 p_linear_size);
3934 if (err)
3935 *p_linear_size = profile->kvd_linear_size;
3936
3937 err = devlink_resource_size_get(devlink,
3938 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3939 p_double_size);
3940 if (err) {
3941 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3942 *p_linear_size;
3943 double_size *= profile->kvd_hash_double_parts;
3944 double_size /= profile->kvd_hash_double_parts +
3945 profile->kvd_hash_single_parts;
3946 *p_double_size = rounddown(double_size,
3947 MLXSW_SP_KVD_GRANULARITY);
3948 }
3949
3950 err = devlink_resource_size_get(devlink,
3951 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3952 p_single_size);
3953 if (err)
3954 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3955 *p_double_size - *p_linear_size;
3956
3957
3958 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3959 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
3960 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
3961 return -EIO;
3962
3963 return 0;
3964}
3965
3966static struct mlxsw_driver mlxsw_sp_driver = {
3967 .kind = mlxsw_sp_driver_name,
3968 .priv_size = sizeof(struct mlxsw_sp),
3969 .init = mlxsw_sp_init,
3970 .fini = mlxsw_sp_fini,
3971 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
3972 .port_split = mlxsw_sp_port_split,
3973 .port_unsplit = mlxsw_sp_port_unsplit,
3974 .sb_pool_get = mlxsw_sp_sb_pool_get,
3975 .sb_pool_set = mlxsw_sp_sb_pool_set,
3976 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3977 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3978 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3979 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3980 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3981 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3982 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3983 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3984 .txhdr_construct = mlxsw_sp_txhdr_construct,
3985 .resources_register = mlxsw_sp_resources_register,
3986 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
3987 .txhdr_len = MLXSW_TXHDR_LEN,
3988 .profile = &mlxsw_sp_config_profile,
3989 .res_query_enabled = true,
3990};
3991
3992bool mlxsw_sp_port_dev_check(const struct net_device *dev)
3993{
3994 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3995}
3996
3997static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
3998{
3999 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
4000 int ret = 0;
4001
4002 if (mlxsw_sp_port_dev_check(lower_dev)) {
4003 *p_mlxsw_sp_port = netdev_priv(lower_dev);
4004 ret = 1;
4005 }
4006
4007 return ret;
4008}
4009
4010struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
4011{
4012 struct mlxsw_sp_port *mlxsw_sp_port;
4013
4014 if (mlxsw_sp_port_dev_check(dev))
4015 return netdev_priv(dev);
4016
4017 mlxsw_sp_port = NULL;
4018 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
4019
4020 return mlxsw_sp_port;
4021}
4022
4023struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
4024{
4025 struct mlxsw_sp_port *mlxsw_sp_port;
4026
4027 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4028 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4029}
4030
4031struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
4032{
4033 struct mlxsw_sp_port *mlxsw_sp_port;
4034
4035 if (mlxsw_sp_port_dev_check(dev))
4036 return netdev_priv(dev);
4037
4038 mlxsw_sp_port = NULL;
4039 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4040 &mlxsw_sp_port);
4041
4042 return mlxsw_sp_port;
4043}
4044
4045struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4046{
4047 struct mlxsw_sp_port *mlxsw_sp_port;
4048
4049 rcu_read_lock();
4050 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4051 if (mlxsw_sp_port)
4052 dev_hold(mlxsw_sp_port->dev);
4053 rcu_read_unlock();
4054 return mlxsw_sp_port;
4055}
4056
4057void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4058{
4059 dev_put(mlxsw_sp_port->dev);
4060}
4061
4062static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4063{
4064 char sldr_pl[MLXSW_REG_SLDR_LEN];
4065
4066 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4067 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4068}
4069
4070static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4071{
4072 char sldr_pl[MLXSW_REG_SLDR_LEN];
4073
4074 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4075 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4076}
4077
4078static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4079 u16 lag_id, u8 port_index)
4080{
4081 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4082 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4083
4084 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4085 lag_id, port_index);
4086 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4087}
4088
4089static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4090 u16 lag_id)
4091{
4092 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4093 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4094
4095 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4096 lag_id);
4097 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4098}
4099
4100static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4101 u16 lag_id)
4102{
4103 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4104 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4105
4106 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4107 lag_id);
4108 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4109}
4110
4111static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4112 u16 lag_id)
4113{
4114 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4115 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4116
4117 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4118 lag_id);
4119 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4120}
4121
4122static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4123 struct net_device *lag_dev,
4124 u16 *p_lag_id)
4125{
4126 struct mlxsw_sp_upper *lag;
4127 int free_lag_id = -1;
4128 u64 max_lag;
4129 int i;
4130
4131 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4132 for (i = 0; i < max_lag; i++) {
4133 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4134 if (lag->ref_count) {
4135 if (lag->dev == lag_dev) {
4136 *p_lag_id = i;
4137 return 0;
4138 }
4139 } else if (free_lag_id < 0) {
4140 free_lag_id = i;
4141 }
4142 }
4143 if (free_lag_id < 0)
4144 return -EBUSY;
4145 *p_lag_id = free_lag_id;
4146 return 0;
4147}
4148
4149static bool
4150mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4151 struct net_device *lag_dev,
4152 struct netdev_lag_upper_info *lag_upper_info)
4153{
4154 u16 lag_id;
4155
4156 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4157 dev_err(mlxsw_sp->bus_info->dev,
4158 "spectrum: Exceeded number of supported LAG devices");
4159 return false;
4160 }
4161 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4162 dev_err(mlxsw_sp->bus_info->dev,
4163 "spectrum: LAG device using unsupported Tx type");
4164 return false;
4165 }
4166 return true;
4167}
4168
4169static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4170 u16 lag_id, u8 *p_port_index)
4171{
4172 u64 max_lag_members;
4173 int i;
4174
4175 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4176 MAX_LAG_MEMBERS);
4177 for (i = 0; i < max_lag_members; i++) {
4178 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4179 *p_port_index = i;
4180 return 0;
4181 }
4182 }
4183 return -EBUSY;
4184}
4185
4186static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4187 struct net_device *lag_dev)
4188{
4189 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4190 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
4191 struct mlxsw_sp_upper *lag;
4192 u16 lag_id;
4193 u8 port_index;
4194 int err;
4195
4196 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4197 if (err)
4198 return err;
4199 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4200 if (!lag->ref_count) {
4201 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4202 if (err)
4203 return err;
4204 lag->dev = lag_dev;
4205 }
4206
4207 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4208 if (err)
4209 return err;
4210 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4211 if (err)
4212 goto err_col_port_add;
4213 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4214 if (err)
4215 goto err_col_port_enable;
4216
4217 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4218 mlxsw_sp_port->local_port);
4219 mlxsw_sp_port->lag_id = lag_id;
4220 mlxsw_sp_port->lagged = 1;
4221 lag->ref_count++;
4222
4223
4224 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4225 if (mlxsw_sp_port_vlan->fid)
4226 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
4227
4228 return 0;
4229
4230err_col_port_enable:
4231 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4232err_col_port_add:
4233 if (!lag->ref_count)
4234 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4235 return err;
4236}
4237
4238static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4239 struct net_device *lag_dev)
4240{
4241 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4242 u16 lag_id = mlxsw_sp_port->lag_id;
4243 struct mlxsw_sp_upper *lag;
4244
4245 if (!mlxsw_sp_port->lagged)
4246 return;
4247 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4248 WARN_ON(lag->ref_count == 0);
4249
4250 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4251 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4252
4253
4254 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
4255
4256 if (lag->ref_count == 1)
4257 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4258
4259 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4260 mlxsw_sp_port->local_port);
4261 mlxsw_sp_port->lagged = 0;
4262 lag->ref_count--;
4263
4264 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4265
4266 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
4267}
4268
4269static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4270 u16 lag_id)
4271{
4272 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4273 char sldr_pl[MLXSW_REG_SLDR_LEN];
4274
4275 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4276 mlxsw_sp_port->local_port);
4277 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4278}
4279
4280static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4281 u16 lag_id)
4282{
4283 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4284 char sldr_pl[MLXSW_REG_SLDR_LEN];
4285
4286 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4287 mlxsw_sp_port->local_port);
4288 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4289}
4290
4291static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4292 bool lag_tx_enabled)
4293{
4294 if (lag_tx_enabled)
4295 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4296 mlxsw_sp_port->lag_id);
4297 else
4298 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4299 mlxsw_sp_port->lag_id);
4300}
4301
4302static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4303 struct netdev_lag_lower_state_info *info)
4304{
4305 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4306}
4307
4308static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4309 bool enable)
4310{
4311 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4312 enum mlxsw_reg_spms_state spms_state;
4313 char *spms_pl;
4314 u16 vid;
4315 int err;
4316
4317 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4318 MLXSW_REG_SPMS_STATE_DISCARDING;
4319
4320 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4321 if (!spms_pl)
4322 return -ENOMEM;
4323 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4324
4325 for (vid = 0; vid < VLAN_N_VID; vid++)
4326 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4327
4328 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4329 kfree(spms_pl);
4330 return err;
4331}
4332
4333static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4334{
4335 u16 vid = 1;
4336 int err;
4337
4338 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
4339 if (err)
4340 return err;
4341 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4342 if (err)
4343 goto err_port_stp_set;
4344 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4345 true, false);
4346 if (err)
4347 goto err_port_vlan_set;
4348
4349 for (; vid <= VLAN_N_VID - 1; vid++) {
4350 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4351 vid, false);
4352 if (err)
4353 goto err_vid_learning_set;
4354 }
4355
4356 return 0;
4357
4358err_vid_learning_set:
4359 for (vid--; vid >= 1; vid--)
4360 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
4361err_port_vlan_set:
4362 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4363err_port_stp_set:
4364 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4365 return err;
4366}
4367
4368static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4369{
4370 u16 vid;
4371
4372 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4373 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4374 vid, true);
4375
4376 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4377 false, false);
4378 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4379 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4380}
4381
4382static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4383 struct net_device *dev,
4384 unsigned long event, void *ptr)
4385{
4386 struct netdev_notifier_changeupper_info *info;
4387 struct mlxsw_sp_port *mlxsw_sp_port;
4388 struct net_device *upper_dev;
4389 struct mlxsw_sp *mlxsw_sp;
4390 int err = 0;
4391
4392 mlxsw_sp_port = netdev_priv(dev);
4393 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4394 info = ptr;
4395
4396 switch (event) {
4397 case NETDEV_PRECHANGEUPPER:
4398 upper_dev = info->upper_dev;
4399 if (!is_vlan_dev(upper_dev) &&
4400 !netif_is_lag_master(upper_dev) &&
4401 !netif_is_bridge_master(upper_dev) &&
4402 !netif_is_ovs_master(upper_dev)) {
4403 dev_err(mlxsw_sp->bus_info->dev,
4404 "spectrum: Unknown upper device type");
4405 return -EINVAL;
4406 }
4407 if (!info->linking)
4408 break;
4409 if (netdev_has_any_upper_dev(upper_dev) &&
4410 (!netif_is_bridge_master(upper_dev) ||
4411 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4412 upper_dev))) {
4413 dev_err(mlxsw_sp->bus_info->dev,
4414 "spectrum: Enslaving a port to a device that already has an upper device is not supported");
4415 return -EINVAL;
4416 }
4417 if (netif_is_lag_master(upper_dev) &&
4418 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4419 info->upper_info))
4420 return -EINVAL;
4421 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4422 dev_err(mlxsw_sp->bus_info->dev,
4423 "spectrum: Master device is a LAG master and this device has a VLAN");
4424 return -EINVAL;
4425 }
4426 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4427 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4428 dev_err(mlxsw_sp->bus_info->dev,
4429 "spectrum: Can not put a VLAN on a LAG port");
4430 return -EINVAL;
4431 }
4432 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4433 dev_err(mlxsw_sp->bus_info->dev,
4434 "spectrum: Master device is an OVS master and this device has a VLAN");
4435 return -EINVAL;
4436 }
4437 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4438 dev_err(mlxsw_sp->bus_info->dev,
4439 "spectrum: Can not put a VLAN on an OVS port");
4440 return -EINVAL;
4441 }
4442 if (is_vlan_dev(upper_dev) &&
4443 vlan_dev_vlan_id(upper_dev) == 1) {
4444 dev_err(mlxsw_sp->bus_info->dev,
4445 "Creating a VLAN device with VID 1 is unsupported: VLAN 1 carries untagged traffic");
4446 return -EINVAL;
4447 }
4448 break;
4449 case NETDEV_CHANGEUPPER:
4450 upper_dev = info->upper_dev;
4451 if (netif_is_bridge_master(upper_dev)) {
4452 if (info->linking)
4453 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4454 lower_dev,
4455 upper_dev);
4456 else
4457 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4458 lower_dev,
4459 upper_dev);
4460 } else if (netif_is_lag_master(upper_dev)) {
4461 if (info->linking)
4462 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4463 upper_dev);
4464 else
4465 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4466 upper_dev);
4467 } else if (netif_is_ovs_master(upper_dev)) {
4468 if (info->linking)
4469 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4470 else
4471 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
4472 }
4473 break;
4474 }
4475
4476 return err;
4477}
4478
4479static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4480 unsigned long event, void *ptr)
4481{
4482 struct netdev_notifier_changelowerstate_info *info;
4483 struct mlxsw_sp_port *mlxsw_sp_port;
4484 int err;
4485
4486 mlxsw_sp_port = netdev_priv(dev);
4487 info = ptr;
4488
4489 switch (event) {
4490 case NETDEV_CHANGELOWERSTATE:
4491 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4492 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4493 info->lower_state_info);
4494 if (err)
4495 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4496 }
4497 break;
4498 }
4499
4500 return 0;
4501}
4502
4503static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4504 struct net_device *port_dev,
4505 unsigned long event, void *ptr)
4506{
4507 switch (event) {
4508 case NETDEV_PRECHANGEUPPER:
4509 case NETDEV_CHANGEUPPER:
4510 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4511 event, ptr);
4512 case NETDEV_CHANGELOWERSTATE:
4513 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4514 ptr);
4515 }
4516
4517 return 0;
4518}
4519
4520static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4521 unsigned long event, void *ptr)
4522{
4523 struct net_device *dev;
4524 struct list_head *iter;
4525 int ret;
4526
4527 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4528 if (mlxsw_sp_port_dev_check(dev)) {
4529 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4530 ptr);
4531 if (ret)
4532 return ret;
4533 }
4534 }
4535
4536 return 0;
4537}
4538
4539static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4540 struct net_device *dev,
4541 unsigned long event, void *ptr,
4542 u16 vid)
4543{
4544 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4545 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4546 struct netdev_notifier_changeupper_info *info = ptr;
4547 struct net_device *upper_dev;
4548 int err = 0;
4549
4550 switch (event) {
4551 case NETDEV_PRECHANGEUPPER:
4552 upper_dev = info->upper_dev;
4553 if (!netif_is_bridge_master(upper_dev)) {
4554 netdev_err(dev, "spectrum: VLAN devices only support bridge and VRF uppers");
4555 return -EINVAL;
4556 }
4557 if (!info->linking)
4558 break;
4559 if (netdev_has_any_upper_dev(upper_dev) &&
4560 (!netif_is_bridge_master(upper_dev) ||
4561 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4562 upper_dev))) {
4563 netdev_err(dev, "spectrum: Enslaving a port to a device that already has an upper device is not supported");
4564 return -EINVAL;
4565 }
4566 break;
4567 case NETDEV_CHANGEUPPER:
4568 upper_dev = info->upper_dev;
4569 if (netif_is_bridge_master(upper_dev)) {
4570 if (info->linking)
4571 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4572 vlan_dev,
4573 upper_dev);
4574 else
4575 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4576 vlan_dev,
4577 upper_dev);
4578 } else {
4579 err = -EINVAL;
4580 WARN_ON(1);
4581 }
4582 break;
4583 }
4584
4585 return err;
4586}
4587
4588static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4589 struct net_device *lag_dev,
4590 unsigned long event,
4591 void *ptr, u16 vid)
4592{
4593 struct net_device *dev;
4594 struct list_head *iter;
4595 int ret;
4596
4597 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4598 if (mlxsw_sp_port_dev_check(dev)) {
4599 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4600 event, ptr,
4601 vid);
4602 if (ret)
4603 return ret;
4604 }
4605 }
4606
4607 return 0;
4608}
4609
4610static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4611 unsigned long event, void *ptr)
4612{
4613 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4614 u16 vid = vlan_dev_vlan_id(vlan_dev);
4615
4616 if (mlxsw_sp_port_dev_check(real_dev))
4617 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4618 event, ptr, vid);
4619 else if (netif_is_lag_master(real_dev))
4620 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4621 real_dev, event,
4622 ptr, vid);
4623
4624 return 0;
4625}
4626
4627static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4628{
4629 struct netdev_notifier_changeupper_info *info = ptr;
4630
4631 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4632 return false;
4633 return netif_is_l3_master(info->upper_dev);
4634}
4635
4636static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
4637 unsigned long event, void *ptr)
4638{
4639 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
4640 struct mlxsw_sp_span_entry *span_entry;
4641 struct mlxsw_sp *mlxsw_sp;
4642 int err = 0;
4643
4644 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
4645 if (event == NETDEV_UNREGISTER) {
4646 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
4647 if (span_entry)
4648 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
4649 }
4650 mlxsw_sp_span_respin(mlxsw_sp);
4651
4652 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
4653 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
4654 event, ptr);
4655 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
4656 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
4657 event, ptr);
4658 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4659 err = mlxsw_sp_netdevice_router_port_event(dev);
4660 else if (mlxsw_sp_is_vrf_event(event, ptr))
4661 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
4662 else if (mlxsw_sp_port_dev_check(dev))
4663 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
4664 else if (netif_is_lag_master(dev))
4665 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4666 else if (is_vlan_dev(dev))
4667 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
4668
4669 return notifier_from_errno(err);
4670}
4671
4672static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4673 .notifier_call = mlxsw_sp_inetaddr_event,
4674 .priority = 10,
4675};
4676
4677static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4678 .notifier_call = mlxsw_sp_inet6addr_event,
4679};
4680
4681static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4682 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4683 {0, },
4684};
4685
4686static struct pci_driver mlxsw_sp_pci_driver = {
4687 .name = mlxsw_sp_driver_name,
4688 .id_table = mlxsw_sp_pci_id_table,
4689};
4690
4691static int __init mlxsw_sp_module_init(void)
4692{
4693 int err;
4694
4695 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4696 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
4697
4698 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4699 if (err)
4700 goto err_core_driver_register;
4701
4702 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4703 if (err)
4704 goto err_pci_driver_register;
4705
4706 return 0;
4707
4708err_pci_driver_register:
4709 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
4710err_core_driver_register:
4711 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
4712 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4713 return err;
4714}
4715
4716static void __exit mlxsw_sp_module_exit(void)
4717{
4718 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
4719 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
4720 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
4721 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4722}
4723
4724module_init(mlxsw_sp_module_init);
4725module_exit(mlxsw_sp_module_exit);
4726
4727MODULE_LICENSE("Dual BSD/GPL");
4728MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4729MODULE_DESCRIPTION("Mellanox Spectrum driver");
4730MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
4731MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);
4732