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33#ifndef RT2800_H
34#define RT2800_H
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58
59#define RF2820 0x0001
60#define RF2850 0x0002
61#define RF2720 0x0003
62#define RF2750 0x0004
63#define RF3020 0x0005
64#define RF2020 0x0006
65#define RF3021 0x0007
66#define RF3022 0x0008
67#define RF3052 0x0009
68#define RF2853 0x000a
69#define RF3320 0x000b
70#define RF3322 0x000c
71#define RF3053 0x000d
72#define RF5592 0x000f
73#define RF3070 0x3070
74#define RF3290 0x3290
75#define RF5350 0x5350
76#define RF5360 0x5360
77#define RF5362 0x5362
78#define RF5370 0x5370
79#define RF5372 0x5372
80#define RF5390 0x5390
81#define RF5392 0x5392
82#define RF7620 0x7620
83
84
85
86
87#define REV_RT2860C 0x0100
88#define REV_RT2860D 0x0101
89#define REV_RT2872E 0x0200
90#define REV_RT3070E 0x0200
91#define REV_RT3070F 0x0201
92#define REV_RT3071E 0x0211
93#define REV_RT3090E 0x0211
94#define REV_RT3390E 0x0211
95#define REV_RT3593E 0x0211
96#define REV_RT5390F 0x0502
97#define REV_RT5390R 0x1502
98#define REV_RT5592C 0x0221
99
100#define DEFAULT_RSSI_OFFSET 120
101
102
103
104
105#define CSR_REG_BASE 0x1000
106#define CSR_REG_SIZE 0x0800
107#define EEPROM_BASE 0x0000
108#define EEPROM_SIZE 0x0200
109#define BBP_BASE 0x0000
110#define BBP_SIZE 0x00ff
111#define RF_BASE 0x0004
112#define RF_SIZE 0x0010
113#define RFCSR_BASE 0x0000
114#define RFCSR_SIZE 0x0040
115
116
117
118
119#define NUM_TX_QUEUES 4
120
121
122
123
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126
127
128
129#define MAC_CSR0_3290 0x0000
130
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134
135
136
137#define E2PROM_CSR 0x0004
138#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
139#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
140#define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
141#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
142#define E2PROM_CSR_TYPE FIELD32(0x00000030)
143#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
144#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
145
146
147
148
149#define CMB_CTRL 0x0020
150#define AUX_OPT_BIT0 FIELD32(0x00000001)
151#define AUX_OPT_BIT1 FIELD32(0x00000002)
152#define AUX_OPT_BIT2 FIELD32(0x00000004)
153#define AUX_OPT_BIT3 FIELD32(0x00000008)
154#define AUX_OPT_BIT4 FIELD32(0x00000010)
155#define AUX_OPT_BIT5 FIELD32(0x00000020)
156#define AUX_OPT_BIT6 FIELD32(0x00000040)
157#define AUX_OPT_BIT7 FIELD32(0x00000080)
158#define AUX_OPT_BIT8 FIELD32(0x00000100)
159#define AUX_OPT_BIT9 FIELD32(0x00000200)
160#define AUX_OPT_BIT10 FIELD32(0x00000400)
161#define AUX_OPT_BIT11 FIELD32(0x00000800)
162#define AUX_OPT_BIT12 FIELD32(0x00001000)
163#define AUX_OPT_BIT13 FIELD32(0x00002000)
164#define AUX_OPT_BIT14 FIELD32(0x00004000)
165#define AUX_OPT_BIT15 FIELD32(0x00008000)
166#define LDO25_LEVEL FIELD32(0x00030000)
167#define LDO25_LARGEA FIELD32(0x00040000)
168#define LDO25_FRC_ON FIELD32(0x00080000)
169#define CMB_RSV FIELD32(0x00300000)
170#define XTAL_RDY FIELD32(0x00400000)
171#define PLL_LD FIELD32(0x00800000)
172#define LDO_CORE_LEVEL FIELD32(0x0F000000)
173#define LDO_BGSEL FIELD32(0x30000000)
174#define LDO3_EN FIELD32(0x40000000)
175#define LDO0_EN FIELD32(0x80000000)
176
177
178
179
180#define EFUSE_CTRL_3290 0x0024
181
182
183
184
185#define EFUSE_DATA3_3290 0x0028
186
187
188
189
190#define EFUSE_DATA2_3290 0x002c
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192
193
194
195#define EFUSE_DATA1_3290 0x0030
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197
198
199
200#define EFUSE_DATA0_3290 0x0034
201
202
203
204
205
206#define OSC_CTRL 0x0038
207#define OSC_REF_CYCLE FIELD32(0x00001fff)
208#define OSC_RSV FIELD32(0x0000e000)
209#define OSC_CAL_CNT FIELD32(0x0fff0000)
210#define OSC_CAL_ACK FIELD32(0x10000000)
211#define OSC_CLK_32K_VLD FIELD32(0x20000000)
212#define OSC_CAL_REQ FIELD32(0x40000000)
213#define OSC_ROSC_EN FIELD32(0x80000000)
214
215
216
217
218#define COEX_CFG0 0x0040
219#define COEX_CFG_ANT FIELD32(0xff000000)
220
221
222
223#define COEX_CFG1 0x0044
224
225
226
227
228#define COEX_CFG2 0x0048
229#define BT_COEX_CFG1 FIELD32(0xff000000)
230#define BT_COEX_CFG0 FIELD32(0x00ff0000)
231#define WL_COEX_CFG1 FIELD32(0x0000ff00)
232#define WL_COEX_CFG0 FIELD32(0x000000ff)
233
234
235
236
237#define PLL_CTRL 0x0050
238#define PLL_RESERVED_INPUT1 FIELD32(0x000000ff)
239#define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00)
240#define PLL_CONTROL FIELD32(0x00070000)
241#define PLL_LPF_R1 FIELD32(0x00080000)
242#define PLL_LPF_C1_CTRL FIELD32(0x00300000)
243#define PLL_LPF_C2_CTRL FIELD32(0x00c00000)
244#define PLL_CP_CURRENT_CTRL FIELD32(0x03000000)
245#define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000)
246#define PLL_LOCK_CTRL FIELD32(0x70000000)
247#define PLL_VBGBK_EN FIELD32(0x80000000)
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249
250
251
252
253
254#define WLAN_FUN_CTRL 0x0080
255#define WLAN_EN FIELD32(0x00000001)
256#define WLAN_CLK_EN FIELD32(0x00000002)
257#define WLAN_RSV1 FIELD32(0x00000004)
258#define WLAN_RESET FIELD32(0x00000008)
259#define PCIE_APP0_CLK_REQ FIELD32(0x00000010)
260#define FRC_WL_ANT_SET FIELD32(0x00000020)
261#define INV_TR_SW0 FIELD32(0x00000040)
262#define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100)
263#define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200)
264#define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400)
265#define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800)
266#define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000)
267#define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000)
268#define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000)
269#define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000)
270#define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00)
271#define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000)
272#define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000)
273#define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000)
274#define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000)
275#define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000)
276#define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000)
277#define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000)
278#define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000)
279#define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000)
280#define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000)
281#define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000)
282#define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000)
283#define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000)
284#define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000)
285#define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000)
286#define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000)
287#define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000)
288#define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000)
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290
291
292
293#define AUX_CTRL 0x10c
294#define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
295#define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
296
297
298
299
300#define OPT_14_CSR 0x0114
301#define OPT_14_CSR_BIT0 FIELD32(0x00000001)
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305
306
307
308#define INT_SOURCE_CSR 0x0200
309#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
310#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
311#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
312#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
313#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
314#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
315#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
316#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
317#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
318#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
319#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
320#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
321#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
322#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
323#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
324#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
325#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
326#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
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328
329
330
331#define INT_MASK_CSR 0x0204
332#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
333#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
334#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
335#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
336#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
337#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
338#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
339#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
340#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
341#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
342#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
343#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
344#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
345#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
346#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
347#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
348#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
349#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
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352
353
354#define WPDMA_GLO_CFG 0x0208
355#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
356#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
357#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
358#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
359#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
360#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
361#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
362#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
363#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
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367
368#define WPDMA_RST_IDX 0x020c
369#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
370#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
371#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
372#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
373#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
374#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
375#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
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377
378
379
380#define DELAY_INT_CFG 0x0210
381#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
382#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
383#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
384#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
385#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
386#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
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389
390
391
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393
394
395#define WMM_AIFSN_CFG 0x0214
396#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
397#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
398#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
399#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
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406
407
408#define WMM_CWMIN_CFG 0x0218
409#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
410#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
411#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
412#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
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419
420
421#define WMM_CWMAX_CFG 0x021c
422#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
423#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
424#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
425#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
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427
428
429
430
431
432#define WMM_TXOP0_CFG 0x0220
433#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
434#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
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436
437
438
439
440
441#define WMM_TXOP1_CFG 0x0224
442#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
443#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
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445
446
447
448
449
450#define GPIO_CTRL 0x0228
451#define GPIO_CTRL_VAL0 FIELD32(0x00000001)
452#define GPIO_CTRL_VAL1 FIELD32(0x00000002)
453#define GPIO_CTRL_VAL2 FIELD32(0x00000004)
454#define GPIO_CTRL_VAL3 FIELD32(0x00000008)
455#define GPIO_CTRL_VAL4 FIELD32(0x00000010)
456#define GPIO_CTRL_VAL5 FIELD32(0x00000020)
457#define GPIO_CTRL_VAL6 FIELD32(0x00000040)
458#define GPIO_CTRL_VAL7 FIELD32(0x00000080)
459#define GPIO_CTRL_DIR0 FIELD32(0x00000100)
460#define GPIO_CTRL_DIR1 FIELD32(0x00000200)
461#define GPIO_CTRL_DIR2 FIELD32(0x00000400)
462#define GPIO_CTRL_DIR3 FIELD32(0x00000800)
463#define GPIO_CTRL_DIR4 FIELD32(0x00001000)
464#define GPIO_CTRL_DIR5 FIELD32(0x00002000)
465#define GPIO_CTRL_DIR6 FIELD32(0x00004000)
466#define GPIO_CTRL_DIR7 FIELD32(0x00008000)
467#define GPIO_CTRL_VAL8 FIELD32(0x00010000)
468#define GPIO_CTRL_VAL9 FIELD32(0x00020000)
469#define GPIO_CTRL_VAL10 FIELD32(0x00040000)
470#define GPIO_CTRL_DIR8 FIELD32(0x01000000)
471#define GPIO_CTRL_DIR9 FIELD32(0x02000000)
472#define GPIO_CTRL_DIR10 FIELD32(0x04000000)
473
474
475
476
477#define MCU_CMD_CFG 0x022c
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479
480
481
482#define TX_BASE_PTR0 0x0230
483#define TX_MAX_CNT0 0x0234
484#define TX_CTX_IDX0 0x0238
485#define TX_DTX_IDX0 0x023c
486
487
488
489
490#define TX_BASE_PTR1 0x0240
491#define TX_MAX_CNT1 0x0244
492#define TX_CTX_IDX1 0x0248
493#define TX_DTX_IDX1 0x024c
494
495
496
497
498#define TX_BASE_PTR2 0x0250
499#define TX_MAX_CNT2 0x0254
500#define TX_CTX_IDX2 0x0258
501#define TX_DTX_IDX2 0x025c
502
503
504
505
506#define TX_BASE_PTR3 0x0260
507#define TX_MAX_CNT3 0x0264
508#define TX_CTX_IDX3 0x0268
509#define TX_DTX_IDX3 0x026c
510
511
512
513
514#define TX_BASE_PTR4 0x0270
515#define TX_MAX_CNT4 0x0274
516#define TX_CTX_IDX4 0x0278
517#define TX_DTX_IDX4 0x027c
518
519
520
521
522#define TX_BASE_PTR5 0x0280
523#define TX_MAX_CNT5 0x0284
524#define TX_CTX_IDX5 0x0288
525#define TX_DTX_IDX5 0x028c
526
527
528
529
530#define RX_BASE_PTR 0x0290
531#define RX_MAX_CNT 0x0294
532#define RX_CRX_IDX 0x0298
533#define RX_DRX_IDX 0x029c
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535
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547
548
549#define USB_DMA_CFG 0x02a0
550#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
551#define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
552#define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
553#define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
554#define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
555#define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
556#define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
557#define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
558#define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
559#define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
560#define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
561
562
563
564
565
566
567
568#define US_CYC_CNT 0x02a4
569#define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
570#define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
571
572
573
574
575
576#define PBF_SYS_CTRL 0x0400
577#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
578#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
579
580
581
582
583#define HOST_CMD_CSR 0x0404
584#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
585
586
587
588
589
590#define PBF_CFG 0x0408
591#define PBF_MAX_PCNT 0x040c
592#define PBF_CTRL 0x0410
593#define PBF_INT_STA 0x0414
594#define PBF_INT_ENA 0x0418
595
596
597
598
599#define BCN_OFFSET0 0x042c
600#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
601#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
602#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
603#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
604
605
606
607
608#define BCN_OFFSET1 0x0430
609#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
610#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
611#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
612#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
613
614
615
616
617
618
619
620
621#define TXRXQ_PCNT 0x0438
622#define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
623#define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
624#define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
625#define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
626
627
628
629
630
631#define PBF_DBG 0x043c
632
633
634
635
636#define RF_CSR_CFG 0x0500
637#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
638#define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
639#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
640#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
641
642
643
644
645#define RF_CSR_CFG_DATA_MT7620 FIELD32(0x0000ff00)
646#define RF_CSR_CFG_REGNUM_MT7620 FIELD32(0x03ff0000)
647#define RF_CSR_CFG_WRITE_MT7620 FIELD32(0x00000010)
648#define RF_CSR_CFG_BUSY_MT7620 FIELD32(0x00000001)
649
650
651#define RF_CONTROL0 0x0518
652#define RF_BYPASS0 0x051c
653#define RF_CONTROL1 0x0520
654#define RF_BYPASS1 0x0524
655#define RF_CONTROL2 0x0528
656#define RF_BYPASS2 0x052c
657#define RF_CONTROL3 0x0530
658#define RF_BYPASS3 0x0534
659
660
661
662
663#define EFUSE_CTRL 0x0580
664#define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
665#define EFUSE_CTRL_MODE FIELD32(0x000000c0)
666#define EFUSE_CTRL_KICK FIELD32(0x40000000)
667#define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
668
669
670
671
672#define EFUSE_DATA0 0x0590
673
674
675
676
677#define EFUSE_DATA1 0x0594
678
679
680
681
682#define EFUSE_DATA2 0x0598
683
684
685
686
687#define EFUSE_DATA3 0x059c
688
689
690
691
692#define LDO_CFG0 0x05d4
693#define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
694#define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
695#define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
696#define LDO_CFG0_BGSEL FIELD32(0x03000000)
697#define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
698#define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
699#define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
700
701
702
703
704#define GPIO_SWITCH 0x05dc
705#define GPIO_SWITCH_0 FIELD32(0x00000001)
706#define GPIO_SWITCH_1 FIELD32(0x00000002)
707#define GPIO_SWITCH_2 FIELD32(0x00000004)
708#define GPIO_SWITCH_3 FIELD32(0x00000008)
709#define GPIO_SWITCH_4 FIELD32(0x00000010)
710#define GPIO_SWITCH_5 FIELD32(0x00000020)
711#define GPIO_SWITCH_6 FIELD32(0x00000040)
712#define GPIO_SWITCH_7 FIELD32(0x00000080)
713
714
715
716
717#define MAC_DEBUG_INDEX 0x05e8
718#define MAC_DEBUG_INDEX_XTAL FIELD32(0x80000000)
719
720
721
722
723
724
725
726
727
728
729
730#define MAC_CSR0 0x1000
731#define MAC_CSR0_REVISION FIELD32(0x0000ffff)
732#define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
733
734
735
736
737#define MAC_SYS_CTRL 0x1004
738#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
739#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
740#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
741#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
742#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
743#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
744#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
745#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
746
747
748
749
750#define MAC_ADDR_DW0 0x1008
751#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
752#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
753#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
754#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
755
756
757
758
759
760
761
762
763
764#define MAC_ADDR_DW1 0x100c
765#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
766#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
767#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
768
769
770
771
772#define MAC_BSSID_DW0 0x1010
773#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
774#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
775#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
776#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
777
778
779
780
781
782
783
784
785
786
787
788
789#define MAC_BSSID_DW1 0x1014
790#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
791#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
792#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
793#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
794
795
796
797
798
799
800
801#define MAX_LEN_CFG 0x1018
802#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
803#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
804#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
805#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
806
807
808
809
810
811
812
813
814
815
816#define BBP_CSR_CFG 0x101c
817#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
818#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
819#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
820#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
821#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
822#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
823
824
825
826
827
828
829
830
831
832#define RF_CSR_CFG0 0x1020
833#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
834#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
835#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
836#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
837#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
838#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
839
840
841
842
843
844
845
846
847#define RF_CSR_CFG1 0x1024
848#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
849#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
850
851
852
853
854
855#define RF_CSR_CFG2 0x1028
856#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872#define LED_CFG 0x102c
873#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
874#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
875#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
876#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
877#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
878#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
879#define LED_CFG_LED_POLAR FIELD32(0x40000000)
880
881
882
883
884
885
886
887
888
889#define AMPDU_BA_WINSIZE 0x1040
890#define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
891#define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
892
893
894
895
896
897
898
899
900
901
902
903#define XIFS_TIME_CFG 0x1100
904#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
905#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
906#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
907#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
908#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
909
910
911
912
913#define BKOFF_SLOT_CFG 0x1104
914#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
915#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
916
917
918
919
920#define NAV_TIME_CFG 0x1108
921#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
922#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
923#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
924#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
925
926
927
928
929
930
931
932
933
934#define CH_TIME_CFG 0x110c
935#define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
936#define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
937#define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
938#define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
939#define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
940
941
942
943
944#define PBF_LIFE_TIMER 0x1110
945
946
947
948
949
950
951
952
953#define BCN_TIME_CFG 0x1114
954#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
955#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
956#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
957#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
958#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
959#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
960
961
962
963
964
965
966#define TBTT_SYNC_CFG 0x1118
967#define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
968#define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
969#define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
970#define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
971
972
973
974
975#define TSF_TIMER_DW0 0x111c
976#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
977
978
979
980
981#define TSF_TIMER_DW1 0x1120
982#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
983
984
985
986
987#define TBTT_TIMER 0x1124
988
989
990
991
992
993
994#define INT_TIMER_CFG 0x1128
995#define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
996#define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
997
998
999
1000
1001#define INT_TIMER_EN 0x112c
1002#define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
1003#define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
1004
1005
1006
1007
1008#define CH_IDLE_STA 0x1130
1009
1010
1011
1012
1013#define CH_BUSY_STA 0x1134
1014
1015
1016
1017
1018#define CH_BUSY_STA_SEC 0x1138
1019
1020
1021
1022
1023
1024
1025#define MAC_STATUS_CFG 0x1200
1026#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
1027
1028
1029
1030
1031#define PWR_PIN_CFG 0x1204
1032
1033
1034
1035
1036
1037
1038#define AUTOWAKEUP_CFG 0x1208
1039#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
1040#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
1041#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
1042
1043
1044
1045
1046#define MIMO_PS_CFG 0x1210
1047#define MIMO_PS_CFG_MMPS_BB_EN FIELD32(0x00000001)
1048#define MIMO_PS_CFG_MMPS_RX_ANT_NUM FIELD32(0x00000006)
1049#define MIMO_PS_CFG_MMPS_RF_EN FIELD32(0x00000008)
1050#define MIMO_PS_CFG_RX_STBY_POL FIELD32(0x00000010)
1051#define MIMO_PS_CFG_RX_RX_STBY0 FIELD32(0x00000020)
1052
1053
1054
1055
1056#define EDCA_AC0_CFG 0x1300
1057#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
1058#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
1059#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
1060#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
1061
1062
1063
1064
1065#define EDCA_AC1_CFG 0x1304
1066#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
1067#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
1068#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
1069#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
1070
1071
1072
1073
1074#define EDCA_AC2_CFG 0x1308
1075#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
1076#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
1077#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
1078#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
1079
1080
1081
1082
1083#define EDCA_AC3_CFG 0x130c
1084#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
1085#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
1086#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
1087#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
1088
1089
1090
1091
1092#define EDCA_TID_AC_MAP 0x1310
1093
1094
1095
1096
1097#define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
1098#define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
1099#define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
1100#define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
1101#define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
1102#define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
1103#define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
1104#define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
1105
1106
1107
1108
1109#define TX_PWR_CFG_0 0x1314
1110#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
1111#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
1112#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
1113#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
1114#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
1115#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
1116#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
1117#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
1118
1119#define TX_PWR_CFG_0_CCK1_CH0 FIELD32(0x0000000f)
1120#define TX_PWR_CFG_0_CCK1_CH1 FIELD32(0x000000f0)
1121#define TX_PWR_CFG_0_CCK5_CH0 FIELD32(0x00000f00)
1122#define TX_PWR_CFG_0_CCK5_CH1 FIELD32(0x0000f000)
1123#define TX_PWR_CFG_0_OFDM6_CH0 FIELD32(0x000f0000)
1124#define TX_PWR_CFG_0_OFDM6_CH1 FIELD32(0x00f00000)
1125#define TX_PWR_CFG_0_OFDM12_CH0 FIELD32(0x0f000000)
1126#define TX_PWR_CFG_0_OFDM12_CH1 FIELD32(0xf0000000)
1127
1128#define TX_PWR_CFG_0B_1MBS_2MBS FIELD32(0x000000ff)
1129#define TX_PWR_CFG_0B_5MBS_11MBS FIELD32(0x0000ff00)
1130#define TX_PWR_CFG_0B_6MBS_9MBS FIELD32(0x00ff0000)
1131#define TX_PWR_CFG_0B_12MBS_18MBS FIELD32(0xff000000)
1132
1133
1134
1135
1136
1137#define TX_PWR_CFG_1 0x1318
1138#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
1139#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
1140#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
1141#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
1142#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
1143#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
1144#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
1145#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
1146
1147#define TX_PWR_CFG_1_OFDM24_CH0 FIELD32(0x0000000f)
1148#define TX_PWR_CFG_1_OFDM24_CH1 FIELD32(0x000000f0)
1149#define TX_PWR_CFG_1_OFDM48_CH0 FIELD32(0x00000f00)
1150#define TX_PWR_CFG_1_OFDM48_CH1 FIELD32(0x0000f000)
1151#define TX_PWR_CFG_1_MCS0_CH0 FIELD32(0x000f0000)
1152#define TX_PWR_CFG_1_MCS0_CH1 FIELD32(0x00f00000)
1153#define TX_PWR_CFG_1_MCS2_CH0 FIELD32(0x0f000000)
1154#define TX_PWR_CFG_1_MCS2_CH1 FIELD32(0xf0000000)
1155
1156#define TX_PWR_CFG_1B_24MBS_36MBS FIELD32(0x000000ff)
1157#define TX_PWR_CFG_1B_48MBS FIELD32(0x0000ff00)
1158#define TX_PWR_CFG_1B_MCS0_MCS1 FIELD32(0x00ff0000)
1159#define TX_PWR_CFG_1B_MCS2_MCS3 FIELD32(0xff000000)
1160
1161
1162
1163
1164#define TX_PWR_CFG_2 0x131c
1165#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
1166#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
1167#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
1168#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
1169#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
1170#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
1171#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
1172#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
1173
1174#define TX_PWR_CFG_2_MCS4_CH0 FIELD32(0x0000000f)
1175#define TX_PWR_CFG_2_MCS4_CH1 FIELD32(0x000000f0)
1176#define TX_PWR_CFG_2_MCS6_CH0 FIELD32(0x00000f00)
1177#define TX_PWR_CFG_2_MCS6_CH1 FIELD32(0x0000f000)
1178#define TX_PWR_CFG_2_MCS8_CH0 FIELD32(0x000f0000)
1179#define TX_PWR_CFG_2_MCS8_CH1 FIELD32(0x00f00000)
1180#define TX_PWR_CFG_2_MCS10_CH0 FIELD32(0x0f000000)
1181#define TX_PWR_CFG_2_MCS10_CH1 FIELD32(0xf0000000)
1182
1183#define TX_PWR_CFG_2B_MCS4_MCS5 FIELD32(0x000000ff)
1184#define TX_PWR_CFG_2B_MCS6_MCS7 FIELD32(0x0000ff00)
1185#define TX_PWR_CFG_2B_MCS8_MCS9 FIELD32(0x00ff0000)
1186#define TX_PWR_CFG_2B_MCS10_MCS11 FIELD32(0xff000000)
1187
1188
1189
1190
1191#define TX_PWR_CFG_3 0x1320
1192#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
1193#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
1194#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
1195#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
1196#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
1197#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
1198#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
1199#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
1200
1201#define TX_PWR_CFG_3_MCS12_CH0 FIELD32(0x0000000f)
1202#define TX_PWR_CFG_3_MCS12_CH1 FIELD32(0x000000f0)
1203#define TX_PWR_CFG_3_MCS14_CH0 FIELD32(0x00000f00)
1204#define TX_PWR_CFG_3_MCS14_CH1 FIELD32(0x0000f000)
1205#define TX_PWR_CFG_3_STBC0_CH0 FIELD32(0x000f0000)
1206#define TX_PWR_CFG_3_STBC0_CH1 FIELD32(0x00f00000)
1207#define TX_PWR_CFG_3_STBC2_CH0 FIELD32(0x0f000000)
1208#define TX_PWR_CFG_3_STBC2_CH1 FIELD32(0xf0000000)
1209
1210#define TX_PWR_CFG_3B_MCS12_MCS13 FIELD32(0x000000ff)
1211#define TX_PWR_CFG_3B_MCS14 FIELD32(0x0000ff00)
1212#define TX_PWR_CFG_3B_STBC_MCS0_MCS1 FIELD32(0x00ff0000)
1213#define TX_PWR_CFG_3B_STBC_MCS2_MSC3 FIELD32(0xff000000)
1214
1215
1216
1217
1218#define TX_PWR_CFG_4 0x1324
1219#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
1220#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
1221#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
1222#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
1223
1224#define TX_PWR_CFG_4_STBC4_CH0 FIELD32(0x0000000f)
1225#define TX_PWR_CFG_4_STBC4_CH1 FIELD32(0x000000f0)
1226#define TX_PWR_CFG_4_STBC6_CH0 FIELD32(0x00000f00)
1227#define TX_PWR_CFG_4_STBC6_CH1 FIELD32(0x0000f000)
1228
1229#define TX_PWR_CFG_4B_STBC_MCS4_MCS5 FIELD32(0x000000ff)
1230#define TX_PWR_CFG_4B_STBC_MCS6 FIELD32(0x0000ff00)
1231
1232
1233
1234
1235#define TX_PIN_CFG 0x1328
1236#define TX_PIN_CFG_PA_PE_DISABLE 0xfcfffff0
1237#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
1238#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
1239#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
1240#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
1241#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
1242#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
1243#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
1244#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
1245#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
1246#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
1247#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
1248#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
1249#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
1250#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
1251#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
1252#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
1253#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
1254#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
1255#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
1256#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
1257#define TX_PIN_CFG_RFRX_EN FIELD32(0x00100000)
1258#define TX_PIN_CFG_RFRX_POL FIELD32(0x00200000)
1259#define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
1260#define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
1261#define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
1262#define TX_PIN_CFG_PA_PE_G2_POL FIELD32(0x08000000)
1263#define TX_PIN_CFG_LNA_PE_A2_EN FIELD32(0x10000000)
1264#define TX_PIN_CFG_LNA_PE_G2_EN FIELD32(0x20000000)
1265#define TX_PIN_CFG_LNA_PE_A2_POL FIELD32(0x40000000)
1266#define TX_PIN_CFG_LNA_PE_G2_POL FIELD32(0x80000000)
1267
1268
1269
1270
1271#define TX_BAND_CFG 0x132c
1272#define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
1273#define TX_BAND_CFG_A FIELD32(0x00000002)
1274#define TX_BAND_CFG_BG FIELD32(0x00000004)
1275
1276
1277
1278
1279#define TX_SW_CFG0 0x1330
1280
1281
1282
1283
1284#define TX_SW_CFG1 0x1334
1285
1286
1287
1288
1289#define TX_SW_CFG2 0x1338
1290
1291
1292
1293
1294#define TXOP_THRES_CFG 0x133c
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312#define TXOP_CTRL_CFG 0x1340
1313#define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
1314#define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
1315#define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1316#define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1317#define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
1318#define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
1319#define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
1320#define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
1321#define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
1322#define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
1323
1324
1325
1326
1327
1328
1329#define TX_RTS_CFG 0x1344
1330#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1331#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
1332#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342#define TX_TIMEOUT_CFG 0x1348
1343#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
1344#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
1345#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358#define TX_RTY_CFG 0x134c
1359#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
1360#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
1361#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
1362#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
1363#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
1364#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378#define TX_LINK_CFG 0x1350
1379#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1380#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
1381#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
1382#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
1383#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
1384#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
1385#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
1386#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
1387
1388
1389
1390
1391#define HT_FBK_CFG0 0x1354
1392#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
1393#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
1394#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
1395#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
1396#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
1397#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
1398#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
1399#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
1400
1401
1402
1403
1404#define HT_FBK_CFG1 0x1358
1405#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
1406#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
1407#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
1408#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
1409#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
1410#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
1411#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
1412#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
1413
1414
1415
1416
1417#define LG_FBK_CFG0 0x135c
1418#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
1419#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
1420#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
1421#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
1422#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
1423#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
1424#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
1425#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
1426
1427
1428
1429
1430#define LG_FBK_CFG1 0x1360
1431#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
1432#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
1433#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
1434#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451#define CCK_PROT_CFG 0x1364
1452#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1453#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1454#define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1455#define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1456#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1457#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1458#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1459#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1460#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1461#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1462#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1463
1464
1465
1466
1467#define OFDM_PROT_CFG 0x1368
1468#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1469#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1470#define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1471#define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1472#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1473#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1474#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1475#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1476#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1477#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1478#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1479
1480
1481
1482
1483#define MM20_PROT_CFG 0x136c
1484#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1485#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1486#define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1487#define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1488#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1489#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1490#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1491#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1492#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1493#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1494#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1495
1496
1497
1498
1499#define MM40_PROT_CFG 0x1370
1500#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1501#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1502#define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1503#define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1504#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1505#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1506#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1507#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1508#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1509#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1510#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1511
1512
1513
1514
1515#define GF20_PROT_CFG 0x1374
1516#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1517#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1518#define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1519#define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1520#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1521#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1522#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1523#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1524#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1525#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1526#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1527
1528
1529
1530
1531#define GF40_PROT_CFG 0x1378
1532#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1533#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1534#define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1535#define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1536#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1537#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1538#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1539#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1540#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1541#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1542#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1543
1544
1545
1546
1547#define EXP_CTS_TIME 0x137c
1548
1549
1550
1551
1552#define EXP_ACK_TIME 0x1380
1553
1554
1555#define TX_PWR_CFG_5 0x1384
1556#define TX_PWR_CFG_5_MCS16_CH0 FIELD32(0x0000000f)
1557#define TX_PWR_CFG_5_MCS16_CH1 FIELD32(0x000000f0)
1558#define TX_PWR_CFG_5_MCS16_CH2 FIELD32(0x00000f00)
1559#define TX_PWR_CFG_5_MCS18_CH0 FIELD32(0x000f0000)
1560#define TX_PWR_CFG_5_MCS18_CH1 FIELD32(0x00f00000)
1561#define TX_PWR_CFG_5_MCS18_CH2 FIELD32(0x0f000000)
1562
1563
1564#define TX_PWR_CFG_6 0x1388
1565#define TX_PWR_CFG_6_MCS20_CH0 FIELD32(0x0000000f)
1566#define TX_PWR_CFG_6_MCS20_CH1 FIELD32(0x000000f0)
1567#define TX_PWR_CFG_6_MCS20_CH2 FIELD32(0x00000f00)
1568#define TX_PWR_CFG_6_MCS22_CH0 FIELD32(0x000f0000)
1569#define TX_PWR_CFG_6_MCS22_CH1 FIELD32(0x00f00000)
1570#define TX_PWR_CFG_6_MCS22_CH2 FIELD32(0x0f000000)
1571
1572
1573#define TX_PWR_CFG_0_EXT 0x1390
1574#define TX_PWR_CFG_0_EXT_CCK1_CH2 FIELD32(0x0000000f)
1575#define TX_PWR_CFG_0_EXT_CCK5_CH2 FIELD32(0x00000f00)
1576#define TX_PWR_CFG_0_EXT_OFDM6_CH2 FIELD32(0x000f0000)
1577#define TX_PWR_CFG_0_EXT_OFDM12_CH2 FIELD32(0x0f000000)
1578
1579
1580#define TX_PWR_CFG_1_EXT 0x1394
1581#define TX_PWR_CFG_1_EXT_OFDM24_CH2 FIELD32(0x0000000f)
1582#define TX_PWR_CFG_1_EXT_OFDM48_CH2 FIELD32(0x00000f00)
1583#define TX_PWR_CFG_1_EXT_MCS0_CH2 FIELD32(0x000f0000)
1584#define TX_PWR_CFG_1_EXT_MCS2_CH2 FIELD32(0x0f000000)
1585
1586
1587#define TX_PWR_CFG_2_EXT 0x1398
1588#define TX_PWR_CFG_2_EXT_MCS4_CH2 FIELD32(0x0000000f)
1589#define TX_PWR_CFG_2_EXT_MCS6_CH2 FIELD32(0x00000f00)
1590#define TX_PWR_CFG_2_EXT_MCS8_CH2 FIELD32(0x000f0000)
1591#define TX_PWR_CFG_2_EXT_MCS10_CH2 FIELD32(0x0f000000)
1592
1593
1594#define TX_PWR_CFG_3_EXT 0x139c
1595#define TX_PWR_CFG_3_EXT_MCS12_CH2 FIELD32(0x0000000f)
1596#define TX_PWR_CFG_3_EXT_MCS14_CH2 FIELD32(0x00000f00)
1597#define TX_PWR_CFG_3_EXT_STBC0_CH2 FIELD32(0x000f0000)
1598#define TX_PWR_CFG_3_EXT_STBC2_CH2 FIELD32(0x0f000000)
1599
1600
1601#define TX_PWR_CFG_4_EXT 0x13a0
1602#define TX_PWR_CFG_4_EXT_STBC4_CH2 FIELD32(0x0000000f)
1603#define TX_PWR_CFG_4_EXT_STBC6_CH2 FIELD32(0x00000f00)
1604
1605
1606
1607
1608#define TX0_RF_GAIN_CORRECT 0x13a0
1609#define TX0_RF_GAIN_CORRECT_GAIN_CORR_0 FIELD32(0x0000003f)
1610#define TX0_RF_GAIN_CORRECT_GAIN_CORR_1 FIELD32(0x00003f00)
1611#define TX0_RF_GAIN_CORRECT_GAIN_CORR_2 FIELD32(0x003f0000)
1612#define TX0_RF_GAIN_CORRECT_GAIN_CORR_3 FIELD32(0x3f000000)
1613
1614#define TX1_RF_GAIN_CORRECT 0x13a4
1615#define TX1_RF_GAIN_CORRECT_GAIN_CORR_0 FIELD32(0x0000003f)
1616#define TX1_RF_GAIN_CORRECT_GAIN_CORR_1 FIELD32(0x00003f00)
1617#define TX1_RF_GAIN_CORRECT_GAIN_CORR_2 FIELD32(0x003f0000)
1618#define TX1_RF_GAIN_CORRECT_GAIN_CORR_3 FIELD32(0x3f000000)
1619
1620
1621
1622
1623
1624#define TX0_RF_GAIN_ATTEN 0x13a8
1625#define TX0_RF_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000007f)
1626#define TX0_RF_GAIN_ATTEN_LEVEL_1 FIELD32(0x00007f00)
1627#define TX0_RF_GAIN_ATTEN_LEVEL_2 FIELD32(0x007f0000)
1628#define TX0_RF_GAIN_ATTEN_LEVEL_3 FIELD32(0x7f000000)
1629#define TX1_RF_GAIN_ATTEN 0x13ac
1630#define TX1_RF_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000007f)
1631#define TX1_RF_GAIN_ATTEN_LEVEL_1 FIELD32(0x00007f00)
1632#define TX1_RF_GAIN_ATTEN_LEVEL_2 FIELD32(0x007f0000)
1633#define TX1_RF_GAIN_ATTEN_LEVEL_3 FIELD32(0x7f000000)
1634
1635
1636
1637
1638
1639
1640#define TX_ALC_CFG_0 0x13b0
1641#define TX_ALC_CFG_0_CH_INIT_0 FIELD32(0x0000003f)
1642#define TX_ALC_CFG_0_CH_INIT_1 FIELD32(0x00003f00)
1643#define TX_ALC_CFG_0_LIMIT_0 FIELD32(0x003f0000)
1644#define TX_ALC_CFG_0_LIMIT_1 FIELD32(0x3f000000)
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661#define TX_ALC_CFG_1 0x13b4
1662#define TX_ALC_CFG_1_TX_TEMP_COMP FIELD32(0x0000003f)
1663#define TX_ALC_CFG_1_TX0_GAIN_FINE FIELD32(0x00000f00)
1664#define TX_ALC_CFG_1_TX1_GAIN_FINE FIELD32(0x0000f000)
1665#define TX_ALC_CFG_1_RF_TOS_DLY FIELD32(0x00070000)
1666#define TX_ALC_CFG_1_TX0_RF_GAIN_ATTEN FIELD32(0x00300000)
1667#define TX_ALC_CFG_1_TX1_RF_GAIN_ATTEN FIELD32(0x00c00000)
1668#define TX_ALC_CFG_1_RF_TOS_TIMEOUT FIELD32(0x3f000000)
1669#define TX_ALC_CFG_1_RF_TOS_ENABLE FIELD32(0x40000000)
1670#define TX_ALC_CFG_1_ROS_BUSY_EN FIELD32(0x80000000)
1671
1672
1673
1674
1675
1676#define TX0_BB_GAIN_ATTEN 0x13c0
1677#define TX0_BB_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000001f)
1678#define TX0_BB_GAIN_ATTEN_LEVEL_1 FIELD32(0x00001f00)
1679#define TX0_BB_GAIN_ATTEN_LEVEL_2 FIELD32(0x001f0000)
1680#define TX0_BB_GAIN_ATTEN_LEVEL_3 FIELD32(0x1f000000)
1681#define TX1_BB_GAIN_ATTEN 0x13c4
1682#define TX1_BB_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000001f)
1683#define TX1_BB_GAIN_ATTEN_LEVEL_1 FIELD32(0x00001f00)
1684#define TX1_BB_GAIN_ATTEN_LEVEL_2 FIELD32(0x001f0000)
1685#define TX1_BB_GAIN_ATTEN_LEVEL_3 FIELD32(0x1f000000)
1686
1687
1688#define TX_ALC_VGA3 0x13c8
1689#define TX_ALC_VGA3_TX0_ALC_VGA3 FIELD32(0x0000001f)
1690#define TX_ALC_VGA3_TX1_ALC_VGA3 FIELD32(0x00001f00)
1691#define TX_ALC_VGA3_TX0_ALC_VGA2 FIELD32(0x001f0000)
1692#define TX_ALC_VGA3_TX1_ALC_VGA2 FIELD32(0x1f000000)
1693
1694
1695#define TX_PWR_CFG_7 0x13d4
1696#define TX_PWR_CFG_7_OFDM54_CH0 FIELD32(0x0000000f)
1697#define TX_PWR_CFG_7_OFDM54_CH1 FIELD32(0x000000f0)
1698#define TX_PWR_CFG_7_OFDM54_CH2 FIELD32(0x00000f00)
1699#define TX_PWR_CFG_7_MCS7_CH0 FIELD32(0x000f0000)
1700#define TX_PWR_CFG_7_MCS7_CH1 FIELD32(0x00f00000)
1701#define TX_PWR_CFG_7_MCS7_CH2 FIELD32(0x0f000000)
1702
1703#define TX_PWR_CFG_7B_54MBS FIELD32(0x000000ff)
1704#define TX_PWR_CFG_7B_MCS7 FIELD32(0x00ff0000)
1705
1706
1707
1708#define TX_PWR_CFG_8 0x13d8
1709#define TX_PWR_CFG_8_MCS15_CH0 FIELD32(0x0000000f)
1710#define TX_PWR_CFG_8_MCS15_CH1 FIELD32(0x000000f0)
1711#define TX_PWR_CFG_8_MCS15_CH2 FIELD32(0x00000f00)
1712#define TX_PWR_CFG_8_MCS23_CH0 FIELD32(0x000f0000)
1713#define TX_PWR_CFG_8_MCS23_CH1 FIELD32(0x00f00000)
1714#define TX_PWR_CFG_8_MCS23_CH2 FIELD32(0x0f000000)
1715
1716#define TX_PWR_CFG_8B_MCS15 FIELD32(0x000000ff)
1717
1718
1719
1720#define TX_PWR_CFG_9 0x13dc
1721#define TX_PWR_CFG_9_STBC7_CH0 FIELD32(0x0000000f)
1722#define TX_PWR_CFG_9_STBC7_CH1 FIELD32(0x000000f0)
1723#define TX_PWR_CFG_9_STBC7_CH2 FIELD32(0x00000f00)
1724
1725#define TX_PWR_CFG_9B_STBC_MCS7 FIELD32(0x000000ff)
1726
1727
1728
1729
1730#define RX_FILTER_CFG 0x1400
1731#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1732#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1733#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1734#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1735#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1736#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1737#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1738#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1739#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1740#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1741#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1742#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1743#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1744#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1745#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1746#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1747#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759#define AUTO_RSP_CFG 0x1404
1760#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1761#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1762#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1763#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1764#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1765#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1766#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1767
1768
1769
1770
1771#define LEGACY_BASIC_RATE 0x1408
1772
1773
1774
1775
1776#define HT_BASIC_RATE 0x140c
1777
1778
1779
1780
1781#define HT_CTRL_CFG 0x1410
1782
1783
1784
1785
1786#define SIFS_COST_CFG 0x1414
1787
1788
1789
1790
1791
1792#define RX_PARSER_CFG 0x1418
1793
1794
1795
1796
1797#define TX_SEC_CNT0 0x1500
1798
1799
1800
1801
1802#define RX_SEC_CNT0 0x1504
1803
1804
1805
1806
1807#define CCMP_FC_MUTE 0x1508
1808
1809
1810
1811
1812#define TXOP_HLDR_ADDR0 0x1600
1813
1814
1815
1816
1817#define TXOP_HLDR_ADDR1 0x1604
1818
1819
1820
1821
1822#define TXOP_HLDR_ET 0x1608
1823
1824
1825
1826
1827#define QOS_CFPOLL_RA_DW0 0x160c
1828
1829
1830
1831
1832#define QOS_CFPOLL_RA_DW1 0x1610
1833
1834
1835
1836
1837#define QOS_CFPOLL_QC 0x1614
1838
1839
1840
1841
1842#define RX_STA_CNT0 0x1700
1843#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1844#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1845
1846
1847
1848
1849#define RX_STA_CNT1 0x1704
1850#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1851#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1852
1853
1854
1855
1856#define RX_STA_CNT2 0x1708
1857#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1858#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1859
1860
1861
1862
1863#define TX_STA_CNT0 0x170c
1864#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1865#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1866
1867
1868
1869
1870#define TX_STA_CNT1 0x1710
1871#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1872#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1873
1874
1875
1876
1877#define TX_STA_CNT2 0x1714
1878#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1879#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905#define TX_STA_FIFO 0x1718
1906#define TX_STA_FIFO_VALID FIELD32(0x00000001)
1907#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1908#define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
1909#define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
1910#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1911#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1912#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1913#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1914#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1915#define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1916#define TX_STA_FIFO_BW FIELD32(0x00800000)
1917#define TX_STA_FIFO_SGI FIELD32(0x01000000)
1918#define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1919
1920
1921
1922
1923#define TX_AGG_CNT 0x171c
1924#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1925#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1926
1927
1928
1929
1930#define TX_AGG_CNT0 0x1720
1931#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1932#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1933
1934
1935
1936
1937#define TX_AGG_CNT1 0x1724
1938#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1939#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1940
1941
1942
1943
1944#define TX_AGG_CNT2 0x1728
1945#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1946#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1947
1948
1949
1950
1951#define TX_AGG_CNT3 0x172c
1952#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1953#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1954
1955
1956
1957
1958#define TX_AGG_CNT4 0x1730
1959#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1960#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1961
1962
1963
1964
1965#define TX_AGG_CNT5 0x1734
1966#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1967#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1968
1969
1970
1971
1972#define TX_AGG_CNT6 0x1738
1973#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1974#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1975
1976
1977
1978
1979#define TX_AGG_CNT7 0x173c
1980#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1981#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1982
1983
1984
1985
1986
1987
1988#define MPDU_DENSITY_CNT 0x1740
1989#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1990#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019#define MAC_WCID_BASE 0x1800
2020#define PAIRWISE_KEY_TABLE_BASE 0x4000
2021#define MAC_IVEIV_TABLE_BASE 0x6000
2022#define MAC_WCID_ATTRIBUTE_BASE 0x6800
2023#define SHARED_KEY_TABLE_BASE 0x6c00
2024#define SHARED_KEY_MODE_BASE 0x7000
2025
2026#define MAC_WCID_ENTRY(__idx) \
2027 (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
2028#define PAIRWISE_KEY_ENTRY(__idx) \
2029 (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
2030#define MAC_IVEIV_ENTRY(__idx) \
2031 (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
2032#define MAC_WCID_ATTR_ENTRY(__idx) \
2033 (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
2034#define SHARED_KEY_ENTRY(__idx) \
2035 (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
2036#define SHARED_KEY_MODE_ENTRY(__idx) \
2037 (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
2038
2039struct mac_wcid_entry {
2040 u8 mac[6];
2041 u8 reserved[2];
2042} __packed;
2043
2044struct hw_key_entry {
2045 u8 key[16];
2046 u8 tx_mic[8];
2047 u8 rx_mic[8];
2048} __packed;
2049
2050struct mac_iveiv_entry {
2051 u8 iv[8];
2052} __packed;
2053
2054
2055
2056
2057#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
2058#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
2059#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
2060#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
2061#define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
2062#define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
2063#define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
2064#define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
2065
2066
2067
2068
2069#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
2070#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
2071#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
2072#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
2073#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
2074#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
2075#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
2076#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086#define H2M_MAILBOX_CSR 0x7010
2087#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
2088#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
2089#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
2090#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
2091
2092
2093
2094
2095
2096
2097#define H2M_MAILBOX_CID 0x7014
2098#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
2099#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
2100#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
2101#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
2102
2103
2104
2105
2106
2107#define H2M_MAILBOX_STATUS 0x701c
2108
2109
2110
2111
2112#define H2M_INT_SRC 0x7024
2113
2114
2115
2116
2117#define H2M_BBP_AGENT 0x7028
2118
2119
2120
2121
2122#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
2123#define MCU_LEDCS_POLARITY FIELD8(0x01)
2124
2125
2126
2127
2128
2129
2130#define HW_CS_CTS_BASE 0x7700
2131
2132
2133
2134
2135
2136#define HW_DFS_CTS_BASE 0x7780
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146#define TXRX_CSR1 0x77d0
2147
2148
2149
2150
2151
2152
2153#define HW_DEBUG_SETTING_BASE 0x77f0
2154#define HW_DEBUG_SETTING_BASE2 0x7770
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171#define HW_BEACON_BASE0 0x7800
2172#define HW_BEACON_BASE1 0x7a00
2173#define HW_BEACON_BASE2 0x7c00
2174#define HW_BEACON_BASE3 0x7e00
2175#define HW_BEACON_BASE4 0x7200
2176#define HW_BEACON_BASE5 0x7400
2177#define HW_BEACON_BASE6 0x5dc0
2178#define HW_BEACON_BASE7 0x5bc0
2179
2180#define HW_BEACON_BASE(__index) \
2181 (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
2182 (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
2183 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
2184
2185#define BEACON_BASE_TO_OFFSET(_base) (((_base) - 0x4000) / 64)
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200#define BBP1_TX_POWER_CTRL FIELD8(0x03)
2201#define BBP1_TX_ANTENNA FIELD8(0x18)
2202
2203
2204
2205
2206#define BBP3_RX_ADC FIELD8(0x03)
2207#define BBP3_RX_ANTENNA FIELD8(0x18)
2208#define BBP3_HT40_MINUS FIELD8(0x20)
2209#define BBP3_ADC_MODE_SWITCH FIELD8(0x40)
2210#define BBP3_ADC_INIT_MODE FIELD8(0x80)
2211
2212
2213
2214
2215#define BBP4_TX_BF FIELD8(0x01)
2216#define BBP4_BANDWIDTH FIELD8(0x18)
2217#define BBP4_MAC_IF_CTRL FIELD8(0x40)
2218
2219
2220#define BBP27_RX_CHAIN_SEL FIELD8(0x60)
2221
2222
2223
2224
2225#define BBP47_TSSI_REPORT_SEL FIELD8(0x03)
2226#define BBP47_TSSI_UPDATE_REQ FIELD8(0x04)
2227#define BBP47_TSSI_TSSI_MODE FIELD8(0x18)
2228#define BBP47_TSSI_ADC6 FIELD8(0x80)
2229
2230
2231
2232
2233#define BBP49_UPDATE_FLAG FIELD8(0x01)
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244#define BBP105_DETECT_SIG_ON_PRIMARY FIELD8(0x01)
2245#define BBP105_FEQ FIELD8(0x02)
2246#define BBP105_MLD FIELD8(0x04)
2247#define BBP105_SIG_REMODULATION FIELD8(0x08)
2248
2249
2250
2251
2252#define BBP109_TX0_POWER FIELD8(0x0f)
2253#define BBP109_TX1_POWER FIELD8(0xf0)
2254
2255
2256#define BBP110_TX2_POWER FIELD8(0x0f)
2257
2258
2259
2260
2261
2262#define BBP138_RX_ADC1 FIELD8(0x02)
2263#define BBP138_RX_ADC2 FIELD8(0x04)
2264#define BBP138_TX_DAC1 FIELD8(0x20)
2265#define BBP138_TX_DAC2 FIELD8(0x40)
2266
2267
2268
2269
2270#define BBP152_RX_DEFAULT_ANT FIELD8(0x80)
2271
2272
2273
2274
2275#define BBP254_BIT7 FIELD8(0x80)
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285#define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
2286#define RFCSR1_PLL_PD FIELD8(0x02)
2287#define RFCSR1_RX0_PD FIELD8(0x04)
2288#define RFCSR1_TX0_PD FIELD8(0x08)
2289#define RFCSR1_RX1_PD FIELD8(0x10)
2290#define RFCSR1_TX1_PD FIELD8(0x20)
2291#define RFCSR1_RX2_PD FIELD8(0x40)
2292#define RFCSR1_TX2_PD FIELD8(0x80)
2293#define RFCSR1_TX2_EN_MT7620 FIELD8(0x02)
2294
2295
2296
2297
2298#define RFCSR2_RESCAL_EN FIELD8(0x80)
2299#define RFCSR2_RX2_EN_MT7620 FIELD8(0x02)
2300#define RFCSR2_TX2_EN_MT7620 FIELD8(0x20)
2301
2302
2303
2304
2305#define RFCSR3_K FIELD8(0x0f)
2306
2307#define RFCSR3_PA1_BIAS_CCK FIELD8(0x70)
2308#define RFCSR3_PA2_CASCODE_BIAS_CCKK FIELD8(0x80)
2309
2310#define RFCSR3_VCOCAL_EN FIELD8(0x80)
2311
2312#define RFCSR3_BIT1 FIELD8(0x02)
2313#define RFCSR3_BIT2 FIELD8(0x04)
2314#define RFCSR3_BIT3 FIELD8(0x08)
2315#define RFCSR3_BIT4 FIELD8(0x10)
2316#define RFCSR3_BIT5 FIELD8(0x20)
2317
2318
2319
2320
2321
2322#define RFCSR4_VCOCAL_EN FIELD8(0x80)
2323
2324
2325
2326
2327#define RFCSR5_R1 FIELD8(0x0c)
2328
2329
2330
2331
2332#define RFCSR6_R1 FIELD8(0x03)
2333#define RFCSR6_R2 FIELD8(0x40)
2334#define RFCSR6_TXDIV FIELD8(0x0c)
2335
2336#define RFCSR6_VCO_IC FIELD8(0xc0)
2337
2338
2339
2340
2341#define RFCSR7_RF_TUNING FIELD8(0x01)
2342#define RFCSR7_BIT1 FIELD8(0x02)
2343#define RFCSR7_BIT2 FIELD8(0x04)
2344#define RFCSR7_BIT3 FIELD8(0x08)
2345#define RFCSR7_BIT4 FIELD8(0x10)
2346#define RFCSR7_BIT5 FIELD8(0x20)
2347#define RFCSR7_BITS67 FIELD8(0xc0)
2348
2349
2350
2351
2352#define RFCSR9_K FIELD8(0x0f)
2353#define RFCSR9_N FIELD8(0x10)
2354#define RFCSR9_UNKNOWN FIELD8(0x60)
2355#define RFCSR9_MOD FIELD8(0x80)
2356
2357
2358
2359
2360#define RFCSR11_R FIELD8(0x03)
2361#define RFCSR11_PLL_MOD FIELD8(0x0c)
2362#define RFCSR11_MOD FIELD8(0xc0)
2363
2364
2365#define RFCSR11_PLL_IDOH FIELD8(0x40)
2366
2367
2368
2369
2370
2371#define RFCSR12_TX_POWER FIELD8(0x1f)
2372#define RFCSR12_DR0 FIELD8(0xe0)
2373
2374
2375
2376
2377#define RFCSR13_TX_POWER FIELD8(0x1f)
2378#define RFCSR13_DR0 FIELD8(0xe0)
2379#define RFCSR13_RDIV_MT7620 FIELD8(0x03)
2380
2381
2382
2383
2384#define RFCSR15_TX_LO2_EN FIELD8(0x08)
2385
2386
2387
2388
2389#define RFCSR16_TXMIXER_GAIN FIELD8(0x07)
2390#define RFCSR16_RF_PLL_FREQ_SEL_MT7620 FIELD8(0x0F)
2391#define RFCSR16_SDM_MODE_MT7620 FIELD8(0xE0)
2392
2393
2394
2395
2396#define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
2397#define RFCSR17_TX_LO1_EN FIELD8(0x08)
2398#define RFCSR17_R FIELD8(0x20)
2399#define RFCSR17_CODE FIELD8(0x7f)
2400
2401
2402#define RFCSR18_XO_TUNE_BYPASS FIELD8(0x40)
2403
2404
2405#define RFCSR19_K FIELD8(0x03)
2406
2407
2408
2409
2410#define RFCSR20_RX_LO1_EN FIELD8(0x08)
2411
2412
2413
2414
2415#define RFCSR21_RX_LO2_EN FIELD8(0x08)
2416#define RFCSR21_BIT1 FIELD8(0x01)
2417#define RFCSR21_BIT8 FIELD8(0x80)
2418
2419
2420
2421
2422#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
2423#define RFCSR22_FREQPLAN_D_MT7620 FIELD8(0x07)
2424
2425
2426
2427
2428#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
2429
2430
2431
2432
2433#define RFCSR24_TX_AGC_FC FIELD8(0x1f)
2434#define RFCSR24_TX_H20M FIELD8(0x20)
2435#define RFCSR24_TX_CALIB FIELD8(0x7f)
2436
2437
2438
2439
2440#define RFCSR27_R1 FIELD8(0x03)
2441#define RFCSR27_R2 FIELD8(0x04)
2442#define RFCSR27_R3 FIELD8(0x30)
2443#define RFCSR27_R4 FIELD8(0x40)
2444
2445
2446
2447
2448#define RFCSR28_CH11_HT40 FIELD8(0x04)
2449
2450
2451
2452
2453#define RFCSR29_ADC6_TEST FIELD8(0x01)
2454#define RFCSR29_ADC6_INT_TEST FIELD8(0x02)
2455#define RFCSR29_RSSI_RESET FIELD8(0x04)
2456#define RFCSR29_RSSI_ON FIELD8(0x08)
2457#define RFCSR29_RSSI_RIP_CTRL FIELD8(0x30)
2458#define RFCSR29_RSSI_GAIN FIELD8(0xc0)
2459
2460
2461
2462
2463#define RFCSR30_TX_H20M FIELD8(0x02)
2464#define RFCSR30_RX_H20M FIELD8(0x04)
2465#define RFCSR30_RX_VCM FIELD8(0x18)
2466#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
2467#define RF3322_RFCSR30_TX_H20M FIELD8(0x01)
2468#define RF3322_RFCSR30_RX_H20M FIELD8(0x02)
2469
2470
2471
2472
2473#define RFCSR31_RX_AGC_FC FIELD8(0x1f)
2474#define RFCSR31_RX_H20M FIELD8(0x20)
2475#define RFCSR31_RX_CALIB FIELD8(0x7f)
2476
2477
2478#define RFCSR32_TX_AGC_FC FIELD8(0xf8)
2479
2480
2481#define RFCSR36_RF_BS FIELD8(0x80)
2482
2483
2484
2485
2486#define RFCSR34_TX0_EXT_PA FIELD8(0x04)
2487#define RFCSR34_TX1_EXT_PA FIELD8(0x08)
2488
2489
2490
2491
2492#define RFCSR38_RX_LO1_EN FIELD8(0x20)
2493
2494
2495
2496
2497#define RFCSR39_RX_DIV FIELD8(0x40)
2498#define RFCSR39_RX_LO2_EN FIELD8(0x80)
2499
2500
2501
2502
2503#define RFCSR41_BIT1 FIELD8(0x01)
2504#define RFCSR41_BIT4 FIELD8(0x08)
2505
2506
2507
2508
2509#define RFCSR42_BIT1 FIELD8(0x01)
2510#define RFCSR42_BIT4 FIELD8(0x08)
2511#define RFCSR42_TX2_EN_MT7620 FIELD8(0x40)
2512
2513
2514
2515
2516#define RFCSR49_TX FIELD8(0x3f)
2517#define RFCSR49_EP FIELD8(0xc0)
2518
2519#define RFCSR49_TX_LO1_IC FIELD8(0x1c)
2520#define RFCSR49_TX_DIV FIELD8(0x20)
2521
2522
2523
2524
2525#define RFCSR50_TX FIELD8(0x3f)
2526#define RFCSR50_TX0_EXT_PA FIELD8(0x02)
2527#define RFCSR50_TX1_EXT_PA FIELD8(0x10)
2528#define RFCSR50_EP FIELD8(0xc0)
2529
2530#define RFCSR50_TX_LO1_EN FIELD8(0x20)
2531#define RFCSR50_TX_LO2_EN FIELD8(0x10)
2532
2533
2534
2535#define RFCSR51_BITS01 FIELD8(0x03)
2536#define RFCSR51_BITS24 FIELD8(0x1c)
2537#define RFCSR51_BITS57 FIELD8(0xe0)
2538
2539#define RFCSR53_TX_POWER FIELD8(0x3f)
2540#define RFCSR53_UNKNOWN FIELD8(0xc0)
2541
2542#define RFCSR54_TX_POWER FIELD8(0x3f)
2543#define RFCSR54_UNKNOWN FIELD8(0xc0)
2544
2545#define RFCSR55_TX_POWER FIELD8(0x3f)
2546#define RFCSR55_UNKNOWN FIELD8(0xc0)
2547
2548#define RFCSR57_DRV_CC FIELD8(0xfc)
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
2559#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
2560#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
2561
2562
2563
2564
2565#define RF3_TXPOWER_G FIELD32(0x00003e00)
2566#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
2567#define RF3_TXPOWER_A FIELD32(0x00003c00)
2568
2569
2570
2571
2572#define RF4_TXPOWER_G FIELD32(0x000007c0)
2573#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
2574#define RF4_TXPOWER_A FIELD32(0x00000780)
2575#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
2576#define RF4_HT40 FIELD32(0x00200000)
2577
2578
2579
2580
2581
2582
2583enum rt2800_eeprom_word {
2584 EEPROM_CHIP_ID = 0,
2585 EEPROM_VERSION,
2586 EEPROM_MAC_ADDR_0,
2587 EEPROM_MAC_ADDR_1,
2588 EEPROM_MAC_ADDR_2,
2589 EEPROM_NIC_CONF0,
2590 EEPROM_NIC_CONF1,
2591 EEPROM_FREQ,
2592 EEPROM_LED_AG_CONF,
2593 EEPROM_LED_ACT_CONF,
2594 EEPROM_LED_POLARITY,
2595 EEPROM_NIC_CONF2,
2596 EEPROM_LNA,
2597 EEPROM_RSSI_BG,
2598 EEPROM_RSSI_BG2,
2599 EEPROM_TXMIXER_GAIN_BG,
2600 EEPROM_RSSI_A,
2601 EEPROM_RSSI_A2,
2602 EEPROM_TXMIXER_GAIN_A,
2603 EEPROM_EIRP_MAX_TX_POWER,
2604 EEPROM_TXPOWER_DELTA,
2605 EEPROM_TXPOWER_BG1,
2606 EEPROM_TXPOWER_BG2,
2607 EEPROM_TSSI_BOUND_BG1,
2608 EEPROM_TSSI_BOUND_BG2,
2609 EEPROM_TSSI_BOUND_BG3,
2610 EEPROM_TSSI_BOUND_BG4,
2611 EEPROM_TSSI_BOUND_BG5,
2612 EEPROM_TXPOWER_A1,
2613 EEPROM_TXPOWER_A2,
2614 EEPROM_TXPOWER_INIT,
2615 EEPROM_TSSI_BOUND_A1,
2616 EEPROM_TSSI_BOUND_A2,
2617 EEPROM_TSSI_BOUND_A3,
2618 EEPROM_TSSI_BOUND_A4,
2619 EEPROM_TSSI_BOUND_A5,
2620 EEPROM_TXPOWER_BYRATE,
2621 EEPROM_BBP_START,
2622
2623
2624 EEPROM_EXT_LNA2,
2625 EEPROM_EXT_TXPOWER_BG3,
2626 EEPROM_EXT_TXPOWER_A3,
2627
2628
2629 EEPROM_WORD_COUNT
2630};
2631
2632
2633
2634
2635#define EEPROM_VERSION_FAE FIELD16(0x00ff)
2636#define EEPROM_VERSION_VERSION FIELD16(0xff00)
2637
2638
2639
2640
2641#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
2642#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
2643#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
2644#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
2645#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
2646#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
2647
2648
2649
2650
2651
2652
2653
2654#define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f)
2655#define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0)
2656#define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00)
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679#define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001)
2680#define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002)
2681#define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004)
2682#define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008)
2683#define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010)
2684#define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020)
2685#define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040)
2686#define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080)
2687#define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100)
2688#define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200)
2689#define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400)
2690#define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800)
2691#define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000)
2692#define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000)
2693#define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000)
2694#define EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352 FIELD16(0x4000)
2695#define EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352 FIELD16(0x8000)
2696
2697
2698
2699
2700#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
2701#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
2702#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
2717#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
2718#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
2719#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
2720#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
2721#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
2722#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
2723#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
2724#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
2725
2726
2727
2728
2729
2730
2731
2732#define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f)
2733#define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0)
2734#define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600)
2735
2736
2737
2738
2739#define EEPROM_LNA_BG FIELD16(0x00ff)
2740#define EEPROM_LNA_A0 FIELD16(0xff00)
2741
2742
2743
2744
2745#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
2746#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
2747
2748
2749
2750
2751#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
2752#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
2753
2754
2755
2756
2757#define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
2758
2759
2760
2761
2762#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
2763#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
2764
2765
2766
2767
2768#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
2769#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
2770
2771
2772
2773
2774#define EEPROM_TXMIXER_GAIN_A_VAL FIELD16(0x0007)
2775
2776
2777
2778
2779#define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff)
2780#define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00)
2781
2782
2783
2784
2785
2786
2787
2788
2789#define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f)
2790#define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040)
2791#define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080)
2792#define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00)
2793#define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000)
2794#define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000)
2795
2796
2797
2798
2799#define EEPROM_TXPOWER_BG_SIZE 7
2800#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
2801#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
2802
2803
2804
2805
2806
2807
2808
2809
2810#define EEPROM_TSSI_BOUND_BG1_MINUS4 FIELD16(0x00ff)
2811#define EEPROM_TSSI_BOUND_BG1_MINUS3 FIELD16(0xff00)
2812
2813
2814
2815
2816
2817
2818
2819
2820#define EEPROM_TSSI_BOUND_BG2_MINUS2 FIELD16(0x00ff)
2821#define EEPROM_TSSI_BOUND_BG2_MINUS1 FIELD16(0xff00)
2822
2823
2824
2825
2826
2827
2828
2829#define EEPROM_TSSI_BOUND_BG3_REF FIELD16(0x00ff)
2830#define EEPROM_TSSI_BOUND_BG3_PLUS1 FIELD16(0xff00)
2831
2832
2833
2834
2835
2836
2837
2838
2839#define EEPROM_TSSI_BOUND_BG4_PLUS2 FIELD16(0x00ff)
2840#define EEPROM_TSSI_BOUND_BG4_PLUS3 FIELD16(0xff00)
2841
2842
2843
2844
2845
2846
2847
2848#define EEPROM_TSSI_BOUND_BG5_PLUS4 FIELD16(0x00ff)
2849#define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00)
2850
2851
2852
2853
2854#define EEPROM_TXPOWER_A_SIZE 6
2855#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
2856#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
2857
2858
2859#define EEPROM_TXPOWER_ALC FIELD8(0x1f)
2860#define EEPROM_TXPOWER_FINE_CTRL FIELD8(0xe0)
2861
2862
2863
2864
2865
2866
2867
2868
2869#define EEPROM_TSSI_BOUND_A1_MINUS4 FIELD16(0x00ff)
2870#define EEPROM_TSSI_BOUND_A1_MINUS3 FIELD16(0xff00)
2871
2872
2873
2874
2875
2876
2877
2878
2879#define EEPROM_TSSI_BOUND_A2_MINUS2 FIELD16(0x00ff)
2880#define EEPROM_TSSI_BOUND_A2_MINUS1 FIELD16(0xff00)
2881
2882
2883
2884
2885
2886
2887
2888#define EEPROM_TSSI_BOUND_A3_REF FIELD16(0x00ff)
2889#define EEPROM_TSSI_BOUND_A3_PLUS1 FIELD16(0xff00)
2890
2891
2892
2893
2894
2895
2896
2897
2898#define EEPROM_TSSI_BOUND_A4_PLUS2 FIELD16(0x00ff)
2899#define EEPROM_TSSI_BOUND_A4_PLUS3 FIELD16(0xff00)
2900
2901
2902
2903
2904
2905
2906
2907#define EEPROM_TSSI_BOUND_A5_PLUS4 FIELD16(0x00ff)
2908#define EEPROM_TSSI_BOUND_A5_AGC_STEP FIELD16(0xff00)
2909
2910
2911
2912
2913#define EEPROM_TXPOWER_BYRATE_SIZE 9
2914
2915#define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f)
2916#define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0)
2917#define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00)
2918#define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000)
2919
2920
2921
2922
2923#define EEPROM_BBP_SIZE 16
2924#define EEPROM_BBP_VALUE FIELD16(0x00ff)
2925#define EEPROM_BBP_REG_ID FIELD16(0xff00)
2926
2927
2928#define EEPROM_EXT_LNA2_A1 FIELD16(0x00ff)
2929#define EEPROM_EXT_LNA2_A2 FIELD16(0xff00)
2930
2931
2932
2933
2934
2935#define EEPROM_IQ_GAIN_CAL_TX0_2G 0x130
2936#define EEPROM_IQ_PHASE_CAL_TX0_2G 0x131
2937#define EEPROM_IQ_GROUPDELAY_CAL_TX0_2G 0x132
2938#define EEPROM_IQ_GAIN_CAL_TX1_2G 0x133
2939#define EEPROM_IQ_PHASE_CAL_TX1_2G 0x134
2940#define EEPROM_IQ_GROUPDELAY_CAL_TX1_2G 0x135
2941#define EEPROM_IQ_GAIN_CAL_RX0_2G 0x136
2942#define EEPROM_IQ_PHASE_CAL_RX0_2G 0x137
2943#define EEPROM_IQ_GROUPDELAY_CAL_RX0_2G 0x138
2944#define EEPROM_IQ_GAIN_CAL_RX1_2G 0x139
2945#define EEPROM_IQ_PHASE_CAL_RX1_2G 0x13A
2946#define EEPROM_IQ_GROUPDELAY_CAL_RX1_2G 0x13B
2947#define EEPROM_RF_IQ_COMPENSATION_CONTROL 0x13C
2948#define EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL 0x13D
2949#define EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G 0x144
2950#define EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G 0x145
2951#define EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G 0X146
2952#define EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G 0x147
2953#define EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G 0x148
2954#define EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G 0x149
2955#define EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G 0x14A
2956#define EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G 0x14B
2957#define EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G 0X14C
2958#define EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G 0x14D
2959#define EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G 0x14E
2960#define EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G 0x14F
2961#define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH36_TO_CH64_5G 0x150
2962#define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH36_TO_CH64_5G 0x151
2963#define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH100_TO_CH138_5G 0x152
2964#define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH100_TO_CH138_5G 0x153
2965#define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH140_TO_CH165_5G 0x154
2966#define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH140_TO_CH165_5G 0x155
2967#define EEPROM_IQ_GAIN_CAL_RX0_CH36_TO_CH64_5G 0x156
2968#define EEPROM_IQ_PHASE_CAL_RX0_CH36_TO_CH64_5G 0x157
2969#define EEPROM_IQ_GAIN_CAL_RX0_CH100_TO_CH138_5G 0X158
2970#define EEPROM_IQ_PHASE_CAL_RX0_CH100_TO_CH138_5G 0x159
2971#define EEPROM_IQ_GAIN_CAL_RX0_CH140_TO_CH165_5G 0x15A
2972#define EEPROM_IQ_PHASE_CAL_RX0_CH140_TO_CH165_5G 0x15B
2973#define EEPROM_IQ_GAIN_CAL_RX1_CH36_TO_CH64_5G 0x15C
2974#define EEPROM_IQ_PHASE_CAL_RX1_CH36_TO_CH64_5G 0x15D
2975#define EEPROM_IQ_GAIN_CAL_RX1_CH100_TO_CH138_5G 0X15E
2976#define EEPROM_IQ_PHASE_CAL_RX1_CH100_TO_CH138_5G 0x15F
2977#define EEPROM_IQ_GAIN_CAL_RX1_CH140_TO_CH165_5G 0x160
2978#define EEPROM_IQ_PHASE_CAL_RX1_CH140_TO_CH165_5G 0x161
2979#define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH36_TO_CH64_5G 0x162
2980#define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH36_TO_CH64_5G 0x163
2981#define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH100_TO_CH138_5G 0x164
2982#define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH100_TO_CH138_5G 0x165
2983#define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH140_TO_CH165_5G 0x166
2984#define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH140_TO_CH165_5G 0x167
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995#define MCU_SLEEP 0x30
2996#define MCU_WAKEUP 0x31
2997#define MCU_RADIO_OFF 0x35
2998#define MCU_CURRENT 0x36
2999#define MCU_LED 0x50
3000#define MCU_LED_STRENGTH 0x51
3001#define MCU_LED_AG_CONF 0x52
3002#define MCU_LED_ACT_CONF 0x53
3003#define MCU_LED_LED_POLARITY 0x54
3004#define MCU_RADAR 0x60
3005#define MCU_BOOT_SIGNAL 0x72
3006#define MCU_ANT_SELECT 0X73
3007#define MCU_FREQ_OFFSET 0x74
3008#define MCU_BBP_SIGNAL 0x80
3009#define MCU_POWER_SAVE 0x83
3010#define MCU_BAND_SELECT 0x91
3011
3012
3013
3014
3015#define TOKEN_SLEEP 1
3016#define TOKEN_RADIO_OFF 2
3017#define TOKEN_WAKEUP 3
3018
3019
3020
3021
3022
3023
3024#define TXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32))
3025#define TXWI_DESC_SIZE_5WORDS (5 * sizeof(__le32))
3026
3027#define RXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32))
3028#define RXWI_DESC_SIZE_5WORDS (5 * sizeof(__le32))
3029#define RXWI_DESC_SIZE_6WORDS (6 * sizeof(__le32))
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052#define TXWI_W0_FRAG FIELD32(0x00000001)
3053#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
3054#define TXWI_W0_CF_ACK FIELD32(0x00000004)
3055#define TXWI_W0_TS FIELD32(0x00000008)
3056#define TXWI_W0_AMPDU FIELD32(0x00000010)
3057#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
3058#define TXWI_W0_TX_OP FIELD32(0x00000300)
3059#define TXWI_W0_MCS FIELD32(0x007f0000)
3060#define TXWI_W0_BW FIELD32(0x00800000)
3061#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
3062#define TXWI_W0_STBC FIELD32(0x06000000)
3063#define TXWI_W0_IFS FIELD32(0x08000000)
3064#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082#define TXWI_W1_ACK FIELD32(0x00000001)
3083#define TXWI_W1_NSEQ FIELD32(0x00000002)
3084#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
3085#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
3086#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
3087#define TXWI_W1_PACKETID FIELD32(0xf0000000)
3088#define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
3089#define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
3090
3091
3092
3093
3094#define TXWI_W2_IV FIELD32(0xffffffff)
3095
3096
3097
3098
3099#define TXWI_W3_EIV FIELD32(0xffffffff)
3100
3101
3102
3103
3104
3105
3106
3107
3108#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
3109#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
3110#define RXWI_W0_BSSID FIELD32(0x00001c00)
3111#define RXWI_W0_UDF FIELD32(0x0000e000)
3112#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
3113#define RXWI_W0_TID FIELD32(0xf0000000)
3114
3115
3116
3117
3118#define RXWI_W1_FRAG FIELD32(0x0000000f)
3119#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
3120#define RXWI_W1_MCS FIELD32(0x007f0000)
3121#define RXWI_W1_BW FIELD32(0x00800000)
3122#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
3123#define RXWI_W1_STBC FIELD32(0x06000000)
3124#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
3125
3126
3127
3128
3129#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
3130#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
3131#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
3132
3133
3134
3135
3136#define RXWI_W3_SNR0 FIELD32(0x000000ff)
3137#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
3138
3139
3140
3141
3142
3143#define MIN_G_TXPOWER 0
3144#define MIN_A_TXPOWER -7
3145#define MAX_G_TXPOWER 31
3146#define MAX_A_TXPOWER 15
3147#define DEFAULT_TXPOWER 5
3148
3149#define MIN_A_TXPOWER_3593 0
3150#define MAX_A_TXPOWER_3593 31
3151
3152#define TXPOWER_G_FROM_DEV(__txpower) \
3153 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
3154
3155#define TXPOWER_A_FROM_DEV(__txpower) \
3156 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
3157
3158
3159
3160
3161#define EIRP_MAX_TX_POWER_LIMIT 0x50
3162
3163
3164
3165
3166
3167#define BCN_TBTT_OFFSET 64
3168
3169#endif
3170