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20#define DSS_SUBSYS_NAME "DSI"
21
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/device.h>
26#include <linux/err.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/mutex.h>
30#include <linux/module.h>
31#include <linux/semaphore.h>
32#include <linux/seq_file.h>
33#include <linux/platform_device.h>
34#include <linux/regulator/consumer.h>
35#include <linux/wait.h>
36#include <linux/workqueue.h>
37#include <linux/sched.h>
38#include <linux/slab.h>
39#include <linux/debugfs.h>
40#include <linux/pm_runtime.h>
41
42#include <video/omapdss.h>
43#include <video/mipi_display.h>
44
45#include "dss.h"
46#include "dss_features.h"
47
48#define DSI_CATCH_MISSING_TE
49
50struct dsi_reg { u16 idx; };
51
52#define DSI_REG(idx) ((const struct dsi_reg) { idx })
53
54#define DSI_SZ_REGS SZ_1K
55
56
57#define DSI_REVISION DSI_REG(0x0000)
58#define DSI_SYSCONFIG DSI_REG(0x0010)
59#define DSI_SYSSTATUS DSI_REG(0x0014)
60#define DSI_IRQSTATUS DSI_REG(0x0018)
61#define DSI_IRQENABLE DSI_REG(0x001C)
62#define DSI_CTRL DSI_REG(0x0040)
63#define DSI_GNQ DSI_REG(0x0044)
64#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
65#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
66#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
67#define DSI_CLK_CTRL DSI_REG(0x0054)
68#define DSI_TIMING1 DSI_REG(0x0058)
69#define DSI_TIMING2 DSI_REG(0x005C)
70#define DSI_VM_TIMING1 DSI_REG(0x0060)
71#define DSI_VM_TIMING2 DSI_REG(0x0064)
72#define DSI_VM_TIMING3 DSI_REG(0x0068)
73#define DSI_CLK_TIMING DSI_REG(0x006C)
74#define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
75#define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
76#define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
77#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
78#define DSI_VM_TIMING4 DSI_REG(0x0080)
79#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
80#define DSI_VM_TIMING5 DSI_REG(0x0088)
81#define DSI_VM_TIMING6 DSI_REG(0x008C)
82#define DSI_VM_TIMING7 DSI_REG(0x0090)
83#define DSI_STOPCLK_TIMING DSI_REG(0x0094)
84#define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
85#define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
86#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
87#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
88#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
89#define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
90#define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
91
92
93
94#define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
95#define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
96#define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
97#define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
98#define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
99
100
101
102#define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
103#define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
104#define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
105#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
106#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
107
108#define REG_GET(dsidev, idx, start, end) \
109 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
110
111#define REG_FLD_MOD(dsidev, idx, val, start, end) \
112 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
113
114
115#define DSI_IRQ_VC0 (1 << 0)
116#define DSI_IRQ_VC1 (1 << 1)
117#define DSI_IRQ_VC2 (1 << 2)
118#define DSI_IRQ_VC3 (1 << 3)
119#define DSI_IRQ_WAKEUP (1 << 4)
120#define DSI_IRQ_RESYNC (1 << 5)
121#define DSI_IRQ_PLL_LOCK (1 << 7)
122#define DSI_IRQ_PLL_UNLOCK (1 << 8)
123#define DSI_IRQ_PLL_RECALL (1 << 9)
124#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
125#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
126#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
127#define DSI_IRQ_TE_TRIGGER (1 << 16)
128#define DSI_IRQ_ACK_TRIGGER (1 << 17)
129#define DSI_IRQ_SYNC_LOST (1 << 18)
130#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
131#define DSI_IRQ_TA_TIMEOUT (1 << 20)
132#define DSI_IRQ_ERROR_MASK \
133 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
134 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
135#define DSI_IRQ_CHANNEL_MASK 0xf
136
137
138#define DSI_VC_IRQ_CS (1 << 0)
139#define DSI_VC_IRQ_ECC_CORR (1 << 1)
140#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
141#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
142#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
143#define DSI_VC_IRQ_BTA (1 << 5)
144#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
145#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
146#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
147#define DSI_VC_IRQ_ERROR_MASK \
148 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
149 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
150 DSI_VC_IRQ_FIFO_TX_UDF)
151
152
153#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
154#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
155#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
156#define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
157#define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
158#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
159#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
160#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
161#define DSI_CIO_IRQ_ERRESC4 (1 << 8)
162#define DSI_CIO_IRQ_ERRESC5 (1 << 9)
163#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
164#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
165#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
166#define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
167#define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
168#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
169#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
170#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
171#define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
172#define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
173#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
174#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
175#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
176#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
177#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
178#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
179#define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
180#define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
181#define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
182#define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
183#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
184#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
185#define DSI_CIO_IRQ_ERROR_MASK \
186 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
187 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
188 DSI_CIO_IRQ_ERRSYNCESC5 | \
189 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
190 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
191 DSI_CIO_IRQ_ERRESC5 | \
192 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
193 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
194 DSI_CIO_IRQ_ERRCONTROL5 | \
195 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
196 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
200
201typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
202
203static int dsi_display_init_dispc(struct platform_device *dsidev,
204 struct omap_overlay_manager *mgr);
205static void dsi_display_uninit_dispc(struct platform_device *dsidev,
206 struct omap_overlay_manager *mgr);
207
208#define DSI_MAX_NR_ISRS 2
209#define DSI_MAX_NR_LANES 5
210
211enum dsi_lane_function {
212 DSI_LANE_UNUSED = 0,
213 DSI_LANE_CLK,
214 DSI_LANE_DATA1,
215 DSI_LANE_DATA2,
216 DSI_LANE_DATA3,
217 DSI_LANE_DATA4,
218};
219
220struct dsi_lane_config {
221 enum dsi_lane_function function;
222 u8 polarity;
223};
224
225struct dsi_isr_data {
226 omap_dsi_isr_t isr;
227 void *arg;
228 u32 mask;
229};
230
231enum fifo_size {
232 DSI_FIFO_SIZE_0 = 0,
233 DSI_FIFO_SIZE_32 = 1,
234 DSI_FIFO_SIZE_64 = 2,
235 DSI_FIFO_SIZE_96 = 3,
236 DSI_FIFO_SIZE_128 = 4,
237};
238
239enum dsi_vc_source {
240 DSI_VC_SOURCE_L4 = 0,
241 DSI_VC_SOURCE_VP,
242};
243
244struct dsi_irq_stats {
245 unsigned long last_reset;
246 unsigned irq_count;
247 unsigned dsi_irqs[32];
248 unsigned vc_irqs[4][32];
249 unsigned cio_irqs[32];
250};
251
252struct dsi_isr_tables {
253 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
254 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
255 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
256};
257
258struct dsi_clk_calc_ctx {
259 struct platform_device *dsidev;
260
261
262
263 const struct omap_dss_dsi_config *config;
264
265 unsigned long req_pck_min, req_pck_nom, req_pck_max;
266
267
268
269 struct dsi_clock_info dsi_cinfo;
270 struct dispc_clock_info dispc_cinfo;
271
272 struct omap_video_timings dispc_vm;
273 struct omap_dss_dsi_videomode_timings dsi_vm;
274};
275
276struct dsi_data {
277 struct platform_device *pdev;
278 void __iomem *base;
279
280 int module_id;
281
282 int irq;
283
284 struct clk *dss_clk;
285 struct clk *sys_clk;
286
287 struct dispc_clock_info user_dispc_cinfo;
288 struct dsi_clock_info user_dsi_cinfo;
289
290 struct dsi_clock_info current_cinfo;
291
292 bool vdds_dsi_enabled;
293 struct regulator *vdds_dsi_reg;
294
295 struct {
296 enum dsi_vc_source source;
297 struct omap_dss_device *dssdev;
298 enum fifo_size fifo_size;
299 int vc_id;
300 } vc[4];
301
302 struct mutex lock;
303 struct semaphore bus_lock;
304
305 unsigned pll_locked;
306
307 spinlock_t irq_lock;
308 struct dsi_isr_tables isr_tables;
309
310 struct dsi_isr_tables isr_tables_copy;
311
312 int update_channel;
313#ifdef DEBUG
314 unsigned update_bytes;
315#endif
316
317 bool te_enabled;
318 bool ulps_enabled;
319
320 void (*framedone_callback)(int, void *);
321 void *framedone_data;
322
323 struct delayed_work framedone_timeout_work;
324
325#ifdef DSI_CATCH_MISSING_TE
326 struct timer_list te_timer;
327#endif
328
329 unsigned long cache_req_pck;
330 unsigned long cache_clk_freq;
331 struct dsi_clock_info cache_cinfo;
332
333 u32 errors;
334 spinlock_t errors_lock;
335#ifdef DEBUG
336 ktime_t perf_setup_time;
337 ktime_t perf_start_time;
338#endif
339 int debug_read;
340 int debug_write;
341
342#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
343 spinlock_t irq_stats_lock;
344 struct dsi_irq_stats irq_stats;
345#endif
346
347 unsigned long regm_max, regn_max;
348 unsigned long regm_dispc_max, regm_dsi_max;
349 unsigned long fint_min, fint_max;
350 unsigned long lpdiv_max;
351
352 unsigned num_lanes_supported;
353 unsigned line_buffer_size;
354
355 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
356 unsigned num_lanes_used;
357
358 unsigned scp_clk_refcount;
359
360 struct dss_lcd_mgr_config mgr_config;
361 struct omap_video_timings timings;
362 enum omap_dss_dsi_pixel_format pix_fmt;
363 enum omap_dss_dsi_mode mode;
364 struct omap_dss_dsi_videomode_timings vm_timings;
365
366 struct omap_dss_output output;
367};
368
369struct dsi_packet_sent_handler_data {
370 struct platform_device *dsidev;
371 struct completion *completion;
372};
373
374#ifdef DEBUG
375static bool dsi_perf;
376module_param(dsi_perf, bool, 0644);
377#endif
378
379static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
380{
381 return dev_get_drvdata(&dsidev->dev);
382}
383
384static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
385{
386 return dssdev->output->pdev;
387}
388
389struct platform_device *dsi_get_dsidev_from_id(int module)
390{
391 struct omap_dss_output *out;
392 enum omap_dss_output_id id;
393
394 switch (module) {
395 case 0:
396 id = OMAP_DSS_OUTPUT_DSI1;
397 break;
398 case 1:
399 id = OMAP_DSS_OUTPUT_DSI2;
400 break;
401 default:
402 return NULL;
403 }
404
405 out = omap_dss_get_output(id);
406
407 return out ? out->pdev : NULL;
408}
409
410static inline void dsi_write_reg(struct platform_device *dsidev,
411 const struct dsi_reg idx, u32 val)
412{
413 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
414
415 __raw_writel(val, dsi->base + idx.idx);
416}
417
418static inline u32 dsi_read_reg(struct platform_device *dsidev,
419 const struct dsi_reg idx)
420{
421 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
422
423 return __raw_readl(dsi->base + idx.idx);
424}
425
426void dsi_bus_lock(struct omap_dss_device *dssdev)
427{
428 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
429 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
430
431 down(&dsi->bus_lock);
432}
433EXPORT_SYMBOL(dsi_bus_lock);
434
435void dsi_bus_unlock(struct omap_dss_device *dssdev)
436{
437 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
438 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
439
440 up(&dsi->bus_lock);
441}
442EXPORT_SYMBOL(dsi_bus_unlock);
443
444static bool dsi_bus_is_locked(struct platform_device *dsidev)
445{
446 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
447
448 return dsi->bus_lock.count == 0;
449}
450
451static void dsi_completion_handler(void *data, u32 mask)
452{
453 complete((struct completion *)data);
454}
455
456static inline int wait_for_bit_change(struct platform_device *dsidev,
457 const struct dsi_reg idx, int bitnum, int value)
458{
459 unsigned long timeout;
460 ktime_t wait;
461 int t;
462
463
464 t = 100;
465 while (t-- > 0) {
466 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
467 return value;
468 }
469
470
471 timeout = jiffies + msecs_to_jiffies(500);
472 while (time_before(jiffies, timeout)) {
473 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
474 return value;
475
476 wait = ns_to_ktime(1000 * 1000);
477 set_current_state(TASK_UNINTERRUPTIBLE);
478 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
479 }
480
481 return !value;
482}
483
484u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
485{
486 switch (fmt) {
487 case OMAP_DSS_DSI_FMT_RGB888:
488 case OMAP_DSS_DSI_FMT_RGB666:
489 return 24;
490 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
491 return 18;
492 case OMAP_DSS_DSI_FMT_RGB565:
493 return 16;
494 default:
495 BUG();
496 return 0;
497 }
498}
499
500#ifdef DEBUG
501static void dsi_perf_mark_setup(struct platform_device *dsidev)
502{
503 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
504 dsi->perf_setup_time = ktime_get();
505}
506
507static void dsi_perf_mark_start(struct platform_device *dsidev)
508{
509 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
510 dsi->perf_start_time = ktime_get();
511}
512
513static void dsi_perf_show(struct platform_device *dsidev, const char *name)
514{
515 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
516 ktime_t t, setup_time, trans_time;
517 u32 total_bytes;
518 u32 setup_us, trans_us, total_us;
519
520 if (!dsi_perf)
521 return;
522
523 t = ktime_get();
524
525 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
526 setup_us = (u32)ktime_to_us(setup_time);
527 if (setup_us == 0)
528 setup_us = 1;
529
530 trans_time = ktime_sub(t, dsi->perf_start_time);
531 trans_us = (u32)ktime_to_us(trans_time);
532 if (trans_us == 0)
533 trans_us = 1;
534
535 total_us = setup_us + trans_us;
536
537 total_bytes = dsi->update_bytes;
538
539 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
540 "%u bytes, %u kbytes/sec\n",
541 name,
542 setup_us,
543 trans_us,
544 total_us,
545 1000*1000 / total_us,
546 total_bytes,
547 total_bytes * 1000 / total_us);
548}
549#else
550static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
551{
552}
553
554static inline void dsi_perf_mark_start(struct platform_device *dsidev)
555{
556}
557
558static inline void dsi_perf_show(struct platform_device *dsidev,
559 const char *name)
560{
561}
562#endif
563
564static int verbose_irq;
565
566static void print_irq_status(u32 status)
567{
568 if (status == 0)
569 return;
570
571 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
572 return;
573
574#define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
575
576 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
577 status,
578 verbose_irq ? PIS(VC0) : "",
579 verbose_irq ? PIS(VC1) : "",
580 verbose_irq ? PIS(VC2) : "",
581 verbose_irq ? PIS(VC3) : "",
582 PIS(WAKEUP),
583 PIS(RESYNC),
584 PIS(PLL_LOCK),
585 PIS(PLL_UNLOCK),
586 PIS(PLL_RECALL),
587 PIS(COMPLEXIO_ERR),
588 PIS(HS_TX_TIMEOUT),
589 PIS(LP_RX_TIMEOUT),
590 PIS(TE_TRIGGER),
591 PIS(ACK_TRIGGER),
592 PIS(SYNC_LOST),
593 PIS(LDO_POWER_GOOD),
594 PIS(TA_TIMEOUT));
595#undef PIS
596}
597
598static void print_irq_status_vc(int channel, u32 status)
599{
600 if (status == 0)
601 return;
602
603 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
604 return;
605
606#define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
607
608 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
609 channel,
610 status,
611 PIS(CS),
612 PIS(ECC_CORR),
613 PIS(ECC_NO_CORR),
614 verbose_irq ? PIS(PACKET_SENT) : "",
615 PIS(BTA),
616 PIS(FIFO_TX_OVF),
617 PIS(FIFO_RX_OVF),
618 PIS(FIFO_TX_UDF),
619 PIS(PP_BUSY_CHANGE));
620#undef PIS
621}
622
623static void print_irq_status_cio(u32 status)
624{
625 if (status == 0)
626 return;
627
628#define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
629
630 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
631 status,
632 PIS(ERRSYNCESC1),
633 PIS(ERRSYNCESC2),
634 PIS(ERRSYNCESC3),
635 PIS(ERRESC1),
636 PIS(ERRESC2),
637 PIS(ERRESC3),
638 PIS(ERRCONTROL1),
639 PIS(ERRCONTROL2),
640 PIS(ERRCONTROL3),
641 PIS(STATEULPS1),
642 PIS(STATEULPS2),
643 PIS(STATEULPS3),
644 PIS(ERRCONTENTIONLP0_1),
645 PIS(ERRCONTENTIONLP1_1),
646 PIS(ERRCONTENTIONLP0_2),
647 PIS(ERRCONTENTIONLP1_2),
648 PIS(ERRCONTENTIONLP0_3),
649 PIS(ERRCONTENTIONLP1_3),
650 PIS(ULPSACTIVENOT_ALL0),
651 PIS(ULPSACTIVENOT_ALL1));
652#undef PIS
653}
654
655#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
656static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
657 u32 *vcstatus, u32 ciostatus)
658{
659 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
660 int i;
661
662 spin_lock(&dsi->irq_stats_lock);
663
664 dsi->irq_stats.irq_count++;
665 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
666
667 for (i = 0; i < 4; ++i)
668 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
669
670 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
671
672 spin_unlock(&dsi->irq_stats_lock);
673}
674#else
675#define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
676#endif
677
678static int debug_irq;
679
680static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
681 u32 *vcstatus, u32 ciostatus)
682{
683 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
684 int i;
685
686 if (irqstatus & DSI_IRQ_ERROR_MASK) {
687 DSSERR("DSI error, irqstatus %x\n", irqstatus);
688 print_irq_status(irqstatus);
689 spin_lock(&dsi->errors_lock);
690 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
691 spin_unlock(&dsi->errors_lock);
692 } else if (debug_irq) {
693 print_irq_status(irqstatus);
694 }
695
696 for (i = 0; i < 4; ++i) {
697 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
698 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
699 i, vcstatus[i]);
700 print_irq_status_vc(i, vcstatus[i]);
701 } else if (debug_irq) {
702 print_irq_status_vc(i, vcstatus[i]);
703 }
704 }
705
706 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
707 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
708 print_irq_status_cio(ciostatus);
709 } else if (debug_irq) {
710 print_irq_status_cio(ciostatus);
711 }
712}
713
714static void dsi_call_isrs(struct dsi_isr_data *isr_array,
715 unsigned isr_array_size, u32 irqstatus)
716{
717 struct dsi_isr_data *isr_data;
718 int i;
719
720 for (i = 0; i < isr_array_size; i++) {
721 isr_data = &isr_array[i];
722 if (isr_data->isr && isr_data->mask & irqstatus)
723 isr_data->isr(isr_data->arg, irqstatus);
724 }
725}
726
727static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
728 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
729{
730 int i;
731
732 dsi_call_isrs(isr_tables->isr_table,
733 ARRAY_SIZE(isr_tables->isr_table),
734 irqstatus);
735
736 for (i = 0; i < 4; ++i) {
737 if (vcstatus[i] == 0)
738 continue;
739 dsi_call_isrs(isr_tables->isr_table_vc[i],
740 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
741 vcstatus[i]);
742 }
743
744 if (ciostatus != 0)
745 dsi_call_isrs(isr_tables->isr_table_cio,
746 ARRAY_SIZE(isr_tables->isr_table_cio),
747 ciostatus);
748}
749
750static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
751{
752 struct platform_device *dsidev;
753 struct dsi_data *dsi;
754 u32 irqstatus, vcstatus[4], ciostatus;
755 int i;
756
757 dsidev = (struct platform_device *) arg;
758 dsi = dsi_get_dsidrv_data(dsidev);
759
760 spin_lock(&dsi->irq_lock);
761
762 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
763
764
765 if (!irqstatus) {
766 spin_unlock(&dsi->irq_lock);
767 return IRQ_NONE;
768 }
769
770 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
771
772 dsi_read_reg(dsidev, DSI_IRQSTATUS);
773
774 for (i = 0; i < 4; ++i) {
775 if ((irqstatus & (1 << i)) == 0) {
776 vcstatus[i] = 0;
777 continue;
778 }
779
780 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
781
782 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
783
784 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
785 }
786
787 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
788 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
789
790 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
791
792 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
793 } else {
794 ciostatus = 0;
795 }
796
797#ifdef DSI_CATCH_MISSING_TE
798 if (irqstatus & DSI_IRQ_TE_TRIGGER)
799 del_timer(&dsi->te_timer);
800#endif
801
802
803
804 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
805 sizeof(dsi->isr_tables));
806
807 spin_unlock(&dsi->irq_lock);
808
809 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
810
811 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
812
813 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
814
815 return IRQ_HANDLED;
816}
817
818
819static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
820 struct dsi_isr_data *isr_array,
821 unsigned isr_array_size, u32 default_mask,
822 const struct dsi_reg enable_reg,
823 const struct dsi_reg status_reg)
824{
825 struct dsi_isr_data *isr_data;
826 u32 mask;
827 u32 old_mask;
828 int i;
829
830 mask = default_mask;
831
832 for (i = 0; i < isr_array_size; i++) {
833 isr_data = &isr_array[i];
834
835 if (isr_data->isr == NULL)
836 continue;
837
838 mask |= isr_data->mask;
839 }
840
841 old_mask = dsi_read_reg(dsidev, enable_reg);
842
843 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
844 dsi_write_reg(dsidev, enable_reg, mask);
845
846
847 dsi_read_reg(dsidev, enable_reg);
848 dsi_read_reg(dsidev, status_reg);
849}
850
851
852static void _omap_dsi_set_irqs(struct platform_device *dsidev)
853{
854 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
855 u32 mask = DSI_IRQ_ERROR_MASK;
856#ifdef DSI_CATCH_MISSING_TE
857 mask |= DSI_IRQ_TE_TRIGGER;
858#endif
859 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
860 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
861 DSI_IRQENABLE, DSI_IRQSTATUS);
862}
863
864
865static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
866{
867 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
868
869 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
870 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
871 DSI_VC_IRQ_ERROR_MASK,
872 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
873}
874
875
876static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
877{
878 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
879
880 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
881 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
882 DSI_CIO_IRQ_ERROR_MASK,
883 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
884}
885
886static void _dsi_initialize_irq(struct platform_device *dsidev)
887{
888 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
889 unsigned long flags;
890 int vc;
891
892 spin_lock_irqsave(&dsi->irq_lock, flags);
893
894 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
895
896 _omap_dsi_set_irqs(dsidev);
897 for (vc = 0; vc < 4; ++vc)
898 _omap_dsi_set_irqs_vc(dsidev, vc);
899 _omap_dsi_set_irqs_cio(dsidev);
900
901 spin_unlock_irqrestore(&dsi->irq_lock, flags);
902}
903
904static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
905 struct dsi_isr_data *isr_array, unsigned isr_array_size)
906{
907 struct dsi_isr_data *isr_data;
908 int free_idx;
909 int i;
910
911 BUG_ON(isr == NULL);
912
913
914 free_idx = -1;
915 for (i = 0; i < isr_array_size; i++) {
916 isr_data = &isr_array[i];
917
918 if (isr_data->isr == isr && isr_data->arg == arg &&
919 isr_data->mask == mask) {
920 return -EINVAL;
921 }
922
923 if (isr_data->isr == NULL && free_idx == -1)
924 free_idx = i;
925 }
926
927 if (free_idx == -1)
928 return -EBUSY;
929
930 isr_data = &isr_array[free_idx];
931 isr_data->isr = isr;
932 isr_data->arg = arg;
933 isr_data->mask = mask;
934
935 return 0;
936}
937
938static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
939 struct dsi_isr_data *isr_array, unsigned isr_array_size)
940{
941 struct dsi_isr_data *isr_data;
942 int i;
943
944 for (i = 0; i < isr_array_size; i++) {
945 isr_data = &isr_array[i];
946 if (isr_data->isr != isr || isr_data->arg != arg ||
947 isr_data->mask != mask)
948 continue;
949
950 isr_data->isr = NULL;
951 isr_data->arg = NULL;
952 isr_data->mask = 0;
953
954 return 0;
955 }
956
957 return -EINVAL;
958}
959
960static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
961 void *arg, u32 mask)
962{
963 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
964 unsigned long flags;
965 int r;
966
967 spin_lock_irqsave(&dsi->irq_lock, flags);
968
969 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
970 ARRAY_SIZE(dsi->isr_tables.isr_table));
971
972 if (r == 0)
973 _omap_dsi_set_irqs(dsidev);
974
975 spin_unlock_irqrestore(&dsi->irq_lock, flags);
976
977 return r;
978}
979
980static int dsi_unregister_isr(struct platform_device *dsidev,
981 omap_dsi_isr_t isr, void *arg, u32 mask)
982{
983 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
984 unsigned long flags;
985 int r;
986
987 spin_lock_irqsave(&dsi->irq_lock, flags);
988
989 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
990 ARRAY_SIZE(dsi->isr_tables.isr_table));
991
992 if (r == 0)
993 _omap_dsi_set_irqs(dsidev);
994
995 spin_unlock_irqrestore(&dsi->irq_lock, flags);
996
997 return r;
998}
999
1000static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
1001 omap_dsi_isr_t isr, void *arg, u32 mask)
1002{
1003 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1004 unsigned long flags;
1005 int r;
1006
1007 spin_lock_irqsave(&dsi->irq_lock, flags);
1008
1009 r = _dsi_register_isr(isr, arg, mask,
1010 dsi->isr_tables.isr_table_vc[channel],
1011 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1012
1013 if (r == 0)
1014 _omap_dsi_set_irqs_vc(dsidev, channel);
1015
1016 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1017
1018 return r;
1019}
1020
1021static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
1022 omap_dsi_isr_t isr, void *arg, u32 mask)
1023{
1024 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1025 unsigned long flags;
1026 int r;
1027
1028 spin_lock_irqsave(&dsi->irq_lock, flags);
1029
1030 r = _dsi_unregister_isr(isr, arg, mask,
1031 dsi->isr_tables.isr_table_vc[channel],
1032 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1033
1034 if (r == 0)
1035 _omap_dsi_set_irqs_vc(dsidev, channel);
1036
1037 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1038
1039 return r;
1040}
1041
1042static int dsi_register_isr_cio(struct platform_device *dsidev,
1043 omap_dsi_isr_t isr, void *arg, u32 mask)
1044{
1045 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1046 unsigned long flags;
1047 int r;
1048
1049 spin_lock_irqsave(&dsi->irq_lock, flags);
1050
1051 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1052 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1053
1054 if (r == 0)
1055 _omap_dsi_set_irqs_cio(dsidev);
1056
1057 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1058
1059 return r;
1060}
1061
1062static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1063 omap_dsi_isr_t isr, void *arg, u32 mask)
1064{
1065 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1066 unsigned long flags;
1067 int r;
1068
1069 spin_lock_irqsave(&dsi->irq_lock, flags);
1070
1071 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1072 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1073
1074 if (r == 0)
1075 _omap_dsi_set_irqs_cio(dsidev);
1076
1077 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1078
1079 return r;
1080}
1081
1082static u32 dsi_get_errors(struct platform_device *dsidev)
1083{
1084 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1085 unsigned long flags;
1086 u32 e;
1087 spin_lock_irqsave(&dsi->errors_lock, flags);
1088 e = dsi->errors;
1089 dsi->errors = 0;
1090 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1091 return e;
1092}
1093
1094int dsi_runtime_get(struct platform_device *dsidev)
1095{
1096 int r;
1097 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1098
1099 DSSDBG("dsi_runtime_get\n");
1100
1101 r = pm_runtime_get_sync(&dsi->pdev->dev);
1102 WARN_ON(r < 0);
1103 return r < 0 ? r : 0;
1104}
1105
1106void dsi_runtime_put(struct platform_device *dsidev)
1107{
1108 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1109 int r;
1110
1111 DSSDBG("dsi_runtime_put\n");
1112
1113 r = pm_runtime_put_sync(&dsi->pdev->dev);
1114 WARN_ON(r < 0 && r != -ENOSYS);
1115}
1116
1117
1118static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1119 bool enable)
1120{
1121 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1122
1123 if (enable)
1124 clk_prepare_enable(dsi->sys_clk);
1125 else
1126 clk_disable_unprepare(dsi->sys_clk);
1127
1128 if (enable && dsi->pll_locked) {
1129 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1130 DSSERR("cannot lock PLL when enabling clocks\n");
1131 }
1132}
1133
1134static void _dsi_print_reset_status(struct platform_device *dsidev)
1135{
1136 u32 l;
1137 int b0, b1, b2;
1138
1139
1140
1141
1142 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1143
1144 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1145 b0 = 28;
1146 b1 = 27;
1147 b2 = 26;
1148 } else {
1149 b0 = 24;
1150 b1 = 25;
1151 b2 = 26;
1152 }
1153
1154#define DSI_FLD_GET(fld, start, end)\
1155 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1156
1157 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1158 DSI_FLD_GET(PLL_STATUS, 0, 0),
1159 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1160 DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1161 DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1162 DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1163 DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1164 DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1165 DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1166
1167#undef DSI_FLD_GET
1168}
1169
1170static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1171{
1172 DSSDBG("dsi_if_enable(%d)\n", enable);
1173
1174 enable = enable ? 1 : 0;
1175 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0);
1176
1177 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1178 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1179 return -EIO;
1180 }
1181
1182 return 0;
1183}
1184
1185unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1186{
1187 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1188
1189 return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1190}
1191
1192static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1193{
1194 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1195
1196 return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1197}
1198
1199static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1200{
1201 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1202
1203 return dsi->current_cinfo.clkin4ddr / 16;
1204}
1205
1206static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1207{
1208 unsigned long r;
1209 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1210
1211 if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1212
1213 r = clk_get_rate(dsi->dss_clk);
1214 } else {
1215
1216 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1217 }
1218
1219 return r;
1220}
1221
1222static int dsi_lp_clock_calc(struct dsi_clock_info *cinfo,
1223 unsigned long lp_clk_min, unsigned long lp_clk_max)
1224{
1225 unsigned long dsi_fclk = cinfo->dsi_pll_hsdiv_dsi_clk;
1226 unsigned lp_clk_div;
1227 unsigned long lp_clk;
1228
1229 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1230 lp_clk = dsi_fclk / 2 / lp_clk_div;
1231
1232 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1233 return -EINVAL;
1234
1235 cinfo->lp_clk_div = lp_clk_div;
1236 cinfo->lp_clk = lp_clk;
1237
1238 return 0;
1239}
1240
1241static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
1242{
1243 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1244 unsigned long dsi_fclk;
1245 unsigned lp_clk_div;
1246 unsigned long lp_clk;
1247
1248 lp_clk_div = dsi->user_dsi_cinfo.lp_clk_div;
1249
1250 if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1251 return -EINVAL;
1252
1253 dsi_fclk = dsi_fclk_rate(dsidev);
1254
1255 lp_clk = dsi_fclk / 2 / lp_clk_div;
1256
1257 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1258 dsi->current_cinfo.lp_clk = lp_clk;
1259 dsi->current_cinfo.lp_clk_div = lp_clk_div;
1260
1261
1262 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1263
1264
1265 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1266
1267 return 0;
1268}
1269
1270static void dsi_enable_scp_clk(struct platform_device *dsidev)
1271{
1272 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1273
1274 if (dsi->scp_clk_refcount++ == 0)
1275 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14);
1276}
1277
1278static void dsi_disable_scp_clk(struct platform_device *dsidev)
1279{
1280 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1281
1282 WARN_ON(dsi->scp_clk_refcount == 0);
1283 if (--dsi->scp_clk_refcount == 0)
1284 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14);
1285}
1286
1287enum dsi_pll_power_state {
1288 DSI_PLL_POWER_OFF = 0x0,
1289 DSI_PLL_POWER_ON_HSCLK = 0x1,
1290 DSI_PLL_POWER_ON_ALL = 0x2,
1291 DSI_PLL_POWER_ON_DIV = 0x3,
1292};
1293
1294static int dsi_pll_power(struct platform_device *dsidev,
1295 enum dsi_pll_power_state state)
1296{
1297 int t = 0;
1298
1299
1300 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1301 state == DSI_PLL_POWER_ON_DIV)
1302 state = DSI_PLL_POWER_ON_ALL;
1303
1304
1305 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1306
1307
1308 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1309 if (++t > 1000) {
1310 DSSERR("Failed to set DSI PLL power mode to %d\n",
1311 state);
1312 return -ENODEV;
1313 }
1314 udelay(1);
1315 }
1316
1317 return 0;
1318}
1319
1320unsigned long dsi_get_pll_clkin(struct platform_device *dsidev)
1321{
1322 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1323 return clk_get_rate(dsi->sys_clk);
1324}
1325
1326bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll,
1327 unsigned long out_min, dsi_hsdiv_calc_func func, void *data)
1328{
1329 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1330 int regm, regm_start, regm_stop;
1331 unsigned long out_max;
1332 unsigned long out;
1333
1334 out_min = out_min ? out_min : 1;
1335 out_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1336
1337 regm_start = max(DIV_ROUND_UP(pll, out_max), 1ul);
1338 regm_stop = min(pll / out_min, dsi->regm_dispc_max);
1339
1340 for (regm = regm_start; regm <= regm_stop; ++regm) {
1341 out = pll / regm;
1342
1343 if (func(regm, out, data))
1344 return true;
1345 }
1346
1347 return false;
1348}
1349
1350bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
1351 unsigned long pll_min, unsigned long pll_max,
1352 dsi_pll_calc_func func, void *data)
1353{
1354 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1355 int regn, regn_start, regn_stop;
1356 int regm, regm_start, regm_stop;
1357 unsigned long fint, pll;
1358 const unsigned long pll_hw_max = 1800000000;
1359 unsigned long fint_hw_min, fint_hw_max;
1360
1361 fint_hw_min = dsi->fint_min;
1362 fint_hw_max = dsi->fint_max;
1363
1364 regn_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);
1365 regn_stop = min(clkin / fint_hw_min, dsi->regn_max);
1366
1367 pll_max = pll_max ? pll_max : ULONG_MAX;
1368
1369 for (regn = regn_start; regn <= regn_stop; ++regn) {
1370 fint = clkin / regn;
1371
1372 regm_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
1373 1ul);
1374 regm_stop = min3(pll_max / fint / 2,
1375 pll_hw_max / fint / 2,
1376 dsi->regm_max);
1377
1378 for (regm = regm_start; regm <= regm_stop; ++regm) {
1379 pll = 2 * regm * fint;
1380
1381 if (func(regn, regm, fint, pll, data))
1382 return true;
1383 }
1384 }
1385
1386 return false;
1387}
1388
1389
1390static int dsi_calc_clock_rates(struct platform_device *dsidev,
1391 struct dsi_clock_info *cinfo)
1392{
1393 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1394
1395 if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1396 return -EINVAL;
1397
1398 if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1399 return -EINVAL;
1400
1401 if (cinfo->regm_dispc > dsi->regm_dispc_max)
1402 return -EINVAL;
1403
1404 if (cinfo->regm_dsi > dsi->regm_dsi_max)
1405 return -EINVAL;
1406
1407 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1408 cinfo->fint = cinfo->clkin / cinfo->regn;
1409
1410 if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1411 return -EINVAL;
1412
1413 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1414
1415 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1416 return -EINVAL;
1417
1418 if (cinfo->regm_dispc > 0)
1419 cinfo->dsi_pll_hsdiv_dispc_clk =
1420 cinfo->clkin4ddr / cinfo->regm_dispc;
1421 else
1422 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1423
1424 if (cinfo->regm_dsi > 0)
1425 cinfo->dsi_pll_hsdiv_dsi_clk =
1426 cinfo->clkin4ddr / cinfo->regm_dsi;
1427 else
1428 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1429
1430 return 0;
1431}
1432
1433static void dsi_pll_calc_dsi_fck(struct dsi_clock_info *cinfo)
1434{
1435 unsigned long max_dsi_fck;
1436
1437 max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
1438
1439 cinfo->regm_dsi = DIV_ROUND_UP(cinfo->clkin4ddr, max_dsi_fck);
1440 cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi;
1441}
1442
1443int dsi_pll_set_clock_div(struct platform_device *dsidev,
1444 struct dsi_clock_info *cinfo)
1445{
1446 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1447 int r = 0;
1448 u32 l;
1449 int f = 0;
1450 u8 regn_start, regn_end, regm_start, regm_end;
1451 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1452
1453 DSSDBG("DSI PLL clock config starts");
1454
1455 dsi->current_cinfo.clkin = cinfo->clkin;
1456 dsi->current_cinfo.fint = cinfo->fint;
1457 dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1458 dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1459 cinfo->dsi_pll_hsdiv_dispc_clk;
1460 dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1461 cinfo->dsi_pll_hsdiv_dsi_clk;
1462
1463 dsi->current_cinfo.regn = cinfo->regn;
1464 dsi->current_cinfo.regm = cinfo->regm;
1465 dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1466 dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1467
1468 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1469
1470 DSSDBG("clkin rate %ld\n", cinfo->clkin);
1471
1472
1473 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1474 cinfo->regm,
1475 cinfo->regn,
1476 cinfo->clkin,
1477 cinfo->clkin4ddr);
1478
1479 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1480 cinfo->clkin4ddr / 1000 / 1000 / 2);
1481
1482 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1483
1484 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1485 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1486 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1487 cinfo->dsi_pll_hsdiv_dispc_clk);
1488 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1489 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1490 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1491 cinfo->dsi_pll_hsdiv_dsi_clk);
1492
1493 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end);
1494 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end);
1495 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start,
1496 ®m_dispc_end);
1497 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start,
1498 ®m_dsi_end);
1499
1500
1501 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1502
1503 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1504 l = FLD_MOD(l, 1, 0, 0);
1505
1506 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1507
1508 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1509
1510 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1511 regm_dispc_start, regm_dispc_end);
1512
1513 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1514 regm_dsi_start, regm_dsi_end);
1515 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1516
1517 BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1518
1519 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1520
1521 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1522 f = cinfo->fint < 1000000 ? 0x3 :
1523 cinfo->fint < 1250000 ? 0x4 :
1524 cinfo->fint < 1500000 ? 0x5 :
1525 cinfo->fint < 1750000 ? 0x6 :
1526 0x7;
1527
1528 l = FLD_MOD(l, f, 4, 1);
1529 } else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO)) {
1530 f = cinfo->clkin4ddr < 1000000000 ? 0x2 : 0x4;
1531
1532 l = FLD_MOD(l, f, 4, 1);
1533 }
1534
1535 l = FLD_MOD(l, 1, 13, 13);
1536 l = FLD_MOD(l, 0, 14, 14);
1537 l = FLD_MOD(l, 1, 20, 20);
1538 if (dss_has_feature(FEAT_DSI_PLL_REFSEL))
1539 l = FLD_MOD(l, 3, 22, 21);
1540 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1541
1542 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0);
1543
1544 if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1545 DSSERR("dsi pll go bit not going down.\n");
1546 r = -EIO;
1547 goto err;
1548 }
1549
1550 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1551 DSSERR("cannot lock PLL\n");
1552 r = -EIO;
1553 goto err;
1554 }
1555
1556 dsi->pll_locked = 1;
1557
1558 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1559 l = FLD_MOD(l, 0, 0, 0);
1560 l = FLD_MOD(l, 0, 5, 5);
1561 l = FLD_MOD(l, 0, 6, 6);
1562 l = FLD_MOD(l, 0, 7, 7);
1563 l = FLD_MOD(l, 0, 8, 8);
1564 l = FLD_MOD(l, 0, 10, 9);
1565 l = FLD_MOD(l, 1, 13, 13);
1566 l = FLD_MOD(l, 1, 14, 14);
1567 l = FLD_MOD(l, 0, 15, 15);
1568 l = FLD_MOD(l, 1, 16, 16);
1569 l = FLD_MOD(l, 0, 17, 17);
1570 l = FLD_MOD(l, 1, 18, 18);
1571 l = FLD_MOD(l, 0, 19, 19);
1572 l = FLD_MOD(l, 0, 20, 20);
1573 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1574
1575 DSSDBG("PLL config done\n");
1576err:
1577 return r;
1578}
1579
1580int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1581 bool enable_hsdiv)
1582{
1583 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1584 int r = 0;
1585 enum dsi_pll_power_state pwstate;
1586
1587 DSSDBG("PLL init\n");
1588
1589
1590
1591
1592
1593 enable_hsclk = enable_hsdiv = true;
1594
1595 if (dsi->vdds_dsi_reg == NULL) {
1596 struct regulator *vdds_dsi;
1597
1598 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1599
1600
1601 if (IS_ERR(vdds_dsi))
1602 vdds_dsi = regulator_get(&dsi->pdev->dev, "VCXIO");
1603
1604 if (IS_ERR(vdds_dsi)) {
1605 DSSERR("can't get VDDS_DSI regulator\n");
1606 return PTR_ERR(vdds_dsi);
1607 }
1608
1609 dsi->vdds_dsi_reg = vdds_dsi;
1610 }
1611
1612 dsi_enable_pll_clock(dsidev, 1);
1613
1614
1615
1616 dsi_enable_scp_clk(dsidev);
1617
1618 if (!dsi->vdds_dsi_enabled) {
1619 r = regulator_enable(dsi->vdds_dsi_reg);
1620 if (r)
1621 goto err0;
1622 dsi->vdds_dsi_enabled = true;
1623 }
1624
1625
1626 dispc_pck_free_enable(1);
1627
1628 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1629 DSSERR("PLL not coming out of reset.\n");
1630 r = -ENODEV;
1631 dispc_pck_free_enable(0);
1632 goto err1;
1633 }
1634
1635
1636
1637 dispc_pck_free_enable(0);
1638
1639 if (enable_hsclk && enable_hsdiv)
1640 pwstate = DSI_PLL_POWER_ON_ALL;
1641 else if (enable_hsclk)
1642 pwstate = DSI_PLL_POWER_ON_HSCLK;
1643 else if (enable_hsdiv)
1644 pwstate = DSI_PLL_POWER_ON_DIV;
1645 else
1646 pwstate = DSI_PLL_POWER_OFF;
1647
1648 r = dsi_pll_power(dsidev, pwstate);
1649
1650 if (r)
1651 goto err1;
1652
1653 DSSDBG("PLL init done\n");
1654
1655 return 0;
1656err1:
1657 if (dsi->vdds_dsi_enabled) {
1658 regulator_disable(dsi->vdds_dsi_reg);
1659 dsi->vdds_dsi_enabled = false;
1660 }
1661err0:
1662 dsi_disable_scp_clk(dsidev);
1663 dsi_enable_pll_clock(dsidev, 0);
1664 return r;
1665}
1666
1667void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1668{
1669 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1670
1671 dsi->pll_locked = 0;
1672 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1673 if (disconnect_lanes) {
1674 WARN_ON(!dsi->vdds_dsi_enabled);
1675 regulator_disable(dsi->vdds_dsi_reg);
1676 dsi->vdds_dsi_enabled = false;
1677 }
1678
1679 dsi_disable_scp_clk(dsidev);
1680 dsi_enable_pll_clock(dsidev, 0);
1681
1682 DSSDBG("PLL uninit done\n");
1683}
1684
1685static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1686 struct seq_file *s)
1687{
1688 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1689 struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1690 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1691 int dsi_module = dsi->module_id;
1692
1693 dispc_clk_src = dss_get_dispc_clk_source();
1694 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1695
1696 if (dsi_runtime_get(dsidev))
1697 return;
1698
1699 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1700
1701 seq_printf(s, "dsi pll clkin\t%lu\n", cinfo->clkin);
1702
1703 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1704
1705 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1706 cinfo->clkin4ddr, cinfo->regm);
1707
1708 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1709 dss_feat_get_clk_source_name(dsi_module == 0 ?
1710 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1711 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1712 cinfo->dsi_pll_hsdiv_dispc_clk,
1713 cinfo->regm_dispc,
1714 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1715 "off" : "on");
1716
1717 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1718 dss_feat_get_clk_source_name(dsi_module == 0 ?
1719 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1720 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1721 cinfo->dsi_pll_hsdiv_dsi_clk,
1722 cinfo->regm_dsi,
1723 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1724 "off" : "on");
1725
1726 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1727
1728 seq_printf(s, "dsi fclk source = %s (%s)\n",
1729 dss_get_generic_clk_source_name(dsi_clk_src),
1730 dss_feat_get_clk_source_name(dsi_clk_src));
1731
1732 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1733
1734 seq_printf(s, "DDR_CLK\t\t%lu\n",
1735 cinfo->clkin4ddr / 4);
1736
1737 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1738
1739 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1740
1741 dsi_runtime_put(dsidev);
1742}
1743
1744void dsi_dump_clocks(struct seq_file *s)
1745{
1746 struct platform_device *dsidev;
1747 int i;
1748
1749 for (i = 0; i < MAX_NUM_DSI; i++) {
1750 dsidev = dsi_get_dsidev_from_id(i);
1751 if (dsidev)
1752 dsi_dump_dsidev_clocks(dsidev, s);
1753 }
1754}
1755
1756#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1757static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1758 struct seq_file *s)
1759{
1760 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1761 unsigned long flags;
1762 struct dsi_irq_stats stats;
1763
1764 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1765
1766 stats = dsi->irq_stats;
1767 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1768 dsi->irq_stats.last_reset = jiffies;
1769
1770 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1771
1772 seq_printf(s, "period %u ms\n",
1773 jiffies_to_msecs(jiffies - stats.last_reset));
1774
1775 seq_printf(s, "irqs %d\n", stats.irq_count);
1776#define PIS(x) \
1777 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1778
1779 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1780 PIS(VC0);
1781 PIS(VC1);
1782 PIS(VC2);
1783 PIS(VC3);
1784 PIS(WAKEUP);
1785 PIS(RESYNC);
1786 PIS(PLL_LOCK);
1787 PIS(PLL_UNLOCK);
1788 PIS(PLL_RECALL);
1789 PIS(COMPLEXIO_ERR);
1790 PIS(HS_TX_TIMEOUT);
1791 PIS(LP_RX_TIMEOUT);
1792 PIS(TE_TRIGGER);
1793 PIS(ACK_TRIGGER);
1794 PIS(SYNC_LOST);
1795 PIS(LDO_POWER_GOOD);
1796 PIS(TA_TIMEOUT);
1797#undef PIS
1798
1799#define PIS(x) \
1800 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1801 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1802 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1803 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1804 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1805
1806 seq_printf(s, "-- VC interrupts --\n");
1807 PIS(CS);
1808 PIS(ECC_CORR);
1809 PIS(PACKET_SENT);
1810 PIS(FIFO_TX_OVF);
1811 PIS(FIFO_RX_OVF);
1812 PIS(BTA);
1813 PIS(ECC_NO_CORR);
1814 PIS(FIFO_TX_UDF);
1815 PIS(PP_BUSY_CHANGE);
1816#undef PIS
1817
1818#define PIS(x) \
1819 seq_printf(s, "%-20s %10d\n", #x, \
1820 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1821
1822 seq_printf(s, "-- CIO interrupts --\n");
1823 PIS(ERRSYNCESC1);
1824 PIS(ERRSYNCESC2);
1825 PIS(ERRSYNCESC3);
1826 PIS(ERRESC1);
1827 PIS(ERRESC2);
1828 PIS(ERRESC3);
1829 PIS(ERRCONTROL1);
1830 PIS(ERRCONTROL2);
1831 PIS(ERRCONTROL3);
1832 PIS(STATEULPS1);
1833 PIS(STATEULPS2);
1834 PIS(STATEULPS3);
1835 PIS(ERRCONTENTIONLP0_1);
1836 PIS(ERRCONTENTIONLP1_1);
1837 PIS(ERRCONTENTIONLP0_2);
1838 PIS(ERRCONTENTIONLP1_2);
1839 PIS(ERRCONTENTIONLP0_3);
1840 PIS(ERRCONTENTIONLP1_3);
1841 PIS(ULPSACTIVENOT_ALL0);
1842 PIS(ULPSACTIVENOT_ALL1);
1843#undef PIS
1844}
1845
1846static void dsi1_dump_irqs(struct seq_file *s)
1847{
1848 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1849
1850 dsi_dump_dsidev_irqs(dsidev, s);
1851}
1852
1853static void dsi2_dump_irqs(struct seq_file *s)
1854{
1855 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1856
1857 dsi_dump_dsidev_irqs(dsidev, s);
1858}
1859#endif
1860
1861static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1862 struct seq_file *s)
1863{
1864#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1865
1866 if (dsi_runtime_get(dsidev))
1867 return;
1868 dsi_enable_scp_clk(dsidev);
1869
1870 DUMPREG(DSI_REVISION);
1871 DUMPREG(DSI_SYSCONFIG);
1872 DUMPREG(DSI_SYSSTATUS);
1873 DUMPREG(DSI_IRQSTATUS);
1874 DUMPREG(DSI_IRQENABLE);
1875 DUMPREG(DSI_CTRL);
1876 DUMPREG(DSI_COMPLEXIO_CFG1);
1877 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1878 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1879 DUMPREG(DSI_CLK_CTRL);
1880 DUMPREG(DSI_TIMING1);
1881 DUMPREG(DSI_TIMING2);
1882 DUMPREG(DSI_VM_TIMING1);
1883 DUMPREG(DSI_VM_TIMING2);
1884 DUMPREG(DSI_VM_TIMING3);
1885 DUMPREG(DSI_CLK_TIMING);
1886 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1887 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1888 DUMPREG(DSI_COMPLEXIO_CFG2);
1889 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1890 DUMPREG(DSI_VM_TIMING4);
1891 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1892 DUMPREG(DSI_VM_TIMING5);
1893 DUMPREG(DSI_VM_TIMING6);
1894 DUMPREG(DSI_VM_TIMING7);
1895 DUMPREG(DSI_STOPCLK_TIMING);
1896
1897 DUMPREG(DSI_VC_CTRL(0));
1898 DUMPREG(DSI_VC_TE(0));
1899 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1900 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1901 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1902 DUMPREG(DSI_VC_IRQSTATUS(0));
1903 DUMPREG(DSI_VC_IRQENABLE(0));
1904
1905 DUMPREG(DSI_VC_CTRL(1));
1906 DUMPREG(DSI_VC_TE(1));
1907 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1908 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1909 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1910 DUMPREG(DSI_VC_IRQSTATUS(1));
1911 DUMPREG(DSI_VC_IRQENABLE(1));
1912
1913 DUMPREG(DSI_VC_CTRL(2));
1914 DUMPREG(DSI_VC_TE(2));
1915 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1916 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1917 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1918 DUMPREG(DSI_VC_IRQSTATUS(2));
1919 DUMPREG(DSI_VC_IRQENABLE(2));
1920
1921 DUMPREG(DSI_VC_CTRL(3));
1922 DUMPREG(DSI_VC_TE(3));
1923 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1924 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1925 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1926 DUMPREG(DSI_VC_IRQSTATUS(3));
1927 DUMPREG(DSI_VC_IRQENABLE(3));
1928
1929 DUMPREG(DSI_DSIPHY_CFG0);
1930 DUMPREG(DSI_DSIPHY_CFG1);
1931 DUMPREG(DSI_DSIPHY_CFG2);
1932 DUMPREG(DSI_DSIPHY_CFG5);
1933
1934 DUMPREG(DSI_PLL_CONTROL);
1935 DUMPREG(DSI_PLL_STATUS);
1936 DUMPREG(DSI_PLL_GO);
1937 DUMPREG(DSI_PLL_CONFIGURATION1);
1938 DUMPREG(DSI_PLL_CONFIGURATION2);
1939
1940 dsi_disable_scp_clk(dsidev);
1941 dsi_runtime_put(dsidev);
1942#undef DUMPREG
1943}
1944
1945static void dsi1_dump_regs(struct seq_file *s)
1946{
1947 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1948
1949 dsi_dump_dsidev_regs(dsidev, s);
1950}
1951
1952static void dsi2_dump_regs(struct seq_file *s)
1953{
1954 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1955
1956 dsi_dump_dsidev_regs(dsidev, s);
1957}
1958
1959enum dsi_cio_power_state {
1960 DSI_COMPLEXIO_POWER_OFF = 0x0,
1961 DSI_COMPLEXIO_POWER_ON = 0x1,
1962 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1963};
1964
1965static int dsi_cio_power(struct platform_device *dsidev,
1966 enum dsi_cio_power_state state)
1967{
1968 int t = 0;
1969
1970
1971 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
1972
1973
1974 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
1975 26, 25) != state) {
1976 if (++t > 1000) {
1977 DSSERR("failed to set complexio power state to "
1978 "%d\n", state);
1979 return -ENODEV;
1980 }
1981 udelay(1);
1982 }
1983
1984 return 0;
1985}
1986
1987static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
1988{
1989 int val;
1990
1991
1992
1993
1994
1995 if (!dss_has_feature(FEAT_DSI_GNQ))
1996 return 1023 * 3;
1997
1998 val = REG_GET(dsidev, DSI_GNQ, 14, 12);
1999
2000 switch (val) {
2001 case 1:
2002 return 512 * 3;
2003 case 2:
2004 return 682 * 3;
2005 case 3:
2006 return 853 * 3;
2007 case 4:
2008 return 1024 * 3;
2009 case 5:
2010 return 1194 * 3;
2011 case 6:
2012 return 1365 * 3;
2013 case 7:
2014 return 1920 * 3;
2015 default:
2016 BUG();
2017 return 0;
2018 }
2019}
2020
2021static int dsi_set_lane_config(struct platform_device *dsidev)
2022{
2023 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2024 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2025 static const enum dsi_lane_function functions[] = {
2026 DSI_LANE_CLK,
2027 DSI_LANE_DATA1,
2028 DSI_LANE_DATA2,
2029 DSI_LANE_DATA3,
2030 DSI_LANE_DATA4,
2031 };
2032 u32 r;
2033 int i;
2034
2035 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2036
2037 for (i = 0; i < dsi->num_lanes_used; ++i) {
2038 unsigned offset = offsets[i];
2039 unsigned polarity, lane_number;
2040 unsigned t;
2041
2042 for (t = 0; t < dsi->num_lanes_supported; ++t)
2043 if (dsi->lanes[t].function == functions[i])
2044 break;
2045
2046 if (t == dsi->num_lanes_supported)
2047 return -EINVAL;
2048
2049 lane_number = t;
2050 polarity = dsi->lanes[t].polarity;
2051
2052 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2053 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2054 }
2055
2056
2057 for (; i < dsi->num_lanes_supported; ++i) {
2058 unsigned offset = offsets[i];
2059
2060 r = FLD_MOD(r, 0, offset + 2, offset);
2061 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2062 }
2063
2064 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2065
2066 return 0;
2067}
2068
2069static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2070{
2071 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2072
2073
2074 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2075 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2076}
2077
2078static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2079{
2080 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2081
2082 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2083 return ddr * 1000 * 1000 / (ddr_clk / 1000);
2084}
2085
2086static void dsi_cio_timings(struct platform_device *dsidev)
2087{
2088 u32 r;
2089 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2090 u32 tlpx_half, tclk_trail, tclk_zero;
2091 u32 tclk_prepare;
2092
2093
2094
2095
2096
2097
2098 ths_prepare = ns2ddr(dsidev, 70) + 2;
2099
2100
2101 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2102
2103
2104 ths_trail = ns2ddr(dsidev, 60) + 5;
2105
2106
2107 ths_exit = ns2ddr(dsidev, 145);
2108
2109
2110 tlpx_half = ns2ddr(dsidev, 25);
2111
2112
2113 tclk_trail = ns2ddr(dsidev, 60) + 2;
2114
2115
2116 tclk_prepare = ns2ddr(dsidev, 65);
2117
2118
2119 tclk_zero = ns2ddr(dsidev, 260);
2120
2121 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2122 ths_prepare, ddr2ns(dsidev, ths_prepare),
2123 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2124 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2125 ths_trail, ddr2ns(dsidev, ths_trail),
2126 ths_exit, ddr2ns(dsidev, ths_exit));
2127
2128 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2129 "tclk_zero %u (%uns)\n",
2130 tlpx_half, ddr2ns(dsidev, tlpx_half),
2131 tclk_trail, ddr2ns(dsidev, tclk_trail),
2132 tclk_zero, ddr2ns(dsidev, tclk_zero));
2133 DSSDBG("tclk_prepare %u (%uns)\n",
2134 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2135
2136
2137
2138 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2139 r = FLD_MOD(r, ths_prepare, 31, 24);
2140 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2141 r = FLD_MOD(r, ths_trail, 15, 8);
2142 r = FLD_MOD(r, ths_exit, 7, 0);
2143 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2144
2145 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2146 r = FLD_MOD(r, tlpx_half, 20, 16);
2147 r = FLD_MOD(r, tclk_trail, 15, 8);
2148 r = FLD_MOD(r, tclk_zero, 7, 0);
2149
2150 if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
2151 r = FLD_MOD(r, 0, 21, 21);
2152 r = FLD_MOD(r, 1, 22, 22);
2153 r = FLD_MOD(r, 1, 23, 23);
2154 }
2155
2156 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2157
2158 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2159 r = FLD_MOD(r, tclk_prepare, 7, 0);
2160 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2161}
2162
2163
2164static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
2165 unsigned mask_p, unsigned mask_n)
2166{
2167 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2168 int i;
2169 u32 l;
2170 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2171
2172 l = 0;
2173
2174 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2175 unsigned p = dsi->lanes[i].polarity;
2176
2177 if (mask_p & (1 << i))
2178 l |= 1 << (i * 2 + (p ? 0 : 1));
2179
2180 if (mask_n & (1 << i))
2181 l |= 1 << (i * 2 + (p ? 1 : 0));
2182 }
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2197
2198
2199
2200
2201 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2202}
2203
2204static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2205{
2206
2207 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27);
2208
2209
2210 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2211}
2212
2213static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
2214{
2215 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2216 int t, i;
2217 bool in_use[DSI_MAX_NR_LANES];
2218 static const u8 offsets_old[] = { 28, 27, 26 };
2219 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2220 const u8 *offsets;
2221
2222 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2223 offsets = offsets_old;
2224 else
2225 offsets = offsets_new;
2226
2227 for (i = 0; i < dsi->num_lanes_supported; ++i)
2228 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2229
2230 t = 100000;
2231 while (true) {
2232 u32 l;
2233 int ok;
2234
2235 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2236
2237 ok = 0;
2238 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2239 if (!in_use[i] || (l & (1 << offsets[i])))
2240 ok++;
2241 }
2242
2243 if (ok == dsi->num_lanes_supported)
2244 break;
2245
2246 if (--t == 0) {
2247 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2248 if (!in_use[i] || (l & (1 << offsets[i])))
2249 continue;
2250
2251 DSSERR("CIO TXCLKESC%d domain not coming " \
2252 "out of reset\n", i);
2253 }
2254 return -EIO;
2255 }
2256 }
2257
2258 return 0;
2259}
2260
2261
2262static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2263{
2264 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2265 unsigned mask = 0;
2266 int i;
2267
2268 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2269 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2270 mask |= 1 << i;
2271 }
2272
2273 return mask;
2274}
2275
2276static int dsi_cio_init(struct platform_device *dsidev)
2277{
2278 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2279 int r;
2280 u32 l;
2281
2282 DSSDBG("DSI CIO init starts");
2283
2284 r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2285 if (r)
2286 return r;
2287
2288 dsi_enable_scp_clk(dsidev);
2289
2290
2291
2292
2293 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2294
2295 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2296 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2297 r = -EIO;
2298 goto err_scp_clk_dom;
2299 }
2300
2301 r = dsi_set_lane_config(dsidev);
2302 if (r)
2303 goto err_scp_clk_dom;
2304
2305
2306 l = dsi_read_reg(dsidev, DSI_TIMING1);
2307 l = FLD_MOD(l, 1, 15, 15);
2308 l = FLD_MOD(l, 1, 14, 14);
2309 l = FLD_MOD(l, 1, 13, 13);
2310 l = FLD_MOD(l, 0x1fff, 12, 0);
2311 dsi_write_reg(dsidev, DSI_TIMING1, l);
2312
2313 if (dsi->ulps_enabled) {
2314 unsigned mask_p;
2315 int i;
2316
2317 DSSDBG("manual ulps exit\n");
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328 mask_p = 0;
2329
2330 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2331 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2332 continue;
2333 mask_p |= 1 << i;
2334 }
2335
2336 dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2337 }
2338
2339 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2340 if (r)
2341 goto err_cio_pwr;
2342
2343 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2344 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2345 r = -ENODEV;
2346 goto err_cio_pwr_dom;
2347 }
2348
2349 dsi_if_enable(dsidev, true);
2350 dsi_if_enable(dsidev, false);
2351 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20);
2352
2353 r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2354 if (r)
2355 goto err_tx_clk_esc_rst;
2356
2357 if (dsi->ulps_enabled) {
2358
2359 ktime_t wait = ns_to_ktime(1000 * 1000);
2360 set_current_state(TASK_UNINTERRUPTIBLE);
2361 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2362
2363
2364
2365 dsi_cio_disable_lane_override(dsidev);
2366 }
2367
2368
2369 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2370
2371 dsi_cio_timings(dsidev);
2372
2373 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2374
2375 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2376 dsi->vm_timings.ddr_clk_always_on, 13, 13);
2377 }
2378
2379 dsi->ulps_enabled = false;
2380
2381 DSSDBG("CIO init done\n");
2382
2383 return 0;
2384
2385err_tx_clk_esc_rst:
2386 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20);
2387err_cio_pwr_dom:
2388 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2389err_cio_pwr:
2390 if (dsi->ulps_enabled)
2391 dsi_cio_disable_lane_override(dsidev);
2392err_scp_clk_dom:
2393 dsi_disable_scp_clk(dsidev);
2394 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2395 return r;
2396}
2397
2398static void dsi_cio_uninit(struct platform_device *dsidev)
2399{
2400 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2401
2402
2403 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2404
2405 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2406 dsi_disable_scp_clk(dsidev);
2407 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2408}
2409
2410static void dsi_config_tx_fifo(struct platform_device *dsidev,
2411 enum fifo_size size1, enum fifo_size size2,
2412 enum fifo_size size3, enum fifo_size size4)
2413{
2414 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2415 u32 r = 0;
2416 int add = 0;
2417 int i;
2418
2419 dsi->vc[0].fifo_size = size1;
2420 dsi->vc[1].fifo_size = size2;
2421 dsi->vc[2].fifo_size = size3;
2422 dsi->vc[3].fifo_size = size4;
2423
2424 for (i = 0; i < 4; i++) {
2425 u8 v;
2426 int size = dsi->vc[i].fifo_size;
2427
2428 if (add + size > 4) {
2429 DSSERR("Illegal FIFO configuration\n");
2430 BUG();
2431 return;
2432 }
2433
2434 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2435 r |= v << (8 * i);
2436
2437 add += size;
2438 }
2439
2440 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2441}
2442
2443static void dsi_config_rx_fifo(struct platform_device *dsidev,
2444 enum fifo_size size1, enum fifo_size size2,
2445 enum fifo_size size3, enum fifo_size size4)
2446{
2447 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2448 u32 r = 0;
2449 int add = 0;
2450 int i;
2451
2452 dsi->vc[0].fifo_size = size1;
2453 dsi->vc[1].fifo_size = size2;
2454 dsi->vc[2].fifo_size = size3;
2455 dsi->vc[3].fifo_size = size4;
2456
2457 for (i = 0; i < 4; i++) {
2458 u8 v;
2459 int size = dsi->vc[i].fifo_size;
2460
2461 if (add + size > 4) {
2462 DSSERR("Illegal FIFO configuration\n");
2463 BUG();
2464 return;
2465 }
2466
2467 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2468 r |= v << (8 * i);
2469
2470 add += size;
2471 }
2472
2473 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2474}
2475
2476static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2477{
2478 u32 r;
2479
2480 r = dsi_read_reg(dsidev, DSI_TIMING1);
2481 r = FLD_MOD(r, 1, 15, 15);
2482 dsi_write_reg(dsidev, DSI_TIMING1, r);
2483
2484 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2485 DSSERR("TX_STOP bit not going down\n");
2486 return -EIO;
2487 }
2488
2489 return 0;
2490}
2491
2492static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2493{
2494 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2495}
2496
2497static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2498{
2499 struct dsi_packet_sent_handler_data *vp_data =
2500 (struct dsi_packet_sent_handler_data *) data;
2501 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2502 const int channel = dsi->update_channel;
2503 u8 bit = dsi->te_enabled ? 30 : 31;
2504
2505 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2506 complete(vp_data->completion);
2507}
2508
2509static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2510{
2511 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2512 DECLARE_COMPLETION_ONSTACK(completion);
2513 struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2514 int r = 0;
2515 u8 bit;
2516
2517 bit = dsi->te_enabled ? 30 : 31;
2518
2519 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2520 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2521 if (r)
2522 goto err0;
2523
2524
2525 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2526 if (wait_for_completion_timeout(&completion,
2527 msecs_to_jiffies(10)) == 0) {
2528 DSSERR("Failed to complete previous frame transfer\n");
2529 r = -EIO;
2530 goto err1;
2531 }
2532 }
2533
2534 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2535 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2536
2537 return 0;
2538err1:
2539 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2540 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2541err0:
2542 return r;
2543}
2544
2545static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2546{
2547 struct dsi_packet_sent_handler_data *l4_data =
2548 (struct dsi_packet_sent_handler_data *) data;
2549 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2550 const int channel = dsi->update_channel;
2551
2552 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2553 complete(l4_data->completion);
2554}
2555
2556static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2557{
2558 DECLARE_COMPLETION_ONSTACK(completion);
2559 struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2560 int r = 0;
2561
2562 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2563 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2564 if (r)
2565 goto err0;
2566
2567
2568 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2569 if (wait_for_completion_timeout(&completion,
2570 msecs_to_jiffies(10)) == 0) {
2571 DSSERR("Failed to complete previous l4 transfer\n");
2572 r = -EIO;
2573 goto err1;
2574 }
2575 }
2576
2577 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2578 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2579
2580 return 0;
2581err1:
2582 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2583 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2584err0:
2585 return r;
2586}
2587
2588static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2589{
2590 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2591
2592 WARN_ON(!dsi_bus_is_locked(dsidev));
2593
2594 WARN_ON(in_interrupt());
2595
2596 if (!dsi_vc_is_enabled(dsidev, channel))
2597 return 0;
2598
2599 switch (dsi->vc[channel].source) {
2600 case DSI_VC_SOURCE_VP:
2601 return dsi_sync_vc_vp(dsidev, channel);
2602 case DSI_VC_SOURCE_L4:
2603 return dsi_sync_vc_l4(dsidev, channel);
2604 default:
2605 BUG();
2606 return -EINVAL;
2607 }
2608}
2609
2610static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2611 bool enable)
2612{
2613 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2614 channel, enable);
2615
2616 enable = enable ? 1 : 0;
2617
2618 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2619
2620 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2621 0, enable) != enable) {
2622 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2623 return -EIO;
2624 }
2625
2626 return 0;
2627}
2628
2629static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2630{
2631 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2632 u32 r;
2633
2634 DSSDBG("Initial config of virtual channel %d", channel);
2635
2636 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2637
2638 if (FLD_GET(r, 15, 15))
2639 DSSERR("VC(%d) busy when trying to configure it!\n",
2640 channel);
2641
2642 r = FLD_MOD(r, 0, 1, 1);
2643 r = FLD_MOD(r, 0, 2, 2);
2644 r = FLD_MOD(r, 0, 3, 3);
2645 r = FLD_MOD(r, 0, 4, 4);
2646 r = FLD_MOD(r, 1, 7, 7);
2647 r = FLD_MOD(r, 1, 8, 8);
2648 r = FLD_MOD(r, 0, 9, 9);
2649 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2650 r = FLD_MOD(r, 3, 11, 10);
2651
2652 r = FLD_MOD(r, 4, 29, 27);
2653 r = FLD_MOD(r, 4, 23, 21);
2654
2655 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2656
2657 dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2658}
2659
2660static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2661 enum dsi_vc_source source)
2662{
2663 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2664
2665 if (dsi->vc[channel].source == source)
2666 return 0;
2667
2668 DSSDBG("Source config of virtual channel %d", channel);
2669
2670 dsi_sync_vc(dsidev, channel);
2671
2672 dsi_vc_enable(dsidev, channel, 0);
2673
2674
2675 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2676 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2677 return -EIO;
2678 }
2679
2680
2681 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2682
2683
2684 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2685 bool enable = source == DSI_VC_SOURCE_VP;
2686 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2687 }
2688
2689 dsi_vc_enable(dsidev, channel, 1);
2690
2691 dsi->vc[channel].source = source;
2692
2693 return 0;
2694}
2695
2696void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2697 bool enable)
2698{
2699 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2700 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2701
2702 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2703
2704 WARN_ON(!dsi_bus_is_locked(dsidev));
2705
2706 dsi_vc_enable(dsidev, channel, 0);
2707 dsi_if_enable(dsidev, 0);
2708
2709 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2710
2711 dsi_vc_enable(dsidev, channel, 1);
2712 dsi_if_enable(dsidev, 1);
2713
2714 dsi_force_tx_stop_mode_io(dsidev);
2715
2716
2717 if (dsi->vm_timings.ddr_clk_always_on && enable)
2718 dsi_vc_send_null(dssdev, channel);
2719}
2720EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2721
2722static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2723{
2724 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2725 u32 val;
2726 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2727 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2728 (val >> 0) & 0xff,
2729 (val >> 8) & 0xff,
2730 (val >> 16) & 0xff,
2731 (val >> 24) & 0xff);
2732 }
2733}
2734
2735static void dsi_show_rx_ack_with_err(u16 err)
2736{
2737 DSSERR("\tACK with ERROR (%#x):\n", err);
2738 if (err & (1 << 0))
2739 DSSERR("\t\tSoT Error\n");
2740 if (err & (1 << 1))
2741 DSSERR("\t\tSoT Sync Error\n");
2742 if (err & (1 << 2))
2743 DSSERR("\t\tEoT Sync Error\n");
2744 if (err & (1 << 3))
2745 DSSERR("\t\tEscape Mode Entry Command Error\n");
2746 if (err & (1 << 4))
2747 DSSERR("\t\tLP Transmit Sync Error\n");
2748 if (err & (1 << 5))
2749 DSSERR("\t\tHS Receive Timeout Error\n");
2750 if (err & (1 << 6))
2751 DSSERR("\t\tFalse Control Error\n");
2752 if (err & (1 << 7))
2753 DSSERR("\t\t(reserved7)\n");
2754 if (err & (1 << 8))
2755 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2756 if (err & (1 << 9))
2757 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2758 if (err & (1 << 10))
2759 DSSERR("\t\tChecksum Error\n");
2760 if (err & (1 << 11))
2761 DSSERR("\t\tData type not recognized\n");
2762 if (err & (1 << 12))
2763 DSSERR("\t\tInvalid VC ID\n");
2764 if (err & (1 << 13))
2765 DSSERR("\t\tInvalid Transmission Length\n");
2766 if (err & (1 << 14))
2767 DSSERR("\t\t(reserved14)\n");
2768 if (err & (1 << 15))
2769 DSSERR("\t\tDSI Protocol Violation\n");
2770}
2771
2772static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2773 int channel)
2774{
2775
2776 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2777 u32 val;
2778 u8 dt;
2779 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2780 DSSERR("\trawval %#08x\n", val);
2781 dt = FLD_GET(val, 5, 0);
2782 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2783 u16 err = FLD_GET(val, 23, 8);
2784 dsi_show_rx_ack_with_err(err);
2785 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2786 DSSERR("\tDCS short response, 1 byte: %#x\n",
2787 FLD_GET(val, 23, 8));
2788 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2789 DSSERR("\tDCS short response, 2 byte: %#x\n",
2790 FLD_GET(val, 23, 8));
2791 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2792 DSSERR("\tDCS long response, len %d\n",
2793 FLD_GET(val, 23, 8));
2794 dsi_vc_flush_long_data(dsidev, channel);
2795 } else {
2796 DSSERR("\tunknown datatype 0x%02x\n", dt);
2797 }
2798 }
2799 return 0;
2800}
2801
2802static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2803{
2804 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2805
2806 if (dsi->debug_write || dsi->debug_read)
2807 DSSDBG("dsi_vc_send_bta %d\n", channel);
2808
2809 WARN_ON(!dsi_bus_is_locked(dsidev));
2810
2811
2812 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2813 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2814 dsi_vc_flush_receive_data(dsidev, channel);
2815 }
2816
2817 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6);
2818
2819
2820 dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2821
2822 return 0;
2823}
2824
2825int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2826{
2827 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2828 DECLARE_COMPLETION_ONSTACK(completion);
2829 int r = 0;
2830 u32 err;
2831
2832 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2833 &completion, DSI_VC_IRQ_BTA);
2834 if (r)
2835 goto err0;
2836
2837 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2838 DSI_IRQ_ERROR_MASK);
2839 if (r)
2840 goto err1;
2841
2842 r = dsi_vc_send_bta(dsidev, channel);
2843 if (r)
2844 goto err2;
2845
2846 if (wait_for_completion_timeout(&completion,
2847 msecs_to_jiffies(500)) == 0) {
2848 DSSERR("Failed to receive BTA\n");
2849 r = -EIO;
2850 goto err2;
2851 }
2852
2853 err = dsi_get_errors(dsidev);
2854 if (err) {
2855 DSSERR("Error while sending BTA: %x\n", err);
2856 r = -EIO;
2857 goto err2;
2858 }
2859err2:
2860 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2861 DSI_IRQ_ERROR_MASK);
2862err1:
2863 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2864 &completion, DSI_VC_IRQ_BTA);
2865err0:
2866 return r;
2867}
2868EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2869
2870static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2871 int channel, u8 data_type, u16 len, u8 ecc)
2872{
2873 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2874 u32 val;
2875 u8 data_id;
2876
2877 WARN_ON(!dsi_bus_is_locked(dsidev));
2878
2879 data_id = data_type | dsi->vc[channel].vc_id << 6;
2880
2881 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2882 FLD_VAL(ecc, 31, 24);
2883
2884 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2885}
2886
2887static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2888 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2889{
2890 u32 val;
2891
2892 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2893
2894
2895
2896
2897 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2898}
2899
2900static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2901 u8 data_type, u8 *data, u16 len, u8 ecc)
2902{
2903
2904 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2905 int i;
2906 u8 *p;
2907 int r = 0;
2908 u8 b1, b2, b3, b4;
2909
2910 if (dsi->debug_write)
2911 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2912
2913
2914 if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
2915 DSSERR("unable to send long packet: packet too long.\n");
2916 return -EINVAL;
2917 }
2918
2919 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2920
2921 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2922
2923 p = data;
2924 for (i = 0; i < len >> 2; i++) {
2925 if (dsi->debug_write)
2926 DSSDBG("\tsending full packet %d\n", i);
2927
2928 b1 = *p++;
2929 b2 = *p++;
2930 b3 = *p++;
2931 b4 = *p++;
2932
2933 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
2934 }
2935
2936 i = len % 4;
2937 if (i) {
2938 b1 = 0; b2 = 0; b3 = 0;
2939
2940 if (dsi->debug_write)
2941 DSSDBG("\tsending remainder bytes %d\n", i);
2942
2943 switch (i) {
2944 case 3:
2945 b1 = *p++;
2946 b2 = *p++;
2947 b3 = *p++;
2948 break;
2949 case 2:
2950 b1 = *p++;
2951 b2 = *p++;
2952 break;
2953 case 1:
2954 b1 = *p++;
2955 break;
2956 }
2957
2958 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
2959 }
2960
2961 return r;
2962}
2963
2964static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
2965 u8 data_type, u16 data, u8 ecc)
2966{
2967 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2968 u32 r;
2969 u8 data_id;
2970
2971 WARN_ON(!dsi_bus_is_locked(dsidev));
2972
2973 if (dsi->debug_write)
2974 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2975 channel,
2976 data_type, data & 0xff, (data >> 8) & 0xff);
2977
2978 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2979
2980 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
2981 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2982 return -EINVAL;
2983 }
2984
2985 data_id = data_type | dsi->vc[channel].vc_id << 6;
2986
2987 r = (data_id << 0) | (data << 8) | (ecc << 24);
2988
2989 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2990
2991 return 0;
2992}
2993
2994int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
2995{
2996 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2997
2998 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
2999 0, 0);
3000}
3001EXPORT_SYMBOL(dsi_vc_send_null);
3002
3003static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
3004 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3005{
3006 int r;
3007
3008 if (len == 0) {
3009 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3010 r = dsi_vc_send_short(dsidev, channel,
3011 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3012 } else if (len == 1) {
3013 r = dsi_vc_send_short(dsidev, channel,
3014 type == DSS_DSI_CONTENT_GENERIC ?
3015 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3016 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3017 } else if (len == 2) {
3018 r = dsi_vc_send_short(dsidev, channel,
3019 type == DSS_DSI_CONTENT_GENERIC ?
3020 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3021 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3022 data[0] | (data[1] << 8), 0);
3023 } else {
3024 r = dsi_vc_send_long(dsidev, channel,
3025 type == DSS_DSI_CONTENT_GENERIC ?
3026 MIPI_DSI_GENERIC_LONG_WRITE :
3027 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3028 }
3029
3030 return r;
3031}
3032
3033int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3034 u8 *data, int len)
3035{
3036 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3037
3038 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3039 DSS_DSI_CONTENT_DCS);
3040}
3041EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3042
3043int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3044 u8 *data, int len)
3045{
3046 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3047
3048 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3049 DSS_DSI_CONTENT_GENERIC);
3050}
3051EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3052
3053static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3054 u8 *data, int len, enum dss_dsi_content_type type)
3055{
3056 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3057 int r;
3058
3059 r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
3060 if (r)
3061 goto err;
3062
3063 r = dsi_vc_send_bta_sync(dssdev, channel);
3064 if (r)
3065 goto err;
3066
3067
3068 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3069 DSSERR("rx fifo not empty after write, dumping data:\n");
3070 dsi_vc_flush_receive_data(dsidev, channel);
3071 r = -EIO;
3072 goto err;
3073 }
3074
3075 return 0;
3076err:
3077 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3078 channel, data[0], len);
3079 return r;
3080}
3081
3082int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3083 int len)
3084{
3085 return dsi_vc_write_common(dssdev, channel, data, len,
3086 DSS_DSI_CONTENT_DCS);
3087}
3088EXPORT_SYMBOL(dsi_vc_dcs_write);
3089
3090int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3091 int len)
3092{
3093 return dsi_vc_write_common(dssdev, channel, data, len,
3094 DSS_DSI_CONTENT_GENERIC);
3095}
3096EXPORT_SYMBOL(dsi_vc_generic_write);
3097
3098int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3099{
3100 return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3101}
3102EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3103
3104int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3105{
3106 return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3107}
3108EXPORT_SYMBOL(dsi_vc_generic_write_0);
3109
3110int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3111 u8 param)
3112{
3113 u8 buf[2];
3114 buf[0] = dcs_cmd;
3115 buf[1] = param;
3116 return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3117}
3118EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3119
3120int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3121 u8 param)
3122{
3123 return dsi_vc_generic_write(dssdev, channel, ¶m, 1);
3124}
3125EXPORT_SYMBOL(dsi_vc_generic_write_1);
3126
3127int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3128 u8 param1, u8 param2)
3129{
3130 u8 buf[2];
3131 buf[0] = param1;
3132 buf[1] = param2;
3133 return dsi_vc_generic_write(dssdev, channel, buf, 2);
3134}
3135EXPORT_SYMBOL(dsi_vc_generic_write_2);
3136
3137static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
3138 int channel, u8 dcs_cmd)
3139{
3140 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3141 int r;
3142
3143 if (dsi->debug_read)
3144 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3145 channel, dcs_cmd);
3146
3147 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3148 if (r) {
3149 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3150 " failed\n", channel, dcs_cmd);
3151 return r;
3152 }
3153
3154 return 0;
3155}
3156
3157static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
3158 int channel, u8 *reqdata, int reqlen)
3159{
3160 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3161 u16 data;
3162 u8 data_type;
3163 int r;
3164
3165 if (dsi->debug_read)
3166 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3167 channel, reqlen);
3168
3169 if (reqlen == 0) {
3170 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3171 data = 0;
3172 } else if (reqlen == 1) {
3173 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3174 data = reqdata[0];
3175 } else if (reqlen == 2) {
3176 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3177 data = reqdata[0] | (reqdata[1] << 8);
3178 } else {
3179 BUG();
3180 return -EINVAL;
3181 }
3182
3183 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3184 if (r) {
3185 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3186 " failed\n", channel, reqlen);
3187 return r;
3188 }
3189
3190 return 0;
3191}
3192
3193static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3194 u8 *buf, int buflen, enum dss_dsi_content_type type)
3195{
3196 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3197 u32 val;
3198 u8 dt;
3199 int r;
3200
3201
3202 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3203 DSSERR("RX fifo empty when trying to read.\n");
3204 r = -EIO;
3205 goto err;
3206 }
3207
3208 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3209 if (dsi->debug_read)
3210 DSSDBG("\theader: %08x\n", val);
3211 dt = FLD_GET(val, 5, 0);
3212 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3213 u16 err = FLD_GET(val, 23, 8);
3214 dsi_show_rx_ack_with_err(err);
3215 r = -EIO;
3216 goto err;
3217
3218 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3219 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3220 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3221 u8 data = FLD_GET(val, 15, 8);
3222 if (dsi->debug_read)
3223 DSSDBG("\t%s short response, 1 byte: %02x\n",
3224 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3225 "DCS", data);
3226
3227 if (buflen < 1) {
3228 r = -EIO;
3229 goto err;
3230 }
3231
3232 buf[0] = data;
3233
3234 return 1;
3235 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3236 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3237 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3238 u16 data = FLD_GET(val, 23, 8);
3239 if (dsi->debug_read)
3240 DSSDBG("\t%s short response, 2 byte: %04x\n",
3241 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3242 "DCS", data);
3243
3244 if (buflen < 2) {
3245 r = -EIO;
3246 goto err;
3247 }
3248
3249 buf[0] = data & 0xff;
3250 buf[1] = (data >> 8) & 0xff;
3251
3252 return 2;
3253 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3254 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3255 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3256 int w;
3257 int len = FLD_GET(val, 23, 8);
3258 if (dsi->debug_read)
3259 DSSDBG("\t%s long response, len %d\n",
3260 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3261 "DCS", len);
3262
3263 if (len > buflen) {
3264 r = -EIO;
3265 goto err;
3266 }
3267
3268
3269 for (w = 0; w < len + 2;) {
3270 int b;
3271 val = dsi_read_reg(dsidev,
3272 DSI_VC_SHORT_PACKET_HEADER(channel));
3273 if (dsi->debug_read)
3274 DSSDBG("\t\t%02x %02x %02x %02x\n",
3275 (val >> 0) & 0xff,
3276 (val >> 8) & 0xff,
3277 (val >> 16) & 0xff,
3278 (val >> 24) & 0xff);
3279
3280 for (b = 0; b < 4; ++b) {
3281 if (w < len)
3282 buf[w] = (val >> (b * 8)) & 0xff;
3283
3284 ++w;
3285 }
3286 }
3287
3288 return len;
3289 } else {
3290 DSSERR("\tunknown datatype 0x%02x\n", dt);
3291 r = -EIO;
3292 goto err;
3293 }
3294
3295err:
3296 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3297 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3298
3299 return r;
3300}
3301
3302int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3303 u8 *buf, int buflen)
3304{
3305 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3306 int r;
3307
3308 r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
3309 if (r)
3310 goto err;
3311
3312 r = dsi_vc_send_bta_sync(dssdev, channel);
3313 if (r)
3314 goto err;
3315
3316 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3317 DSS_DSI_CONTENT_DCS);
3318 if (r < 0)
3319 goto err;
3320
3321 if (r != buflen) {
3322 r = -EIO;
3323 goto err;
3324 }
3325
3326 return 0;
3327err:
3328 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3329 return r;
3330}
3331EXPORT_SYMBOL(dsi_vc_dcs_read);
3332
3333static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3334 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3335{
3336 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3337 int r;
3338
3339 r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3340 if (r)
3341 return r;
3342
3343 r = dsi_vc_send_bta_sync(dssdev, channel);
3344 if (r)
3345 return r;
3346
3347 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3348 DSS_DSI_CONTENT_GENERIC);
3349 if (r < 0)
3350 return r;
3351
3352 if (r != buflen) {
3353 r = -EIO;
3354 return r;
3355 }
3356
3357 return 0;
3358}
3359
3360int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3361 int buflen)
3362{
3363 int r;
3364
3365 r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3366 if (r) {
3367 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3368 return r;
3369 }
3370
3371 return 0;
3372}
3373EXPORT_SYMBOL(dsi_vc_generic_read_0);
3374
3375int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3376 u8 *buf, int buflen)
3377{
3378 int r;
3379
3380 r = dsi_vc_generic_read(dssdev, channel, ¶m, 1, buf, buflen);
3381 if (r) {
3382 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3383 return r;
3384 }
3385
3386 return 0;
3387}
3388EXPORT_SYMBOL(dsi_vc_generic_read_1);
3389
3390int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3391 u8 param1, u8 param2, u8 *buf, int buflen)
3392{
3393 int r;
3394 u8 reqdata[2];
3395
3396 reqdata[0] = param1;
3397 reqdata[1] = param2;
3398
3399 r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3400 if (r) {
3401 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3402 return r;
3403 }
3404
3405 return 0;
3406}
3407EXPORT_SYMBOL(dsi_vc_generic_read_2);
3408
3409int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3410 u16 len)
3411{
3412 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3413
3414 return dsi_vc_send_short(dsidev, channel,
3415 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3416}
3417EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3418
3419static int dsi_enter_ulps(struct platform_device *dsidev)
3420{
3421 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3422 DECLARE_COMPLETION_ONSTACK(completion);
3423 int r, i;
3424 unsigned mask;
3425
3426 DSSDBG("Entering ULPS");
3427
3428 WARN_ON(!dsi_bus_is_locked(dsidev));
3429
3430 WARN_ON(dsi->ulps_enabled);
3431
3432 if (dsi->ulps_enabled)
3433 return 0;
3434
3435
3436 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3437 dsi_if_enable(dsidev, 0);
3438 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3439 dsi_if_enable(dsidev, 1);
3440 }
3441
3442 dsi_sync_vc(dsidev, 0);
3443 dsi_sync_vc(dsidev, 1);
3444 dsi_sync_vc(dsidev, 2);
3445 dsi_sync_vc(dsidev, 3);
3446
3447 dsi_force_tx_stop_mode_io(dsidev);
3448
3449 dsi_vc_enable(dsidev, 0, false);
3450 dsi_vc_enable(dsidev, 1, false);
3451 dsi_vc_enable(dsidev, 2, false);
3452 dsi_vc_enable(dsidev, 3, false);
3453
3454 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) {
3455 DSSERR("HS busy when enabling ULPS\n");
3456 return -EIO;
3457 }
3458
3459 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) {
3460 DSSERR("LP busy when enabling ULPS\n");
3461 return -EIO;
3462 }
3463
3464 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3465 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3466 if (r)
3467 return r;
3468
3469 mask = 0;
3470
3471 for (i = 0; i < dsi->num_lanes_supported; ++i) {
3472 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3473 continue;
3474 mask |= 1 << i;
3475 }
3476
3477
3478 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3479
3480
3481 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3482
3483 if (wait_for_completion_timeout(&completion,
3484 msecs_to_jiffies(1000)) == 0) {
3485 DSSERR("ULPS enable timeout\n");
3486 r = -EIO;
3487 goto err;
3488 }
3489
3490 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3491 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3492
3493
3494 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3495
3496
3497 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3498
3499 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3500
3501 dsi_if_enable(dsidev, false);
3502
3503 dsi->ulps_enabled = true;
3504
3505 return 0;
3506
3507err:
3508 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3509 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3510 return r;
3511}
3512
3513static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3514 unsigned ticks, bool x4, bool x16)
3515{
3516 unsigned long fck;
3517 unsigned long total_ticks;
3518 u32 r;
3519
3520 BUG_ON(ticks > 0x1fff);
3521
3522
3523 fck = dsi_fclk_rate(dsidev);
3524
3525 r = dsi_read_reg(dsidev, DSI_TIMING2);
3526 r = FLD_MOD(r, 1, 15, 15);
3527 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);
3528 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);
3529 r = FLD_MOD(r, ticks, 12, 0);
3530 dsi_write_reg(dsidev, DSI_TIMING2, r);
3531
3532 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3533
3534 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3535 total_ticks,
3536 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3537 (total_ticks * 1000) / (fck / 1000 / 1000));
3538}
3539
3540static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3541 bool x8, bool x16)
3542{
3543 unsigned long fck;
3544 unsigned long total_ticks;
3545 u32 r;
3546
3547 BUG_ON(ticks > 0x1fff);
3548
3549
3550 fck = dsi_fclk_rate(dsidev);
3551
3552 r = dsi_read_reg(dsidev, DSI_TIMING1);
3553 r = FLD_MOD(r, 1, 31, 31);
3554 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);
3555 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29);
3556 r = FLD_MOD(r, ticks, 28, 16);
3557 dsi_write_reg(dsidev, DSI_TIMING1, r);
3558
3559 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3560
3561 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3562 total_ticks,
3563 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3564 (total_ticks * 1000) / (fck / 1000 / 1000));
3565}
3566
3567static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3568 unsigned ticks, bool x4, bool x16)
3569{
3570 unsigned long fck;
3571 unsigned long total_ticks;
3572 u32 r;
3573
3574 BUG_ON(ticks > 0x1fff);
3575
3576
3577 fck = dsi_fclk_rate(dsidev);
3578
3579 r = dsi_read_reg(dsidev, DSI_TIMING1);
3580 r = FLD_MOD(r, 1, 15, 15);
3581 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);
3582 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);
3583 r = FLD_MOD(r, ticks, 12, 0);
3584 dsi_write_reg(dsidev, DSI_TIMING1, r);
3585
3586 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3587
3588 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3589 total_ticks,
3590 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3591 (total_ticks * 1000) / (fck / 1000 / 1000));
3592}
3593
3594static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3595 unsigned ticks, bool x4, bool x16)
3596{
3597 unsigned long fck;
3598 unsigned long total_ticks;
3599 u32 r;
3600
3601 BUG_ON(ticks > 0x1fff);
3602
3603
3604 fck = dsi_get_txbyteclkhs(dsidev);
3605
3606 r = dsi_read_reg(dsidev, DSI_TIMING2);
3607 r = FLD_MOD(r, 1, 31, 31);
3608 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);
3609 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29);
3610 r = FLD_MOD(r, ticks, 28, 16);
3611 dsi_write_reg(dsidev, DSI_TIMING2, r);
3612
3613 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3614
3615 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3616 total_ticks,
3617 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3618 (total_ticks * 1000) / (fck / 1000 / 1000));
3619}
3620
3621static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3622{
3623 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3624 int num_line_buffers;
3625
3626 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3627 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3628 struct omap_video_timings *timings = &dsi->timings;
3629
3630
3631
3632
3633 if (dsi->line_buffer_size <= timings->x_res * bpp / 8)
3634 num_line_buffers = 0;
3635 else
3636 num_line_buffers = 2;
3637 } else {
3638
3639 num_line_buffers = 2;
3640 }
3641
3642
3643 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3644}
3645
3646static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3647{
3648 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3649 bool sync_end;
3650 u32 r;
3651
3652 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3653 sync_end = true;
3654 else
3655 sync_end = false;
3656
3657 r = dsi_read_reg(dsidev, DSI_CTRL);
3658 r = FLD_MOD(r, 1, 9, 9);
3659 r = FLD_MOD(r, 1, 10, 10);
3660 r = FLD_MOD(r, 1, 11, 11);
3661 r = FLD_MOD(r, 1, 15, 15);
3662 r = FLD_MOD(r, sync_end, 16, 16);
3663 r = FLD_MOD(r, 1, 17, 17);
3664 r = FLD_MOD(r, sync_end, 18, 18);
3665 dsi_write_reg(dsidev, DSI_CTRL, r);
3666}
3667
3668static void dsi_config_blanking_modes(struct platform_device *dsidev)
3669{
3670 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3671 int blanking_mode = dsi->vm_timings.blanking_mode;
3672 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3673 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3674 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3675 u32 r;
3676
3677
3678
3679
3680
3681 r = dsi_read_reg(dsidev, DSI_CTRL);
3682 r = FLD_MOD(r, blanking_mode, 20, 20);
3683 r = FLD_MOD(r, hfp_blanking_mode, 21, 21);
3684 r = FLD_MOD(r, hbp_blanking_mode, 22, 22);
3685 r = FLD_MOD(r, hsa_blanking_mode, 23, 23);
3686 dsi_write_reg(dsidev, DSI_CTRL, r);
3687}
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3698 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3699{
3700 int transition;
3701
3702
3703
3704
3705
3706
3707
3708 if (ddr_alwon) {
3709 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3710 } else {
3711 int trans1, trans2;
3712 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3713 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3714 enter_hs + 1;
3715 transition = max(trans1, trans2);
3716 }
3717
3718 return blank > transition ? blank - transition : 0;
3719}
3720
3721
3722
3723
3724
3725
3726
3727
3728static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3729 int lp_clk_div, int tdsi_fclk)
3730{
3731 int trans_lp;
3732 int tlp_avail;
3733 int ttxclkesc;
3734 int thsbyte_clk = 16;
3735 int lp_inter;
3736
3737
3738 trans_lp = exit_hs + max(enter_hs, 2) + 1;
3739
3740
3741 tlp_avail = thsbyte_clk * (blank - trans_lp);
3742
3743 ttxclkesc = tdsi_fclk * lp_clk_div;
3744
3745 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3746 26) / 16;
3747
3748 return max(lp_inter, 0);
3749}
3750
3751static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3752{
3753 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3754 int blanking_mode;
3755 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3756 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3757 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3758 int tclk_trail, ths_exit, exiths_clk;
3759 bool ddr_alwon;
3760 struct omap_video_timings *timings = &dsi->timings;
3761 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3762 int ndl = dsi->num_lanes_used - 1;
3763 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.regm_dsi + 1;
3764 int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3765 int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3766 int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3767 int bl_interleave_hs = 0, bl_interleave_lp = 0;
3768 u32 r;
3769
3770 r = dsi_read_reg(dsidev, DSI_CTRL);
3771 blanking_mode = FLD_GET(r, 20, 20);
3772 hfp_blanking_mode = FLD_GET(r, 21, 21);
3773 hbp_blanking_mode = FLD_GET(r, 22, 22);
3774 hsa_blanking_mode = FLD_GET(r, 23, 23);
3775
3776 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3777 hbp = FLD_GET(r, 11, 0);
3778 hfp = FLD_GET(r, 23, 12);
3779 hsa = FLD_GET(r, 31, 24);
3780
3781 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3782 ddr_clk_post = FLD_GET(r, 7, 0);
3783 ddr_clk_pre = FLD_GET(r, 15, 8);
3784
3785 r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3786 exit_hs_mode_lat = FLD_GET(r, 15, 0);
3787 enter_hs_mode_lat = FLD_GET(r, 31, 16);
3788
3789 r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3790 lp_clk_div = FLD_GET(r, 12, 0);
3791 ddr_alwon = FLD_GET(r, 13, 13);
3792
3793 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3794 ths_exit = FLD_GET(r, 7, 0);
3795
3796 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3797 tclk_trail = FLD_GET(r, 15, 8);
3798
3799 exiths_clk = ths_exit + tclk_trail;
3800
3801 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3802 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3803
3804 if (!hsa_blanking_mode) {
3805 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3806 enter_hs_mode_lat, exit_hs_mode_lat,
3807 exiths_clk, ddr_clk_pre, ddr_clk_post);
3808 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3809 enter_hs_mode_lat, exit_hs_mode_lat,
3810 lp_clk_div, dsi_fclk_hsdiv);
3811 }
3812
3813 if (!hfp_blanking_mode) {
3814 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3815 enter_hs_mode_lat, exit_hs_mode_lat,
3816 exiths_clk, ddr_clk_pre, ddr_clk_post);
3817 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3818 enter_hs_mode_lat, exit_hs_mode_lat,
3819 lp_clk_div, dsi_fclk_hsdiv);
3820 }
3821
3822 if (!hbp_blanking_mode) {
3823 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3824 enter_hs_mode_lat, exit_hs_mode_lat,
3825 exiths_clk, ddr_clk_pre, ddr_clk_post);
3826
3827 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3828 enter_hs_mode_lat, exit_hs_mode_lat,
3829 lp_clk_div, dsi_fclk_hsdiv);
3830 }
3831
3832 if (!blanking_mode) {
3833 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3834 enter_hs_mode_lat, exit_hs_mode_lat,
3835 exiths_clk, ddr_clk_pre, ddr_clk_post);
3836
3837 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3838 enter_hs_mode_lat, exit_hs_mode_lat,
3839 lp_clk_div, dsi_fclk_hsdiv);
3840 }
3841
3842 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3843 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3844 bl_interleave_hs);
3845
3846 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3847 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3848 bl_interleave_lp);
3849
3850 r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3851 r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3852 r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3853 r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3854 dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
3855
3856 r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
3857 r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3858 r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3859 r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3860 dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
3861
3862 r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
3863 r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3864 r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3865 dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
3866}
3867
3868static int dsi_proto_config(struct platform_device *dsidev)
3869{
3870 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3871 u32 r;
3872 int buswidth = 0;
3873
3874 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3875 DSI_FIFO_SIZE_32,
3876 DSI_FIFO_SIZE_32,
3877 DSI_FIFO_SIZE_32);
3878
3879 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3880 DSI_FIFO_SIZE_32,
3881 DSI_FIFO_SIZE_32,
3882 DSI_FIFO_SIZE_32);
3883
3884
3885 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3886 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3887 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3888 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3889
3890 switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3891 case 16:
3892 buswidth = 0;
3893 break;
3894 case 18:
3895 buswidth = 1;
3896 break;
3897 case 24:
3898 buswidth = 2;
3899 break;
3900 default:
3901 BUG();
3902 return -EINVAL;
3903 }
3904
3905 r = dsi_read_reg(dsidev, DSI_CTRL);
3906 r = FLD_MOD(r, 1, 1, 1);
3907 r = FLD_MOD(r, 1, 2, 2);
3908 r = FLD_MOD(r, 1, 3, 3);
3909 r = FLD_MOD(r, 1, 4, 4);
3910 r = FLD_MOD(r, buswidth, 7, 6);
3911 r = FLD_MOD(r, 0, 8, 8);
3912 r = FLD_MOD(r, 1, 14, 14);
3913 r = FLD_MOD(r, 1, 19, 19);
3914 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3915 r = FLD_MOD(r, 1, 24, 24);
3916
3917 r = FLD_MOD(r, 0, 25, 25);
3918 }
3919
3920 dsi_write_reg(dsidev, DSI_CTRL, r);
3921
3922 dsi_config_vp_num_line_buffers(dsidev);
3923
3924 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3925 dsi_config_vp_sync_events(dsidev);
3926 dsi_config_blanking_modes(dsidev);
3927 dsi_config_cmd_mode_interleaving(dsidev);
3928 }
3929
3930 dsi_vc_initial_config(dsidev, 0);
3931 dsi_vc_initial_config(dsidev, 1);
3932 dsi_vc_initial_config(dsidev, 2);
3933 dsi_vc_initial_config(dsidev, 3);
3934
3935 return 0;
3936}
3937
3938static void dsi_proto_timings(struct platform_device *dsidev)
3939{
3940 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3941 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3942 unsigned tclk_pre, tclk_post;
3943 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3944 unsigned ths_trail, ths_exit;
3945 unsigned ddr_clk_pre, ddr_clk_post;
3946 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3947 unsigned ths_eot;
3948 int ndl = dsi->num_lanes_used - 1;
3949 u32 r;
3950
3951 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3952 ths_prepare = FLD_GET(r, 31, 24);
3953 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3954 ths_zero = ths_prepare_ths_zero - ths_prepare;
3955 ths_trail = FLD_GET(r, 15, 8);
3956 ths_exit = FLD_GET(r, 7, 0);
3957
3958 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3959 tlpx = FLD_GET(r, 20, 16) * 2;
3960 tclk_trail = FLD_GET(r, 15, 8);
3961 tclk_zero = FLD_GET(r, 7, 0);
3962
3963 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3964 tclk_prepare = FLD_GET(r, 7, 0);
3965
3966
3967 tclk_pre = 20;
3968
3969 tclk_post = ns2ddr(dsidev, 60) + 26;
3970
3971 ths_eot = DIV_ROUND_UP(4, ndl);
3972
3973 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3974 4);
3975 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3976
3977 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3978 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3979
3980 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3981 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3982 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3983 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3984
3985 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3986 ddr_clk_pre,
3987 ddr_clk_post);
3988
3989 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3990 DIV_ROUND_UP(ths_prepare, 4) +
3991 DIV_ROUND_UP(ths_zero + 3, 4);
3992
3993 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3994
3995 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3996 FLD_VAL(exit_hs_mode_lat, 15, 0);
3997 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3998
3999 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
4000 enter_hs_mode_lat, exit_hs_mode_lat);
4001
4002 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4003
4004 int hsa = dsi->vm_timings.hsa;
4005 int hfp = dsi->vm_timings.hfp;
4006 int hbp = dsi->vm_timings.hbp;
4007 int vsa = dsi->vm_timings.vsa;
4008 int vfp = dsi->vm_timings.vfp;
4009 int vbp = dsi->vm_timings.vbp;
4010 int window_sync = dsi->vm_timings.window_sync;
4011 bool hsync_end;
4012 struct omap_video_timings *timings = &dsi->timings;
4013 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
4014 int tl, t_he, width_bytes;
4015
4016 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
4017 t_he = hsync_end ?
4018 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
4019
4020 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
4021
4022
4023 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
4024 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
4025
4026 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
4027 hfp, hsync_end ? hsa : 0, tl);
4028 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
4029 vsa, timings->y_res);
4030
4031 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
4032 r = FLD_MOD(r, hbp, 11, 0);
4033 r = FLD_MOD(r, hfp, 23, 12);
4034 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24);
4035 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
4036
4037 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
4038 r = FLD_MOD(r, vbp, 7, 0);
4039 r = FLD_MOD(r, vfp, 15, 8);
4040 r = FLD_MOD(r, vsa, 23, 16);
4041 r = FLD_MOD(r, window_sync, 27, 24);
4042 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
4043
4044 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
4045 r = FLD_MOD(r, timings->y_res, 14, 0);
4046 r = FLD_MOD(r, tl, 31, 16);
4047 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
4048 }
4049}
4050
4051int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
4052 const struct omap_dsi_pin_config *pin_cfg)
4053{
4054 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4055 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4056 int num_pins;
4057 const int *pins;
4058 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
4059 int num_lanes;
4060 int i;
4061
4062 static const enum dsi_lane_function functions[] = {
4063 DSI_LANE_CLK,
4064 DSI_LANE_DATA1,
4065 DSI_LANE_DATA2,
4066 DSI_LANE_DATA3,
4067 DSI_LANE_DATA4,
4068 };
4069
4070 num_pins = pin_cfg->num_pins;
4071 pins = pin_cfg->pins;
4072
4073 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
4074 || num_pins % 2 != 0)
4075 return -EINVAL;
4076
4077 for (i = 0; i < DSI_MAX_NR_LANES; ++i)
4078 lanes[i].function = DSI_LANE_UNUSED;
4079
4080 num_lanes = 0;
4081
4082 for (i = 0; i < num_pins; i += 2) {
4083 u8 lane, pol;
4084 int dx, dy;
4085
4086 dx = pins[i];
4087 dy = pins[i + 1];
4088
4089 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
4090 return -EINVAL;
4091
4092 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
4093 return -EINVAL;
4094
4095 if (dx & 1) {
4096 if (dy != dx - 1)
4097 return -EINVAL;
4098 pol = 1;
4099 } else {
4100 if (dy != dx + 1)
4101 return -EINVAL;
4102 pol = 0;
4103 }
4104
4105 lane = dx / 2;
4106
4107 lanes[lane].function = functions[i / 2];
4108 lanes[lane].polarity = pol;
4109 num_lanes++;
4110 }
4111
4112 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
4113 dsi->num_lanes_used = num_lanes;
4114
4115 return 0;
4116}
4117EXPORT_SYMBOL(omapdss_dsi_configure_pins);
4118
4119int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
4120{
4121 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4122 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4123 struct omap_overlay_manager *mgr = dsi->output.manager;
4124 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
4125 struct omap_dss_output *out = &dsi->output;
4126 u8 data_type;
4127 u16 word_count;
4128 int r;
4129
4130 if (out == NULL || out->manager == NULL) {
4131 DSSERR("failed to enable display: no output/manager\n");
4132 return -ENODEV;
4133 }
4134
4135 r = dsi_display_init_dispc(dsidev, mgr);
4136 if (r)
4137 goto err_init_dispc;
4138
4139 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4140 switch (dsi->pix_fmt) {
4141 case OMAP_DSS_DSI_FMT_RGB888:
4142 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
4143 break;
4144 case OMAP_DSS_DSI_FMT_RGB666:
4145 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
4146 break;
4147 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
4148 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
4149 break;
4150 case OMAP_DSS_DSI_FMT_RGB565:
4151 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
4152 break;
4153 default:
4154 r = -EINVAL;
4155 goto err_pix_fmt;
4156 };
4157
4158 dsi_if_enable(dsidev, false);
4159 dsi_vc_enable(dsidev, channel, false);
4160
4161
4162 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
4163
4164 word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
4165
4166 dsi_vc_write_long_header(dsidev, channel, data_type,
4167 word_count, 0);
4168
4169 dsi_vc_enable(dsidev, channel, true);
4170 dsi_if_enable(dsidev, true);
4171 }
4172
4173 r = dss_mgr_enable(mgr);
4174 if (r)
4175 goto err_mgr_enable;
4176
4177 return 0;
4178
4179err_mgr_enable:
4180 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4181 dsi_if_enable(dsidev, false);
4182 dsi_vc_enable(dsidev, channel, false);
4183 }
4184err_pix_fmt:
4185 dsi_display_uninit_dispc(dsidev, mgr);
4186err_init_dispc:
4187 return r;
4188}
4189EXPORT_SYMBOL(dsi_enable_video_output);
4190
4191void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
4192{
4193 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4194 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4195 struct omap_overlay_manager *mgr = dsi->output.manager;
4196
4197 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4198 dsi_if_enable(dsidev, false);
4199 dsi_vc_enable(dsidev, channel, false);
4200
4201
4202 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4203
4204 dsi_vc_enable(dsidev, channel, true);
4205 dsi_if_enable(dsidev, true);
4206 }
4207
4208 dss_mgr_disable(mgr);
4209
4210 dsi_display_uninit_dispc(dsidev, mgr);
4211}
4212EXPORT_SYMBOL(dsi_disable_video_output);
4213
4214static void dsi_update_screen_dispc(struct platform_device *dsidev)
4215{
4216 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4217 struct omap_overlay_manager *mgr = dsi->output.manager;
4218 unsigned bytespp;
4219 unsigned bytespl;
4220 unsigned bytespf;
4221 unsigned total_len;
4222 unsigned packet_payload;
4223 unsigned packet_len;
4224 u32 l;
4225 int r;
4226 const unsigned channel = dsi->update_channel;
4227 const unsigned line_buf_size = dsi->line_buffer_size;
4228 u16 w = dsi->timings.x_res;
4229 u16 h = dsi->timings.y_res;
4230
4231 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4232
4233 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4234
4235 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
4236 bytespl = w * bytespp;
4237 bytespf = bytespl * h;
4238
4239
4240
4241
4242 if (bytespf < line_buf_size)
4243 packet_payload = bytespf;
4244 else
4245 packet_payload = (line_buf_size) / bytespl * bytespl;
4246
4247 packet_len = packet_payload + 1;
4248 total_len = (bytespf / packet_payload) * packet_len;
4249
4250 if (bytespf % packet_payload)
4251 total_len += (bytespf % packet_payload) + 1;
4252
4253 l = FLD_VAL(total_len, 23, 0);
4254 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4255
4256 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4257 packet_len, 0);
4258
4259 if (dsi->te_enabled)
4260 l = FLD_MOD(l, 1, 30, 30);
4261 else
4262 l = FLD_MOD(l, 1, 31, 31);
4263 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4264
4265
4266
4267
4268
4269
4270
4271 dispc_disable_sidle();
4272
4273 dsi_perf_mark_start(dsidev);
4274
4275 r = schedule_delayed_work(&dsi->framedone_timeout_work,
4276 msecs_to_jiffies(250));
4277 BUG_ON(r == 0);
4278
4279 dss_mgr_set_timings(mgr, &dsi->timings);
4280
4281 dss_mgr_start_update(mgr);
4282
4283 if (dsi->te_enabled) {
4284
4285
4286 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15);
4287
4288 dsi_vc_send_bta(dsidev, channel);
4289
4290#ifdef DSI_CATCH_MISSING_TE
4291 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4292#endif
4293 }
4294}
4295
4296#ifdef DSI_CATCH_MISSING_TE
4297static void dsi_te_timeout(unsigned long arg)
4298{
4299 DSSERR("TE not received for 250ms!\n");
4300}
4301#endif
4302
4303static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4304{
4305 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4306
4307
4308 dispc_enable_sidle();
4309
4310 if (dsi->te_enabled) {
4311
4312 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15);
4313 }
4314
4315 dsi->framedone_callback(error, dsi->framedone_data);
4316
4317 if (!error)
4318 dsi_perf_show(dsidev, "DISPC");
4319}
4320
4321static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4322{
4323 struct dsi_data *dsi = container_of(work, struct dsi_data,
4324 framedone_timeout_work.work);
4325
4326
4327
4328
4329
4330
4331
4332 DSSERR("Framedone not received for 250ms!\n");
4333
4334 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4335}
4336
4337static void dsi_framedone_irq_callback(void *data)
4338{
4339 struct platform_device *dsidev = (struct platform_device *) data;
4340 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4341
4342
4343
4344
4345
4346
4347 cancel_delayed_work(&dsi->framedone_timeout_work);
4348
4349 dsi_handle_framedone(dsidev, 0);
4350}
4351
4352int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
4353 void (*callback)(int, void *), void *data)
4354{
4355 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4356 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4357 u16 dw, dh;
4358
4359 dsi_perf_mark_setup(dsidev);
4360
4361 dsi->update_channel = channel;
4362
4363 dsi->framedone_callback = callback;
4364 dsi->framedone_data = data;
4365
4366 dw = dsi->timings.x_res;
4367 dh = dsi->timings.y_res;
4368
4369#ifdef DEBUG
4370 dsi->update_bytes = dw * dh *
4371 dsi_get_pixel_size(dsi->pix_fmt) / 8;
4372#endif
4373 dsi_update_screen_dispc(dsidev);
4374
4375 return 0;
4376}
4377EXPORT_SYMBOL(omap_dsi_update);
4378
4379
4380
4381static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
4382{
4383 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4384 struct dispc_clock_info dispc_cinfo;
4385 int r;
4386 unsigned long fck;
4387
4388 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4389
4390 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
4391 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
4392
4393 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4394 if (r) {
4395 DSSERR("Failed to calc dispc clocks\n");
4396 return r;
4397 }
4398
4399 dsi->mgr_config.clock_info = dispc_cinfo;
4400
4401 return 0;
4402}
4403
4404static int dsi_display_init_dispc(struct platform_device *dsidev,
4405 struct omap_overlay_manager *mgr)
4406{
4407 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4408 int r;
4409
4410 dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ?
4411 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
4412 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC);
4413
4414 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4415 r = dss_mgr_register_framedone_handler(mgr,
4416 dsi_framedone_irq_callback, dsidev);
4417 if (r) {
4418 DSSERR("can't register FRAMEDONE handler\n");
4419 goto err;
4420 }
4421
4422 dsi->mgr_config.stallmode = true;
4423 dsi->mgr_config.fifohandcheck = true;
4424 } else {
4425 dsi->mgr_config.stallmode = false;
4426 dsi->mgr_config.fifohandcheck = false;
4427 }
4428
4429
4430
4431
4432
4433 dsi->timings.interlace = false;
4434 dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4435 dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4436 dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4437 dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4438 dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
4439
4440 dss_mgr_set_timings(mgr, &dsi->timings);
4441
4442 r = dsi_configure_dispc_clocks(dsidev);
4443 if (r)
4444 goto err1;
4445
4446 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4447 dsi->mgr_config.video_port_width =
4448 dsi_get_pixel_size(dsi->pix_fmt);
4449 dsi->mgr_config.lcden_sig_polarity = 0;
4450
4451 dss_mgr_set_lcd_config(mgr, &dsi->mgr_config);
4452
4453 return 0;
4454err1:
4455 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4456 dss_mgr_unregister_framedone_handler(mgr,
4457 dsi_framedone_irq_callback, dsidev);
4458err:
4459 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4460 return r;
4461}
4462
4463static void dsi_display_uninit_dispc(struct platform_device *dsidev,
4464 struct omap_overlay_manager *mgr)
4465{
4466 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4467
4468 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4469 dss_mgr_unregister_framedone_handler(mgr,
4470 dsi_framedone_irq_callback, dsidev);
4471
4472 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4473}
4474
4475static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
4476{
4477 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4478 struct dsi_clock_info cinfo;
4479 int r;
4480
4481 cinfo = dsi->user_dsi_cinfo;
4482
4483 r = dsi_calc_clock_rates(dsidev, &cinfo);
4484 if (r) {
4485 DSSERR("Failed to calc dsi clocks\n");
4486 return r;
4487 }
4488
4489 r = dsi_pll_set_clock_div(dsidev, &cinfo);
4490 if (r) {
4491 DSSERR("Failed to set dsi clocks\n");
4492 return r;
4493 }
4494
4495 return 0;
4496}
4497
4498static int dsi_display_init_dsi(struct platform_device *dsidev)
4499{
4500 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4501 int r;
4502
4503 r = dsi_pll_init(dsidev, true, true);
4504 if (r)
4505 goto err0;
4506
4507 r = dsi_configure_dsi_clocks(dsidev);
4508 if (r)
4509 goto err1;
4510
4511 dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ?
4512 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
4513 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI);
4514
4515 DSSDBG("PLL OK\n");
4516
4517 r = dsi_cio_init(dsidev);
4518 if (r)
4519 goto err2;
4520
4521 _dsi_print_reset_status(dsidev);
4522
4523 dsi_proto_timings(dsidev);
4524 dsi_set_lp_clk_divisor(dsidev);
4525
4526 if (1)
4527 _dsi_print_reset_status(dsidev);
4528
4529 r = dsi_proto_config(dsidev);
4530 if (r)
4531 goto err3;
4532
4533
4534 dsi_vc_enable(dsidev, 0, 1);
4535 dsi_vc_enable(dsidev, 1, 1);
4536 dsi_vc_enable(dsidev, 2, 1);
4537 dsi_vc_enable(dsidev, 3, 1);
4538 dsi_if_enable(dsidev, 1);
4539 dsi_force_tx_stop_mode_io(dsidev);
4540
4541 return 0;
4542err3:
4543 dsi_cio_uninit(dsidev);
4544err2:
4545 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4546err1:
4547 dsi_pll_uninit(dsidev, true);
4548err0:
4549 return r;
4550}
4551
4552static void dsi_display_uninit_dsi(struct platform_device *dsidev,
4553 bool disconnect_lanes, bool enter_ulps)
4554{
4555 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4556
4557 if (enter_ulps && !dsi->ulps_enabled)
4558 dsi_enter_ulps(dsidev);
4559
4560
4561 dsi_if_enable(dsidev, 0);
4562 dsi_vc_enable(dsidev, 0, 0);
4563 dsi_vc_enable(dsidev, 1, 0);
4564 dsi_vc_enable(dsidev, 2, 0);
4565 dsi_vc_enable(dsidev, 3, 0);
4566
4567 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4568 dsi_cio_uninit(dsidev);
4569 dsi_pll_uninit(dsidev, disconnect_lanes);
4570}
4571
4572int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4573{
4574 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4575 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4576 int r = 0;
4577
4578 DSSDBG("dsi_display_enable\n");
4579
4580 WARN_ON(!dsi_bus_is_locked(dsidev));
4581
4582 mutex_lock(&dsi->lock);
4583
4584 r = omap_dss_start_device(dssdev);
4585 if (r) {
4586 DSSERR("failed to start device\n");
4587 goto err_start_dev;
4588 }
4589
4590 r = dsi_runtime_get(dsidev);
4591 if (r)
4592 goto err_get_dsi;
4593
4594 dsi_enable_pll_clock(dsidev, 1);
4595
4596 _dsi_initialize_irq(dsidev);
4597
4598 r = dsi_display_init_dsi(dsidev);
4599 if (r)
4600 goto err_init_dsi;
4601
4602 mutex_unlock(&dsi->lock);
4603
4604 return 0;
4605
4606err_init_dsi:
4607 dsi_enable_pll_clock(dsidev, 0);
4608 dsi_runtime_put(dsidev);
4609err_get_dsi:
4610 omap_dss_stop_device(dssdev);
4611err_start_dev:
4612 mutex_unlock(&dsi->lock);
4613 DSSDBG("dsi_display_enable FAILED\n");
4614 return r;
4615}
4616EXPORT_SYMBOL(omapdss_dsi_display_enable);
4617
4618void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4619 bool disconnect_lanes, bool enter_ulps)
4620{
4621 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4622 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4623
4624 DSSDBG("dsi_display_disable\n");
4625
4626 WARN_ON(!dsi_bus_is_locked(dsidev));
4627
4628 mutex_lock(&dsi->lock);
4629
4630 dsi_sync_vc(dsidev, 0);
4631 dsi_sync_vc(dsidev, 1);
4632 dsi_sync_vc(dsidev, 2);
4633 dsi_sync_vc(dsidev, 3);
4634
4635 dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps);
4636
4637 dsi_runtime_put(dsidev);
4638 dsi_enable_pll_clock(dsidev, 0);
4639
4640 omap_dss_stop_device(dssdev);
4641
4642 mutex_unlock(&dsi->lock);
4643}
4644EXPORT_SYMBOL(omapdss_dsi_display_disable);
4645
4646int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4647{
4648 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4649 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4650
4651 dsi->te_enabled = enable;
4652 return 0;
4653}
4654EXPORT_SYMBOL(omapdss_dsi_enable_te);
4655
4656#ifdef PRINT_VERBOSE_VM_TIMINGS
4657static void print_dsi_vm(const char *str,
4658 const struct omap_dss_dsi_videomode_timings *t)
4659{
4660 unsigned long byteclk = t->hsclk / 4;
4661 int bl, wc, pps, tot;
4662
4663 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4664 pps = DIV_ROUND_UP(wc + 6, t->ndl);
4665 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
4666 tot = bl + pps;
4667
4668#define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4669
4670 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4671 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4672 str,
4673 byteclk,
4674 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
4675 bl, pps, tot,
4676 TO_DSI_T(t->hss),
4677 TO_DSI_T(t->hsa),
4678 TO_DSI_T(t->hse),
4679 TO_DSI_T(t->hbp),
4680 TO_DSI_T(pps),
4681 TO_DSI_T(t->hfp),
4682
4683 TO_DSI_T(bl),
4684 TO_DSI_T(pps),
4685
4686 TO_DSI_T(tot));
4687#undef TO_DSI_T
4688}
4689
4690static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
4691{
4692 unsigned long pck = t->pixel_clock * 1000;
4693 int hact, bl, tot;
4694
4695 hact = t->x_res;
4696 bl = t->hsw + t->hbp + t->hfp;
4697 tot = hact + bl;
4698
4699#define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4700
4701 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4702 "%u/%u/%u/%u = %u + %u = %u\n",
4703 str,
4704 pck,
4705 t->hsw, t->hbp, hact, t->hfp,
4706 bl, hact, tot,
4707 TO_DISPC_T(t->hsw),
4708 TO_DISPC_T(t->hbp),
4709 TO_DISPC_T(hact),
4710 TO_DISPC_T(t->hfp),
4711 TO_DISPC_T(bl),
4712 TO_DISPC_T(hact),
4713 TO_DISPC_T(tot));
4714#undef TO_DISPC_T
4715}
4716
4717
4718static void print_dsi_dispc_vm(const char *str,
4719 const struct omap_dss_dsi_videomode_timings *t)
4720{
4721 struct omap_video_timings vm = { 0 };
4722 unsigned long byteclk = t->hsclk / 4;
4723 unsigned long pck;
4724 u64 dsi_tput;
4725 int dsi_hact, dsi_htot;
4726
4727 dsi_tput = (u64)byteclk * t->ndl * 8;
4728 pck = (u32)div64_u64(dsi_tput, t->bitspp);
4729 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4730 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4731
4732 vm.pixel_clock = pck / 1000;
4733 vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4734 vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
4735 vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
4736 vm.x_res = t->hact;
4737
4738 print_dispc_vm(str, &vm);
4739}
4740#endif
4741
4742static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4743 unsigned long pck, void *data)
4744{
4745 struct dsi_clk_calc_ctx *ctx = data;
4746 struct omap_video_timings *t = &ctx->dispc_vm;
4747
4748 ctx->dispc_cinfo.lck_div = lckd;
4749 ctx->dispc_cinfo.pck_div = pckd;
4750 ctx->dispc_cinfo.lck = lck;
4751 ctx->dispc_cinfo.pck = pck;
4752
4753 *t = *ctx->config->timings;
4754 t->pixel_clock = pck / 1000;
4755 t->x_res = ctx->config->timings->x_res;
4756 t->y_res = ctx->config->timings->y_res;
4757 t->hsw = t->hfp = t->hbp = t->vsw = 1;
4758 t->vfp = t->vbp = 0;
4759
4760 return true;
4761}
4762
4763static bool dsi_cm_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
4764 void *data)
4765{
4766 struct dsi_clk_calc_ctx *ctx = data;
4767
4768 ctx->dsi_cinfo.regm_dispc = regm_dispc;
4769 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
4770
4771 return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max,
4772 dsi_cm_calc_dispc_cb, ctx);
4773}
4774
4775static bool dsi_cm_calc_pll_cb(int regn, int regm, unsigned long fint,
4776 unsigned long pll, void *data)
4777{
4778 struct dsi_clk_calc_ctx *ctx = data;
4779
4780 ctx->dsi_cinfo.regn = regn;
4781 ctx->dsi_cinfo.regm = regm;
4782 ctx->dsi_cinfo.fint = fint;
4783 ctx->dsi_cinfo.clkin4ddr = pll;
4784
4785 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->req_pck_min,
4786 dsi_cm_calc_hsdiv_cb, ctx);
4787}
4788
4789static bool dsi_cm_calc(struct dsi_data *dsi,
4790 const struct omap_dss_dsi_config *cfg,
4791 struct dsi_clk_calc_ctx *ctx)
4792{
4793 unsigned long clkin;
4794 int bitspp, ndl;
4795 unsigned long pll_min, pll_max;
4796 unsigned long pck, txbyteclk;
4797
4798 clkin = clk_get_rate(dsi->sys_clk);
4799 bitspp = dsi_get_pixel_size(cfg->pixel_format);
4800 ndl = dsi->num_lanes_used - 1;
4801
4802
4803
4804
4805
4806
4807
4808 pck = cfg->timings->pixel_clock * 1000;
4809 pck = pck * 3 / 2;
4810 txbyteclk = pck * bitspp / 8 / ndl;
4811
4812 memset(ctx, 0, sizeof(*ctx));
4813 ctx->dsidev = dsi->pdev;
4814 ctx->config = cfg;
4815 ctx->req_pck_min = pck;
4816 ctx->req_pck_nom = pck;
4817 ctx->req_pck_max = pck * 3 / 2;
4818 ctx->dsi_cinfo.clkin = clkin;
4819
4820 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4821 pll_max = cfg->hs_clk_max * 4;
4822
4823 return dsi_pll_calc(dsi->pdev, clkin,
4824 pll_min, pll_max,
4825 dsi_cm_calc_pll_cb, ctx);
4826}
4827
4828static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4829{
4830 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev);
4831 const struct omap_dss_dsi_config *cfg = ctx->config;
4832 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4833 int ndl = dsi->num_lanes_used - 1;
4834 unsigned long hsclk = ctx->dsi_cinfo.clkin4ddr / 4;
4835 unsigned long byteclk = hsclk / 4;
4836
4837 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4838 int xres;
4839 int panel_htot, panel_hbl;
4840 int dispc_htot, dispc_hbl;
4841 int dsi_htot, dsi_hact, dsi_hbl, hss, hse;
4842 int hfp, hsa, hbp;
4843 const struct omap_video_timings *req_vm;
4844 struct omap_video_timings *dispc_vm;
4845 struct omap_dss_dsi_videomode_timings *dsi_vm;
4846 u64 dsi_tput, dispc_tput;
4847
4848 dsi_tput = (u64)byteclk * ndl * 8;
4849
4850 req_vm = cfg->timings;
4851 req_pck_min = ctx->req_pck_min;
4852 req_pck_max = ctx->req_pck_max;
4853 req_pck_nom = ctx->req_pck_nom;
4854
4855 dispc_pck = ctx->dispc_cinfo.pck;
4856 dispc_tput = (u64)dispc_pck * bitspp;
4857
4858 xres = req_vm->x_res;
4859
4860 panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw;
4861 panel_htot = xres + panel_hbl;
4862
4863 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4864
4865
4866
4867
4868
4869 if (dsi->line_buffer_size < xres * bitspp / 8) {
4870 if (dispc_tput != dsi_tput)
4871 return false;
4872 } else {
4873 if (dispc_tput < dsi_tput)
4874 return false;
4875 }
4876
4877
4878 if (dsi_tput < (u64)bitspp * req_pck_min)
4879 return false;
4880
4881
4882 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4883 if (dsi_tput > (u64)bitspp * req_pck_max)
4884 return false;
4885 }
4886
4887 hss = DIV_ROUND_UP(4, ndl);
4888
4889 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4890 if (ndl == 3 && req_vm->hsw == 0)
4891 hse = 1;
4892 else
4893 hse = DIV_ROUND_UP(4, ndl);
4894 } else {
4895 hse = 0;
4896 }
4897
4898
4899 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4900
4901
4902 if (dsi_htot < hss + hse + dsi_hact)
4903 return false;
4904
4905
4906 dsi_hbl = dsi_htot - dsi_hact;
4907
4908
4909 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4910
4911
4912 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4913 return false;
4914
4915 dispc_hbl = dispc_htot - xres;
4916
4917
4918
4919 dsi_vm = &ctx->dsi_vm;
4920 memset(dsi_vm, 0, sizeof(*dsi_vm));
4921
4922 dsi_vm->hsclk = hsclk;
4923
4924 dsi_vm->ndl = ndl;
4925 dsi_vm->bitspp = bitspp;
4926
4927 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4928 hsa = 0;
4929 } else if (ndl == 3 && req_vm->hsw == 0) {
4930 hsa = 0;
4931 } else {
4932 hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom);
4933 hsa = max(hsa - hse, 1);
4934 }
4935
4936 hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom);
4937 hbp = max(hbp, 1);
4938
4939 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4940 if (hfp < 1) {
4941 int t;
4942
4943
4944 t = 1 - hfp;
4945 hbp = max(hbp - t, 1);
4946 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4947
4948 if (hfp < 1 && hsa > 0) {
4949
4950 t = 1 - hfp;
4951 hsa = max(hsa - t, 1);
4952 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4953 }
4954 }
4955
4956 if (hfp < 1)
4957 return false;
4958
4959 dsi_vm->hss = hss;
4960 dsi_vm->hsa = hsa;
4961 dsi_vm->hse = hse;
4962 dsi_vm->hbp = hbp;
4963 dsi_vm->hact = xres;
4964 dsi_vm->hfp = hfp;
4965
4966 dsi_vm->vsa = req_vm->vsw;
4967 dsi_vm->vbp = req_vm->vbp;
4968 dsi_vm->vact = req_vm->y_res;
4969 dsi_vm->vfp = req_vm->vfp;
4970
4971 dsi_vm->trans_mode = cfg->trans_mode;
4972
4973 dsi_vm->blanking_mode = 0;
4974 dsi_vm->hsa_blanking_mode = 1;
4975 dsi_vm->hfp_blanking_mode = 1;
4976 dsi_vm->hbp_blanking_mode = 1;
4977
4978 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4979 dsi_vm->window_sync = 4;
4980
4981
4982
4983 dispc_vm = &ctx->dispc_vm;
4984 *dispc_vm = *req_vm;
4985 dispc_vm->pixel_clock = dispc_pck / 1000;
4986
4987 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4988 hsa = div64_u64((u64)req_vm->hsw * dispc_pck,
4989 req_pck_nom);
4990 hsa = max(hsa, 1);
4991 } else {
4992 hsa = 1;
4993 }
4994
4995 hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom);
4996 hbp = max(hbp, 1);
4997
4998 hfp = dispc_hbl - hsa - hbp;
4999 if (hfp < 1) {
5000 int t;
5001
5002
5003 t = 1 - hfp;
5004 hbp = max(hbp - t, 1);
5005 hfp = dispc_hbl - hsa - hbp;
5006
5007 if (hfp < 1) {
5008
5009 t = 1 - hfp;
5010 hsa = max(hsa - t, 1);
5011 hfp = dispc_hbl - hsa - hbp;
5012 }
5013 }
5014
5015 if (hfp < 1)
5016 return false;
5017
5018 dispc_vm->hfp = hfp;
5019 dispc_vm->hsw = hsa;
5020 dispc_vm->hbp = hbp;
5021
5022 return true;
5023}
5024
5025
5026static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
5027 unsigned long pck, void *data)
5028{
5029 struct dsi_clk_calc_ctx *ctx = data;
5030
5031 ctx->dispc_cinfo.lck_div = lckd;
5032 ctx->dispc_cinfo.pck_div = pckd;
5033 ctx->dispc_cinfo.lck = lck;
5034 ctx->dispc_cinfo.pck = pck;
5035
5036 if (dsi_vm_calc_blanking(ctx) == false)
5037 return false;
5038
5039#ifdef PRINT_VERBOSE_VM_TIMINGS
5040 print_dispc_vm("dispc", &ctx->dispc_vm);
5041 print_dsi_vm("dsi ", &ctx->dsi_vm);
5042 print_dispc_vm("req ", ctx->config->timings);
5043 print_dsi_dispc_vm("act ", &ctx->dsi_vm);
5044#endif
5045
5046 return true;
5047}
5048
5049static bool dsi_vm_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
5050 void *data)
5051{
5052 struct dsi_clk_calc_ctx *ctx = data;
5053 unsigned long pck_max;
5054
5055 ctx->dsi_cinfo.regm_dispc = regm_dispc;
5056 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
5057
5058
5059
5060
5061
5062
5063 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
5064 pck_max = ctx->req_pck_max + 10000000;
5065 else
5066 pck_max = ctx->req_pck_max;
5067
5068 return dispc_div_calc(dispc, ctx->req_pck_min, pck_max,
5069 dsi_vm_calc_dispc_cb, ctx);
5070}
5071
5072static bool dsi_vm_calc_pll_cb(int regn, int regm, unsigned long fint,
5073 unsigned long pll, void *data)
5074{
5075 struct dsi_clk_calc_ctx *ctx = data;
5076
5077 ctx->dsi_cinfo.regn = regn;
5078 ctx->dsi_cinfo.regm = regm;
5079 ctx->dsi_cinfo.fint = fint;
5080 ctx->dsi_cinfo.clkin4ddr = pll;
5081
5082 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->req_pck_min,
5083 dsi_vm_calc_hsdiv_cb, ctx);
5084}
5085
5086static bool dsi_vm_calc(struct dsi_data *dsi,
5087 const struct omap_dss_dsi_config *cfg,
5088 struct dsi_clk_calc_ctx *ctx)
5089{
5090 const struct omap_video_timings *t = cfg->timings;
5091 unsigned long clkin;
5092 unsigned long pll_min;
5093 unsigned long pll_max;
5094 int ndl = dsi->num_lanes_used - 1;
5095 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
5096 unsigned long byteclk_min;
5097
5098 clkin = clk_get_rate(dsi->sys_clk);
5099
5100 memset(ctx, 0, sizeof(*ctx));
5101 ctx->dsidev = dsi->pdev;
5102 ctx->config = cfg;
5103
5104 ctx->dsi_cinfo.clkin = clkin;
5105
5106
5107 ctx->req_pck_min = t->pixel_clock * 1000 - 1000;
5108 ctx->req_pck_nom = t->pixel_clock * 1000;
5109 ctx->req_pck_max = t->pixel_clock * 1000 + 1000;
5110
5111 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
5112 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
5113
5114 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
5115 pll_max = cfg->hs_clk_max * 4;
5116 } else {
5117 unsigned long byteclk_max;
5118 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
5119 ndl * 8);
5120
5121 pll_max = byteclk_max * 4 * 4;
5122 }
5123
5124 return dsi_pll_calc(dsi->pdev, clkin,
5125 pll_min, pll_max,
5126 dsi_vm_calc_pll_cb, ctx);
5127}
5128
5129int omapdss_dsi_set_config(struct omap_dss_device *dssdev,
5130 const struct omap_dss_dsi_config *config)
5131{
5132 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5133 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5134 struct dsi_clk_calc_ctx ctx;
5135 bool ok;
5136 int r;
5137
5138 mutex_lock(&dsi->lock);
5139
5140 dsi->pix_fmt = config->pixel_format;
5141 dsi->mode = config->mode;
5142
5143 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
5144 ok = dsi_vm_calc(dsi, config, &ctx);
5145 else
5146 ok = dsi_cm_calc(dsi, config, &ctx);
5147
5148 if (!ok) {
5149 DSSERR("failed to find suitable DSI clock settings\n");
5150 r = -EINVAL;
5151 goto err;
5152 }
5153
5154 dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo);
5155
5156 r = dsi_lp_clock_calc(&ctx.dsi_cinfo, config->lp_clk_min,
5157 config->lp_clk_max);
5158 if (r) {
5159 DSSERR("failed to find suitable DSI LP clock settings\n");
5160 goto err;
5161 }
5162
5163 dsi->user_dsi_cinfo = ctx.dsi_cinfo;
5164 dsi->user_dispc_cinfo = ctx.dispc_cinfo;
5165
5166 dsi->timings = ctx.dispc_vm;
5167 dsi->vm_timings = ctx.dsi_vm;
5168
5169 mutex_unlock(&dsi->lock);
5170
5171 return 0;
5172err:
5173 mutex_unlock(&dsi->lock);
5174
5175 return r;
5176}
5177EXPORT_SYMBOL(omapdss_dsi_set_config);
5178
5179
5180
5181
5182
5183
5184
5185static enum omap_channel dsi_get_channel(int module_id)
5186{
5187 switch (omapdss_get_version()) {
5188 case OMAPDSS_VER_OMAP24xx:
5189 DSSWARN("DSI not supported\n");
5190 return OMAP_DSS_CHANNEL_LCD;
5191
5192 case OMAPDSS_VER_OMAP34xx_ES1:
5193 case OMAPDSS_VER_OMAP34xx_ES3:
5194 case OMAPDSS_VER_OMAP3630:
5195 case OMAPDSS_VER_AM35xx:
5196 return OMAP_DSS_CHANNEL_LCD;
5197
5198 case OMAPDSS_VER_OMAP4430_ES1:
5199 case OMAPDSS_VER_OMAP4430_ES2:
5200 case OMAPDSS_VER_OMAP4:
5201 switch (module_id) {
5202 case 0:
5203 return OMAP_DSS_CHANNEL_LCD;
5204 case 1:
5205 return OMAP_DSS_CHANNEL_LCD2;
5206 default:
5207 DSSWARN("unsupported module id\n");
5208 return OMAP_DSS_CHANNEL_LCD;
5209 }
5210
5211 case OMAPDSS_VER_OMAP5:
5212 switch (module_id) {
5213 case 0:
5214 return OMAP_DSS_CHANNEL_LCD;
5215 case 1:
5216 return OMAP_DSS_CHANNEL_LCD3;
5217 default:
5218 DSSWARN("unsupported module id\n");
5219 return OMAP_DSS_CHANNEL_LCD;
5220 }
5221
5222 default:
5223 DSSWARN("unsupported DSS version\n");
5224 return OMAP_DSS_CHANNEL_LCD;
5225 }
5226}
5227
5228static int dsi_init_display(struct omap_dss_device *dssdev)
5229{
5230 struct platform_device *dsidev =
5231 dsi_get_dsidev_from_id(dssdev->phy.dsi.module);
5232 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5233
5234 DSSDBG("DSI init\n");
5235
5236 if (dsi->vdds_dsi_reg == NULL) {
5237 struct regulator *vdds_dsi;
5238
5239 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
5240
5241
5242 if (IS_ERR(vdds_dsi))
5243 vdds_dsi = regulator_get(&dsi->pdev->dev, "VCXIO");
5244
5245 if (IS_ERR(vdds_dsi)) {
5246 DSSERR("can't get VDDS_DSI regulator\n");
5247 return PTR_ERR(vdds_dsi);
5248 }
5249
5250 dsi->vdds_dsi_reg = vdds_dsi;
5251 }
5252
5253 return 0;
5254}
5255
5256int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
5257{
5258 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5259 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5260 int i;
5261
5262 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5263 if (!dsi->vc[i].dssdev) {
5264 dsi->vc[i].dssdev = dssdev;
5265 *channel = i;
5266 return 0;
5267 }
5268 }
5269
5270 DSSERR("cannot get VC for display %s", dssdev->name);
5271 return -ENOSPC;
5272}
5273EXPORT_SYMBOL(omap_dsi_request_vc);
5274
5275int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
5276{
5277 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5278 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5279
5280 if (vc_id < 0 || vc_id > 3) {
5281 DSSERR("VC ID out of range\n");
5282 return -EINVAL;
5283 }
5284
5285 if (channel < 0 || channel > 3) {
5286 DSSERR("Virtual Channel out of range\n");
5287 return -EINVAL;
5288 }
5289
5290 if (dsi->vc[channel].dssdev != dssdev) {
5291 DSSERR("Virtual Channel not allocated to display %s\n",
5292 dssdev->name);
5293 return -EINVAL;
5294 }
5295
5296 dsi->vc[channel].vc_id = vc_id;
5297
5298 return 0;
5299}
5300EXPORT_SYMBOL(omap_dsi_set_vc_id);
5301
5302void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
5303{
5304 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5305 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5306
5307 if ((channel >= 0 && channel <= 3) &&
5308 dsi->vc[channel].dssdev == dssdev) {
5309 dsi->vc[channel].dssdev = NULL;
5310 dsi->vc[channel].vc_id = 0;
5311 }
5312}
5313EXPORT_SYMBOL(omap_dsi_release_vc);
5314
5315void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
5316{
5317 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
5318 DSSERR("%s (%s) not active\n",
5319 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
5320 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
5321}
5322
5323void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
5324{
5325 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
5326 DSSERR("%s (%s) not active\n",
5327 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
5328 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
5329}
5330
5331static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
5332{
5333 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5334
5335 dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
5336 dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
5337 dsi->regm_dispc_max =
5338 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
5339 dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
5340 dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
5341 dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
5342 dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
5343}
5344
5345static int dsi_get_clocks(struct platform_device *dsidev)
5346{
5347 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5348 struct clk *clk;
5349
5350 clk = devm_clk_get(&dsidev->dev, "fck");
5351 if (IS_ERR(clk)) {
5352 DSSERR("can't get fck\n");
5353 return PTR_ERR(clk);
5354 }
5355
5356 dsi->dss_clk = clk;
5357
5358 clk = devm_clk_get(&dsidev->dev, "sys_clk");
5359 if (IS_ERR(clk)) {
5360 DSSERR("can't get sys_clk\n");
5361 return PTR_ERR(clk);
5362 }
5363
5364 dsi->sys_clk = clk;
5365
5366 return 0;
5367}
5368
5369static struct omap_dss_device *dsi_find_dssdev(struct platform_device *pdev)
5370{
5371 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
5372 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5373 const char *def_disp_name = omapdss_get_default_display_name();
5374 struct omap_dss_device *def_dssdev;
5375 int i;
5376
5377 def_dssdev = NULL;
5378
5379 for (i = 0; i < pdata->num_devices; ++i) {
5380 struct omap_dss_device *dssdev = pdata->devices[i];
5381
5382 if (dssdev->type != OMAP_DISPLAY_TYPE_DSI)
5383 continue;
5384
5385 if (dssdev->phy.dsi.module != dsi->module_id)
5386 continue;
5387
5388 if (def_dssdev == NULL)
5389 def_dssdev = dssdev;
5390
5391 if (def_disp_name != NULL &&
5392 strcmp(dssdev->name, def_disp_name) == 0) {
5393 def_dssdev = dssdev;
5394 break;
5395 }
5396 }
5397
5398 return def_dssdev;
5399}
5400
5401static int dsi_probe_pdata(struct platform_device *dsidev)
5402{
5403 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5404 struct omap_dss_device *plat_dssdev;
5405 struct omap_dss_device *dssdev;
5406 int r;
5407
5408 plat_dssdev = dsi_find_dssdev(dsidev);
5409
5410 if (!plat_dssdev)
5411 return 0;
5412
5413 dssdev = dss_alloc_and_init_device(&dsidev->dev);
5414 if (!dssdev)
5415 return -ENOMEM;
5416
5417 dss_copy_device_pdata(dssdev, plat_dssdev);
5418
5419 r = dsi_init_display(dssdev);
5420 if (r) {
5421 DSSERR("device %s init failed: %d\n", dssdev->name, r);
5422 dss_put_device(dssdev);
5423 return r;
5424 }
5425
5426 r = omapdss_output_set_device(&dsi->output, dssdev);
5427 if (r) {
5428 DSSERR("failed to connect output to new device: %s\n",
5429 dssdev->name);
5430 dss_put_device(dssdev);
5431 return r;
5432 }
5433
5434 r = dss_add_device(dssdev);
5435 if (r) {
5436 DSSERR("device %s register failed: %d\n", dssdev->name, r);
5437 omapdss_output_unset_device(&dsi->output);
5438 dss_put_device(dssdev);
5439 return r;
5440 }
5441
5442 return 0;
5443}
5444
5445static void dsi_init_output(struct platform_device *dsidev)
5446{
5447 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5448 struct omap_dss_output *out = &dsi->output;
5449
5450 out->pdev = dsidev;
5451 out->id = dsi->module_id == 0 ?
5452 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5453
5454 out->type = OMAP_DISPLAY_TYPE_DSI;
5455 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5456 out->dispc_channel = dsi_get_channel(dsi->module_id);
5457
5458 dss_register_output(out);
5459}
5460
5461static void dsi_uninit_output(struct platform_device *dsidev)
5462{
5463 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5464 struct omap_dss_output *out = &dsi->output;
5465
5466 dss_unregister_output(out);
5467}
5468
5469
5470static int omap_dsihw_probe(struct platform_device *dsidev)
5471{
5472 u32 rev;
5473 int r, i;
5474 struct resource *dsi_mem;
5475 struct dsi_data *dsi;
5476
5477 dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5478 if (!dsi)
5479 return -ENOMEM;
5480
5481 dsi->module_id = dsidev->id;
5482 dsi->pdev = dsidev;
5483 dev_set_drvdata(&dsidev->dev, dsi);
5484
5485 spin_lock_init(&dsi->irq_lock);
5486 spin_lock_init(&dsi->errors_lock);
5487 dsi->errors = 0;
5488
5489#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5490 spin_lock_init(&dsi->irq_stats_lock);
5491 dsi->irq_stats.last_reset = jiffies;
5492#endif
5493
5494 mutex_init(&dsi->lock);
5495 sema_init(&dsi->bus_lock, 1);
5496
5497 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5498 dsi_framedone_timeout_work_callback);
5499
5500#ifdef DSI_CATCH_MISSING_TE
5501 init_timer(&dsi->te_timer);
5502 dsi->te_timer.function = dsi_te_timeout;
5503 dsi->te_timer.data = 0;
5504#endif
5505 dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
5506 if (!dsi_mem) {
5507 DSSERR("can't get IORESOURCE_MEM DSI\n");
5508 return -EINVAL;
5509 }
5510
5511 dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start,
5512 resource_size(dsi_mem));
5513 if (!dsi->base) {
5514 DSSERR("can't ioremap DSI\n");
5515 return -ENOMEM;
5516 }
5517
5518 dsi->irq = platform_get_irq(dsi->pdev, 0);
5519 if (dsi->irq < 0) {
5520 DSSERR("platform_get_irq failed\n");
5521 return -ENODEV;
5522 }
5523
5524 r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5525 IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5526 if (r < 0) {
5527 DSSERR("request_irq failed\n");
5528 return r;
5529 }
5530
5531
5532 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5533 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5534 dsi->vc[i].dssdev = NULL;
5535 dsi->vc[i].vc_id = 0;
5536 }
5537
5538 dsi_calc_clock_param_ranges(dsidev);
5539
5540 r = dsi_get_clocks(dsidev);
5541 if (r)
5542 return r;
5543
5544 pm_runtime_enable(&dsidev->dev);
5545
5546 r = dsi_runtime_get(dsidev);
5547 if (r)
5548 goto err_runtime_get;
5549
5550 rev = dsi_read_reg(dsidev, DSI_REVISION);
5551 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5552 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5553
5554
5555
5556 if (dss_has_feature(FEAT_DSI_GNQ))
5557
5558 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5559 else
5560 dsi->num_lanes_supported = 3;
5561
5562 dsi->line_buffer_size = dsi_get_line_buf_size(dsidev);
5563
5564 dsi_init_output(dsidev);
5565
5566 r = dsi_probe_pdata(dsidev);
5567 if (r) {
5568 dsi_runtime_put(dsidev);
5569 dsi_uninit_output(dsidev);
5570 pm_runtime_disable(&dsidev->dev);
5571 return r;
5572 }
5573
5574 dsi_runtime_put(dsidev);
5575
5576 if (dsi->module_id == 0)
5577 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5578 else if (dsi->module_id == 1)
5579 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5580
5581#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5582 if (dsi->module_id == 0)
5583 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5584 else if (dsi->module_id == 1)
5585 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5586#endif
5587 return 0;
5588
5589err_runtime_get:
5590 pm_runtime_disable(&dsidev->dev);
5591 return r;
5592}
5593
5594static int __exit omap_dsihw_remove(struct platform_device *dsidev)
5595{
5596 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5597
5598 WARN_ON(dsi->scp_clk_refcount > 0);
5599
5600 dss_unregister_child_devices(&dsidev->dev);
5601
5602 dsi_uninit_output(dsidev);
5603
5604 pm_runtime_disable(&dsidev->dev);
5605
5606 if (dsi->vdds_dsi_reg != NULL) {
5607 if (dsi->vdds_dsi_enabled) {
5608 regulator_disable(dsi->vdds_dsi_reg);
5609 dsi->vdds_dsi_enabled = false;
5610 }
5611
5612 regulator_put(dsi->vdds_dsi_reg);
5613 dsi->vdds_dsi_reg = NULL;
5614 }
5615
5616 return 0;
5617}
5618
5619static int dsi_runtime_suspend(struct device *dev)
5620{
5621 dispc_runtime_put();
5622
5623 return 0;
5624}
5625
5626static int dsi_runtime_resume(struct device *dev)
5627{
5628 int r;
5629
5630 r = dispc_runtime_get();
5631 if (r)
5632 return r;
5633
5634 return 0;
5635}
5636
5637static const struct dev_pm_ops dsi_pm_ops = {
5638 .runtime_suspend = dsi_runtime_suspend,
5639 .runtime_resume = dsi_runtime_resume,
5640};
5641
5642static struct platform_driver omap_dsihw_driver = {
5643 .probe = omap_dsihw_probe,
5644 .remove = __exit_p(omap_dsihw_remove),
5645 .driver = {
5646 .name = "omapdss_dsi",
5647 .owner = THIS_MODULE,
5648 .pm = &dsi_pm_ops,
5649 },
5650};
5651
5652int __init dsi_init_platform_driver(void)
5653{
5654 return platform_driver_register(&omap_dsihw_driver);
5655}
5656
5657void __exit dsi_uninit_platform_driver(void)
5658{
5659 platform_driver_unregister(&omap_dsihw_driver);
5660}
5661
