LXR linux/sound/soc/intel/skylake/skl-ssp-clk.h

   1/*
   2 *  skl-ssp-clk.h - Skylake ssp clock information and ipc structure
   3 *
   4 *  Copyright (C) 2017 Intel Corp
   5 *  Author: Jaikrishna Nemallapudi <jaikrishnax.nemallapudi@intel.com>
   6 *  Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
   7 *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   8 *
   9 *  This program is free software; you can redistribute it and/or modify
  10 *  it under the terms of the GNU General Public License as published by
  11 *  the Free Software Foundation; version 2 of the License.
  12 *
  13 *  This program is distributed in the hope that it will be useful, but
  14 *  WITHOUT ANY WARRANTY; without even the implied warranty of
  15 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16 *  General Public License for more details.
  17 *
  18 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  19 *
  20 */
  21
  22#ifndef SOUND_SOC_SKL_SSP_CLK_H
  23#define SOUND_SOC_SKL_SSP_CLK_H
  24
  25#define SKL_MAX_SSP             6
  26/* xtal/cardinal/pll, parent of ssp clocks and mclk */
  27#define SKL_MAX_CLK_SRC         3
  28#define SKL_MAX_SSP_CLK_TYPES   3 /* mclk, sclk, sclkfs */
  29
  30#define SKL_MAX_CLK_CNT         (SKL_MAX_SSP * SKL_MAX_SSP_CLK_TYPES)
  31
  32/* Max number of configurations supported for each clock */
  33#define SKL_MAX_CLK_RATES       10
  34
  35#define SKL_SCLK_OFS            SKL_MAX_SSP
  36#define SKL_SCLKFS_OFS          (SKL_SCLK_OFS + SKL_MAX_SSP)
  37
  38enum skl_clk_type {
  39        SKL_MCLK,
  40        SKL_SCLK,
  41        SKL_SCLK_FS,
  42};
  43
  44enum skl_clk_src_type {
  45        SKL_XTAL,
  46        SKL_CARDINAL,
  47        SKL_PLL,
  48};
  49
  50struct skl_clk_parent_src {
  51        u8 clk_id;
  52        const char *name;
  53        unsigned long rate;
  54        const char *parent_name;
  55};
  56
  57struct skl_tlv_hdr {
  58        u32 type;
  59        u32 size;
  60};
  61
  62struct skl_dmactrl_mclk_cfg {
  63        struct skl_tlv_hdr hdr;
  64        /* DMA Clk TLV params */
  65        u32 clk_warm_up:16;
  66        u32 mclk:1;
  67        u32 warm_up_over:1;
  68        u32 rsvd0:14;
  69        u32 clk_stop_delay:16;
  70        u32 keep_running:1;
  71        u32 clk_stop_over:1;
  72        u32 rsvd1:14;
  73};
  74
  75struct skl_dmactrl_sclkfs_cfg {
  76        struct skl_tlv_hdr hdr;
  77        /* DMA SClk&FS  TLV params */
  78        u32 sampling_frequency;
  79        u32 bit_depth;
  80        u32 channel_map;
  81        u32 channel_config;
  82        u32 interleaving_style;
  83        u32 number_of_channels : 8;
  84        u32 valid_bit_depth : 8;
  85        u32 sample_type : 8;
  86        u32 reserved : 8;
  87};
  88
  89union skl_clk_ctrl_ipc {
  90        struct skl_dmactrl_mclk_cfg mclk;
  91        struct skl_dmactrl_sclkfs_cfg sclk_fs;
  92};
  93
  94struct skl_clk_rate_cfg_table {
  95        unsigned long rate;
  96        union skl_clk_ctrl_ipc dma_ctl_ipc;
  97        void *config;
  98};
  99
 100/*
 101 * rate for mclk will be in rates[0]. For sclk and sclkfs, rates[] store
 102 * all possible clocks ssp can generate for that platform.
 103 */
 104struct skl_ssp_clk {
 105        const char *name;
 106        const char *parent_name;
 107        struct skl_clk_rate_cfg_table rate_cfg[SKL_MAX_CLK_RATES];
 108};
 109
 110struct skl_clk_pdata {
 111        struct skl_clk_parent_src *parent_clks;
 112        int num_clks;
 113        struct skl_ssp_clk *ssp_clks;
 114        void *pvt_data;
 115};
 116
 117#endif /* SOUND_SOC_SKL_SSP_CLK_H */
 118