1#include <linux/module.h>
2#include <linux/slab.h>
3
4#include <asm/cpu.h>
5
6#include "mce_amd.h"
7
8static struct amd_decoder_ops *fam_ops;
9
10static u8 xec_mask = 0xf;
11
12static bool report_gart_errors;
13static void (*decode_dram_ecc)(int node_id, struct mce *m);
14
15void amd_report_gart_errors(bool v)
16{
17 report_gart_errors = v;
18}
19EXPORT_SYMBOL_GPL(amd_report_gart_errors);
20
21void amd_register_ecc_decoder(void (*f)(int, struct mce *))
22{
23 decode_dram_ecc = f;
24}
25EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
26
27void amd_unregister_ecc_decoder(void (*f)(int, struct mce *))
28{
29 if (decode_dram_ecc) {
30 WARN_ON(decode_dram_ecc != f);
31
32 decode_dram_ecc = NULL;
33 }
34}
35EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
36
37
38
39
40
41
42
43static const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
44
45
46static const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
47
48
49static const char * const rrrr_msgs[] = {
50 "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
51};
52
53
54const char * const pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
55EXPORT_SYMBOL_GPL(pp_msgs);
56
57
58static const char * const to_msgs[] = { "no timeout", "timed out" };
59
60
61static const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
62
63
64static const char * const uu_msgs[] = { "RESV", "RESV", "HWA", "RESV" };
65
66static const char * const f15h_mc1_mce_desc[] = {
67 "UC during a demand linefill from L2",
68 "Parity error during data load from IC",
69 "Parity error for IC valid bit",
70 "Main tag parity error",
71 "Parity error in prediction queue",
72 "PFB data/address parity error",
73 "Parity error in the branch status reg",
74 "PFB promotion address error",
75 "Tag error during probe/victimization",
76 "Parity error for IC probe tag valid bit",
77 "PFB non-cacheable bit parity error",
78 "PFB valid bit parity error",
79 "Microcode Patch Buffer",
80 "uop queue",
81 "insn buffer",
82 "predecode buffer",
83 "fetch address FIFO",
84 "dispatch uop queue"
85};
86
87static const char * const f15h_mc2_mce_desc[] = {
88 "Fill ECC error on data fills",
89 "Fill parity error on insn fills",
90 "Prefetcher request FIFO parity error",
91 "PRQ address parity error",
92 "PRQ data parity error",
93 "WCC Tag ECC error",
94 "WCC Data ECC error",
95 "WCB Data parity error",
96 "VB Data ECC or parity error",
97 "L2 Tag ECC error",
98 "Hard L2 Tag ECC error",
99 "Multiple hits on L2 tag",
100 "XAB parity error",
101 "PRB address parity error"
102};
103
104static const char * const mc4_mce_desc[] = {
105 "DRAM ECC error detected on the NB",
106 "CRC error detected on HT link",
107 "Link-defined sync error packets detected on HT link",
108 "HT Master abort",
109 "HT Target abort",
110 "Invalid GART PTE entry during GART table walk",
111 "Unsupported atomic RMW received from an IO link",
112 "Watchdog timeout due to lack of progress",
113 "DRAM ECC error detected on the NB",
114 "SVM DMA Exclusion Vector error",
115 "HT data error detected on link",
116 "Protocol error (link, L3, probe filter)",
117 "NB internal arrays parity error",
118 "DRAM addr/ctl signals parity error",
119 "IO link transmission error",
120 "L3 data cache ECC error",
121 "L3 cache tag error",
122 "L3 LRU parity bits error",
123 "ECC Error in the Probe Filter directory"
124};
125
126static const char * const mc5_mce_desc[] = {
127 "CPU Watchdog timer expire",
128 "Wakeup array dest tag",
129 "AG payload array",
130 "EX payload array",
131 "IDRF array",
132 "Retire dispatch queue",
133 "Mapper checkpoint array",
134 "Physical register file EX0 port",
135 "Physical register file EX1 port",
136 "Physical register file AG0 port",
137 "Physical register file AG1 port",
138 "Flag register file",
139 "DE error occurred",
140 "Retire status queue"
141};
142
143static const char * const mc6_mce_desc[] = {
144 "Hardware Assertion",
145 "Free List",
146 "Physical Register File",
147 "Retire Queue",
148 "Scheduler table",
149 "Status Register File",
150};
151
152
153static const char * const smca_ls_mce_desc[] = {
154 "Load queue parity",
155 "Store queue parity",
156 "Miss address buffer payload parity",
157 "L1 TLB parity",
158 "DC Tag error type 5",
159 "DC tag error type 6",
160 "DC tag error type 1",
161 "Internal error type 1",
162 "Internal error type 2",
163 "Sys Read data error thread 0",
164 "Sys read data error thread 1",
165 "DC tag error type 2",
166 "DC data error type 1 (poison consumption)",
167 "DC data error type 2",
168 "DC data error type 3",
169 "DC tag error type 4",
170 "L2 TLB parity",
171 "PDC parity error",
172 "DC tag error type 3",
173 "DC tag error type 5",
174 "L2 fill data error",
175};
176
177static const char * const smca_if_mce_desc[] = {
178 "microtag probe port parity error",
179 "IC microtag or full tag multi-hit error",
180 "IC full tag parity",
181 "IC data array parity",
182 "Decoupling queue phys addr parity error",
183 "L0 ITLB parity error",
184 "L1 ITLB parity error",
185 "L2 ITLB parity error",
186 "BPQ snoop parity on Thread 0",
187 "BPQ snoop parity on Thread 1",
188 "L1 BTB multi-match error",
189 "L2 BTB multi-match error",
190 "L2 Cache Response Poison error",
191 "System Read Data error",
192};
193
194static const char * const smca_l2_mce_desc[] = {
195 "L2M tag multi-way-hit error",
196 "L2M tag ECC error",
197 "L2M data ECC error",
198 "HW assert",
199};
200
201static const char * const smca_de_mce_desc[] = {
202 "uop cache tag parity error",
203 "uop cache data parity error",
204 "Insn buffer parity error",
205 "uop queue parity error",
206 "Insn dispatch queue parity error",
207 "Fetch address FIFO parity",
208 "Patch RAM data parity",
209 "Patch RAM sequencer parity",
210 "uop buffer parity"
211};
212
213static const char * const smca_ex_mce_desc[] = {
214 "Watchdog timeout error",
215 "Phy register file parity",
216 "Flag register file parity",
217 "Immediate displacement register file parity",
218 "Address generator payload parity",
219 "EX payload parity",
220 "Checkpoint queue parity",
221 "Retire dispatch queue parity",
222 "Retire status queue parity error",
223 "Scheduling queue parity error",
224 "Branch buffer queue parity error",
225 "Hardware Assertion error",
226};
227
228static const char * const smca_fp_mce_desc[] = {
229 "Physical register file parity",
230 "Freelist parity error",
231 "Schedule queue parity",
232 "NSQ parity error",
233 "Retire queue parity",
234 "Status register file parity",
235 "Hardware assertion",
236};
237
238static const char * const smca_l3_mce_desc[] = {
239 "Shadow tag macro ECC error",
240 "Shadow tag macro multi-way-hit error",
241 "L3M tag ECC error",
242 "L3M tag multi-way-hit error",
243 "L3M data ECC error",
244 "XI parity, L3 fill done channel error",
245 "L3 victim queue parity",
246 "L3 HW assert",
247};
248
249static const char * const smca_cs_mce_desc[] = {
250 "Illegal request from transport layer",
251 "Address violation",
252 "Security violation",
253 "Illegal response from transport layer",
254 "Unexpected response",
255 "Parity error on incoming request or probe response data",
256 "Parity error on incoming read response data",
257 "Atomic request parity",
258 "ECC error on probe filter access",
259};
260
261static const char * const smca_cs2_mce_desc[] = {
262 "Illegal Request",
263 "Address Violation",
264 "Security Violation",
265 "Illegal Response",
266 "Unexpected Response",
267 "Request or Probe Parity Error",
268 "Read Response Parity Error",
269 "Atomic Request Parity Error",
270 "SDP read response had no match in the CS queue",
271 "Probe Filter Protocol Error",
272 "Probe Filter ECC Error",
273 "SDP read response had an unexpected RETRY error",
274 "Counter overflow error",
275 "Counter underflow error",
276};
277
278static const char * const smca_pie_mce_desc[] = {
279 "HW assert",
280 "Internal PIE register security violation",
281 "Error on GMI link",
282 "Poison data written to internal PIE register",
283 "A deferred error was detected in the DF"
284};
285
286static const char * const smca_umc_mce_desc[] = {
287 "DRAM ECC error",
288 "Data poison error on DRAM",
289 "SDP parity error",
290 "Advanced peripheral bus error",
291 "Command/address parity error",
292 "Write data CRC error",
293 "DCQ SRAM ECC error",
294 "AES SRAM ECC error",
295};
296
297static const char * const smca_pb_mce_desc[] = {
298 "Parameter Block RAM ECC error",
299};
300
301static const char * const smca_psp_mce_desc[] = {
302 "PSP RAM ECC or parity error",
303};
304
305static const char * const smca_psp2_mce_desc[] = {
306 "High SRAM ECC or parity error",
307 "Low SRAM ECC or parity error",
308 "Instruction Cache Bank 0 ECC or parity error",
309 "Instruction Cache Bank 1 ECC or parity error",
310 "Instruction Tag Ram 0 parity error",
311 "Instruction Tag Ram 1 parity error",
312 "Data Cache Bank 0 ECC or parity error",
313 "Data Cache Bank 1 ECC or parity error",
314 "Data Cache Bank 2 ECC or parity error",
315 "Data Cache Bank 3 ECC or parity error",
316 "Data Tag Bank 0 parity error",
317 "Data Tag Bank 1 parity error",
318 "Data Tag Bank 2 parity error",
319 "Data Tag Bank 3 parity error",
320 "Dirty Data Ram parity error",
321 "TLB Bank 0 parity error",
322 "TLB Bank 1 parity error",
323 "System Hub Read Buffer ECC or parity error",
324};
325
326static const char * const smca_smu_mce_desc[] = {
327 "SMU RAM ECC or parity error",
328};
329
330static const char * const smca_smu2_mce_desc[] = {
331 "High SRAM ECC or parity error",
332 "Low SRAM ECC or parity error",
333 "Data Cache Bank A ECC or parity error",
334 "Data Cache Bank B ECC or parity error",
335 "Data Tag Cache Bank A ECC or parity error",
336 "Data Tag Cache Bank B ECC or parity error",
337 "Instruction Cache Bank A ECC or parity error",
338 "Instruction Cache Bank B ECC or parity error",
339 "Instruction Tag Cache Bank A ECC or parity error",
340 "Instruction Tag Cache Bank B ECC or parity error",
341 "System Hub Read Buffer ECC or parity error",
342};
343
344static const char * const smca_mp5_mce_desc[] = {
345 "High SRAM ECC or parity error",
346 "Low SRAM ECC or parity error",
347 "Data Cache Bank A ECC or parity error",
348 "Data Cache Bank B ECC or parity error",
349 "Data Tag Cache Bank A ECC or parity error",
350 "Data Tag Cache Bank B ECC or parity error",
351 "Instruction Cache Bank A ECC or parity error",
352 "Instruction Cache Bank B ECC or parity error",
353 "Instruction Tag Cache Bank A ECC or parity error",
354 "Instruction Tag Cache Bank B ECC or parity error",
355};
356
357static const char * const smca_nbio_mce_desc[] = {
358 "ECC or Parity error",
359 "PCIE error",
360 "SDP ErrEvent error",
361 "SDP Egress Poison Error",
362 "IOHC Internal Poison Error",
363};
364
365static const char * const smca_pcie_mce_desc[] = {
366 "CCIX PER Message logging",
367 "CCIX Read Response with Status: Non-Data Error",
368 "CCIX Write Response with Status: Non-Data Error",
369 "CCIX Read Response with Status: Data Error",
370 "CCIX Non-okay write response with data error",
371};
372
373struct smca_mce_desc {
374 const char * const *descs;
375 unsigned int num_descs;
376};
377
378static struct smca_mce_desc smca_mce_descs[] = {
379 [SMCA_LS] = { smca_ls_mce_desc, ARRAY_SIZE(smca_ls_mce_desc) },
380 [SMCA_IF] = { smca_if_mce_desc, ARRAY_SIZE(smca_if_mce_desc) },
381 [SMCA_L2_CACHE] = { smca_l2_mce_desc, ARRAY_SIZE(smca_l2_mce_desc) },
382 [SMCA_DE] = { smca_de_mce_desc, ARRAY_SIZE(smca_de_mce_desc) },
383 [SMCA_EX] = { smca_ex_mce_desc, ARRAY_SIZE(smca_ex_mce_desc) },
384 [SMCA_FP] = { smca_fp_mce_desc, ARRAY_SIZE(smca_fp_mce_desc) },
385 [SMCA_L3_CACHE] = { smca_l3_mce_desc, ARRAY_SIZE(smca_l3_mce_desc) },
386 [SMCA_CS] = { smca_cs_mce_desc, ARRAY_SIZE(smca_cs_mce_desc) },
387 [SMCA_CS_V2] = { smca_cs2_mce_desc, ARRAY_SIZE(smca_cs2_mce_desc) },
388 [SMCA_PIE] = { smca_pie_mce_desc, ARRAY_SIZE(smca_pie_mce_desc) },
389 [SMCA_UMC] = { smca_umc_mce_desc, ARRAY_SIZE(smca_umc_mce_desc) },
390 [SMCA_PB] = { smca_pb_mce_desc, ARRAY_SIZE(smca_pb_mce_desc) },
391 [SMCA_PSP] = { smca_psp_mce_desc, ARRAY_SIZE(smca_psp_mce_desc) },
392 [SMCA_PSP_V2] = { smca_psp2_mce_desc, ARRAY_SIZE(smca_psp2_mce_desc) },
393 [SMCA_SMU] = { smca_smu_mce_desc, ARRAY_SIZE(smca_smu_mce_desc) },
394 [SMCA_SMU_V2] = { smca_smu2_mce_desc, ARRAY_SIZE(smca_smu2_mce_desc) },
395 [SMCA_MP5] = { smca_mp5_mce_desc, ARRAY_SIZE(smca_mp5_mce_desc) },
396 [SMCA_NBIO] = { smca_nbio_mce_desc, ARRAY_SIZE(smca_nbio_mce_desc) },
397 [SMCA_PCIE] = { smca_pcie_mce_desc, ARRAY_SIZE(smca_pcie_mce_desc) },
398};
399
400static bool f12h_mc0_mce(u16 ec, u8 xec)
401{
402 bool ret = false;
403
404 if (MEM_ERROR(ec)) {
405 u8 ll = LL(ec);
406 ret = true;
407
408 if (ll == LL_L2)
409 pr_cont("during L1 linefill from L2.\n");
410 else if (ll == LL_L1)
411 pr_cont("Data/Tag %s error.\n", R4_MSG(ec));
412 else
413 ret = false;
414 }
415 return ret;
416}
417
418static bool f10h_mc0_mce(u16 ec, u8 xec)
419{
420 if (R4(ec) == R4_GEN && LL(ec) == LL_L1) {
421 pr_cont("during data scrub.\n");
422 return true;
423 }
424 return f12h_mc0_mce(ec, xec);
425}
426
427static bool k8_mc0_mce(u16 ec, u8 xec)
428{
429 if (BUS_ERROR(ec)) {
430 pr_cont("during system linefill.\n");
431 return true;
432 }
433
434 return f10h_mc0_mce(ec, xec);
435}
436
437static bool cat_mc0_mce(u16 ec, u8 xec)
438{
439 u8 r4 = R4(ec);
440 bool ret = true;
441
442 if (MEM_ERROR(ec)) {
443
444 if (TT(ec) != TT_DATA || LL(ec) != LL_L1)
445 return false;
446
447 switch (r4) {
448 case R4_DRD:
449 case R4_DWR:
450 pr_cont("Data/Tag parity error due to %s.\n",
451 (r4 == R4_DRD ? "load/hw prf" : "store"));
452 break;
453 case R4_EVICT:
454 pr_cont("Copyback parity error on a tag miss.\n");
455 break;
456 case R4_SNOOP:
457 pr_cont("Tag parity error during snoop.\n");
458 break;
459 default:
460 ret = false;
461 }
462 } else if (BUS_ERROR(ec)) {
463
464 if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG)
465 return false;
466
467 pr_cont("System read data error on a ");
468
469 switch (r4) {
470 case R4_RD:
471 pr_cont("TLB reload.\n");
472 break;
473 case R4_DWR:
474 pr_cont("store.\n");
475 break;
476 case R4_DRD:
477 pr_cont("load.\n");
478 break;
479 default:
480 ret = false;
481 }
482 } else {
483 ret = false;
484 }
485
486 return ret;
487}
488
489static bool f15h_mc0_mce(u16 ec, u8 xec)
490{
491 bool ret = true;
492
493 if (MEM_ERROR(ec)) {
494
495 switch (xec) {
496 case 0x0:
497 pr_cont("Data Array access error.\n");
498 break;
499
500 case 0x1:
501 pr_cont("UC error during a linefill from L2/NB.\n");
502 break;
503
504 case 0x2:
505 case 0x11:
506 pr_cont("STQ access error.\n");
507 break;
508
509 case 0x3:
510 pr_cont("SCB access error.\n");
511 break;
512
513 case 0x10:
514 pr_cont("Tag error.\n");
515 break;
516
517 case 0x12:
518 pr_cont("LDQ access error.\n");
519 break;
520
521 default:
522 ret = false;
523 }
524 } else if (BUS_ERROR(ec)) {
525
526 if (!xec)
527 pr_cont("System Read Data Error.\n");
528 else
529 pr_cont(" Internal error condition type %d.\n", xec);
530 } else if (INT_ERROR(ec)) {
531 if (xec <= 0x1f)
532 pr_cont("Hardware Assert.\n");
533 else
534 ret = false;
535
536 } else
537 ret = false;
538
539 return ret;
540}
541
542static void decode_mc0_mce(struct mce *m)
543{
544 u16 ec = EC(m->status);
545 u8 xec = XEC(m->status, xec_mask);
546
547 pr_emerg(HW_ERR "MC0 Error: ");
548
549
550 if (TLB_ERROR(ec)) {
551 if (TT(ec) == TT_DATA) {
552 pr_cont("%s TLB %s.\n", LL_MSG(ec),
553 ((xec == 2) ? "locked miss"
554 : (xec ? "multimatch" : "parity")));
555 return;
556 }
557 } else if (fam_ops->mc0_mce(ec, xec))
558 ;
559 else
560 pr_emerg(HW_ERR "Corrupted MC0 MCE info?\n");
561}
562
563static bool k8_mc1_mce(u16 ec, u8 xec)
564{
565 u8 ll = LL(ec);
566 bool ret = true;
567
568 if (!MEM_ERROR(ec))
569 return false;
570
571 if (ll == 0x2)
572 pr_cont("during a linefill from L2.\n");
573 else if (ll == 0x1) {
574 switch (R4(ec)) {
575 case R4_IRD:
576 pr_cont("Parity error during data load.\n");
577 break;
578
579 case R4_EVICT:
580 pr_cont("Copyback Parity/Victim error.\n");
581 break;
582
583 case R4_SNOOP:
584 pr_cont("Tag Snoop error.\n");
585 break;
586
587 default:
588 ret = false;
589 break;
590 }
591 } else
592 ret = false;
593
594 return ret;
595}
596
597static bool cat_mc1_mce(u16 ec, u8 xec)
598{
599 u8 r4 = R4(ec);
600 bool ret = true;
601
602 if (!MEM_ERROR(ec))
603 return false;
604
605 if (TT(ec) != TT_INSTR)
606 return false;
607
608 if (r4 == R4_IRD)
609 pr_cont("Data/tag array parity error for a tag hit.\n");
610 else if (r4 == R4_SNOOP)
611 pr_cont("Tag error during snoop/victimization.\n");
612 else if (xec == 0x0)
613 pr_cont("Tag parity error from victim castout.\n");
614 else if (xec == 0x2)
615 pr_cont("Microcode patch RAM parity error.\n");
616 else
617 ret = false;
618
619 return ret;
620}
621
622static bool f15h_mc1_mce(u16 ec, u8 xec)
623{
624 bool ret = true;
625
626 if (!MEM_ERROR(ec))
627 return false;
628
629 switch (xec) {
630 case 0x0 ... 0xa:
631 pr_cont("%s.\n", f15h_mc1_mce_desc[xec]);
632 break;
633
634 case 0xd:
635 pr_cont("%s.\n", f15h_mc1_mce_desc[xec-2]);
636 break;
637
638 case 0x10:
639 pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]);
640 break;
641
642 case 0x11 ... 0x15:
643 pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]);
644 break;
645
646 default:
647 ret = false;
648 }
649 return ret;
650}
651
652static void decode_mc1_mce(struct mce *m)
653{
654 u16 ec = EC(m->status);
655 u8 xec = XEC(m->status, xec_mask);
656
657 pr_emerg(HW_ERR "MC1 Error: ");
658
659 if (TLB_ERROR(ec))
660 pr_cont("%s TLB %s.\n", LL_MSG(ec),
661 (xec ? "multimatch" : "parity error"));
662 else if (BUS_ERROR(ec)) {
663 bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));
664
665 pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read"));
666 } else if (INT_ERROR(ec)) {
667 if (xec <= 0x3f)
668 pr_cont("Hardware Assert.\n");
669 else
670 goto wrong_mc1_mce;
671 } else if (fam_ops->mc1_mce(ec, xec))
672 ;
673 else
674 goto wrong_mc1_mce;
675
676 return;
677
678wrong_mc1_mce:
679 pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n");
680}
681
682static bool k8_mc2_mce(u16 ec, u8 xec)
683{
684 bool ret = true;
685
686 if (xec == 0x1)
687 pr_cont(" in the write data buffers.\n");
688 else if (xec == 0x3)
689 pr_cont(" in the victim data buffers.\n");
690 else if (xec == 0x2 && MEM_ERROR(ec))
691 pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec));
692 else if (xec == 0x0) {
693 if (TLB_ERROR(ec))
694 pr_cont("%s error in a Page Descriptor Cache or Guest TLB.\n",
695 TT_MSG(ec));
696 else if (BUS_ERROR(ec))
697 pr_cont(": %s/ECC error in data read from NB: %s.\n",
698 R4_MSG(ec), PP_MSG(ec));
699 else if (MEM_ERROR(ec)) {
700 u8 r4 = R4(ec);
701
702 if (r4 >= 0x7)
703 pr_cont(": %s error during data copyback.\n",
704 R4_MSG(ec));
705 else if (r4 <= 0x1)
706 pr_cont(": %s parity/ECC error during data "
707 "access from L2.\n", R4_MSG(ec));
708 else
709 ret = false;
710 } else
711 ret = false;
712 } else
713 ret = false;
714
715 return ret;
716}
717
718static bool f15h_mc2_mce(u16 ec, u8 xec)
719{
720 bool ret = true;
721
722 if (TLB_ERROR(ec)) {
723 if (xec == 0x0)
724 pr_cont("Data parity TLB read error.\n");
725 else if (xec == 0x1)
726 pr_cont("Poison data provided for TLB fill.\n");
727 else
728 ret = false;
729 } else if (BUS_ERROR(ec)) {
730 if (xec > 2)
731 ret = false;
732
733 pr_cont("Error during attempted NB data read.\n");
734 } else if (MEM_ERROR(ec)) {
735 switch (xec) {
736 case 0x4 ... 0xc:
737 pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x4]);
738 break;
739
740 case 0x10 ... 0x14:
741 pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x7]);
742 break;
743
744 default:
745 ret = false;
746 }
747 } else if (INT_ERROR(ec)) {
748 if (xec <= 0x3f)
749 pr_cont("Hardware Assert.\n");
750 else
751 ret = false;
752 }
753
754 return ret;
755}
756
757static bool f16h_mc2_mce(u16 ec, u8 xec)
758{
759 u8 r4 = R4(ec);
760
761 if (!MEM_ERROR(ec))
762 return false;
763
764 switch (xec) {
765 case 0x04 ... 0x05:
766 pr_cont("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O');
767 break;
768
769 case 0x09 ... 0x0b:
770 case 0x0d ... 0x0f:
771 pr_cont("ECC error in L2 tag (%s).\n",
772 ((r4 == R4_GEN) ? "BankReq" :
773 ((r4 == R4_SNOOP) ? "Prb" : "Fill")));
774 break;
775
776 case 0x10 ... 0x19:
777 case 0x1b:
778 pr_cont("ECC error in L2 data array (%s).\n",
779 (((r4 == R4_RD) && !(xec & 0x3)) ? "Hit" :
780 ((r4 == R4_GEN) ? "Attr" :
781 ((r4 == R4_EVICT) ? "Vict" : "Fill"))));
782 break;
783
784 case 0x1c ... 0x1d:
785 case 0x1f:
786 pr_cont("Parity error in L2 attribute bits (%s).\n",
787 ((r4 == R4_RD) ? "Hit" :
788 ((r4 == R4_GEN) ? "Attr" : "Fill")));
789 break;
790
791 default:
792 return false;
793 }
794
795 return true;
796}
797
798static void decode_mc2_mce(struct mce *m)
799{
800 u16 ec = EC(m->status);
801 u8 xec = XEC(m->status, xec_mask);
802
803 pr_emerg(HW_ERR "MC2 Error: ");
804
805 if (!fam_ops->mc2_mce(ec, xec))
806 pr_cont(HW_ERR "Corrupted MC2 MCE info?\n");
807}
808
809static void decode_mc3_mce(struct mce *m)
810{
811 u16 ec = EC(m->status);
812 u8 xec = XEC(m->status, xec_mask);
813
814 if (boot_cpu_data.x86 >= 0x14) {
815 pr_emerg("You shouldn't be seeing MC3 MCE on this cpu family,"
816 " please report on LKML.\n");
817 return;
818 }
819
820 pr_emerg(HW_ERR "MC3 Error");
821
822 if (xec == 0x0) {
823 u8 r4 = R4(ec);
824
825 if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR))
826 goto wrong_mc3_mce;
827
828 pr_cont(" during %s.\n", R4_MSG(ec));
829 } else
830 goto wrong_mc3_mce;
831
832 return;
833
834 wrong_mc3_mce:
835 pr_emerg(HW_ERR "Corrupted MC3 MCE info?\n");
836}
837
838static void decode_mc4_mce(struct mce *m)
839{
840 unsigned int fam = x86_family(m->cpuid);
841 int node_id = amd_get_nb_id(m->extcpu);
842 u16 ec = EC(m->status);
843 u8 xec = XEC(m->status, 0x1f);
844 u8 offset = 0;
845
846 pr_emerg(HW_ERR "MC4 Error (node %d): ", node_id);
847
848 switch (xec) {
849 case 0x0 ... 0xe:
850
851
852 if (xec == 0x0 || xec == 0x8) {
853
854 if (fam == 0x11)
855 goto wrong_mc4_mce;
856
857 pr_cont("%s.\n", mc4_mce_desc[xec]);
858
859 if (decode_dram_ecc)
860 decode_dram_ecc(node_id, m);
861 return;
862 }
863 break;
864
865 case 0xf:
866 if (TLB_ERROR(ec))
867 pr_cont("GART Table Walk data error.\n");
868 else if (BUS_ERROR(ec))
869 pr_cont("DMA Exclusion Vector Table Walk error.\n");
870 else
871 goto wrong_mc4_mce;
872 return;
873
874 case 0x19:
875 if (fam == 0x15 || fam == 0x16)
876 pr_cont("Compute Unit Data Error.\n");
877 else
878 goto wrong_mc4_mce;
879 return;
880
881 case 0x1c ... 0x1f:
882 offset = 13;
883 break;
884
885 default:
886 goto wrong_mc4_mce;
887 }
888
889 pr_cont("%s.\n", mc4_mce_desc[xec - offset]);
890 return;
891
892 wrong_mc4_mce:
893 pr_emerg(HW_ERR "Corrupted MC4 MCE info?\n");
894}
895
896static void decode_mc5_mce(struct mce *m)
897{
898 unsigned int fam = x86_family(m->cpuid);
899 u16 ec = EC(m->status);
900 u8 xec = XEC(m->status, xec_mask);
901
902 if (fam == 0xf || fam == 0x11)
903 goto wrong_mc5_mce;
904
905 pr_emerg(HW_ERR "MC5 Error: ");
906
907 if (INT_ERROR(ec)) {
908 if (xec <= 0x1f) {
909 pr_cont("Hardware Assert.\n");
910 return;
911 } else
912 goto wrong_mc5_mce;
913 }
914
915 if (xec == 0x0 || xec == 0xc)
916 pr_cont("%s.\n", mc5_mce_desc[xec]);
917 else if (xec <= 0xd)
918 pr_cont("%s parity error.\n", mc5_mce_desc[xec]);
919 else
920 goto wrong_mc5_mce;
921
922 return;
923
924 wrong_mc5_mce:
925 pr_emerg(HW_ERR "Corrupted MC5 MCE info?\n");
926}
927
928static void decode_mc6_mce(struct mce *m)
929{
930 u8 xec = XEC(m->status, xec_mask);
931
932 pr_emerg(HW_ERR "MC6 Error: ");
933
934 if (xec > 0x5)
935 goto wrong_mc6_mce;
936
937 pr_cont("%s parity error.\n", mc6_mce_desc[xec]);
938 return;
939
940 wrong_mc6_mce:
941 pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n");
942}
943
944
945static void decode_smca_error(struct mce *m)
946{
947 struct smca_hwid *hwid;
948 enum smca_bank_types bank_type;
949 const char *ip_name;
950 u8 xec = XEC(m->status, xec_mask);
951
952 if (m->bank >= ARRAY_SIZE(smca_banks))
953 return;
954
955 hwid = smca_banks[m->bank].hwid;
956 if (!hwid)
957 return;
958
959 bank_type = hwid->bank_type;
960
961 if (bank_type == SMCA_RESERVED) {
962 pr_emerg(HW_ERR "Bank %d is reserved.\n", m->bank);
963 return;
964 }
965
966 ip_name = smca_get_long_name(bank_type);
967
968 pr_emerg(HW_ERR "%s Extended Error Code: %d\n", ip_name, xec);
969
970
971 if (xec < smca_mce_descs[bank_type].num_descs &&
972 (hwid->xec_bitmap & BIT_ULL(xec))) {
973 pr_emerg(HW_ERR "%s Error: ", ip_name);
974 pr_cont("%s.\n", smca_mce_descs[bank_type].descs[xec]);
975 }
976
977 if (bank_type == SMCA_UMC && xec == 0 && decode_dram_ecc)
978 decode_dram_ecc(cpu_to_node(m->extcpu), m);
979}
980
981static inline void amd_decode_err_code(u16 ec)
982{
983 if (INT_ERROR(ec)) {
984 pr_emerg(HW_ERR "internal: %s\n", UU_MSG(ec));
985 return;
986 }
987
988 pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec));
989
990 if (BUS_ERROR(ec))
991 pr_cont(", mem/io: %s", II_MSG(ec));
992 else
993 pr_cont(", tx: %s", TT_MSG(ec));
994
995 if (MEM_ERROR(ec) || BUS_ERROR(ec)) {
996 pr_cont(", mem-tx: %s", R4_MSG(ec));
997
998 if (BUS_ERROR(ec))
999 pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec));
1000 }
1001
1002 pr_cont("\n");
1003}
1004
1005
1006
1007
1008static bool amd_filter_mce(struct mce *m)
1009{
1010
1011
1012
1013 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5 && !report_gart_errors)
1014 return true;
1015
1016 return false;
1017}
1018
1019static const char *decode_error_status(struct mce *m)
1020{
1021 if (m->status & MCI_STATUS_UC) {
1022 if (m->status & MCI_STATUS_PCC)
1023 return "System Fatal error.";
1024 if (m->mcgstatus & MCG_STATUS_RIPV)
1025 return "Uncorrected, software restartable error.";
1026 return "Uncorrected, software containable error.";
1027 }
1028
1029 if (m->status & MCI_STATUS_DEFERRED)
1030 return "Deferred error, no action required.";
1031
1032 return "Corrected error, no action required.";
1033}
1034
1035static int
1036amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
1037{
1038 struct mce *m = (struct mce *)data;
1039 unsigned int fam = x86_family(m->cpuid);
1040 int ecc;
1041
1042 if (amd_filter_mce(m))
1043 return NOTIFY_STOP;
1044
1045 pr_emerg(HW_ERR "%s\n", decode_error_status(m));
1046
1047 pr_emerg(HW_ERR "CPU:%d (%x:%x:%x) MC%d_STATUS[%s|%s|%s|%s|%s",
1048 m->extcpu,
1049 fam, x86_model(m->cpuid), x86_stepping(m->cpuid),
1050 m->bank,
1051 ((m->status & MCI_STATUS_OVER) ? "Over" : "-"),
1052 ((m->status & MCI_STATUS_UC) ? "UE" :
1053 (m->status & MCI_STATUS_DEFERRED) ? "-" : "CE"),
1054 ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"),
1055 ((m->status & MCI_STATUS_PCC) ? "PCC" : "-"),
1056 ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"));
1057
1058 if (fam >= 0x15) {
1059 pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-"));
1060
1061
1062 if (fam != 0x15 || m->bank != 4)
1063 pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-"));
1064 }
1065
1066 if (boot_cpu_has(X86_FEATURE_SMCA)) {
1067 u32 low, high;
1068 u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);
1069
1070 pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-"));
1071
1072 if (!rdmsr_safe(addr, &low, &high) &&
1073 (low & MCI_CONFIG_MCAX))
1074 pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-"));
1075 }
1076
1077
1078 ecc = (m->status >> 45) & 0x3;
1079 if (ecc)
1080 pr_cont("|%sECC", ((ecc == 2) ? "C" : "U"));
1081
1082 pr_cont("]: 0x%016llx\n", m->status);
1083
1084 if (m->status & MCI_STATUS_ADDRV)
1085 pr_emerg(HW_ERR "Error Addr: 0x%016llx\n", m->addr);
1086
1087 if (boot_cpu_has(X86_FEATURE_SMCA)) {
1088 pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid);
1089
1090 if (m->status & MCI_STATUS_SYNDV)
1091 pr_cont(", Syndrome: 0x%016llx", m->synd);
1092
1093 pr_cont("\n");
1094
1095 decode_smca_error(m);
1096 goto err_code;
1097 }
1098
1099 if (m->tsc)
1100 pr_emerg(HW_ERR "TSC: %llu\n", m->tsc);
1101
1102 if (!fam_ops)
1103 goto err_code;
1104
1105 switch (m->bank) {
1106 case 0:
1107 decode_mc0_mce(m);
1108 break;
1109
1110 case 1:
1111 decode_mc1_mce(m);
1112 break;
1113
1114 case 2:
1115 decode_mc2_mce(m);
1116 break;
1117
1118 case 3:
1119 decode_mc3_mce(m);
1120 break;
1121
1122 case 4:
1123 decode_mc4_mce(m);
1124 break;
1125
1126 case 5:
1127 decode_mc5_mce(m);
1128 break;
1129
1130 case 6:
1131 decode_mc6_mce(m);
1132 break;
1133
1134 default:
1135 break;
1136 }
1137
1138 err_code:
1139 amd_decode_err_code(m->status & 0xffff);
1140
1141 return NOTIFY_STOP;
1142}
1143
1144static struct notifier_block amd_mce_dec_nb = {
1145 .notifier_call = amd_decode_mce,
1146 .priority = MCE_PRIO_EDAC,
1147};
1148
1149static int __init mce_amd_init(void)
1150{
1151 struct cpuinfo_x86 *c = &boot_cpu_data;
1152
1153 if (c->x86_vendor != X86_VENDOR_AMD)
1154 return -ENODEV;
1155
1156 fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
1157 if (!fam_ops)
1158 return -ENOMEM;
1159
1160 switch (c->x86) {
1161 case 0xf:
1162 fam_ops->mc0_mce = k8_mc0_mce;
1163 fam_ops->mc1_mce = k8_mc1_mce;
1164 fam_ops->mc2_mce = k8_mc2_mce;
1165 break;
1166
1167 case 0x10:
1168 fam_ops->mc0_mce = f10h_mc0_mce;
1169 fam_ops->mc1_mce = k8_mc1_mce;
1170 fam_ops->mc2_mce = k8_mc2_mce;
1171 break;
1172
1173 case 0x11:
1174 fam_ops->mc0_mce = k8_mc0_mce;
1175 fam_ops->mc1_mce = k8_mc1_mce;
1176 fam_ops->mc2_mce = k8_mc2_mce;
1177 break;
1178
1179 case 0x12:
1180 fam_ops->mc0_mce = f12h_mc0_mce;
1181 fam_ops->mc1_mce = k8_mc1_mce;
1182 fam_ops->mc2_mce = k8_mc2_mce;
1183 break;
1184
1185 case 0x14:
1186 fam_ops->mc0_mce = cat_mc0_mce;
1187 fam_ops->mc1_mce = cat_mc1_mce;
1188 fam_ops->mc2_mce = k8_mc2_mce;
1189 break;
1190
1191 case 0x15:
1192 xec_mask = c->x86_model == 0x60 ? 0x3f : 0x1f;
1193
1194 fam_ops->mc0_mce = f15h_mc0_mce;
1195 fam_ops->mc1_mce = f15h_mc1_mce;
1196 fam_ops->mc2_mce = f15h_mc2_mce;
1197 break;
1198
1199 case 0x16:
1200 xec_mask = 0x1f;
1201 fam_ops->mc0_mce = cat_mc0_mce;
1202 fam_ops->mc1_mce = cat_mc1_mce;
1203 fam_ops->mc2_mce = f16h_mc2_mce;
1204 break;
1205
1206 case 0x17:
1207 xec_mask = 0x3f;
1208 if (!boot_cpu_has(X86_FEATURE_SMCA)) {
1209 printk(KERN_WARNING "Decoding supported only on Scalable MCA processors.\n");
1210 goto err_out;
1211 }
1212 break;
1213
1214 default:
1215 printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86);
1216 goto err_out;
1217 }
1218
1219 pr_info("MCE: In-kernel MCE decoding enabled.\n");
1220
1221 mce_register_decode_chain(&amd_mce_dec_nb);
1222
1223 return 0;
1224
1225err_out:
1226 kfree(fam_ops);
1227 fam_ops = NULL;
1228 return -EINVAL;
1229}
1230early_initcall(mce_amd_init);
1231
1232#ifdef MODULE
1233static void __exit mce_amd_exit(void)
1234{
1235 mce_unregister_decode_chain(&amd_mce_dec_nb);
1236 kfree(fam_ops);
1237}
1238
1239MODULE_DESCRIPTION("AMD MCE decoder");
1240MODULE_ALIAS("edac-mce-amd");
1241MODULE_LICENSE("GPL");
1242module_exit(mce_amd_exit);
1243#endif
1244
