LXR linux/drivers/gpu/drm/amd/display/dc/inc/hw

   1/*
   2 * Copyright 2015 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#ifndef __DC_HW_SEQUENCER_H__
  27#define __DC_HW_SEQUENCER_H__
  28#include "dc_types.h"
  29#include "clock_source.h"
  30#include "inc/hw/timing_generator.h"
  31#include "inc/hw/opp.h"
  32#include "inc/hw/link_encoder.h"
  33#include "core_status.h"
  34
  35enum pipe_gating_control {
  36        PIPE_GATING_CONTROL_DISABLE = 0,
  37        PIPE_GATING_CONTROL_ENABLE,
  38        PIPE_GATING_CONTROL_INIT
  39};
  40
  41enum vline_select {
  42        VLINE0,
  43        VLINE1
  44};
  45
  46struct dce_hwseq_wa {
  47        bool blnd_crtc_trigger;
  48        bool DEGVIDCN10_253;
  49        bool false_optc_underflow;
  50        bool DEGVIDCN10_254;
  51};
  52
  53struct hwseq_wa_state {
  54        bool DEGVIDCN10_253_applied;
  55};
  56
  57struct dce_hwseq {
  58        struct dc_context *ctx;
  59        const struct dce_hwseq_registers *regs;
  60        const struct dce_hwseq_shift *shifts;
  61        const struct dce_hwseq_mask *masks;
  62        struct dce_hwseq_wa wa;
  63        struct hwseq_wa_state wa_state;
  64};
  65
  66struct pipe_ctx;
  67struct dc_state;
  68struct dchub_init_data;
  69struct dc_static_screen_events;
  70struct resource_pool;
  71struct resource_context;
  72struct stream_resource;
  73
  74struct hw_sequencer_funcs {
  75
  76        void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
  77
  78        void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
  79
  80        void (*init_hw)(struct dc *dc);
  81
  82        void (*init_pipes)(struct dc *dc, struct dc_state *context);
  83
  84        enum dc_status (*apply_ctx_to_hw)(
  85                        struct dc *dc, struct dc_state *context);
  86
  87        void (*reset_hw_ctx_wrap)(
  88                        struct dc *dc, struct dc_state *context);
  89
  90        void (*apply_ctx_for_surface)(
  91                        struct dc *dc,
  92                        const struct dc_stream_state *stream,
  93                        int num_planes,
  94                        struct dc_state *context);
  95
  96        void (*program_gamut_remap)(
  97                        struct pipe_ctx *pipe_ctx);
  98
  99        void (*program_output_csc)(struct dc *dc,
 100                        struct pipe_ctx *pipe_ctx,
 101                        enum dc_color_space colorspace,
 102                        uint16_t *matrix,
 103                        int opp_id);
 104
 105        void (*update_plane_addr)(
 106                const struct dc *dc,
 107                struct pipe_ctx *pipe_ctx);
 108
 109        void (*plane_atomic_disconnect)(
 110                struct dc *dc,
 111                struct pipe_ctx *pipe_ctx);
 112
 113        void (*update_dchub)(
 114                struct dce_hwseq *hws,
 115                struct dchub_init_data *dh_data);
 116
 117        void (*update_mpcc)(
 118                struct dc *dc,
 119                struct pipe_ctx *pipe_ctx);
 120
 121        void (*update_pending_status)(
 122                        struct pipe_ctx *pipe_ctx);
 123
 124        bool (*set_input_transfer_func)(
 125                                struct pipe_ctx *pipe_ctx,
 126                                const struct dc_plane_state *plane_state);
 127
 128        bool (*set_output_transfer_func)(
 129                                struct pipe_ctx *pipe_ctx,
 130                                const struct dc_stream_state *stream);
 131
 132        void (*power_down)(struct dc *dc);
 133
 134        void (*enable_accelerated_mode)(struct dc *dc, struct dc_state *context);
 135
 136        void (*enable_timing_synchronization)(
 137                        struct dc *dc,
 138                        int group_index,
 139                        int group_size,
 140                        struct pipe_ctx *grouped_pipes[]);
 141
 142        void (*enable_per_frame_crtc_position_reset)(
 143                        struct dc *dc,
 144                        int group_size,
 145                        struct pipe_ctx *grouped_pipes[]);
 146
 147        void (*enable_display_pipe_clock_gating)(
 148                                        struct dc_context *ctx,
 149                                        bool clock_gating);
 150
 151        bool (*enable_display_power_gating)(
 152                                        struct dc *dc,
 153                                        uint8_t controller_id,
 154                                        struct dc_bios *dcb,
 155                                        enum pipe_gating_control power_gating);
 156
 157        void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 158
 159        void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
 160
 161        void (*enable_stream)(struct pipe_ctx *pipe_ctx);
 162
 163        void (*disable_stream)(struct pipe_ctx *pipe_ctx,
 164                        int option);
 165
 166        void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
 167                        struct dc_link_settings *link_settings);
 168
 169        void (*blank_stream)(struct pipe_ctx *pipe_ctx);
 170
 171        void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);
 172
 173        void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx, int option);
 174
 175        void (*pipe_control_lock)(
 176                                struct dc *dc,
 177                                struct pipe_ctx *pipe,
 178                                bool lock);
 179        void (*blank_pixel_data)(
 180                        struct dc *dc,
 181                        struct pipe_ctx *pipe_ctx,
 182                        bool blank);
 183
 184        void (*prepare_bandwidth)(
 185                        struct dc *dc,
 186                        struct dc_state *context);
 187        void (*optimize_bandwidth)(
 188                        struct dc *dc,
 189                        struct dc_state *context);
 190
 191        void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
 192                        int vmin, int vmax);
 193
 194        void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
 195                        struct crtc_position *position);
 196
 197        void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
 198                        int num_pipes, const struct dc_static_screen_events *events);
 199
 200        enum dc_status (*enable_stream_timing)(
 201                        struct pipe_ctx *pipe_ctx,
 202                        struct dc_state *context,
 203                        struct dc *dc);
 204
 205        void (*setup_stereo)(
 206                        struct pipe_ctx *pipe_ctx,
 207                        struct dc *dc);
 208
 209        void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
 210
 211        void (*log_hw_state)(struct dc *dc,
 212                struct dc_log_buffer_ctx *log_ctx);
 213        void (*get_hw_state)(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask);
 214        void (*clear_status_bits)(struct dc *dc, unsigned int mask);
 215
 216        void (*wait_for_mpcc_disconnect)(struct dc *dc,
 217                        struct resource_pool *res_pool,
 218                        struct pipe_ctx *pipe_ctx);
 219
 220        void (*edp_power_control)(
 221                        struct dc_link *link,
 222                        bool enable);
 223        void (*edp_backlight_control)(
 224                        struct dc_link *link,
 225                        bool enable);
 226        void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
 227
 228        void (*set_cursor_position)(struct pipe_ctx *pipe);
 229        void (*set_cursor_attribute)(struct pipe_ctx *pipe);
 230        void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);
 231
 232        void (*setup_periodic_interrupt)(struct pipe_ctx *pipe_ctx, enum vline_select vline);
 233        void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx);
 234
 235};
 236
 237void color_space_to_black_color(
 238        const struct dc *dc,
 239        enum dc_color_space colorspace,
 240        struct tg_color *black_color);
 241
 242bool hwss_wait_for_blank_complete(
 243                struct timing_generator *tg);
 244
 245const uint16_t *find_color_matrix(
 246                enum dc_color_space color_space,
 247                uint32_t *array_size);
 248
 249#endif /* __DC_HW_SEQUENCER_H__ */
 250