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24#ifndef VEGA12_SMU9_DRIVER_IF_H
25#define VEGA12_SMU9_DRIVER_IF_H
26
27
28
29
30
31#define SMU9_DRIVER_IF_VERSION 0x10
32
33#define PPTABLE_V12_SMU_VERSION 1
34
35#define NUM_GFXCLK_DPM_LEVELS 16
36#define NUM_VCLK_DPM_LEVELS 8
37#define NUM_DCLK_DPM_LEVELS 8
38#define NUM_ECLK_DPM_LEVELS 8
39#define NUM_MP0CLK_DPM_LEVELS 2
40#define NUM_UCLK_DPM_LEVELS 4
41#define NUM_SOCCLK_DPM_LEVELS 8
42#define NUM_DCEFCLK_DPM_LEVELS 8
43#define NUM_DISPCLK_DPM_LEVELS 8
44#define NUM_PIXCLK_DPM_LEVELS 8
45#define NUM_PHYCLK_DPM_LEVELS 8
46#define NUM_LINK_LEVELS 2
47
48#define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
49#define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
50#define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
51#define MAX_ECLK_DPM_LEVEL (NUM_ECLK_DPM_LEVELS - 1)
52#define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
53#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
54#define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
55#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
56#define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
57#define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
58#define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
59#define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
60
61
62#define PPSMC_GeminiModeNone 0
63#define PPSMC_GeminiModeMaster 1
64#define PPSMC_GeminiModeSlave 2
65
66
67#define FEATURE_DPM_PREFETCHER_BIT 0
68#define FEATURE_DPM_GFXCLK_BIT 1
69#define FEATURE_DPM_UCLK_BIT 2
70#define FEATURE_DPM_SOCCLK_BIT 3
71#define FEATURE_DPM_UVD_BIT 4
72#define FEATURE_DPM_VCE_BIT 5
73#define FEATURE_ULV_BIT 6
74#define FEATURE_DPM_MP0CLK_BIT 7
75#define FEATURE_DPM_LINK_BIT 8
76#define FEATURE_DPM_DCEFCLK_BIT 9
77#define FEATURE_DS_GFXCLK_BIT 10
78#define FEATURE_DS_SOCCLK_BIT 11
79#define FEATURE_DS_LCLK_BIT 12
80#define FEATURE_PPT_BIT 13
81#define FEATURE_TDC_BIT 14
82#define FEATURE_THERMAL_BIT 15
83#define FEATURE_GFX_PER_CU_CG_BIT 16
84#define FEATURE_RM_BIT 17
85#define FEATURE_DS_DCEFCLK_BIT 18
86#define FEATURE_ACDC_BIT 19
87#define FEATURE_VR0HOT_BIT 20
88#define FEATURE_VR1HOT_BIT 21
89#define FEATURE_FW_CTF_BIT 22
90#define FEATURE_LED_DISPLAY_BIT 23
91#define FEATURE_FAN_CONTROL_BIT 24
92#define FEATURE_GFX_EDC_BIT 25
93#define FEATURE_GFXOFF_BIT 26
94#define FEATURE_CG_BIT 27
95#define FEATURE_ACG_BIT 28
96#define FEATURE_SPARE_29_BIT 29
97#define FEATURE_SPARE_30_BIT 30
98#define FEATURE_SPARE_31_BIT 31
99
100#define NUM_FEATURES 32
101
102#define FEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT )
103#define FEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT )
104#define FEATURE_DPM_UCLK_MASK (1 << FEATURE_DPM_UCLK_BIT )
105#define FEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT )
106#define FEATURE_DPM_UVD_MASK (1 << FEATURE_DPM_UVD_BIT )
107#define FEATURE_DPM_VCE_MASK (1 << FEATURE_DPM_VCE_BIT )
108#define FEATURE_ULV_MASK (1 << FEATURE_ULV_BIT )
109#define FEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT )
110#define FEATURE_DPM_LINK_MASK (1 << FEATURE_DPM_LINK_BIT )
111#define FEATURE_DPM_DCEFCLK_MASK (1 << FEATURE_DPM_DCEFCLK_BIT )
112#define FEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT )
113#define FEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT )
114#define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT )
115#define FEATURE_PPT_MASK (1 << FEATURE_PPT_BIT )
116#define FEATURE_TDC_MASK (1 << FEATURE_TDC_BIT )
117#define FEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT )
118#define FEATURE_GFX_PER_CU_CG_MASK (1 << FEATURE_GFX_PER_CU_CG_BIT )
119#define FEATURE_RM_MASK (1 << FEATURE_RM_BIT )
120#define FEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFCLK_BIT )
121#define FEATURE_ACDC_MASK (1 << FEATURE_ACDC_BIT )
122#define FEATURE_VR0HOT_MASK (1 << FEATURE_VR0HOT_BIT )
123#define FEATURE_VR1HOT_MASK (1 << FEATURE_VR1HOT_BIT )
124#define FEATURE_FW_CTF_MASK (1 << FEATURE_FW_CTF_BIT )
125#define FEATURE_LED_DISPLAY_MASK (1 << FEATURE_LED_DISPLAY_BIT )
126#define FEATURE_FAN_CONTROL_MASK (1 << FEATURE_FAN_CONTROL_BIT )
127#define FEATURE_GFX_EDC_MASK (1 << FEATURE_GFX_EDC_BIT )
128#define FEATURE_GFXOFF_MASK (1 << FEATURE_GFXOFF_BIT )
129#define FEATURE_CG_MASK (1 << FEATURE_CG_BIT )
130#define FEATURE_ACG_MASK (1 << FEATURE_ACG_BIT)
131#define FEATURE_SPARE_29_MASK (1 << FEATURE_SPARE_29_BIT )
132#define FEATURE_SPARE_30_MASK (1 << FEATURE_SPARE_30_BIT )
133#define FEATURE_SPARE_31_MASK (1 << FEATURE_SPARE_31_BIT )
134
135
136#define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001
137#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002
138#define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_SOCCLK 0x00000004
139#define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_UCLK 0x00000008
140#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_SOCCLK 0x00000010
141#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_UCLK 0x00000020
142#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_SOCCLK 0x00000040
143#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_UCLK 0x00000080
144#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_SOCCLK 0x00000100
145#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_UCLK 0x00000200
146#define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_SOCCLK 0x00000400
147#define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_UCLK 0x00000800
148#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00001000
149#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK 0x00002000
150#define DPM_OVERRIDE_ENABLE_GFXOFF_GFXCLK_SWITCH 0x00004000
151#define DPM_OVERRIDE_ENABLE_GFXOFF_SOCCLK_SWITCH 0x00008000
152#define DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH 0x00010000
153
154
155#define VR_MAPPING_VR_SELECT_MASK 0x01
156#define VR_MAPPING_VR_SELECT_SHIFT 0x00
157
158#define VR_MAPPING_PLANE_SELECT_MASK 0x02
159#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
160
161
162#define PSI_SEL_VR0_PLANE0_PSI0 0x01
163#define PSI_SEL_VR0_PLANE0_PSI1 0x02
164#define PSI_SEL_VR0_PLANE1_PSI0 0x04
165#define PSI_SEL_VR0_PLANE1_PSI1 0x08
166#define PSI_SEL_VR1_PLANE0_PSI0 0x10
167#define PSI_SEL_VR1_PLANE0_PSI1 0x20
168#define PSI_SEL_VR1_PLANE1_PSI0 0x40
169#define PSI_SEL_VR1_PLANE1_PSI1 0x80
170
171
172#define THROTTLER_STATUS_PADDING_BIT 0
173#define THROTTLER_STATUS_TEMP_EDGE_BIT 1
174#define THROTTLER_STATUS_TEMP_HOTSPOT_BIT 2
175#define THROTTLER_STATUS_TEMP_HBM_BIT 3
176#define THROTTLER_STATUS_TEMP_VR_GFX_BIT 4
177#define THROTTLER_STATUS_TEMP_VR_MEM_BIT 5
178#define THROTTLER_STATUS_TEMP_LIQUID_BIT 6
179#define THROTTLER_STATUS_TEMP_PLX_BIT 7
180#define THROTTLER_STATUS_TEMP_SKIN_BIT 8
181#define THROTTLER_STATUS_TDC_GFX_BIT 9
182#define THROTTLER_STATUS_TDC_SOC_BIT 10
183#define THROTTLER_STATUS_PPT_BIT 11
184#define THROTTLER_STATUS_FIT_BIT 12
185#define THROTTLER_STATUS_PPM_BIT 13
186
187
188#define TABLE_TRANSFER_OK 0x0
189#define TABLE_TRANSFER_FAILED 0xFF
190
191
192#define WORKLOAD_DEFAULT_BIT 0
193#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
194#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2
195#define WORKLOAD_PPLIB_VIDEO_BIT 3
196#define WORKLOAD_PPLIB_VR_BIT 4
197#define WORKLOAD_PPLIB_COMPUTE_BIT 5
198#define WORKLOAD_PPLIB_CUSTOM_BIT 6
199#define WORKLOAD_PPLIB_COUNT 7
200
201typedef struct {
202 uint32_t a;
203 uint32_t b;
204 uint32_t c;
205} QuadraticInt_t;
206
207typedef struct {
208 uint32_t m;
209 uint32_t b;
210} LinearInt_t;
211
212typedef struct {
213 uint32_t a;
214 uint32_t b;
215 uint32_t c;
216} DroopInt_t;
217
218typedef enum {
219 PPCLK_GFXCLK,
220 PPCLK_VCLK,
221 PPCLK_DCLK,
222 PPCLK_ECLK,
223 PPCLK_SOCCLK,
224 PPCLK_UCLK,
225 PPCLK_DCEFCLK,
226 PPCLK_DISPCLK,
227 PPCLK_PIXCLK,
228 PPCLK_PHYCLK,
229 PPCLK_COUNT,
230} PPCLK_e;
231
232enum {
233 VOLTAGE_MODE_AVFS,
234 VOLTAGE_MODE_AVFS_SS,
235 VOLTAGE_MODE_SS,
236 VOLTAGE_MODE_COUNT,
237};
238
239typedef struct {
240 uint8_t VoltageMode;
241 uint8_t SnapToDiscrete;
242 uint8_t NumDiscreteLevels;
243 uint8_t padding;
244 LinearInt_t ConversionToAvfsClk;
245 QuadraticInt_t SsCurve;
246} DpmDescriptor_t;
247
248typedef struct {
249 uint32_t Version;
250
251
252 uint32_t FeaturesToRun[2];
253
254
255 uint16_t SocketPowerLimitAc0;
256 uint16_t SocketPowerLimitAc0Tau;
257 uint16_t SocketPowerLimitAc1;
258 uint16_t SocketPowerLimitAc1Tau;
259 uint16_t SocketPowerLimitAc2;
260 uint16_t SocketPowerLimitAc2Tau;
261 uint16_t SocketPowerLimitAc3;
262 uint16_t SocketPowerLimitAc3Tau;
263 uint16_t SocketPowerLimitDc;
264 uint16_t SocketPowerLimitDcTau;
265 uint16_t TdcLimitSoc;
266 uint16_t TdcLimitSocTau;
267 uint16_t TdcLimitGfx;
268 uint16_t TdcLimitGfxTau;
269
270 uint16_t TedgeLimit;
271 uint16_t ThotspotLimit;
272 uint16_t ThbmLimit;
273 uint16_t Tvr_gfxLimit;
274 uint16_t Tvr_memLimit;
275 uint16_t Tliquid1Limit;
276 uint16_t Tliquid2Limit;
277 uint16_t TplxLimit;
278 uint32_t FitLimit;
279
280 uint16_t PpmPowerLimit;
281 uint16_t PpmTemperatureThreshold;
282
283 uint8_t MemoryOnPackage;
284 uint8_t padding8_limits[3];
285
286
287 uint16_t UlvVoltageOffsetSoc;
288 uint16_t UlvVoltageOffsetGfx;
289
290 uint8_t UlvSmnclkDid;
291 uint8_t UlvMp1clkDid;
292 uint8_t UlvGfxclkBypass;
293 uint8_t Padding234;
294
295
296 uint16_t MinVoltageGfx;
297 uint16_t MinVoltageSoc;
298 uint16_t MaxVoltageGfx;
299 uint16_t MaxVoltageSoc;
300
301 uint16_t LoadLineResistance;
302 uint16_t LoadLine_padding;
303
304
305 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
306
307 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ];
308 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ];
309 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ];
310 uint16_t FreqTableEclk [NUM_ECLK_DPM_LEVELS ];
311 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ];
312 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
313 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ];
314 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ];
315 uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ];
316 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ];
317
318 uint16_t DcModeMaxFreq [PPCLK_COUNT ];
319
320
321 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS];
322 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS];
323
324
325 uint16_t GfxclkFidle;
326 uint16_t GfxclkSlewRate;
327 uint16_t CksEnableFreq;
328 uint16_t Padding789;
329 QuadraticInt_t CksVoltageOffset;
330 uint16_t AcgThresholdFreqHigh;
331 uint16_t AcgThresholdFreqLow;
332 uint16_t GfxclkDsMaxFreq;
333 uint8_t Padding456[2];
334
335
336 uint8_t LowestUclkReservedForUlv;
337 uint8_t Padding8_Uclk[3];
338
339
340 uint8_t PcieGenSpeed[NUM_LINK_LEVELS];
341 uint8_t PcieLaneCount[NUM_LINK_LEVELS];
342 uint16_t LclkFreq[NUM_LINK_LEVELS];
343
344
345 uint16_t EnableTdpm;
346 uint16_t TdpmHighHystTemperature;
347 uint16_t TdpmLowHystTemperature;
348 uint16_t GfxclkFreqHighTempLimit;
349
350
351 uint16_t FanStopTemp;
352 uint16_t FanStartTemp;
353
354 uint16_t FanGainEdge;
355 uint16_t FanGainHotspot;
356 uint16_t FanGainLiquid;
357 uint16_t FanGainVrVddc;
358 uint16_t FanGainVrMvdd;
359 uint16_t FanGainPlx;
360 uint16_t FanGainHbm;
361 uint16_t FanPwmMin;
362 uint16_t FanAcousticLimitRpm;
363 uint16_t FanThrottlingRpm;
364 uint16_t FanMaximumRpm;
365 uint16_t FanTargetTemperature;
366 uint16_t FanTargetGfxclk;
367 uint8_t FanZeroRpmEnable;
368 uint8_t FanTachEdgePerRev;
369
370
371
372 int16_t FuzzyFan_ErrorSetDelta;
373 int16_t FuzzyFan_ErrorRateSetDelta;
374 int16_t FuzzyFan_PwmSetDelta;
375 uint16_t FuzzyFan_Reserved;
376
377
378
379
380 uint8_t OverrideAvfsGb;
381 uint8_t Padding8_Avfs[3];
382
383 QuadraticInt_t qAvfsGb;
384 DroopInt_t dBtcGbGfxCksOn;
385 DroopInt_t dBtcGbGfxCksOff;
386 DroopInt_t dBtcGbGfxAcg;
387 DroopInt_t dBtcGbSoc;
388 LinearInt_t qAgingGbGfx;
389 LinearInt_t qAgingGbSoc;
390
391 QuadraticInt_t qStaticVoltageOffsetGfx;
392 QuadraticInt_t qStaticVoltageOffsetSoc;
393
394 uint16_t DcTolGfx;
395 uint16_t DcTolSoc;
396
397 uint8_t DcBtcGfxEnabled;
398 uint8_t DcBtcSocEnabled;
399 uint8_t Padding8_GfxBtc[2];
400
401 uint16_t DcBtcGfxMin;
402 uint16_t DcBtcGfxMax;
403
404 uint16_t DcBtcSocMin;
405 uint16_t DcBtcSocMax;
406
407
408
409 uint32_t DebugOverrides;
410 QuadraticInt_t ReservedEquation0;
411 QuadraticInt_t ReservedEquation1;
412 QuadraticInt_t ReservedEquation2;
413 QuadraticInt_t ReservedEquation3;
414
415 uint16_t MinVoltageUlvGfx;
416 uint16_t MinVoltageUlvSoc;
417
418 uint32_t Reserved[14];
419
420
421
422 uint8_t Liquid1_I2C_address;
423 uint8_t Liquid2_I2C_address;
424 uint8_t Vr_I2C_address;
425 uint8_t Plx_I2C_address;
426
427 uint8_t Liquid_I2C_LineSCL;
428 uint8_t Liquid_I2C_LineSDA;
429 uint8_t Vr_I2C_LineSCL;
430 uint8_t Vr_I2C_LineSDA;
431
432 uint8_t Plx_I2C_LineSCL;
433 uint8_t Plx_I2C_LineSDA;
434 uint8_t VrSensorPresent;
435 uint8_t LiquidSensorPresent;
436
437 uint16_t MaxVoltageStepGfx;
438 uint16_t MaxVoltageStepSoc;
439
440 uint8_t VddGfxVrMapping;
441 uint8_t VddSocVrMapping;
442 uint8_t VddMem0VrMapping;
443 uint8_t VddMem1VrMapping;
444
445 uint8_t GfxUlvPhaseSheddingMask;
446 uint8_t SocUlvPhaseSheddingMask;
447 uint8_t ExternalSensorPresent;
448 uint8_t Padding8_V;
449
450
451 uint16_t GfxMaxCurrent;
452 int8_t GfxOffset;
453 uint8_t Padding_TelemetryGfx;
454
455 uint16_t SocMaxCurrent;
456 int8_t SocOffset;
457 uint8_t Padding_TelemetrySoc;
458
459 uint16_t Mem0MaxCurrent;
460 int8_t Mem0Offset;
461 uint8_t Padding_TelemetryMem0;
462
463 uint16_t Mem1MaxCurrent;
464 int8_t Mem1Offset;
465 uint8_t Padding_TelemetryMem1;
466
467
468 uint8_t AcDcGpio;
469 uint8_t AcDcPolarity;
470 uint8_t VR0HotGpio;
471 uint8_t VR0HotPolarity;
472
473 uint8_t VR1HotGpio;
474 uint8_t VR1HotPolarity;
475 uint8_t Padding1;
476 uint8_t Padding2;
477
478
479
480 uint8_t LedPin0;
481 uint8_t LedPin1;
482 uint8_t LedPin2;
483 uint8_t padding8_4;
484
485
486 uint8_t PllGfxclkSpreadEnabled;
487 uint8_t PllGfxclkSpreadPercent;
488 uint16_t PllGfxclkSpreadFreq;
489
490 uint8_t UclkSpreadEnabled;
491 uint8_t UclkSpreadPercent;
492 uint16_t UclkSpreadFreq;
493
494 uint8_t SocclkSpreadEnabled;
495 uint8_t SocclkSpreadPercent;
496 uint16_t SocclkSpreadFreq;
497
498 uint8_t AcgGfxclkSpreadEnabled;
499 uint8_t AcgGfxclkSpreadPercent;
500 uint16_t AcgGfxclkSpreadFreq;
501
502 uint8_t Vr2_I2C_address;
503 uint8_t padding_vr2[3];
504
505 uint32_t BoardReserved[9];
506
507
508 uint32_t MmHubPadding[7];
509
510} PPTable_t;
511
512typedef struct {
513
514 uint16_t GfxclkAverageLpfTau;
515 uint16_t SocclkAverageLpfTau;
516 uint16_t UclkAverageLpfTau;
517 uint16_t GfxActivityLpfTau;
518 uint16_t UclkActivityLpfTau;
519
520
521 uint32_t MmHubPadding[7];
522} DriverSmuConfig_t;
523
524typedef struct {
525
526 uint16_t GfxclkFmin;
527 uint16_t GfxclkFmax;
528 uint16_t GfxclkFreq1;
529 uint16_t GfxclkOffsetVolt1;
530 uint16_t GfxclkFreq2;
531 uint16_t GfxclkOffsetVolt2;
532 uint16_t GfxclkFreq3;
533 uint16_t GfxclkOffsetVolt3;
534 uint16_t UclkFmax;
535 int16_t OverDrivePct;
536 uint16_t FanMaximumRpm;
537 uint16_t FanMinimumPwm;
538 uint16_t FanTargetTemperature;
539 uint16_t MaxOpTemp;
540
541} OverDriveTable_t;
542
543typedef struct {
544 uint16_t CurrClock[PPCLK_COUNT];
545 uint16_t AverageGfxclkFrequency;
546 uint16_t AverageSocclkFrequency;
547 uint16_t AverageUclkFrequency ;
548 uint16_t AverageGfxActivity ;
549 uint16_t AverageUclkActivity ;
550 uint8_t CurrSocVoltageOffset ;
551 uint8_t CurrGfxVoltageOffset ;
552 uint8_t CurrMemVidOffset ;
553 uint8_t Padding8 ;
554 uint16_t CurrSocketPower ;
555 uint16_t TemperatureEdge ;
556 uint16_t TemperatureHotspot ;
557 uint16_t TemperatureHBM ;
558 uint16_t TemperatureVrGfx ;
559 uint16_t TemperatureVrMem ;
560 uint16_t TemperatureLiquid ;
561 uint16_t TemperaturePlx ;
562 uint32_t ThrottlerStatus ;
563
564 uint8_t LinkDpmLevel;
565 uint8_t Padding[3];
566
567
568 uint32_t MmHubPadding[7];
569} SmuMetrics_t;
570
571typedef struct {
572 uint16_t MinClock;
573 uint16_t MaxClock;
574 uint16_t MinUclk;
575 uint16_t MaxUclk;
576
577 uint8_t WmSetting;
578 uint8_t Padding[3];
579} WatermarkRowGeneric_t;
580
581#define NUM_WM_RANGES 4
582
583typedef enum {
584 WM_SOCCLK = 0,
585 WM_DCEFCLK,
586 WM_COUNT_PP,
587} WM_CLOCK_e;
588
589typedef struct {
590
591 WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES];
592
593 uint32_t MmHubPadding[7];
594} Watermarks_t;
595
596typedef struct {
597 uint16_t avgPsmCount[30];
598 uint16_t minPsmCount[30];
599 float avgPsmVoltage[30];
600 float minPsmVoltage[30];
601
602 uint32_t MmHubPadding[7];
603} AvfsDebugTable_t;
604
605typedef struct {
606 uint8_t AvfsEn;
607 uint8_t AvfsVersion;
608 uint8_t OverrideVFT;
609 uint8_t OverrideAvfsGb;
610
611 uint8_t OverrideTemperatures;
612 uint8_t OverrideVInversion;
613 uint8_t OverrideP2V;
614 uint8_t OverrideP2VCharzFreq;
615
616 int32_t VFT0_m1;
617 int32_t VFT0_m2;
618 int32_t VFT0_b;
619
620 int32_t VFT1_m1;
621 int32_t VFT1_m2;
622 int32_t VFT1_b;
623
624 int32_t VFT2_m1;
625 int32_t VFT2_m2;
626 int32_t VFT2_b;
627
628 int32_t AvfsGb0_m1;
629 int32_t AvfsGb0_m2;
630 int32_t AvfsGb0_b;
631
632 int32_t AcBtcGb_m1;
633 int32_t AcBtcGb_m2;
634 int32_t AcBtcGb_b;
635
636 uint32_t AvfsTempCold;
637 uint32_t AvfsTempMid;
638 uint32_t AvfsTempHot;
639
640 uint32_t GfxVInversion;
641 uint32_t SocVInversion;
642
643 int32_t P2V_m1;
644 int32_t P2V_m2;
645 int32_t P2V_b;
646
647 uint32_t P2VCharzFreq;
648
649 uint32_t EnabledAvfsModules;
650
651 uint32_t MmHubPadding[7];
652} AvfsFuseOverride_t;
653
654typedef struct {
655
656 uint8_t Gfx_ActiveHystLimit;
657 uint8_t Gfx_IdleHystLimit;
658 uint8_t Gfx_FPS;
659 uint8_t Gfx_MinActiveFreqType;
660 uint8_t Gfx_BoosterFreqType;
661 uint8_t Gfx_UseRlcBusy;
662 uint16_t Gfx_MinActiveFreq;
663 uint16_t Gfx_BoosterFreq;
664 uint16_t Gfx_PD_Data_time_constant;
665 uint32_t Gfx_PD_Data_limit_a;
666 uint32_t Gfx_PD_Data_limit_b;
667 uint32_t Gfx_PD_Data_limit_c;
668 uint32_t Gfx_PD_Data_error_coeff;
669 uint32_t Gfx_PD_Data_error_rate_coeff;
670
671 uint8_t Soc_ActiveHystLimit;
672 uint8_t Soc_IdleHystLimit;
673 uint8_t Soc_FPS;
674 uint8_t Soc_MinActiveFreqType;
675 uint8_t Soc_BoosterFreqType;
676 uint8_t Soc_UseRlcBusy;
677 uint16_t Soc_MinActiveFreq;
678 uint16_t Soc_BoosterFreq;
679 uint16_t Soc_PD_Data_time_constant;
680 uint32_t Soc_PD_Data_limit_a;
681 uint32_t Soc_PD_Data_limit_b;
682 uint32_t Soc_PD_Data_limit_c;
683 uint32_t Soc_PD_Data_error_coeff;
684 uint32_t Soc_PD_Data_error_rate_coeff;
685
686 uint8_t Mem_ActiveHystLimit;
687 uint8_t Mem_IdleHystLimit;
688 uint8_t Mem_FPS;
689 uint8_t Mem_MinActiveFreqType;
690 uint8_t Mem_BoosterFreqType;
691 uint8_t Mem_UseRlcBusy;
692 uint16_t Mem_MinActiveFreq;
693 uint16_t Mem_BoosterFreq;
694 uint16_t Mem_PD_Data_time_constant;
695 uint32_t Mem_PD_Data_limit_a;
696 uint32_t Mem_PD_Data_limit_b;
697 uint32_t Mem_PD_Data_limit_c;
698 uint32_t Mem_PD_Data_error_coeff;
699 uint32_t Mem_PD_Data_error_rate_coeff;
700
701} DpmActivityMonitorCoeffInt_t;
702
703
704
705
706#define TABLE_PPTABLE 0
707#define TABLE_WATERMARKS 1
708#define TABLE_AVFS 2
709#define TABLE_AVFS_PSM_DEBUG 3
710#define TABLE_AVFS_FUSE_OVERRIDE 4
711#define TABLE_PMSTATUSLOG 5
712#define TABLE_SMU_METRICS 6
713#define TABLE_DRIVER_SMU_CONFIG 7
714#define TABLE_ACTIVITY_MONITOR_COEFF 8
715#define TABLE_OVERDRIVE 9
716#define TABLE_COUNT 10
717
718
719#define UCLK_SWITCH_SLOW 0
720#define UCLK_SWITCH_FAST 1
721
722
723#define SQ_Enable_MASK 0x1
724#define SQ_IR_MASK 0x2
725#define SQ_PCC_MASK 0x4
726#define SQ_EDC_MASK 0x8
727
728#define TCP_Enable_MASK 0x100
729#define TCP_IR_MASK 0x200
730#define TCP_PCC_MASK 0x400
731#define TCP_EDC_MASK 0x800
732
733#define TD_Enable_MASK 0x10000
734#define TD_IR_MASK 0x20000
735#define TD_PCC_MASK 0x40000
736#define TD_EDC_MASK 0x80000
737
738#define DB_Enable_MASK 0x1000000
739#define DB_IR_MASK 0x2000000
740#define DB_PCC_MASK 0x4000000
741#define DB_EDC_MASK 0x8000000
742
743#define SQ_Enable_SHIFT 0
744#define SQ_IR_SHIFT 1
745#define SQ_PCC_SHIFT 2
746#define SQ_EDC_SHIFT 3
747
748#define TCP_Enable_SHIFT 8
749#define TCP_IR_SHIFT 9
750#define TCP_PCC_SHIFT 10
751#define TCP_EDC_SHIFT 11
752
753#define TD_Enable_SHIFT 16
754#define TD_IR_SHIFT 17
755#define TD_PCC_SHIFT 18
756#define TD_EDC_SHIFT 19
757
758#define DB_Enable_SHIFT 24
759#define DB_IR_SHIFT 25
760#define DB_PCC_SHIFT 26
761#define DB_EDC_SHIFT 27
762
763#define REMOVE_FMAX_MARGIN_BIT 0x0
764#define REMOVE_DCTOL_MARGIN_BIT 0x1
765#define REMOVE_PLATFORM_MARGIN_BIT 0x2
766
767#endif
768
