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8#ifndef ARMADA_CRTC_H
9#define ARMADA_CRTC_H
10
11#include <drm/drm_crtc.h>
12
13struct armada_gem_object;
14
15struct armada_regs {
16 uint32_t offset;
17 uint32_t mask;
18 uint32_t val;
19};
20
21#define armada_reg_queue_mod(_r, _i, _v, _m, _o) \
22 do { \
23 struct armada_regs *__reg = _r; \
24 __reg[_i].offset = _o; \
25 __reg[_i].mask = ~(_m); \
26 __reg[_i].val = _v; \
27 _i++; \
28 } while (0)
29
30#define armada_reg_queue_set(_r, _i, _v, _o) \
31 armada_reg_queue_mod(_r, _i, _v, ~0, _o)
32
33#define armada_reg_queue_end(_r, _i) \
34 armada_reg_queue_mod(_r, _i, 0, 0, ~0)
35
36struct armada_crtc;
37struct armada_variant;
38
39struct armada_crtc {
40 struct drm_crtc crtc;
41 const struct armada_variant *variant;
42 unsigned num;
43 void __iomem *base;
44 struct clk *clk;
45 struct clk *extclk[2];
46 struct {
47 uint32_t spu_v_h_total;
48 uint32_t spu_v_porch;
49 uint32_t spu_adv_reg;
50 } v[2];
51 bool interlaced;
52 bool cursor_update;
53
54 struct armada_gem_object *cursor_obj;
55 int cursor_x;
56 int cursor_y;
57 uint32_t cursor_hw_pos;
58 uint32_t cursor_hw_sz;
59 uint32_t cursor_w;
60 uint32_t cursor_h;
61
62 uint32_t cfg_dumb_ctrl;
63 uint32_t spu_iopad_ctrl;
64
65 spinlock_t irq_lock;
66 uint32_t irq_ena;
67
68 bool update_pending;
69 struct drm_pending_vblank_event *event;
70 struct armada_regs atomic_regs[32];
71 struct armada_regs *regs;
72 unsigned int regs_idx;
73};
74#define drm_to_armada_crtc(c) container_of(c, struct armada_crtc, crtc)
75
76void armada_drm_crtc_update_regs(struct armada_crtc *, struct armada_regs *);
77
78extern struct platform_driver armada_lcd_platform_driver;
79
80#endif
81