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8#include <linux/bitops.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12#include <linux/irqchip.h>
13#include <linux/irqchip/chained_irq.h>
14#include <linux/irqdomain.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/syscore_ops.h>
18
19#include <dt-bindings/interrupt-controller/arm-gic.h>
20
21#define IRQS_PER_BANK 32
22
23struct stm32_exti_bank {
24 u32 imr_ofst;
25 u32 emr_ofst;
26 u32 rtsr_ofst;
27 u32 ftsr_ofst;
28 u32 swier_ofst;
29 u32 rpr_ofst;
30 u32 fpr_ofst;
31};
32
33#define UNDEF_REG ~0
34
35struct stm32_desc_irq {
36 u32 exti;
37 u32 irq_parent;
38};
39
40struct stm32_exti_drv_data {
41 const struct stm32_exti_bank **exti_banks;
42 const struct stm32_desc_irq *desc_irqs;
43 u32 bank_nr;
44 u32 irq_nr;
45};
46
47struct stm32_exti_chip_data {
48 struct stm32_exti_host_data *host_data;
49 const struct stm32_exti_bank *reg_bank;
50 struct raw_spinlock rlock;
51 u32 wake_active;
52 u32 mask_cache;
53 u32 rtsr_cache;
54 u32 ftsr_cache;
55};
56
57struct stm32_exti_host_data {
58 void __iomem *base;
59 struct stm32_exti_chip_data *chips_data;
60 const struct stm32_exti_drv_data *drv_data;
61};
62
63static struct stm32_exti_host_data *stm32_host_data;
64
65static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
66 .imr_ofst = 0x00,
67 .emr_ofst = 0x04,
68 .rtsr_ofst = 0x08,
69 .ftsr_ofst = 0x0C,
70 .swier_ofst = 0x10,
71 .rpr_ofst = 0x14,
72 .fpr_ofst = UNDEF_REG,
73};
74
75static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
76 &stm32f4xx_exti_b1,
77};
78
79static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
80 .exti_banks = stm32f4xx_exti_banks,
81 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
82};
83
84static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
85 .imr_ofst = 0x80,
86 .emr_ofst = 0x84,
87 .rtsr_ofst = 0x00,
88 .ftsr_ofst = 0x04,
89 .swier_ofst = 0x08,
90 .rpr_ofst = 0x88,
91 .fpr_ofst = UNDEF_REG,
92};
93
94static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
95 .imr_ofst = 0x90,
96 .emr_ofst = 0x94,
97 .rtsr_ofst = 0x20,
98 .ftsr_ofst = 0x24,
99 .swier_ofst = 0x28,
100 .rpr_ofst = 0x98,
101 .fpr_ofst = UNDEF_REG,
102};
103
104static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
105 .imr_ofst = 0xA0,
106 .emr_ofst = 0xA4,
107 .rtsr_ofst = 0x40,
108 .ftsr_ofst = 0x44,
109 .swier_ofst = 0x48,
110 .rpr_ofst = 0xA8,
111 .fpr_ofst = UNDEF_REG,
112};
113
114static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
115 &stm32h7xx_exti_b1,
116 &stm32h7xx_exti_b2,
117 &stm32h7xx_exti_b3,
118};
119
120static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
121 .exti_banks = stm32h7xx_exti_banks,
122 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
123};
124
125static const struct stm32_exti_bank stm32mp1_exti_b1 = {
126 .imr_ofst = 0x80,
127 .emr_ofst = 0x84,
128 .rtsr_ofst = 0x00,
129 .ftsr_ofst = 0x04,
130 .swier_ofst = 0x08,
131 .rpr_ofst = 0x0C,
132 .fpr_ofst = 0x10,
133};
134
135static const struct stm32_exti_bank stm32mp1_exti_b2 = {
136 .imr_ofst = 0x90,
137 .emr_ofst = 0x94,
138 .rtsr_ofst = 0x20,
139 .ftsr_ofst = 0x24,
140 .swier_ofst = 0x28,
141 .rpr_ofst = 0x2C,
142 .fpr_ofst = 0x30,
143};
144
145static const struct stm32_exti_bank stm32mp1_exti_b3 = {
146 .imr_ofst = 0xA0,
147 .emr_ofst = 0xA4,
148 .rtsr_ofst = 0x40,
149 .ftsr_ofst = 0x44,
150 .swier_ofst = 0x48,
151 .rpr_ofst = 0x4C,
152 .fpr_ofst = 0x50,
153};
154
155static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
156 &stm32mp1_exti_b1,
157 &stm32mp1_exti_b2,
158 &stm32mp1_exti_b3,
159};
160
161static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
162 { .exti = 1, .irq_parent = 7 },
163 { .exti = 2, .irq_parent = 8 },
164 { .exti = 3, .irq_parent = 9 },
165 { .exti = 4, .irq_parent = 10 },
166 { .exti = 5, .irq_parent = 23 },
167 { .exti = 6, .irq_parent = 64 },
168 { .exti = 7, .irq_parent = 65 },
169 { .exti = 8, .irq_parent = 66 },
170 { .exti = 9, .irq_parent = 67 },
171 { .exti = 10, .irq_parent = 40 },
172 { .exti = 11, .irq_parent = 42 },
173 { .exti = 12, .irq_parent = 76 },
174 { .exti = 13, .irq_parent = 77 },
175 { .exti = 14, .irq_parent = 121 },
176 { .exti = 15, .irq_parent = 127 },
177 { .exti = 16, .irq_parent = 1 },
178 { .exti = 65, .irq_parent = 144 },
179 { .exti = 68, .irq_parent = 143 },
180 { .exti = 73, .irq_parent = 129 },
181};
182
183static const struct stm32_exti_drv_data stm32mp1_drv_data = {
184 .exti_banks = stm32mp1_exti_banks,
185 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
186 .desc_irqs = stm32mp1_desc_irq,
187 .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
188};
189
190static int stm32_exti_to_irq(const struct stm32_exti_drv_data *drv_data,
191 irq_hw_number_t hwirq)
192{
193 const struct stm32_desc_irq *desc_irq;
194 int i;
195
196 if (!drv_data->desc_irqs)
197 return -EINVAL;
198
199 for (i = 0; i < drv_data->irq_nr; i++) {
200 desc_irq = &drv_data->desc_irqs[i];
201 if (desc_irq->exti == hwirq)
202 return desc_irq->irq_parent;
203 }
204
205 return -EINVAL;
206}
207
208static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
209{
210 struct stm32_exti_chip_data *chip_data = gc->private;
211 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
212 unsigned long pending;
213
214 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
215 if (stm32_bank->fpr_ofst != UNDEF_REG)
216 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
217
218 return pending;
219}
220
221static void stm32_irq_handler(struct irq_desc *desc)
222{
223 struct irq_domain *domain = irq_desc_get_handler_data(desc);
224 struct irq_chip *chip = irq_desc_get_chip(desc);
225 unsigned int virq, nbanks = domain->gc->num_chips;
226 struct irq_chip_generic *gc;
227 unsigned long pending;
228 int n, i, irq_base = 0;
229
230 chained_irq_enter(chip, desc);
231
232 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
233 gc = irq_get_domain_generic_chip(domain, irq_base);
234
235 while ((pending = stm32_exti_pending(gc))) {
236 for_each_set_bit(n, &pending, IRQS_PER_BANK) {
237 virq = irq_find_mapping(domain, irq_base + n);
238 generic_handle_irq(virq);
239 }
240 }
241 }
242
243 chained_irq_exit(chip, desc);
244}
245
246static int stm32_exti_set_type(struct irq_data *d,
247 unsigned int type, u32 *rtsr, u32 *ftsr)
248{
249 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
250
251 switch (type) {
252 case IRQ_TYPE_EDGE_RISING:
253 *rtsr |= mask;
254 *ftsr &= ~mask;
255 break;
256 case IRQ_TYPE_EDGE_FALLING:
257 *rtsr &= ~mask;
258 *ftsr |= mask;
259 break;
260 case IRQ_TYPE_EDGE_BOTH:
261 *rtsr |= mask;
262 *ftsr |= mask;
263 break;
264 default:
265 return -EINVAL;
266 }
267
268 return 0;
269}
270
271static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
272{
273 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
274 struct stm32_exti_chip_data *chip_data = gc->private;
275 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
276 u32 rtsr, ftsr;
277 int err;
278
279 irq_gc_lock(gc);
280
281 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
282 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
283
284 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
285 if (err) {
286 irq_gc_unlock(gc);
287 return err;
288 }
289
290 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
291 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
292
293 irq_gc_unlock(gc);
294
295 return 0;
296}
297
298static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
299 u32 wake_active)
300{
301 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
302 void __iomem *base = chip_data->host_data->base;
303
304
305 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
306 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
307
308 writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
309}
310
311static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
312 u32 mask_cache)
313{
314 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
315 void __iomem *base = chip_data->host_data->base;
316
317
318 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
319 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
320
321 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
322}
323
324static void stm32_irq_suspend(struct irq_chip_generic *gc)
325{
326 struct stm32_exti_chip_data *chip_data = gc->private;
327
328 irq_gc_lock(gc);
329 stm32_chip_suspend(chip_data, gc->wake_active);
330 irq_gc_unlock(gc);
331}
332
333static void stm32_irq_resume(struct irq_chip_generic *gc)
334{
335 struct stm32_exti_chip_data *chip_data = gc->private;
336
337 irq_gc_lock(gc);
338 stm32_chip_resume(chip_data, gc->mask_cache);
339 irq_gc_unlock(gc);
340}
341
342static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
343 unsigned int nr_irqs, void *data)
344{
345 struct irq_fwspec *fwspec = data;
346 irq_hw_number_t hwirq;
347
348 hwirq = fwspec->param[0];
349
350 irq_map_generic_chip(d, virq, hwirq);
351
352 return 0;
353}
354
355static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
356 unsigned int nr_irqs)
357{
358 struct irq_data *data = irq_domain_get_irq_data(d, virq);
359
360 irq_domain_reset_irq_data(data);
361}
362
363static const struct irq_domain_ops irq_exti_domain_ops = {
364 .map = irq_map_generic_chip,
365 .alloc = stm32_exti_alloc,
366 .free = stm32_exti_free,
367};
368
369static void stm32_irq_ack(struct irq_data *d)
370{
371 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
372 struct stm32_exti_chip_data *chip_data = gc->private;
373 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
374
375 irq_gc_lock(gc);
376
377 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
378 if (stm32_bank->fpr_ofst != UNDEF_REG)
379 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
380
381 irq_gc_unlock(gc);
382}
383
384static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
385{
386 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
387 void __iomem *base = chip_data->host_data->base;
388 u32 val;
389
390 val = readl_relaxed(base + reg);
391 val |= BIT(d->hwirq % IRQS_PER_BANK);
392 writel_relaxed(val, base + reg);
393
394 return val;
395}
396
397static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
398{
399 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
400 void __iomem *base = chip_data->host_data->base;
401 u32 val;
402
403 val = readl_relaxed(base + reg);
404 val &= ~BIT(d->hwirq % IRQS_PER_BANK);
405 writel_relaxed(val, base + reg);
406
407 return val;
408}
409
410static void stm32_exti_h_eoi(struct irq_data *d)
411{
412 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
413 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
414
415 raw_spin_lock(&chip_data->rlock);
416
417 stm32_exti_set_bit(d, stm32_bank->rpr_ofst);
418 if (stm32_bank->fpr_ofst != UNDEF_REG)
419 stm32_exti_set_bit(d, stm32_bank->fpr_ofst);
420
421 raw_spin_unlock(&chip_data->rlock);
422
423 if (d->parent_data->chip)
424 irq_chip_eoi_parent(d);
425}
426
427static void stm32_exti_h_mask(struct irq_data *d)
428{
429 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
430 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
431
432 raw_spin_lock(&chip_data->rlock);
433 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
434 raw_spin_unlock(&chip_data->rlock);
435
436 if (d->parent_data->chip)
437 irq_chip_mask_parent(d);
438}
439
440static void stm32_exti_h_unmask(struct irq_data *d)
441{
442 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
443 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
444
445 raw_spin_lock(&chip_data->rlock);
446 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
447 raw_spin_unlock(&chip_data->rlock);
448
449 if (d->parent_data->chip)
450 irq_chip_unmask_parent(d);
451}
452
453static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
454{
455 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
456 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
457 void __iomem *base = chip_data->host_data->base;
458 u32 rtsr, ftsr;
459 int err;
460
461 raw_spin_lock(&chip_data->rlock);
462 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
463 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
464
465 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
466 if (err) {
467 raw_spin_unlock(&chip_data->rlock);
468 return err;
469 }
470
471 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
472 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
473 raw_spin_unlock(&chip_data->rlock);
474
475 return 0;
476}
477
478static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
479{
480 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
481 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
482
483 raw_spin_lock(&chip_data->rlock);
484
485 if (on)
486 chip_data->wake_active |= mask;
487 else
488 chip_data->wake_active &= ~mask;
489
490 raw_spin_unlock(&chip_data->rlock);
491
492 return 0;
493}
494
495static int stm32_exti_h_set_affinity(struct irq_data *d,
496 const struct cpumask *dest, bool force)
497{
498 if (d->parent_data->chip)
499 return irq_chip_set_affinity_parent(d, dest, force);
500
501 return -EINVAL;
502}
503
504#ifdef CONFIG_PM
505static int stm32_exti_h_suspend(void)
506{
507 struct stm32_exti_chip_data *chip_data;
508 int i;
509
510 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
511 chip_data = &stm32_host_data->chips_data[i];
512 raw_spin_lock(&chip_data->rlock);
513 stm32_chip_suspend(chip_data, chip_data->wake_active);
514 raw_spin_unlock(&chip_data->rlock);
515 }
516
517 return 0;
518}
519
520static void stm32_exti_h_resume(void)
521{
522 struct stm32_exti_chip_data *chip_data;
523 int i;
524
525 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
526 chip_data = &stm32_host_data->chips_data[i];
527 raw_spin_lock(&chip_data->rlock);
528 stm32_chip_resume(chip_data, chip_data->mask_cache);
529 raw_spin_unlock(&chip_data->rlock);
530 }
531}
532
533static struct syscore_ops stm32_exti_h_syscore_ops = {
534 .suspend = stm32_exti_h_suspend,
535 .resume = stm32_exti_h_resume,
536};
537
538static void stm32_exti_h_syscore_init(void)
539{
540 register_syscore_ops(&stm32_exti_h_syscore_ops);
541}
542#else
543static inline void stm32_exti_h_syscore_init(void) {}
544#endif
545
546static struct irq_chip stm32_exti_h_chip = {
547 .name = "stm32-exti-h",
548 .irq_eoi = stm32_exti_h_eoi,
549 .irq_mask = stm32_exti_h_mask,
550 .irq_unmask = stm32_exti_h_unmask,
551 .irq_retrigger = irq_chip_retrigger_hierarchy,
552 .irq_set_type = stm32_exti_h_set_type,
553 .irq_set_wake = stm32_exti_h_set_wake,
554 .flags = IRQCHIP_MASK_ON_SUSPEND,
555 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
556};
557
558static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
559 unsigned int virq,
560 unsigned int nr_irqs, void *data)
561{
562 struct stm32_exti_host_data *host_data = dm->host_data;
563 struct stm32_exti_chip_data *chip_data;
564 struct irq_fwspec *fwspec = data;
565 struct irq_fwspec p_fwspec;
566 irq_hw_number_t hwirq;
567 int p_irq, bank;
568
569 hwirq = fwspec->param[0];
570 bank = hwirq / IRQS_PER_BANK;
571 chip_data = &host_data->chips_data[bank];
572
573 irq_domain_set_hwirq_and_chip(dm, virq, hwirq,
574 &stm32_exti_h_chip, chip_data);
575
576 p_irq = stm32_exti_to_irq(host_data->drv_data, hwirq);
577 if (p_irq >= 0) {
578 p_fwspec.fwnode = dm->parent->fwnode;
579 p_fwspec.param_count = 3;
580 p_fwspec.param[0] = GIC_SPI;
581 p_fwspec.param[1] = p_irq;
582 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
583
584 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
585 }
586
587 return 0;
588}
589
590static struct
591stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
592 struct device_node *node)
593{
594 struct stm32_exti_host_data *host_data;
595
596 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
597 if (!host_data)
598 return NULL;
599
600 host_data->drv_data = dd;
601 host_data->chips_data = kcalloc(dd->bank_nr,
602 sizeof(struct stm32_exti_chip_data),
603 GFP_KERNEL);
604 if (!host_data->chips_data)
605 return NULL;
606
607 host_data->base = of_iomap(node, 0);
608 if (!host_data->base) {
609 pr_err("%pOF: Unable to map registers\n", node);
610 return NULL;
611 }
612
613 stm32_host_data = host_data;
614
615 return host_data;
616}
617
618static struct
619stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
620 u32 bank_idx,
621 struct device_node *node)
622{
623 const struct stm32_exti_bank *stm32_bank;
624 struct stm32_exti_chip_data *chip_data;
625 void __iomem *base = h_data->base;
626 u32 irqs_mask;
627
628 stm32_bank = h_data->drv_data->exti_banks[bank_idx];
629 chip_data = &h_data->chips_data[bank_idx];
630 chip_data->host_data = h_data;
631 chip_data->reg_bank = stm32_bank;
632
633 raw_spin_lock_init(&chip_data->rlock);
634
635
636 writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
637 irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
638
639
640
641
642
643 writel_relaxed(0, base + stm32_bank->imr_ofst);
644 writel_relaxed(0, base + stm32_bank->emr_ofst);
645 writel_relaxed(0, base + stm32_bank->rtsr_ofst);
646 writel_relaxed(0, base + stm32_bank->ftsr_ofst);
647 writel_relaxed(~0UL, base + stm32_bank->rpr_ofst);
648 if (stm32_bank->fpr_ofst != UNDEF_REG)
649 writel_relaxed(~0UL, base + stm32_bank->fpr_ofst);
650
651 pr_info("%s: bank%d, External IRQs available:%#x\n",
652 node->full_name, bank_idx, irqs_mask);
653
654 return chip_data;
655}
656
657static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
658 struct device_node *node)
659{
660 struct stm32_exti_host_data *host_data;
661 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
662 int nr_irqs, ret, i;
663 struct irq_chip_generic *gc;
664 struct irq_domain *domain;
665
666 host_data = stm32_exti_host_init(drv_data, node);
667 if (!host_data) {
668 ret = -ENOMEM;
669 goto out_free_mem;
670 }
671
672 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
673 &irq_exti_domain_ops, NULL);
674 if (!domain) {
675 pr_err("%s: Could not register interrupt domain.\n",
676 node->name);
677 ret = -ENOMEM;
678 goto out_unmap;
679 }
680
681 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
682 handle_edge_irq, clr, 0, 0);
683 if (ret) {
684 pr_err("%pOF: Could not allocate generic interrupt chip.\n",
685 node);
686 goto out_free_domain;
687 }
688
689 for (i = 0; i < drv_data->bank_nr; i++) {
690 const struct stm32_exti_bank *stm32_bank;
691 struct stm32_exti_chip_data *chip_data;
692
693 stm32_bank = drv_data->exti_banks[i];
694 chip_data = stm32_exti_chip_init(host_data, i, node);
695
696 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
697
698 gc->reg_base = host_data->base;
699 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
700 gc->chip_types->chip.irq_ack = stm32_irq_ack;
701 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
702 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
703 gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
704 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
705 gc->suspend = stm32_irq_suspend;
706 gc->resume = stm32_irq_resume;
707 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
708
709 gc->chip_types->regs.mask = stm32_bank->imr_ofst;
710 gc->private = (void *)chip_data;
711 }
712
713 nr_irqs = of_irq_count(node);
714 for (i = 0; i < nr_irqs; i++) {
715 unsigned int irq = irq_of_parse_and_map(node, i);
716
717 irq_set_handler_data(irq, domain);
718 irq_set_chained_handler(irq, stm32_irq_handler);
719 }
720
721 return 0;
722
723out_free_domain:
724 irq_domain_remove(domain);
725out_unmap:
726 iounmap(host_data->base);
727out_free_mem:
728 kfree(host_data->chips_data);
729 kfree(host_data);
730 return ret;
731}
732
733static const struct irq_domain_ops stm32_exti_h_domain_ops = {
734 .alloc = stm32_exti_h_domain_alloc,
735 .free = irq_domain_free_irqs_common,
736};
737
738static int
739__init stm32_exti_hierarchy_init(const struct stm32_exti_drv_data *drv_data,
740 struct device_node *node,
741 struct device_node *parent)
742{
743 struct irq_domain *parent_domain, *domain;
744 struct stm32_exti_host_data *host_data;
745 int ret, i;
746
747 parent_domain = irq_find_host(parent);
748 if (!parent_domain) {
749 pr_err("interrupt-parent not found\n");
750 return -EINVAL;
751 }
752
753 host_data = stm32_exti_host_init(drv_data, node);
754 if (!host_data) {
755 ret = -ENOMEM;
756 goto out_free_mem;
757 }
758
759 for (i = 0; i < drv_data->bank_nr; i++)
760 stm32_exti_chip_init(host_data, i, node);
761
762 domain = irq_domain_add_hierarchy(parent_domain, 0,
763 drv_data->bank_nr * IRQS_PER_BANK,
764 node, &stm32_exti_h_domain_ops,
765 host_data);
766
767 if (!domain) {
768 pr_err("%s: Could not register exti domain.\n", node->name);
769 ret = -ENOMEM;
770 goto out_unmap;
771 }
772
773 stm32_exti_h_syscore_init();
774
775 return 0;
776
777out_unmap:
778 iounmap(host_data->base);
779out_free_mem:
780 kfree(host_data->chips_data);
781 kfree(host_data);
782 return ret;
783}
784
785static int __init stm32f4_exti_of_init(struct device_node *np,
786 struct device_node *parent)
787{
788 return stm32_exti_init(&stm32f4xx_drv_data, np);
789}
790
791IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
792
793static int __init stm32h7_exti_of_init(struct device_node *np,
794 struct device_node *parent)
795{
796 return stm32_exti_init(&stm32h7xx_drv_data, np);
797}
798
799IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
800
801static int __init stm32mp1_exti_of_init(struct device_node *np,
802 struct device_node *parent)
803{
804 return stm32_exti_hierarchy_init(&stm32mp1_drv_data, np, parent);
805}
806
807IRQCHIP_DECLARE(stm32mp1_exti, "st,stm32mp1-exti", stm32mp1_exti_of_init);
808
