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25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/device.h>
28#include <linux/jiffies.h>
29#include <linux/string.h>
30#include <linux/slab.h>
31#include <linux/types.h>
32
33
34#include <media/dvb_frontend.h>
35#include "m88rs2000.h"
36
37struct m88rs2000_state {
38 struct i2c_adapter *i2c;
39 const struct m88rs2000_config *config;
40 struct dvb_frontend frontend;
41 u8 no_lock_count;
42 u32 tuner_frequency;
43 u32 symbol_rate;
44 enum fe_code_rate fec_inner;
45 u8 tuner_level;
46 int errmode;
47};
48
49static int m88rs2000_debug;
50
51module_param_named(debug, m88rs2000_debug, int, 0644);
52MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
53
54#define dprintk(level, args...) do { \
55 if (level & m88rs2000_debug) \
56 printk(KERN_DEBUG "m88rs2000-fe: " args); \
57} while (0)
58
59#define deb_info(args...) dprintk(0x01, args)
60#define info(format, arg...) \
61 printk(KERN_INFO "m88rs2000-fe: " format "\n" , ## arg)
62
63static int m88rs2000_writereg(struct m88rs2000_state *state,
64 u8 reg, u8 data)
65{
66 int ret;
67 u8 buf[] = { reg, data };
68 struct i2c_msg msg = {
69 .addr = state->config->demod_addr,
70 .flags = 0,
71 .buf = buf,
72 .len = 2
73 };
74
75 ret = i2c_transfer(state->i2c, &msg, 1);
76
77 if (ret != 1)
78 deb_info("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
79 __func__, reg, data, ret);
80
81 return (ret != 1) ? -EREMOTEIO : 0;
82}
83
84static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 reg)
85{
86 int ret;
87 u8 b0[] = { reg };
88 u8 b1[] = { 0 };
89
90 struct i2c_msg msg[] = {
91 {
92 .addr = state->config->demod_addr,
93 .flags = 0,
94 .buf = b0,
95 .len = 1
96 }, {
97 .addr = state->config->demod_addr,
98 .flags = I2C_M_RD,
99 .buf = b1,
100 .len = 1
101 }
102 };
103
104 ret = i2c_transfer(state->i2c, msg, 2);
105
106 if (ret != 2)
107 deb_info("%s: readreg error (reg == 0x%02x, ret == %i)\n",
108 __func__, reg, ret);
109
110 return b1[0];
111}
112
113static u32 m88rs2000_get_mclk(struct dvb_frontend *fe)
114{
115 struct m88rs2000_state *state = fe->demodulator_priv;
116 u32 mclk;
117 u8 reg;
118
119 reg = m88rs2000_readreg(state, 0x86);
120 if (!reg || reg == 0xff)
121 return 0;
122
123 reg /= 2;
124 reg += 1;
125
126 mclk = (u32)(reg * RS2000_FE_CRYSTAL_KHZ + 28 / 2) / 28;
127
128 return mclk;
129}
130
131static int m88rs2000_set_carrieroffset(struct dvb_frontend *fe, s16 offset)
132{
133 struct m88rs2000_state *state = fe->demodulator_priv;
134 u32 mclk;
135 s32 tmp;
136 u8 reg;
137 int ret;
138
139 mclk = m88rs2000_get_mclk(fe);
140 if (!mclk)
141 return -EINVAL;
142
143 tmp = (offset * 4096 + (s32)mclk / 2) / (s32)mclk;
144 if (tmp < 0)
145 tmp += 4096;
146
147
148 ret = m88rs2000_writereg(state, 0x9c, (u8)(tmp >> 4));
149
150 reg = m88rs2000_readreg(state, 0x9d);
151 reg &= 0xf;
152 reg |= (u8)(tmp & 0xf) << 4;
153
154 ret |= m88rs2000_writereg(state, 0x9d, reg);
155
156 return ret;
157}
158
159static int m88rs2000_set_symbolrate(struct dvb_frontend *fe, u32 srate)
160{
161 struct m88rs2000_state *state = fe->demodulator_priv;
162 int ret;
163 u64 temp;
164 u32 mclk;
165 u8 b[3];
166
167 if ((srate < 1000000) || (srate > 45000000))
168 return -EINVAL;
169
170 mclk = m88rs2000_get_mclk(fe);
171 if (!mclk)
172 return -EINVAL;
173
174 temp = srate / 1000;
175 temp *= 1 << 24;
176
177 do_div(temp, mclk);
178
179 b[0] = (u8) (temp >> 16) & 0xff;
180 b[1] = (u8) (temp >> 8) & 0xff;
181 b[2] = (u8) temp & 0xff;
182
183 ret = m88rs2000_writereg(state, 0x93, b[2]);
184 ret |= m88rs2000_writereg(state, 0x94, b[1]);
185 ret |= m88rs2000_writereg(state, 0x95, b[0]);
186
187 if (srate > 10000000)
188 ret |= m88rs2000_writereg(state, 0xa0, 0x20);
189 else
190 ret |= m88rs2000_writereg(state, 0xa0, 0x60);
191
192 ret |= m88rs2000_writereg(state, 0xa1, 0xe0);
193
194 if (srate > 12000000)
195 ret |= m88rs2000_writereg(state, 0xa3, 0x20);
196 else if (srate > 2800000)
197 ret |= m88rs2000_writereg(state, 0xa3, 0x98);
198 else
199 ret |= m88rs2000_writereg(state, 0xa3, 0x90);
200
201 deb_info("m88rs2000: m88rs2000_set_symbolrate\n");
202 return ret;
203}
204
205static int m88rs2000_send_diseqc_msg(struct dvb_frontend *fe,
206 struct dvb_diseqc_master_cmd *m)
207{
208 struct m88rs2000_state *state = fe->demodulator_priv;
209
210 int i;
211 u8 reg;
212 deb_info("%s\n", __func__);
213 m88rs2000_writereg(state, 0x9a, 0x30);
214 reg = m88rs2000_readreg(state, 0xb2);
215 reg &= 0x3f;
216 m88rs2000_writereg(state, 0xb2, reg);
217 for (i = 0; i < m->msg_len; i++)
218 m88rs2000_writereg(state, 0xb3 + i, m->msg[i]);
219
220 reg = m88rs2000_readreg(state, 0xb1);
221 reg &= 0x87;
222 reg |= ((m->msg_len - 1) << 3) | 0x07;
223 reg &= 0x7f;
224 m88rs2000_writereg(state, 0xb1, reg);
225
226 for (i = 0; i < 15; i++) {
227 if ((m88rs2000_readreg(state, 0xb1) & 0x40) == 0x0)
228 break;
229 msleep(20);
230 }
231
232 reg = m88rs2000_readreg(state, 0xb1);
233 if ((reg & 0x40) > 0x0) {
234 reg &= 0x7f;
235 reg |= 0x40;
236 m88rs2000_writereg(state, 0xb1, reg);
237 }
238
239 reg = m88rs2000_readreg(state, 0xb2);
240 reg &= 0x3f;
241 reg |= 0x80;
242 m88rs2000_writereg(state, 0xb2, reg);
243 m88rs2000_writereg(state, 0x9a, 0xb0);
244
245
246 return 0;
247}
248
249static int m88rs2000_send_diseqc_burst(struct dvb_frontend *fe,
250 enum fe_sec_mini_cmd burst)
251{
252 struct m88rs2000_state *state = fe->demodulator_priv;
253 u8 reg0, reg1;
254 deb_info("%s\n", __func__);
255 m88rs2000_writereg(state, 0x9a, 0x30);
256 msleep(50);
257 reg0 = m88rs2000_readreg(state, 0xb1);
258 reg1 = m88rs2000_readreg(state, 0xb2);
259
260 m88rs2000_writereg(state, 0xb2, reg1);
261 m88rs2000_writereg(state, 0xb1, reg0);
262 m88rs2000_writereg(state, 0x9a, 0xb0);
263
264 return 0;
265}
266
267static int m88rs2000_set_tone(struct dvb_frontend *fe,
268 enum fe_sec_tone_mode tone)
269{
270 struct m88rs2000_state *state = fe->demodulator_priv;
271 u8 reg0, reg1;
272 m88rs2000_writereg(state, 0x9a, 0x30);
273 reg0 = m88rs2000_readreg(state, 0xb1);
274 reg1 = m88rs2000_readreg(state, 0xb2);
275
276 reg1 &= 0x3f;
277
278 switch (tone) {
279 case SEC_TONE_ON:
280 reg0 |= 0x4;
281 reg0 &= 0xbc;
282 break;
283 case SEC_TONE_OFF:
284 reg1 |= 0x80;
285 break;
286 default:
287 break;
288 }
289 m88rs2000_writereg(state, 0xb2, reg1);
290 m88rs2000_writereg(state, 0xb1, reg0);
291 m88rs2000_writereg(state, 0x9a, 0xb0);
292 return 0;
293}
294
295struct inittab {
296 u8 cmd;
297 u8 reg;
298 u8 val;
299};
300
301static struct inittab m88rs2000_setup[] = {
302 {DEMOD_WRITE, 0x9a, 0x30},
303 {DEMOD_WRITE, 0x00, 0x01},
304 {WRITE_DELAY, 0x19, 0x00},
305 {DEMOD_WRITE, 0x00, 0x00},
306 {DEMOD_WRITE, 0x9a, 0xb0},
307 {DEMOD_WRITE, 0x81, 0xc1},
308 {DEMOD_WRITE, 0x81, 0x81},
309 {DEMOD_WRITE, 0x86, 0xc6},
310 {DEMOD_WRITE, 0x9a, 0x30},
311 {DEMOD_WRITE, 0xf0, 0x22},
312 {DEMOD_WRITE, 0xf1, 0xbf},
313 {DEMOD_WRITE, 0xb0, 0x45},
314 {DEMOD_WRITE, 0xb2, 0x01},
315 {DEMOD_WRITE, 0x9a, 0xb0},
316 {0xff, 0xaa, 0xff}
317};
318
319static struct inittab m88rs2000_shutdown[] = {
320 {DEMOD_WRITE, 0x9a, 0x30},
321 {DEMOD_WRITE, 0xb0, 0x00},
322 {DEMOD_WRITE, 0xf1, 0x89},
323 {DEMOD_WRITE, 0x00, 0x01},
324 {DEMOD_WRITE, 0x9a, 0xb0},
325 {DEMOD_WRITE, 0x81, 0x81},
326 {0xff, 0xaa, 0xff}
327};
328
329static struct inittab fe_reset[] = {
330 {DEMOD_WRITE, 0x00, 0x01},
331 {DEMOD_WRITE, 0x20, 0x81},
332 {DEMOD_WRITE, 0x21, 0x80},
333 {DEMOD_WRITE, 0x10, 0x33},
334 {DEMOD_WRITE, 0x11, 0x44},
335 {DEMOD_WRITE, 0x12, 0x07},
336 {DEMOD_WRITE, 0x18, 0x20},
337 {DEMOD_WRITE, 0x28, 0x04},
338 {DEMOD_WRITE, 0x29, 0x8e},
339 {DEMOD_WRITE, 0x3b, 0xff},
340 {DEMOD_WRITE, 0x32, 0x10},
341 {DEMOD_WRITE, 0x33, 0x02},
342 {DEMOD_WRITE, 0x34, 0x30},
343 {DEMOD_WRITE, 0x35, 0xff},
344 {DEMOD_WRITE, 0x38, 0x50},
345 {DEMOD_WRITE, 0x39, 0x68},
346 {DEMOD_WRITE, 0x3c, 0x7f},
347 {DEMOD_WRITE, 0x3d, 0x0f},
348 {DEMOD_WRITE, 0x45, 0x20},
349 {DEMOD_WRITE, 0x46, 0x24},
350 {DEMOD_WRITE, 0x47, 0x7c},
351 {DEMOD_WRITE, 0x48, 0x16},
352 {DEMOD_WRITE, 0x49, 0x04},
353 {DEMOD_WRITE, 0x4a, 0x01},
354 {DEMOD_WRITE, 0x4b, 0x78},
355 {DEMOD_WRITE, 0X4d, 0xd2},
356 {DEMOD_WRITE, 0x4e, 0x6d},
357 {DEMOD_WRITE, 0x50, 0x30},
358 {DEMOD_WRITE, 0x51, 0x30},
359 {DEMOD_WRITE, 0x54, 0x7b},
360 {DEMOD_WRITE, 0x56, 0x09},
361 {DEMOD_WRITE, 0x58, 0x59},
362 {DEMOD_WRITE, 0x59, 0x37},
363 {DEMOD_WRITE, 0x63, 0xfa},
364 {0xff, 0xaa, 0xff}
365};
366
367static struct inittab fe_trigger[] = {
368 {DEMOD_WRITE, 0x97, 0x04},
369 {DEMOD_WRITE, 0x99, 0x77},
370 {DEMOD_WRITE, 0x9b, 0x64},
371 {DEMOD_WRITE, 0x9e, 0x00},
372 {DEMOD_WRITE, 0x9f, 0xf8},
373 {DEMOD_WRITE, 0x98, 0xff},
374 {DEMOD_WRITE, 0xc0, 0x0f},
375 {DEMOD_WRITE, 0x89, 0x01},
376 {DEMOD_WRITE, 0x00, 0x00},
377 {WRITE_DELAY, 0x0a, 0x00},
378 {DEMOD_WRITE, 0x00, 0x01},
379 {DEMOD_WRITE, 0x00, 0x00},
380 {DEMOD_WRITE, 0x9a, 0xb0},
381 {0xff, 0xaa, 0xff}
382};
383
384static int m88rs2000_tab_set(struct m88rs2000_state *state,
385 struct inittab *tab)
386{
387 int ret = 0;
388 u8 i;
389 if (tab == NULL)
390 return -EINVAL;
391
392 for (i = 0; i < 255; i++) {
393 switch (tab[i].cmd) {
394 case 0x01:
395 ret = m88rs2000_writereg(state, tab[i].reg,
396 tab[i].val);
397 break;
398 case 0x10:
399 if (tab[i].reg > 0)
400 mdelay(tab[i].reg);
401 break;
402 case 0xff:
403 if (tab[i].reg == 0xaa && tab[i].val == 0xff)
404 return 0;
405 case 0x00:
406 break;
407 default:
408 return -EINVAL;
409 }
410 if (ret < 0)
411 return -ENODEV;
412 }
413 return 0;
414}
415
416static int m88rs2000_set_voltage(struct dvb_frontend *fe,
417 enum fe_sec_voltage volt)
418{
419 struct m88rs2000_state *state = fe->demodulator_priv;
420 u8 data;
421
422 data = m88rs2000_readreg(state, 0xb2);
423 data |= 0x03;
424
425 switch (volt) {
426 case SEC_VOLTAGE_18:
427 data &= ~0x03;
428 break;
429 case SEC_VOLTAGE_13:
430 data &= ~0x03;
431 data |= 0x01;
432 break;
433 case SEC_VOLTAGE_OFF:
434 break;
435 }
436
437 m88rs2000_writereg(state, 0xb2, data);
438
439 return 0;
440}
441
442static int m88rs2000_init(struct dvb_frontend *fe)
443{
444 struct m88rs2000_state *state = fe->demodulator_priv;
445 int ret;
446
447 deb_info("m88rs2000: init chip\n");
448
449 if (state->config->inittab)
450 ret = m88rs2000_tab_set(state,
451 (struct inittab *)state->config->inittab);
452 else
453 ret = m88rs2000_tab_set(state, m88rs2000_setup);
454
455 return ret;
456}
457
458static int m88rs2000_sleep(struct dvb_frontend *fe)
459{
460 struct m88rs2000_state *state = fe->demodulator_priv;
461 int ret;
462
463 ret = m88rs2000_tab_set(state, m88rs2000_shutdown);
464 return ret;
465}
466
467static int m88rs2000_read_status(struct dvb_frontend *fe,
468 enum fe_status *status)
469{
470 struct m88rs2000_state *state = fe->demodulator_priv;
471 u8 reg = m88rs2000_readreg(state, 0x8c);
472
473 *status = 0;
474
475 if ((reg & 0xee) == 0xee) {
476 *status = FE_HAS_CARRIER | FE_HAS_SIGNAL | FE_HAS_VITERBI
477 | FE_HAS_SYNC | FE_HAS_LOCK;
478 if (state->config->set_ts_params)
479 state->config->set_ts_params(fe, CALL_IS_READ);
480 }
481 return 0;
482}
483
484static int m88rs2000_read_ber(struct dvb_frontend *fe, u32 *ber)
485{
486 struct m88rs2000_state *state = fe->demodulator_priv;
487 u8 tmp0, tmp1;
488
489 m88rs2000_writereg(state, 0x9a, 0x30);
490 tmp0 = m88rs2000_readreg(state, 0xd8);
491 if ((tmp0 & 0x10) != 0) {
492 m88rs2000_writereg(state, 0x9a, 0xb0);
493 *ber = 0xffffffff;
494 return 0;
495 }
496
497 *ber = (m88rs2000_readreg(state, 0xd7) << 8) |
498 m88rs2000_readreg(state, 0xd6);
499
500 tmp1 = m88rs2000_readreg(state, 0xd9);
501 m88rs2000_writereg(state, 0xd9, (tmp1 & ~7) | 4);
502
503 m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
504 m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
505 m88rs2000_writereg(state, 0x9a, 0xb0);
506
507 return 0;
508}
509
510static int m88rs2000_read_signal_strength(struct dvb_frontend *fe,
511 u16 *strength)
512{
513 if (fe->ops.tuner_ops.get_rf_strength)
514 fe->ops.tuner_ops.get_rf_strength(fe, strength);
515
516 return 0;
517}
518
519static int m88rs2000_read_snr(struct dvb_frontend *fe, u16 *snr)
520{
521 struct m88rs2000_state *state = fe->demodulator_priv;
522
523 *snr = 512 * m88rs2000_readreg(state, 0x65);
524
525 return 0;
526}
527
528static int m88rs2000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
529{
530 struct m88rs2000_state *state = fe->demodulator_priv;
531 u8 tmp;
532
533 *ucblocks = (m88rs2000_readreg(state, 0xd5) << 8) |
534 m88rs2000_readreg(state, 0xd4);
535 tmp = m88rs2000_readreg(state, 0xd8);
536 m88rs2000_writereg(state, 0xd8, tmp & ~0x20);
537
538 m88rs2000_writereg(state, 0xd8, tmp | 0x20);
539 m88rs2000_writereg(state, 0xd8, tmp | 0x20);
540
541 return 0;
542}
543
544static int m88rs2000_set_fec(struct m88rs2000_state *state,
545 enum fe_code_rate fec)
546{
547 u8 fec_set, reg;
548 int ret;
549
550 switch (fec) {
551 case FEC_1_2:
552 fec_set = 0x8;
553 break;
554 case FEC_2_3:
555 fec_set = 0x10;
556 break;
557 case FEC_3_4:
558 fec_set = 0x20;
559 break;
560 case FEC_5_6:
561 fec_set = 0x40;
562 break;
563 case FEC_7_8:
564 fec_set = 0x80;
565 break;
566 case FEC_AUTO:
567 default:
568 fec_set = 0x0;
569 }
570
571 reg = m88rs2000_readreg(state, 0x70);
572 reg &= 0x7;
573 ret = m88rs2000_writereg(state, 0x70, reg | fec_set);
574
575 ret |= m88rs2000_writereg(state, 0x76, 0x8);
576
577 return ret;
578}
579
580static enum fe_code_rate m88rs2000_get_fec(struct m88rs2000_state *state)
581{
582 u8 reg;
583 m88rs2000_writereg(state, 0x9a, 0x30);
584 reg = m88rs2000_readreg(state, 0x76);
585 m88rs2000_writereg(state, 0x9a, 0xb0);
586
587 reg &= 0xf0;
588 reg >>= 5;
589
590 switch (reg) {
591 case 0x4:
592 return FEC_1_2;
593 case 0x3:
594 return FEC_2_3;
595 case 0x2:
596 return FEC_3_4;
597 case 0x1:
598 return FEC_5_6;
599 case 0x0:
600 return FEC_7_8;
601 default:
602 break;
603 }
604
605 return FEC_AUTO;
606}
607
608static int m88rs2000_set_frontend(struct dvb_frontend *fe)
609{
610 struct m88rs2000_state *state = fe->demodulator_priv;
611 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
612 enum fe_status status = 0;
613 int i, ret = 0;
614 u32 tuner_freq;
615 s16 offset = 0;
616 u8 reg;
617
618 state->no_lock_count = 0;
619
620 if (c->delivery_system != SYS_DVBS) {
621 deb_info("%s: unsupported delivery system selected (%d)\n",
622 __func__, c->delivery_system);
623 return -EOPNOTSUPP;
624 }
625
626
627 if (fe->ops.tuner_ops.set_params)
628 ret = fe->ops.tuner_ops.set_params(fe);
629
630 if (ret < 0)
631 return -ENODEV;
632
633 if (fe->ops.tuner_ops.get_frequency) {
634 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_freq);
635
636 if (ret < 0)
637 return -ENODEV;
638
639 offset = (s16)((s32)tuner_freq - c->frequency);
640 } else {
641 offset = 0;
642 }
643
644
645 if (((c->frequency % 192857) >= (192857 - 3000)) ||
646 (c->frequency % 192857) <= 3000)
647 ret = m88rs2000_writereg(state, 0x86, 0xc2);
648 else
649 ret = m88rs2000_writereg(state, 0x86, 0xc6);
650
651 ret |= m88rs2000_set_carrieroffset(fe, offset);
652 if (ret < 0)
653 return -ENODEV;
654
655
656 if (c->symbol_rate > 27500000)
657 ret = m88rs2000_writereg(state, 0xf1, 0xa4);
658 else
659 ret = m88rs2000_writereg(state, 0xf1, 0xbf);
660
661 ret |= m88rs2000_tab_set(state, fe_reset);
662 if (ret < 0)
663 return -ENODEV;
664
665
666 ret = m88rs2000_set_fec(state, c->fec_inner);
667 ret |= m88rs2000_writereg(state, 0x85, 0x1);
668 ret |= m88rs2000_writereg(state, 0x8a, 0xbf);
669 ret |= m88rs2000_writereg(state, 0x8d, 0x1e);
670 ret |= m88rs2000_writereg(state, 0x90, 0xf1);
671 ret |= m88rs2000_writereg(state, 0x91, 0x08);
672
673 if (ret < 0)
674 return -ENODEV;
675
676
677 ret = m88rs2000_set_symbolrate(fe, c->symbol_rate);
678 if (ret < 0)
679 return -ENODEV;
680
681
682 ret = m88rs2000_tab_set(state, fe_trigger);
683 if (ret < 0)
684 return -ENODEV;
685
686 for (i = 0; i < 25; i++) {
687 reg = m88rs2000_readreg(state, 0x8c);
688 if ((reg & 0xee) == 0xee) {
689 status = FE_HAS_LOCK;
690 break;
691 }
692 state->no_lock_count++;
693 if (state->no_lock_count == 15) {
694 reg = m88rs2000_readreg(state, 0x70);
695 reg ^= 0x4;
696 m88rs2000_writereg(state, 0x70, reg);
697 state->no_lock_count = 0;
698 }
699 msleep(20);
700 }
701
702 if (status & FE_HAS_LOCK) {
703 state->fec_inner = m88rs2000_get_fec(state);
704
705 reg = m88rs2000_readreg(state, 0x65);
706 }
707
708 state->tuner_frequency = c->frequency;
709 state->symbol_rate = c->symbol_rate;
710 return 0;
711}
712
713static int m88rs2000_get_frontend(struct dvb_frontend *fe,
714 struct dtv_frontend_properties *c)
715{
716 struct m88rs2000_state *state = fe->demodulator_priv;
717
718 c->fec_inner = state->fec_inner;
719 c->frequency = state->tuner_frequency;
720 c->symbol_rate = state->symbol_rate;
721 return 0;
722}
723
724static int m88rs2000_get_tune_settings(struct dvb_frontend *fe,
725 struct dvb_frontend_tune_settings *tune)
726{
727 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
728
729 if (c->symbol_rate > 3000000)
730 tune->min_delay_ms = 2000;
731 else
732 tune->min_delay_ms = 3000;
733
734 tune->step_size = c->symbol_rate / 16000;
735 tune->max_drift = c->symbol_rate / 2000;
736
737 return 0;
738}
739
740static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
741{
742 struct m88rs2000_state *state = fe->demodulator_priv;
743
744 if (enable)
745 m88rs2000_writereg(state, 0x81, 0x84);
746 else
747 m88rs2000_writereg(state, 0x81, 0x81);
748 udelay(10);
749 return 0;
750}
751
752static void m88rs2000_release(struct dvb_frontend *fe)
753{
754 struct m88rs2000_state *state = fe->demodulator_priv;
755 kfree(state);
756}
757
758static const struct dvb_frontend_ops m88rs2000_ops = {
759 .delsys = { SYS_DVBS },
760 .info = {
761 .name = "M88RS2000 DVB-S",
762 .frequency_min = 950000,
763 .frequency_max = 2150000,
764 .frequency_stepsize = 1000,
765 .frequency_tolerance = 5000,
766 .symbol_rate_min = 1000000,
767 .symbol_rate_max = 45000000,
768 .symbol_rate_tolerance = 500,
769 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
770 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
771 FE_CAN_QPSK | FE_CAN_INVERSION_AUTO |
772 FE_CAN_FEC_AUTO
773 },
774
775 .release = m88rs2000_release,
776 .init = m88rs2000_init,
777 .sleep = m88rs2000_sleep,
778 .i2c_gate_ctrl = m88rs2000_i2c_gate_ctrl,
779 .read_status = m88rs2000_read_status,
780 .read_ber = m88rs2000_read_ber,
781 .read_signal_strength = m88rs2000_read_signal_strength,
782 .read_snr = m88rs2000_read_snr,
783 .read_ucblocks = m88rs2000_read_ucblocks,
784 .diseqc_send_master_cmd = m88rs2000_send_diseqc_msg,
785 .diseqc_send_burst = m88rs2000_send_diseqc_burst,
786 .set_tone = m88rs2000_set_tone,
787 .set_voltage = m88rs2000_set_voltage,
788
789 .set_frontend = m88rs2000_set_frontend,
790 .get_frontend = m88rs2000_get_frontend,
791 .get_tune_settings = m88rs2000_get_tune_settings,
792};
793
794struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config,
795 struct i2c_adapter *i2c)
796{
797 struct m88rs2000_state *state = NULL;
798
799
800 state = kzalloc(sizeof(struct m88rs2000_state), GFP_KERNEL);
801 if (state == NULL)
802 goto error;
803
804
805 state->config = config;
806 state->i2c = i2c;
807 state->tuner_frequency = 0;
808 state->symbol_rate = 0;
809 state->fec_inner = 0;
810
811
812 memcpy(&state->frontend.ops, &m88rs2000_ops,
813 sizeof(struct dvb_frontend_ops));
814 state->frontend.demodulator_priv = state;
815 return &state->frontend;
816
817error:
818 kfree(state);
819
820 return NULL;
821}
822EXPORT_SYMBOL(m88rs2000_attach);
823
824MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver");
825MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
826MODULE_LICENSE("GPL");
827MODULE_VERSION("1.13");
828
829
