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13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
21#include <linux/videodev2.h>
22#include <media/v4l2-event.h>
23#include <linux/workqueue.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/of_reserved_mem.h>
27#include <media/videobuf2-v4l2.h>
28#include "s5p_mfc_common.h"
29#include "s5p_mfc_ctrl.h"
30#include "s5p_mfc_debug.h"
31#include "s5p_mfc_dec.h"
32#include "s5p_mfc_enc.h"
33#include "s5p_mfc_intr.h"
34#include "s5p_mfc_iommu.h"
35#include "s5p_mfc_opr.h"
36#include "s5p_mfc_cmd.h"
37#include "s5p_mfc_pm.h"
38
39#define S5P_MFC_DEC_NAME "s5p-mfc-dec"
40#define S5P_MFC_ENC_NAME "s5p-mfc-enc"
41
42int mfc_debug_level;
43module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
44MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
45
46static char *mfc_mem_size;
47module_param_named(mem, mfc_mem_size, charp, 0644);
48MODULE_PARM_DESC(mem, "Preallocated memory size for the firmware and context buffers");
49
50
51
52
53void clear_work_bit(struct s5p_mfc_ctx *ctx)
54{
55 struct s5p_mfc_dev *dev = ctx->dev;
56
57 spin_lock(&dev->condlock);
58 __clear_bit(ctx->num, &dev->ctx_work_bits);
59 spin_unlock(&dev->condlock);
60}
61
62
63void set_work_bit(struct s5p_mfc_ctx *ctx)
64{
65 struct s5p_mfc_dev *dev = ctx->dev;
66
67 spin_lock(&dev->condlock);
68 __set_bit(ctx->num, &dev->ctx_work_bits);
69 spin_unlock(&dev->condlock);
70}
71
72
73void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
74{
75 struct s5p_mfc_dev *dev = ctx->dev;
76 unsigned long flags;
77
78 spin_lock_irqsave(&dev->condlock, flags);
79 __clear_bit(ctx->num, &dev->ctx_work_bits);
80 spin_unlock_irqrestore(&dev->condlock, flags);
81}
82
83
84void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
85{
86 struct s5p_mfc_dev *dev = ctx->dev;
87 unsigned long flags;
88
89 spin_lock_irqsave(&dev->condlock, flags);
90 __set_bit(ctx->num, &dev->ctx_work_bits);
91 spin_unlock_irqrestore(&dev->condlock, flags);
92}
93
94int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
95{
96 unsigned long flags;
97 int ctx;
98
99 spin_lock_irqsave(&dev->condlock, flags);
100 ctx = dev->curr_ctx;
101 do {
102 ctx = (ctx + 1) % MFC_NUM_CONTEXTS;
103 if (ctx == dev->curr_ctx) {
104 if (!test_bit(ctx, &dev->ctx_work_bits))
105 ctx = -EAGAIN;
106 break;
107 }
108 } while (!test_bit(ctx, &dev->ctx_work_bits));
109 spin_unlock_irqrestore(&dev->condlock, flags);
110
111 return ctx;
112}
113
114
115static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
116 unsigned int err)
117{
118 ctx->int_cond = 1;
119 ctx->int_type = reason;
120 ctx->int_err = err;
121 wake_up(&ctx->queue);
122}
123
124
125static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
126 unsigned int err)
127{
128 dev->int_cond = 1;
129 dev->int_type = reason;
130 dev->int_err = err;
131 wake_up(&dev->queue);
132}
133
134void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq)
135{
136 struct s5p_mfc_buf *b;
137 int i;
138
139 while (!list_empty(lh)) {
140 b = list_entry(lh->next, struct s5p_mfc_buf, list);
141 for (i = 0; i < b->b->vb2_buf.num_planes; i++)
142 vb2_set_plane_payload(&b->b->vb2_buf, i, 0);
143 vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR);
144 list_del(&b->list);
145 }
146}
147
148static void s5p_mfc_watchdog(struct timer_list *t)
149{
150 struct s5p_mfc_dev *dev = from_timer(dev, t, watchdog_timer);
151
152 if (test_bit(0, &dev->hw_lock))
153 atomic_inc(&dev->watchdog_cnt);
154 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
155
156
157
158
159
160 mfc_err("Time out during waiting for HW\n");
161 schedule_work(&dev->watchdog_work);
162 }
163 dev->watchdog_timer.expires = jiffies +
164 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
165 add_timer(&dev->watchdog_timer);
166}
167
168static void s5p_mfc_watchdog_worker(struct work_struct *work)
169{
170 struct s5p_mfc_dev *dev;
171 struct s5p_mfc_ctx *ctx;
172 unsigned long flags;
173 int mutex_locked;
174 int i, ret;
175
176 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
177
178 mfc_err("Driver timeout error handling\n");
179
180
181 mutex_locked = mutex_trylock(&dev->mfc_mutex);
182 if (!mutex_locked)
183 mfc_err("Error: some instance may be closing/opening\n");
184 spin_lock_irqsave(&dev->irqlock, flags);
185
186 s5p_mfc_clock_off();
187
188 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
189 ctx = dev->ctx[i];
190 if (!ctx)
191 continue;
192 ctx->state = MFCINST_ERROR;
193 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
194 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
195 clear_work_bit(ctx);
196 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
197 }
198 clear_bit(0, &dev->hw_lock);
199 spin_unlock_irqrestore(&dev->irqlock, flags);
200
201
202 s5p_mfc_deinit_hw(dev);
203
204
205
206 if (dev->num_inst > 0) {
207 ret = s5p_mfc_load_firmware(dev);
208 if (ret) {
209 mfc_err("Failed to reload FW\n");
210 goto unlock;
211 }
212 s5p_mfc_clock_on();
213 ret = s5p_mfc_init_hw(dev);
214 s5p_mfc_clock_off();
215 if (ret)
216 mfc_err("Failed to reinit FW\n");
217 }
218unlock:
219 if (mutex_locked)
220 mutex_unlock(&dev->mfc_mutex);
221}
222
223static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
224{
225 struct s5p_mfc_buf *dst_buf;
226 struct s5p_mfc_dev *dev = ctx->dev;
227
228 ctx->state = MFCINST_FINISHED;
229 ctx->sequence++;
230 while (!list_empty(&ctx->dst_queue)) {
231 dst_buf = list_entry(ctx->dst_queue.next,
232 struct s5p_mfc_buf, list);
233 mfc_debug(2, "Cleaning up buffer: %d\n",
234 dst_buf->b->vb2_buf.index);
235 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
236 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
237 list_del(&dst_buf->list);
238 dst_buf->flags |= MFC_BUF_FLAG_EOS;
239 ctx->dst_queue_cnt--;
240 dst_buf->b->sequence = (ctx->sequence++);
241
242 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
243 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
244 dst_buf->b->field = V4L2_FIELD_NONE;
245 else
246 dst_buf->b->field = V4L2_FIELD_INTERLACED;
247 dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
248
249 ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
250 vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
251 }
252}
253
254static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
255{
256 struct s5p_mfc_dev *dev = ctx->dev;
257 struct s5p_mfc_buf *dst_buf, *src_buf;
258 size_t dec_y_addr;
259 unsigned int frame_type;
260
261
262 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
263 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
264 return;
265 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
266
267
268
269 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
270 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
271 if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
272 == dec_y_addr) {
273 dst_buf->b->timecode =
274 src_buf->b->timecode;
275 dst_buf->b->vb2_buf.timestamp =
276 src_buf->b->vb2_buf.timestamp;
277 dst_buf->b->flags &=
278 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
279 dst_buf->b->flags |=
280 src_buf->b->flags
281 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
282 switch (frame_type) {
283 case S5P_FIMV_DECODE_FRAME_I_FRAME:
284 dst_buf->b->flags |=
285 V4L2_BUF_FLAG_KEYFRAME;
286 break;
287 case S5P_FIMV_DECODE_FRAME_P_FRAME:
288 dst_buf->b->flags |=
289 V4L2_BUF_FLAG_PFRAME;
290 break;
291 case S5P_FIMV_DECODE_FRAME_B_FRAME:
292 dst_buf->b->flags |=
293 V4L2_BUF_FLAG_BFRAME;
294 break;
295 default:
296
297
298 mfc_debug(2, "Unexpected frame type: %d\n",
299 frame_type);
300 }
301 break;
302 }
303 }
304}
305
306static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
307{
308 struct s5p_mfc_dev *dev = ctx->dev;
309 struct s5p_mfc_buf *dst_buf;
310 size_t dspl_y_addr;
311 unsigned int frame_type;
312
313 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
314 if (IS_MFCV6_PLUS(dev))
315 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
316 get_disp_frame_type, ctx);
317 else
318 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
319 get_dec_frame_type, dev);
320
321
322 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
323 if (!ctx->after_packed_pb)
324 ctx->sequence++;
325 ctx->after_packed_pb = 0;
326 return;
327 }
328 ctx->sequence++;
329
330
331 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
332
333 if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
334 == dspl_y_addr) {
335 list_del(&dst_buf->list);
336 ctx->dst_queue_cnt--;
337 dst_buf->b->sequence = ctx->sequence;
338 if (s5p_mfc_hw_call(dev->mfc_ops,
339 get_pic_type_top, ctx) ==
340 s5p_mfc_hw_call(dev->mfc_ops,
341 get_pic_type_bot, ctx))
342 dst_buf->b->field = V4L2_FIELD_NONE;
343 else
344 dst_buf->b->field =
345 V4L2_FIELD_INTERLACED;
346 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
347 ctx->luma_size);
348 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
349 ctx->chroma_size);
350 clear_bit(dst_buf->b->vb2_buf.index,
351 &ctx->dec_dst_flag);
352
353 vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
354 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
355
356 break;
357 }
358 }
359}
360
361
362static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
363 unsigned int reason, unsigned int err)
364{
365 struct s5p_mfc_dev *dev = ctx->dev;
366 unsigned int dst_frame_status;
367 unsigned int dec_frame_status;
368 struct s5p_mfc_buf *src_buf;
369 unsigned int res_change;
370
371 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
372 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
373 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
374 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
375 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
376 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
377 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
378 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
379 if (ctx->state == MFCINST_RES_CHANGE_INIT)
380 ctx->state = MFCINST_RES_CHANGE_FLUSH;
381 if (res_change == S5P_FIMV_RES_INCREASE ||
382 res_change == S5P_FIMV_RES_DECREASE) {
383 ctx->state = MFCINST_RES_CHANGE_INIT;
384 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
385 wake_up_ctx(ctx, reason, err);
386 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
387 s5p_mfc_clock_off();
388 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
389 return;
390 }
391 if (ctx->dpb_flush_flag)
392 ctx->dpb_flush_flag = 0;
393
394
395 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
396 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
397 static const struct v4l2_event ev_src_ch = {
398 .type = V4L2_EVENT_SOURCE_CHANGE,
399 .u.src_change.changes =
400 V4L2_EVENT_SRC_CH_RESOLUTION,
401 };
402
403 s5p_mfc_handle_frame_all_extracted(ctx);
404 ctx->state = MFCINST_RES_CHANGE_END;
405 v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
406
407 goto leave_handle_frame;
408 } else {
409 s5p_mfc_handle_frame_all_extracted(ctx);
410 }
411 }
412
413 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
414 s5p_mfc_handle_frame_copy_time(ctx);
415
416
417 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
418 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
419 s5p_mfc_handle_frame_new(ctx, err);
420 } else {
421 mfc_debug(2, "No frame decode\n");
422 }
423
424 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
425 && !list_empty(&ctx->src_queue)) {
426 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
427 list);
428 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
429 get_consumed_stream, dev);
430 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
431 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
432 ctx->consumed_stream + STUFF_BYTE <
433 src_buf->b->vb2_buf.planes[0].bytesused) {
434
435 mfc_debug(2, "Running again the same buffer\n");
436 ctx->after_packed_pb = 1;
437 } else {
438 mfc_debug(2, "MFC needs next buffer\n");
439 ctx->consumed_stream = 0;
440 if (src_buf->flags & MFC_BUF_FLAG_EOS)
441 ctx->state = MFCINST_FINISHING;
442 list_del(&src_buf->list);
443 ctx->src_queue_cnt--;
444 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
445 vb2_buffer_done(&src_buf->b->vb2_buf,
446 VB2_BUF_STATE_ERROR);
447 else
448 vb2_buffer_done(&src_buf->b->vb2_buf,
449 VB2_BUF_STATE_DONE);
450 }
451 }
452leave_handle_frame:
453 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
454 || ctx->dst_queue_cnt < ctx->pb_count)
455 clear_work_bit(ctx);
456 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
457 wake_up_ctx(ctx, reason, err);
458 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
459 s5p_mfc_clock_off();
460
461 if (test_bit(0, &dev->enter_suspend))
462 wake_up_dev(dev, reason, err);
463 else
464 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
465}
466
467
468static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
469 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
470{
471 mfc_err("Interrupt Error: %08x\n", err);
472
473 if (ctx) {
474
475 switch (ctx->state) {
476 case MFCINST_RES_CHANGE_INIT:
477 case MFCINST_RES_CHANGE_FLUSH:
478 case MFCINST_RES_CHANGE_END:
479 case MFCINST_FINISHING:
480 case MFCINST_FINISHED:
481 case MFCINST_RUNNING:
482
483
484 clear_work_bit(ctx);
485 ctx->state = MFCINST_ERROR;
486
487 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
488
489 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
490 wake_up_ctx(ctx, reason, err);
491 break;
492 default:
493 clear_work_bit(ctx);
494 ctx->state = MFCINST_ERROR;
495 wake_up_ctx(ctx, reason, err);
496 break;
497 }
498 }
499 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
500 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
501 s5p_mfc_clock_off();
502 wake_up_dev(dev, reason, err);
503}
504
505
506static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
507 unsigned int reason, unsigned int err)
508{
509 struct s5p_mfc_dev *dev;
510
511 if (!ctx)
512 return;
513 dev = ctx->dev;
514 if (ctx->c_ops->post_seq_start) {
515 if (ctx->c_ops->post_seq_start(ctx))
516 mfc_err("post_seq_start() failed\n");
517 } else {
518 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
519 dev);
520 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
521 dev);
522
523 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
524
525 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
526 dev);
527 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
528 dev);
529 ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops,
530 get_min_scratch_buf_size, dev);
531 if (ctx->img_width == 0 || ctx->img_height == 0)
532 ctx->state = MFCINST_ERROR;
533 else
534 ctx->state = MFCINST_HEAD_PARSED;
535
536 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
537 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
538 !list_empty(&ctx->src_queue)) {
539 struct s5p_mfc_buf *src_buf;
540 src_buf = list_entry(ctx->src_queue.next,
541 struct s5p_mfc_buf, list);
542 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
543 dev) <
544 src_buf->b->vb2_buf.planes[0].bytesused)
545 ctx->head_processed = 0;
546 else
547 ctx->head_processed = 1;
548 } else {
549 ctx->head_processed = 1;
550 }
551 }
552 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
553 clear_work_bit(ctx);
554 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
555 s5p_mfc_clock_off();
556 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
557 wake_up_ctx(ctx, reason, err);
558}
559
560
561static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
562 unsigned int reason, unsigned int err)
563{
564 struct s5p_mfc_buf *src_buf;
565 struct s5p_mfc_dev *dev;
566
567 if (!ctx)
568 return;
569 dev = ctx->dev;
570 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
571 ctx->int_type = reason;
572 ctx->int_err = err;
573 ctx->int_cond = 1;
574 clear_work_bit(ctx);
575 if (err == 0) {
576 ctx->state = MFCINST_RUNNING;
577 if (!ctx->dpb_flush_flag && ctx->head_processed) {
578 if (!list_empty(&ctx->src_queue)) {
579 src_buf = list_entry(ctx->src_queue.next,
580 struct s5p_mfc_buf, list);
581 list_del(&src_buf->list);
582 ctx->src_queue_cnt--;
583 vb2_buffer_done(&src_buf->b->vb2_buf,
584 VB2_BUF_STATE_DONE);
585 }
586 } else {
587 ctx->dpb_flush_flag = 0;
588 }
589 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
590
591 s5p_mfc_clock_off();
592
593 wake_up(&ctx->queue);
594 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
595 } else {
596 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
597
598 s5p_mfc_clock_off();
599
600 wake_up(&ctx->queue);
601 }
602}
603
604static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
605{
606 struct s5p_mfc_dev *dev = ctx->dev;
607 struct s5p_mfc_buf *mb_entry;
608
609 mfc_debug(2, "Stream completed\n");
610
611 ctx->state = MFCINST_FINISHED;
612
613 if (!list_empty(&ctx->dst_queue)) {
614 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
615 list);
616 list_del(&mb_entry->list);
617 ctx->dst_queue_cnt--;
618 vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
619 vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
620 }
621
622 clear_work_bit(ctx);
623
624 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
625
626 s5p_mfc_clock_off();
627 wake_up(&ctx->queue);
628 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
629}
630
631
632static irqreturn_t s5p_mfc_irq(int irq, void *priv)
633{
634 struct s5p_mfc_dev *dev = priv;
635 struct s5p_mfc_ctx *ctx;
636 unsigned int reason;
637 unsigned int err;
638
639 mfc_debug_enter();
640
641 atomic_set(&dev->watchdog_cnt, 0);
642 spin_lock(&dev->irqlock);
643 ctx = dev->ctx[dev->curr_ctx];
644
645 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
646 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
647 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
648 switch (reason) {
649 case S5P_MFC_R2H_CMD_ERR_RET:
650
651 if (ctx->state == MFCINST_RUNNING &&
652 (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
653 dev->warn_start ||
654 err == S5P_FIMV_ERR_NO_VALID_SEQ_HDR ||
655 err == S5P_FIMV_ERR_INCOMPLETE_FRAME ||
656 err == S5P_FIMV_ERR_TIMEOUT))
657 s5p_mfc_handle_frame(ctx, reason, err);
658 else
659 s5p_mfc_handle_error(dev, ctx, reason, err);
660 clear_bit(0, &dev->enter_suspend);
661 break;
662
663 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
664 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
665 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
666 if (ctx->c_ops->post_frame_start) {
667 if (ctx->c_ops->post_frame_start(ctx))
668 mfc_err("post_frame_start() failed\n");
669
670 if (ctx->state == MFCINST_FINISHING &&
671 list_empty(&ctx->ref_queue)) {
672 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
673 s5p_mfc_handle_stream_complete(ctx);
674 break;
675 }
676 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
677 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
678 s5p_mfc_clock_off();
679 wake_up_ctx(ctx, reason, err);
680 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
681 } else {
682 s5p_mfc_handle_frame(ctx, reason, err);
683 }
684 break;
685
686 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
687 s5p_mfc_handle_seq_done(ctx, reason, err);
688 break;
689
690 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
691 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
692 ctx->state = MFCINST_GOT_INST;
693 goto irq_cleanup_hw;
694
695 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
696 ctx->inst_no = MFC_NO_INSTANCE_SET;
697 ctx->state = MFCINST_FREE;
698 goto irq_cleanup_hw;
699
700 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
701 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
702 case S5P_MFC_R2H_CMD_SLEEP_RET:
703 case S5P_MFC_R2H_CMD_WAKEUP_RET:
704 if (ctx)
705 clear_work_bit(ctx);
706 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
707 clear_bit(0, &dev->hw_lock);
708 clear_bit(0, &dev->enter_suspend);
709 wake_up_dev(dev, reason, err);
710 break;
711
712 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
713 s5p_mfc_handle_init_buffers(ctx, reason, err);
714 break;
715
716 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
717 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
718 ctx->int_type = reason;
719 ctx->int_err = err;
720 s5p_mfc_handle_stream_complete(ctx);
721 break;
722
723 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
724 ctx->state = MFCINST_RUNNING;
725 goto irq_cleanup_hw;
726
727 default:
728 mfc_debug(2, "Unknown int reason\n");
729 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
730 }
731 spin_unlock(&dev->irqlock);
732 mfc_debug_leave();
733 return IRQ_HANDLED;
734irq_cleanup_hw:
735 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
736 ctx->int_type = reason;
737 ctx->int_err = err;
738 ctx->int_cond = 1;
739 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
740 mfc_err("Failed to unlock hw\n");
741
742 s5p_mfc_clock_off();
743 clear_work_bit(ctx);
744 wake_up(&ctx->queue);
745
746 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
747 spin_unlock(&dev->irqlock);
748 mfc_debug(2, "Exit via irq_cleanup_hw\n");
749 return IRQ_HANDLED;
750}
751
752
753static int s5p_mfc_open(struct file *file)
754{
755 struct video_device *vdev = video_devdata(file);
756 struct s5p_mfc_dev *dev = video_drvdata(file);
757 struct s5p_mfc_ctx *ctx = NULL;
758 struct vb2_queue *q;
759 int ret = 0;
760
761 mfc_debug_enter();
762 if (mutex_lock_interruptible(&dev->mfc_mutex))
763 return -ERESTARTSYS;
764 dev->num_inst++;
765
766 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
767 if (!ctx) {
768 ret = -ENOMEM;
769 goto err_alloc;
770 }
771 init_waitqueue_head(&ctx->queue);
772 v4l2_fh_init(&ctx->fh, vdev);
773 file->private_data = &ctx->fh;
774 v4l2_fh_add(&ctx->fh);
775 ctx->dev = dev;
776 INIT_LIST_HEAD(&ctx->src_queue);
777 INIT_LIST_HEAD(&ctx->dst_queue);
778 ctx->src_queue_cnt = 0;
779 ctx->dst_queue_cnt = 0;
780
781 ctx->num = 0;
782 while (dev->ctx[ctx->num]) {
783 ctx->num++;
784 if (ctx->num >= MFC_NUM_CONTEXTS) {
785 mfc_debug(2, "Too many open contexts\n");
786 ret = -EBUSY;
787 goto err_no_ctx;
788 }
789 }
790
791 clear_work_bit_irqsave(ctx);
792 dev->ctx[ctx->num] = ctx;
793 if (vdev == dev->vfd_dec) {
794 ctx->type = MFCINST_DECODER;
795 ctx->c_ops = get_dec_codec_ops();
796 s5p_mfc_dec_init(ctx);
797
798 ret = s5p_mfc_dec_ctrls_setup(ctx);
799 if (ret) {
800 mfc_err("Failed to setup mfc controls\n");
801 goto err_ctrls_setup;
802 }
803 } else if (vdev == dev->vfd_enc) {
804 ctx->type = MFCINST_ENCODER;
805 ctx->c_ops = get_enc_codec_ops();
806
807 INIT_LIST_HEAD(&ctx->ref_queue);
808 ctx->ref_queue_cnt = 0;
809 s5p_mfc_enc_init(ctx);
810
811 ret = s5p_mfc_enc_ctrls_setup(ctx);
812 if (ret) {
813 mfc_err("Failed to setup mfc controls\n");
814 goto err_ctrls_setup;
815 }
816 } else {
817 ret = -ENOENT;
818 goto err_bad_node;
819 }
820 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
821 ctx->inst_no = MFC_NO_INSTANCE_SET;
822
823 if (dev->num_inst == 1) {
824 dev->watchdog_timer.expires = jiffies +
825 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
826 add_timer(&dev->watchdog_timer);
827 ret = s5p_mfc_power_on();
828 if (ret < 0) {
829 mfc_err("power on failed\n");
830 goto err_pwr_enable;
831 }
832 s5p_mfc_clock_on();
833 ret = s5p_mfc_load_firmware(dev);
834 if (ret) {
835 s5p_mfc_clock_off();
836 goto err_load_fw;
837 }
838
839 ret = s5p_mfc_init_hw(dev);
840 s5p_mfc_clock_off();
841 if (ret)
842 goto err_init_hw;
843 }
844
845 q = &ctx->vq_dst;
846 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
847 q->drv_priv = &ctx->fh;
848 q->lock = &dev->mfc_mutex;
849 if (vdev == dev->vfd_dec) {
850 q->io_modes = VB2_MMAP;
851 q->ops = get_dec_queue_ops();
852 } else if (vdev == dev->vfd_enc) {
853 q->io_modes = VB2_MMAP | VB2_USERPTR;
854 q->ops = get_enc_queue_ops();
855 } else {
856 ret = -ENOENT;
857 goto err_queue_init;
858 }
859
860
861
862
863 q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
864 q->mem_ops = &vb2_dma_contig_memops;
865 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
866 ret = vb2_queue_init(q);
867 if (ret) {
868 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
869 goto err_queue_init;
870 }
871
872 q = &ctx->vq_src;
873 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
874 q->drv_priv = &ctx->fh;
875 q->lock = &dev->mfc_mutex;
876 if (vdev == dev->vfd_dec) {
877 q->io_modes = VB2_MMAP;
878 q->ops = get_dec_queue_ops();
879 } else if (vdev == dev->vfd_enc) {
880 q->io_modes = VB2_MMAP | VB2_USERPTR;
881 q->ops = get_enc_queue_ops();
882 } else {
883 ret = -ENOENT;
884 goto err_queue_init;
885 }
886
887
888
889
890
891
892 q->allow_zero_bytesused = 1;
893
894
895
896
897
898 q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
899 q->mem_ops = &vb2_dma_contig_memops;
900 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
901 ret = vb2_queue_init(q);
902 if (ret) {
903 mfc_err("Failed to initialize videobuf2 queue(output)\n");
904 goto err_queue_init;
905 }
906 mutex_unlock(&dev->mfc_mutex);
907 mfc_debug_leave();
908 return ret;
909
910err_queue_init:
911 if (dev->num_inst == 1)
912 s5p_mfc_deinit_hw(dev);
913err_init_hw:
914err_load_fw:
915err_pwr_enable:
916 if (dev->num_inst == 1) {
917 if (s5p_mfc_power_off() < 0)
918 mfc_err("power off failed\n");
919 del_timer_sync(&dev->watchdog_timer);
920 }
921err_ctrls_setup:
922 s5p_mfc_dec_ctrls_delete(ctx);
923err_bad_node:
924 dev->ctx[ctx->num] = NULL;
925err_no_ctx:
926 v4l2_fh_del(&ctx->fh);
927 v4l2_fh_exit(&ctx->fh);
928 kfree(ctx);
929err_alloc:
930 dev->num_inst--;
931 mutex_unlock(&dev->mfc_mutex);
932 mfc_debug_leave();
933 return ret;
934}
935
936
937static int s5p_mfc_release(struct file *file)
938{
939 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
940 struct s5p_mfc_dev *dev = ctx->dev;
941
942
943 mfc_debug_enter();
944 if (dev)
945 mutex_lock(&dev->mfc_mutex);
946 vb2_queue_release(&ctx->vq_src);
947 vb2_queue_release(&ctx->vq_dst);
948 if (dev) {
949 s5p_mfc_clock_on();
950
951
952 clear_work_bit_irqsave(ctx);
953
954
955
956
957 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
958 mfc_debug(2, "Has to free instance\n");
959 s5p_mfc_close_mfc_inst(dev, ctx);
960 }
961
962 if (dev->curr_ctx == ctx->num)
963 clear_bit(0, &dev->hw_lock);
964 dev->num_inst--;
965 if (dev->num_inst == 0) {
966 mfc_debug(2, "Last instance\n");
967 s5p_mfc_deinit_hw(dev);
968 del_timer_sync(&dev->watchdog_timer);
969 s5p_mfc_clock_off();
970 if (s5p_mfc_power_off() < 0)
971 mfc_err("Power off failed\n");
972 } else {
973 mfc_debug(2, "Shutting down clock\n");
974 s5p_mfc_clock_off();
975 }
976 }
977 if (dev)
978 dev->ctx[ctx->num] = NULL;
979 s5p_mfc_dec_ctrls_delete(ctx);
980 v4l2_fh_del(&ctx->fh);
981
982 if (dev)
983 v4l2_fh_exit(&ctx->fh);
984 kfree(ctx);
985 mfc_debug_leave();
986 if (dev)
987 mutex_unlock(&dev->mfc_mutex);
988
989 return 0;
990}
991
992
993static __poll_t s5p_mfc_poll(struct file *file,
994 struct poll_table_struct *wait)
995{
996 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
997 struct s5p_mfc_dev *dev = ctx->dev;
998 struct vb2_queue *src_q, *dst_q;
999 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
1000 __poll_t rc = 0;
1001 unsigned long flags;
1002
1003 mutex_lock(&dev->mfc_mutex);
1004 src_q = &ctx->vq_src;
1005 dst_q = &ctx->vq_dst;
1006
1007
1008
1009
1010
1011 if ((!src_q->streaming || list_empty(&src_q->queued_list))
1012 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
1013 rc = EPOLLERR;
1014 goto end;
1015 }
1016 mutex_unlock(&dev->mfc_mutex);
1017 poll_wait(file, &ctx->fh.wait, wait);
1018 poll_wait(file, &src_q->done_wq, wait);
1019 poll_wait(file, &dst_q->done_wq, wait);
1020 mutex_lock(&dev->mfc_mutex);
1021 if (v4l2_event_pending(&ctx->fh))
1022 rc |= EPOLLPRI;
1023 spin_lock_irqsave(&src_q->done_lock, flags);
1024 if (!list_empty(&src_q->done_list))
1025 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
1026 done_entry);
1027 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
1028 || src_vb->state == VB2_BUF_STATE_ERROR))
1029 rc |= EPOLLOUT | EPOLLWRNORM;
1030 spin_unlock_irqrestore(&src_q->done_lock, flags);
1031 spin_lock_irqsave(&dst_q->done_lock, flags);
1032 if (!list_empty(&dst_q->done_list))
1033 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
1034 done_entry);
1035 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
1036 || dst_vb->state == VB2_BUF_STATE_ERROR))
1037 rc |= EPOLLIN | EPOLLRDNORM;
1038 spin_unlock_irqrestore(&dst_q->done_lock, flags);
1039end:
1040 mutex_unlock(&dev->mfc_mutex);
1041 return rc;
1042}
1043
1044
1045static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
1046{
1047 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
1048 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1049 int ret;
1050
1051 if (offset < DST_QUEUE_OFF_BASE) {
1052 mfc_debug(2, "mmaping source\n");
1053 ret = vb2_mmap(&ctx->vq_src, vma);
1054 } else {
1055 mfc_debug(2, "mmaping destination\n");
1056 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1057 ret = vb2_mmap(&ctx->vq_dst, vma);
1058 }
1059 return ret;
1060}
1061
1062
1063static const struct v4l2_file_operations s5p_mfc_fops = {
1064 .owner = THIS_MODULE,
1065 .open = s5p_mfc_open,
1066 .release = s5p_mfc_release,
1067 .poll = s5p_mfc_poll,
1068 .unlocked_ioctl = video_ioctl2,
1069 .mmap = s5p_mfc_mmap,
1070};
1071
1072
1073static void s5p_mfc_memdev_release(struct device *dev)
1074{
1075 of_reserved_mem_device_release(dev);
1076}
1077
1078static struct device *s5p_mfc_alloc_memdev(struct device *dev,
1079 const char *name, unsigned int idx)
1080{
1081 struct device *child;
1082 int ret;
1083
1084 child = devm_kzalloc(dev, sizeof(*child), GFP_KERNEL);
1085 if (!child)
1086 return NULL;
1087
1088 device_initialize(child);
1089 dev_set_name(child, "%s:%s", dev_name(dev), name);
1090 child->parent = dev;
1091 child->bus = dev->bus;
1092 child->coherent_dma_mask = dev->coherent_dma_mask;
1093 child->dma_mask = dev->dma_mask;
1094 child->release = s5p_mfc_memdev_release;
1095
1096 if (device_add(child) == 0) {
1097 ret = of_reserved_mem_device_init_by_idx(child, dev->of_node,
1098 idx);
1099 if (ret == 0)
1100 return child;
1101 device_del(child);
1102 }
1103
1104 put_device(child);
1105 return NULL;
1106}
1107
1108static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev)
1109{
1110 struct device *dev = &mfc_dev->plat_dev->dev;
1111 void *bank2_virt;
1112 dma_addr_t bank2_dma_addr;
1113 unsigned long align_size = 1 << MFC_BASE_ALIGN_ORDER;
1114 int ret;
1115
1116
1117
1118
1119
1120 mfc_dev->mem_dev[BANK_L_CTX] = s5p_mfc_alloc_memdev(dev, "left",
1121 BANK_L_CTX);
1122 if (!mfc_dev->mem_dev[BANK_L_CTX])
1123 return -ENODEV;
1124 mfc_dev->mem_dev[BANK_R_CTX] = s5p_mfc_alloc_memdev(dev, "right",
1125 BANK_R_CTX);
1126 if (!mfc_dev->mem_dev[BANK_R_CTX]) {
1127 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1128 return -ENODEV;
1129 }
1130
1131
1132 ret = s5p_mfc_alloc_firmware(mfc_dev);
1133 if (ret) {
1134 device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1135 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1136 return ret;
1137 }
1138
1139 mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->fw_buf.dma;
1140
1141 bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK_R_CTX],
1142 align_size, &bank2_dma_addr, GFP_KERNEL);
1143 if (!bank2_virt) {
1144 mfc_err("Allocating bank2 base failed\n");
1145 s5p_mfc_release_firmware(mfc_dev);
1146 device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1147 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1148 return -ENOMEM;
1149 }
1150
1151
1152
1153
1154
1155 mfc_dev->dma_base[BANK_R_CTX] = bank2_dma_addr - align_size;
1156
1157 dma_free_coherent(mfc_dev->mem_dev[BANK_R_CTX], align_size, bank2_virt,
1158 bank2_dma_addr);
1159
1160 vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX],
1161 DMA_BIT_MASK(32));
1162 vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX],
1163 DMA_BIT_MASK(32));
1164
1165 return 0;
1166}
1167
1168static void s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev *mfc_dev)
1169{
1170 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1171 device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1172 vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX]);
1173 vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX]);
1174}
1175
1176static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev)
1177{
1178 struct device *dev = &mfc_dev->plat_dev->dev;
1179 unsigned long mem_size = SZ_4M;
1180 unsigned int bitmap_size;
1181
1182 if (IS_ENABLED(CONFIG_DMA_CMA) || exynos_is_iommu_available(dev))
1183 mem_size = SZ_8M;
1184
1185 if (mfc_mem_size)
1186 mem_size = memparse(mfc_mem_size, NULL);
1187
1188 bitmap_size = BITS_TO_LONGS(mem_size >> PAGE_SHIFT) * sizeof(long);
1189
1190 mfc_dev->mem_bitmap = kzalloc(bitmap_size, GFP_KERNEL);
1191 if (!mfc_dev->mem_bitmap)
1192 return -ENOMEM;
1193
1194 mfc_dev->mem_virt = dma_alloc_coherent(dev, mem_size,
1195 &mfc_dev->mem_base, GFP_KERNEL);
1196 if (!mfc_dev->mem_virt) {
1197 kfree(mfc_dev->mem_bitmap);
1198 dev_err(dev, "failed to preallocate %ld MiB for the firmware and context buffers\n",
1199 (mem_size / SZ_1M));
1200 return -ENOMEM;
1201 }
1202 mfc_dev->mem_size = mem_size;
1203 mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->mem_base;
1204 mfc_dev->dma_base[BANK_R_CTX] = mfc_dev->mem_base;
1205
1206
1207
1208
1209
1210 if (mfc_dev->mem_base == (dma_addr_t)0) {
1211 unsigned int offset = 1 << MFC_BASE_ALIGN_ORDER;
1212
1213 bitmap_set(mfc_dev->mem_bitmap, 0, offset >> PAGE_SHIFT);
1214 mfc_dev->dma_base[BANK_L_CTX] += offset;
1215 mfc_dev->dma_base[BANK_R_CTX] += offset;
1216 }
1217
1218
1219 s5p_mfc_alloc_firmware(mfc_dev);
1220
1221 mfc_dev->mem_dev[BANK_L_CTX] = mfc_dev->mem_dev[BANK_R_CTX] = dev;
1222 vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
1223
1224 dev_info(dev, "preallocated %ld MiB buffer for the firmware and context buffers\n",
1225 (mem_size / SZ_1M));
1226
1227 return 0;
1228}
1229
1230static void s5p_mfc_unconfigure_common_memory(struct s5p_mfc_dev *mfc_dev)
1231{
1232 struct device *dev = &mfc_dev->plat_dev->dev;
1233
1234 dma_free_coherent(dev, mfc_dev->mem_size, mfc_dev->mem_virt,
1235 mfc_dev->mem_base);
1236 kfree(mfc_dev->mem_bitmap);
1237 vb2_dma_contig_clear_max_seg_size(dev);
1238}
1239
1240static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1241{
1242 struct device *dev = &mfc_dev->plat_dev->dev;
1243
1244 if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev))
1245 return s5p_mfc_configure_common_memory(mfc_dev);
1246 else
1247 return s5p_mfc_configure_2port_memory(mfc_dev);
1248}
1249
1250static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1251{
1252 struct device *dev = &mfc_dev->plat_dev->dev;
1253
1254 s5p_mfc_release_firmware(mfc_dev);
1255 if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev))
1256 s5p_mfc_unconfigure_common_memory(mfc_dev);
1257 else
1258 s5p_mfc_unconfigure_2port_memory(mfc_dev);
1259}
1260
1261
1262static int s5p_mfc_probe(struct platform_device *pdev)
1263{
1264 struct s5p_mfc_dev *dev;
1265 struct video_device *vfd;
1266 struct resource *res;
1267 int ret;
1268
1269 pr_debug("%s++\n", __func__);
1270 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1271 if (!dev)
1272 return -ENOMEM;
1273
1274 spin_lock_init(&dev->irqlock);
1275 spin_lock_init(&dev->condlock);
1276 dev->plat_dev = pdev;
1277 if (!dev->plat_dev) {
1278 dev_err(&pdev->dev, "No platform data specified\n");
1279 return -ENODEV;
1280 }
1281
1282 dev->variant = of_device_get_match_data(&pdev->dev);
1283
1284 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1285 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1286 if (IS_ERR(dev->regs_base))
1287 return PTR_ERR(dev->regs_base);
1288
1289 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1290 if (!res) {
1291 dev_err(&pdev->dev, "failed to get irq resource\n");
1292 return -ENOENT;
1293 }
1294 dev->irq = res->start;
1295 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1296 0, pdev->name, dev);
1297 if (ret) {
1298 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1299 return ret;
1300 }
1301
1302 ret = s5p_mfc_configure_dma_memory(dev);
1303 if (ret < 0) {
1304 dev_err(&pdev->dev, "failed to configure DMA memory\n");
1305 return ret;
1306 }
1307
1308 ret = s5p_mfc_init_pm(dev);
1309 if (ret < 0) {
1310 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1311 goto err_dma;
1312 }
1313
1314
1315
1316
1317
1318 s5p_mfc_load_firmware(dev);
1319
1320 mutex_init(&dev->mfc_mutex);
1321 init_waitqueue_head(&dev->queue);
1322 dev->hw_lock = 0;
1323 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1324 atomic_set(&dev->watchdog_cnt, 0);
1325 timer_setup(&dev->watchdog_timer, s5p_mfc_watchdog, 0);
1326
1327 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1328 if (ret)
1329 goto err_v4l2_dev_reg;
1330
1331
1332 vfd = video_device_alloc();
1333 if (!vfd) {
1334 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1335 ret = -ENOMEM;
1336 goto err_dec_alloc;
1337 }
1338 vfd->fops = &s5p_mfc_fops;
1339 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1340 vfd->release = video_device_release;
1341 vfd->lock = &dev->mfc_mutex;
1342 vfd->v4l2_dev = &dev->v4l2_dev;
1343 vfd->vfl_dir = VFL_DIR_M2M;
1344 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1345 dev->vfd_dec = vfd;
1346 video_set_drvdata(vfd, dev);
1347
1348
1349 vfd = video_device_alloc();
1350 if (!vfd) {
1351 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1352 ret = -ENOMEM;
1353 goto err_enc_alloc;
1354 }
1355 vfd->fops = &s5p_mfc_fops;
1356 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1357 vfd->release = video_device_release;
1358 vfd->lock = &dev->mfc_mutex;
1359 vfd->v4l2_dev = &dev->v4l2_dev;
1360 vfd->vfl_dir = VFL_DIR_M2M;
1361 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1362 dev->vfd_enc = vfd;
1363 video_set_drvdata(vfd, dev);
1364 platform_set_drvdata(pdev, dev);
1365
1366
1367 s5p_mfc_init_hw_ops(dev);
1368 s5p_mfc_init_hw_cmds(dev);
1369 s5p_mfc_init_regs(dev);
1370
1371
1372 ret = video_register_device(dev->vfd_dec, VFL_TYPE_GRABBER, 0);
1373 if (ret) {
1374 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1375 goto err_dec_reg;
1376 }
1377 v4l2_info(&dev->v4l2_dev,
1378 "decoder registered as /dev/video%d\n", dev->vfd_dec->num);
1379
1380 ret = video_register_device(dev->vfd_enc, VFL_TYPE_GRABBER, 0);
1381 if (ret) {
1382 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1383 goto err_enc_reg;
1384 }
1385 v4l2_info(&dev->v4l2_dev,
1386 "encoder registered as /dev/video%d\n", dev->vfd_enc->num);
1387
1388 pr_debug("%s--\n", __func__);
1389 return 0;
1390
1391
1392err_enc_reg:
1393 video_unregister_device(dev->vfd_dec);
1394err_dec_reg:
1395 video_device_release(dev->vfd_enc);
1396err_enc_alloc:
1397 video_device_release(dev->vfd_dec);
1398err_dec_alloc:
1399 v4l2_device_unregister(&dev->v4l2_dev);
1400err_v4l2_dev_reg:
1401 s5p_mfc_final_pm(dev);
1402err_dma:
1403 s5p_mfc_unconfigure_dma_memory(dev);
1404
1405 pr_debug("%s-- with error\n", __func__);
1406 return ret;
1407
1408}
1409
1410
1411static int s5p_mfc_remove(struct platform_device *pdev)
1412{
1413 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1414 struct s5p_mfc_ctx *ctx;
1415 int i;
1416
1417 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1418
1419
1420
1421
1422
1423
1424 mutex_lock(&dev->mfc_mutex);
1425 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
1426 ctx = dev->ctx[i];
1427 if (!ctx)
1428 continue;
1429
1430 ctx->dev = NULL;
1431 }
1432 mutex_unlock(&dev->mfc_mutex);
1433
1434 del_timer_sync(&dev->watchdog_timer);
1435 flush_work(&dev->watchdog_work);
1436
1437 video_unregister_device(dev->vfd_enc);
1438 video_unregister_device(dev->vfd_dec);
1439 video_device_release(dev->vfd_enc);
1440 video_device_release(dev->vfd_dec);
1441 v4l2_device_unregister(&dev->v4l2_dev);
1442 s5p_mfc_unconfigure_dma_memory(dev);
1443
1444 s5p_mfc_final_pm(dev);
1445 return 0;
1446}
1447
1448#ifdef CONFIG_PM_SLEEP
1449
1450static int s5p_mfc_suspend(struct device *dev)
1451{
1452 struct platform_device *pdev = to_platform_device(dev);
1453 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1454 int ret;
1455
1456 if (m_dev->num_inst == 0)
1457 return 0;
1458
1459 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1460 mfc_err("Error: going to suspend for a second time\n");
1461 return -EIO;
1462 }
1463
1464
1465 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1466
1467
1468 ret = wait_event_interruptible_timeout(m_dev->queue,
1469 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1470 if (ret == 0) {
1471 mfc_err("Waiting for hardware to finish timed out\n");
1472 clear_bit(0, &m_dev->enter_suspend);
1473 return -EIO;
1474 }
1475 }
1476
1477 ret = s5p_mfc_sleep(m_dev);
1478 if (ret) {
1479 clear_bit(0, &m_dev->enter_suspend);
1480 clear_bit(0, &m_dev->hw_lock);
1481 }
1482 return ret;
1483}
1484
1485static int s5p_mfc_resume(struct device *dev)
1486{
1487 struct platform_device *pdev = to_platform_device(dev);
1488 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1489
1490 if (m_dev->num_inst == 0)
1491 return 0;
1492 return s5p_mfc_wakeup(m_dev);
1493}
1494#endif
1495
1496
1497static const struct dev_pm_ops s5p_mfc_pm_ops = {
1498 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1499};
1500
1501static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1502 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1503 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1504 .dsc = DESC_BUF_SIZE,
1505 .shm = SHARED_BUF_SIZE,
1506};
1507
1508static struct s5p_mfc_buf_size buf_size_v5 = {
1509 .fw = MAX_FW_SIZE,
1510 .cpb = MAX_CPB_SIZE,
1511 .priv = &mfc_buf_size_v5,
1512};
1513
1514static struct s5p_mfc_variant mfc_drvdata_v5 = {
1515 .version = MFC_VERSION,
1516 .version_bit = MFC_V5_BIT,
1517 .port_num = MFC_NUM_PORTS,
1518 .buf_size = &buf_size_v5,
1519 .fw_name[0] = "s5p-mfc.fw",
1520 .clk_names = {"mfc", "sclk_mfc"},
1521 .num_clocks = 2,
1522 .use_clock_gating = true,
1523};
1524
1525static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1526 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1527 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1528 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1529 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1530 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1531};
1532
1533static struct s5p_mfc_buf_size buf_size_v6 = {
1534 .fw = MAX_FW_SIZE_V6,
1535 .cpb = MAX_CPB_SIZE_V6,
1536 .priv = &mfc_buf_size_v6,
1537};
1538
1539static struct s5p_mfc_variant mfc_drvdata_v6 = {
1540 .version = MFC_VERSION_V6,
1541 .version_bit = MFC_V6_BIT,
1542 .port_num = MFC_NUM_PORTS_V6,
1543 .buf_size = &buf_size_v6,
1544 .fw_name[0] = "s5p-mfc-v6.fw",
1545
1546
1547
1548
1549 .fw_name[1] = "s5p-mfc-v6-v2.fw",
1550 .clk_names = {"mfc"},
1551 .num_clocks = 1,
1552};
1553
1554static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1555 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1556 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1557 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1558 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1559 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1560};
1561
1562static struct s5p_mfc_buf_size buf_size_v7 = {
1563 .fw = MAX_FW_SIZE_V7,
1564 .cpb = MAX_CPB_SIZE_V7,
1565 .priv = &mfc_buf_size_v7,
1566};
1567
1568static struct s5p_mfc_variant mfc_drvdata_v7 = {
1569 .version = MFC_VERSION_V7,
1570 .version_bit = MFC_V7_BIT,
1571 .port_num = MFC_NUM_PORTS_V7,
1572 .buf_size = &buf_size_v7,
1573 .fw_name[0] = "s5p-mfc-v7.fw",
1574 .clk_names = {"mfc", "sclk_mfc"},
1575 .num_clocks = 2,
1576};
1577
1578static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1579 .dev_ctx = MFC_CTX_BUF_SIZE_V8,
1580 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1581 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1582 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1583 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1584};
1585
1586static struct s5p_mfc_buf_size buf_size_v8 = {
1587 .fw = MAX_FW_SIZE_V8,
1588 .cpb = MAX_CPB_SIZE_V8,
1589 .priv = &mfc_buf_size_v8,
1590};
1591
1592static struct s5p_mfc_variant mfc_drvdata_v8 = {
1593 .version = MFC_VERSION_V8,
1594 .version_bit = MFC_V8_BIT,
1595 .port_num = MFC_NUM_PORTS_V8,
1596 .buf_size = &buf_size_v8,
1597 .fw_name[0] = "s5p-mfc-v8.fw",
1598 .clk_names = {"mfc"},
1599 .num_clocks = 1,
1600};
1601
1602static struct s5p_mfc_variant mfc_drvdata_v8_5433 = {
1603 .version = MFC_VERSION_V8,
1604 .version_bit = MFC_V8_BIT,
1605 .port_num = MFC_NUM_PORTS_V8,
1606 .buf_size = &buf_size_v8,
1607 .fw_name[0] = "s5p-mfc-v8.fw",
1608 .clk_names = {"pclk", "aclk", "aclk_xiu"},
1609 .num_clocks = 3,
1610};
1611
1612static struct s5p_mfc_buf_size_v6 mfc_buf_size_v10 = {
1613 .dev_ctx = MFC_CTX_BUF_SIZE_V10,
1614 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V10,
1615 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
1616 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V10,
1617 .hevc_enc_ctx = MFC_HEVC_ENC_CTX_BUF_SIZE_V10,
1618 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
1619};
1620
1621static struct s5p_mfc_buf_size buf_size_v10 = {
1622 .fw = MAX_FW_SIZE_V10,
1623 .cpb = MAX_CPB_SIZE_V10,
1624 .priv = &mfc_buf_size_v10,
1625};
1626
1627static struct s5p_mfc_variant mfc_drvdata_v10 = {
1628 .version = MFC_VERSION_V10,
1629 .version_bit = MFC_V10_BIT,
1630 .port_num = MFC_NUM_PORTS_V10,
1631 .buf_size = &buf_size_v10,
1632 .fw_name[0] = "s5p-mfc-v10.fw",
1633};
1634
1635static const struct of_device_id exynos_mfc_match[] = {
1636 {
1637 .compatible = "samsung,mfc-v5",
1638 .data = &mfc_drvdata_v5,
1639 }, {
1640 .compatible = "samsung,mfc-v6",
1641 .data = &mfc_drvdata_v6,
1642 }, {
1643 .compatible = "samsung,mfc-v7",
1644 .data = &mfc_drvdata_v7,
1645 }, {
1646 .compatible = "samsung,mfc-v8",
1647 .data = &mfc_drvdata_v8,
1648 }, {
1649 .compatible = "samsung,exynos5433-mfc",
1650 .data = &mfc_drvdata_v8_5433,
1651 }, {
1652 .compatible = "samsung,mfc-v10",
1653 .data = &mfc_drvdata_v10,
1654 },
1655 {},
1656};
1657MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1658
1659static struct platform_driver s5p_mfc_driver = {
1660 .probe = s5p_mfc_probe,
1661 .remove = s5p_mfc_remove,
1662 .driver = {
1663 .name = S5P_MFC_NAME,
1664 .pm = &s5p_mfc_pm_ops,
1665 .of_match_table = exynos_mfc_match,
1666 },
1667};
1668
1669module_platform_driver(s5p_mfc_driver);
1670
1671MODULE_LICENSE("GPL");
1672MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1673MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1674
1675
