LXR linux/drivers/misc/cxl/cxl.h

   1/*
   2 * Copyright 2014 IBM Corp.
   3 *
   4 * This program is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU General Public License
   6 * as published by the Free Software Foundation; either version
   7 * 2 of the License, or (at your option) any later version.
   8 */
   9
  10#ifndef _CXL_H_
  11#define _CXL_H_
  12
  13#include <linux/interrupt.h>
  14#include <linux/semaphore.h>
  15#include <linux/device.h>
  16#include <linux/types.h>
  17#include <linux/cdev.h>
  18#include <linux/pid.h>
  19#include <linux/io.h>
  20#include <linux/pci.h>
  21#include <linux/fs.h>
  22#include <asm/cputable.h>
  23#include <asm/mmu.h>
  24#include <asm/reg.h>
  25#include <misc/cxl-base.h>
  26
  27#include <misc/cxl.h>
  28#include <uapi/misc/cxl.h>
  29
  30extern uint cxl_verbose;
  31
  32#define CXL_TIMEOUT 5
  33
  34/*
  35 * Bump version each time a user API change is made, whether it is
  36 * backwards compatible ot not.
  37 */
  38#define CXL_API_VERSION 3
  39#define CXL_API_VERSION_COMPATIBLE 1
  40
  41/*
  42 * Opaque types to avoid accidentally passing registers for the wrong MMIO
  43 *
  44 * At the end of the day, I'm not married to using typedef here, but it might
  45 * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
  46 * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
  47 *
  48 * I'm quite happy if these are changed back to #defines before upstreaming, it
  49 * should be little more than a regexp search+replace operation in this file.
  50 */
  51typedef struct {
  52        const int x;
  53} cxl_p1_reg_t;
  54typedef struct {
  55        const int x;
  56} cxl_p1n_reg_t;
  57typedef struct {
  58        const int x;
  59} cxl_p2n_reg_t;
  60#define cxl_reg_off(reg) \
  61        (reg.x)
  62
  63/* Memory maps. Ref CXL Appendix A */
  64
  65/* PSL Privilege 1 Memory Map */
  66/* Configuration and Control area - CAIA 1&2 */
  67static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
  68static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
  69static const cxl_p1_reg_t CXL_PSL_KEY1    = {0x0010};
  70static const cxl_p1_reg_t CXL_PSL_KEY2    = {0x0018};
  71static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
  72/* Downloading */
  73static const cxl_p1_reg_t CXL_PSL_DLCNTL  = {0x0060};
  74static const cxl_p1_reg_t CXL_PSL_DLADDR  = {0x0068};
  75
  76/* PSL Lookaside Buffer Management Area - CAIA 1 */
  77static const cxl_p1_reg_t CXL_PSL_LBISEL  = {0x0080};
  78static const cxl_p1_reg_t CXL_PSL_SLBIE   = {0x0088};
  79static const cxl_p1_reg_t CXL_PSL_SLBIA   = {0x0090};
  80static const cxl_p1_reg_t CXL_PSL_TLBIE   = {0x00A0};
  81static const cxl_p1_reg_t CXL_PSL_TLBIA   = {0x00A8};
  82static const cxl_p1_reg_t CXL_PSL_AFUSEL  = {0x00B0};
  83
  84/* 0x00C0:7EFF Implementation dependent area */
  85/* PSL registers - CAIA 1 */
  86static const cxl_p1_reg_t CXL_PSL_FIR1      = {0x0100};
  87static const cxl_p1_reg_t CXL_PSL_FIR2      = {0x0108};
  88static const cxl_p1_reg_t CXL_PSL_Timebase  = {0x0110};
  89static const cxl_p1_reg_t CXL_PSL_VERSION   = {0x0118};
  90static const cxl_p1_reg_t CXL_PSL_RESLCKTO  = {0x0128};
  91static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
  92static const cxl_p1_reg_t CXL_PSL_FIR_CNTL  = {0x0148};
  93static const cxl_p1_reg_t CXL_PSL_DSNDCTL   = {0x0150};
  94static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
  95static const cxl_p1_reg_t CXL_PSL_TRACE     = {0x0170};
  96/* XSL registers (Mellanox CX4) */
  97static const cxl_p1_reg_t CXL_XSL_Timebase  = {0x0100};
  98static const cxl_p1_reg_t CXL_XSL_TB_CTLSTAT = {0x0108};
  99static const cxl_p1_reg_t CXL_XSL_FEC       = {0x0158};
 100static const cxl_p1_reg_t CXL_XSL_DSNCTL    = {0x0168};
 101/* PSL registers - CAIA 2 */
 102static const cxl_p1_reg_t CXL_PSL9_CONTROL  = {0x0020};
 103static const cxl_p1_reg_t CXL_XSL9_INV      = {0x0110};
 104static const cxl_p1_reg_t CXL_XSL9_DBG      = {0x0130};
 105static const cxl_p1_reg_t CXL_XSL9_DEF      = {0x0140};
 106static const cxl_p1_reg_t CXL_XSL9_DSNCTL   = {0x0168};
 107static const cxl_p1_reg_t CXL_PSL9_FIR1     = {0x0300};
 108static const cxl_p1_reg_t CXL_PSL9_FIR_MASK = {0x0308};
 109static const cxl_p1_reg_t CXL_PSL9_Timebase = {0x0310};
 110static const cxl_p1_reg_t CXL_PSL9_DEBUG    = {0x0320};
 111static const cxl_p1_reg_t CXL_PSL9_FIR_CNTL = {0x0348};
 112static const cxl_p1_reg_t CXL_PSL9_DSNDCTL  = {0x0350};
 113static const cxl_p1_reg_t CXL_PSL9_TB_CTLSTAT = {0x0340};
 114static const cxl_p1_reg_t CXL_PSL9_TRACECFG = {0x0368};
 115static const cxl_p1_reg_t CXL_PSL9_APCDEDALLOC = {0x0378};
 116static const cxl_p1_reg_t CXL_PSL9_APCDEDTYPE = {0x0380};
 117static const cxl_p1_reg_t CXL_PSL9_TNR_ADDR = {0x0388};
 118static const cxl_p1_reg_t CXL_PSL9_CTCCFG = {0x0390};
 119static const cxl_p1_reg_t CXL_PSL9_GP_CT = {0x0398};
 120static const cxl_p1_reg_t CXL_XSL9_IERAT = {0x0588};
 121static const cxl_p1_reg_t CXL_XSL9_ILPP  = {0x0590};
 122
 123/* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
 124/* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
 125
 126/* PSL Slice Privilege 1 Memory Map */
 127/* Configuration Area - CAIA 1&2 */
 128static const cxl_p1n_reg_t CXL_PSL_SR_An          = {0x00};
 129static const cxl_p1n_reg_t CXL_PSL_LPID_An        = {0x08};
 130static const cxl_p1n_reg_t CXL_PSL_AMBAR_An       = {0x10};
 131static const cxl_p1n_reg_t CXL_PSL_SPOffset_An    = {0x18};
 132static const cxl_p1n_reg_t CXL_PSL_ID_An          = {0x20};
 133static const cxl_p1n_reg_t CXL_PSL_SERR_An        = {0x28};
 134/* Memory Management and Lookaside Buffer Management - CAIA 1*/
 135static const cxl_p1n_reg_t CXL_PSL_SDR_An         = {0x30};
 136/* Memory Management and Lookaside Buffer Management - CAIA 1&2 */
 137static const cxl_p1n_reg_t CXL_PSL_AMOR_An        = {0x38};
 138/* Pointer Area - CAIA 1&2 */
 139static const cxl_p1n_reg_t CXL_HAURP_An           = {0x80};
 140static const cxl_p1n_reg_t CXL_PSL_SPAP_An        = {0x88};
 141static const cxl_p1n_reg_t CXL_PSL_LLCMD_An       = {0x90};
 142/* Control Area - CAIA 1&2 */
 143static const cxl_p1n_reg_t CXL_PSL_SCNTL_An       = {0xA0};
 144static const cxl_p1n_reg_t CXL_PSL_CtxTime_An     = {0xA8};
 145static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
 146static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An  = {0xB8};
 147/* 0xC0:FF Implementation Dependent Area - CAIA 1&2 */
 148static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An   = {0xC0};
 149static const cxl_p1n_reg_t CXL_AFU_DEBUG_An       = {0xC8};
 150/* 0xC0:FF Implementation Dependent Area - CAIA 1 */
 151static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A     = {0xD0};
 152static const cxl_p1n_reg_t CXL_PSL_COALLOC_A      = {0xD8};
 153static const cxl_p1n_reg_t CXL_PSL_RXCTL_A        = {0xE0};
 154static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE    = {0xE8};
 155
 156/* PSL Slice Privilege 2 Memory Map */
 157/* Configuration and Control Area - CAIA 1&2 */
 158static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
 159static const cxl_p2n_reg_t CXL_CSRP_An        = {0x008};
 160/* Configuration and Control Area - CAIA 1 */
 161static const cxl_p2n_reg_t CXL_AURP0_An       = {0x010};
 162static const cxl_p2n_reg_t CXL_AURP1_An       = {0x018};
 163static const cxl_p2n_reg_t CXL_SSTP0_An       = {0x020};
 164static const cxl_p2n_reg_t CXL_SSTP1_An       = {0x028};
 165/* Configuration and Control Area - CAIA 1 */
 166static const cxl_p2n_reg_t CXL_PSL_AMR_An     = {0x030};
 167/* Segment Lookaside Buffer Management - CAIA 1 */
 168static const cxl_p2n_reg_t CXL_SLBIE_An       = {0x040};
 169static const cxl_p2n_reg_t CXL_SLBIA_An       = {0x048};
 170static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
 171/* Interrupt Registers - CAIA 1&2 */
 172static const cxl_p2n_reg_t CXL_PSL_DSISR_An   = {0x060};
 173static const cxl_p2n_reg_t CXL_PSL_DAR_An     = {0x068};
 174static const cxl_p2n_reg_t CXL_PSL_DSR_An     = {0x070};
 175static const cxl_p2n_reg_t CXL_PSL_TFC_An     = {0x078};
 176static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
 177static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
 178/* AFU Registers - CAIA 1&2 */
 179static const cxl_p2n_reg_t CXL_AFU_Cntl_An    = {0x090};
 180static const cxl_p2n_reg_t CXL_AFU_ERR_An     = {0x098};
 181/* Work Element Descriptor - CAIA 1&2 */
 182static const cxl_p2n_reg_t CXL_PSL_WED_An     = {0x0A0};
 183/* 0x0C0:FFF Implementation Dependent Area */
 184
 185#define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
 186#define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
 187#define CXL_PSL_SPAP_Size_Shift 4
 188#define CXL_PSL_SPAP_V    0x0000000000000001ULL
 189
 190/****** CXL_PSL_Control ****************************************************/
 191#define CXL_PSL_Control_tb              (0x1ull << (63-63))
 192#define CXL_PSL_Control_Fr              (0x1ull << (63-31))
 193#define CXL_PSL_Control_Fs_MASK         (0x3ull << (63-29))
 194#define CXL_PSL_Control_Fs_Complete     (0x3ull << (63-29))
 195
 196/****** CXL_PSL_DLCNTL *****************************************************/
 197#define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
 198#define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
 199#define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
 200#define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
 201#define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
 202#define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
 203
 204/****** CXL_PSL_SR_An ******************************************************/
 205#define CXL_PSL_SR_An_SF  MSR_SF            /* 64bit */
 206#define CXL_PSL_SR_An_TA  (1ull << (63-1))  /* Tags active,   GA1: 0 */
 207#define CXL_PSL_SR_An_HV  MSR_HV            /* Hypervisor,    GA1: 0 */
 208#define CXL_PSL_SR_An_XLAT_hpt (0ull << (63-6))/* Hashed page table (HPT) mode */
 209#define CXL_PSL_SR_An_XLAT_roh (2ull << (63-6))/* Radix on HPT mode */
 210#define CXL_PSL_SR_An_XLAT_ror (3ull << (63-6))/* Radix on Radix mode */
 211#define CXL_PSL_SR_An_BOT (1ull << (63-10)) /* Use the in-memory segment table */
 212#define CXL_PSL_SR_An_PR  MSR_PR            /* Problem state, GA1: 1 */
 213#define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
 214#define CXL_PSL_SR_An_TC  (1ull << (63-54)) /* Page Table secondary hash */
 215#define CXL_PSL_SR_An_US  (1ull << (63-56)) /* User state,    GA1: X */
 216#define CXL_PSL_SR_An_SC  (1ull << (63-58)) /* Segment Table secondary hash */
 217#define CXL_PSL_SR_An_R   MSR_DR            /* Relocate,      GA1: 1 */
 218#define CXL_PSL_SR_An_MP  (1ull << (63-62)) /* Master Process */
 219#define CXL_PSL_SR_An_LE  (1ull << (63-63)) /* Little Endian */
 220
 221/****** CXL_PSL_ID_An ****************************************************/
 222#define CXL_PSL_ID_An_F (1ull << (63-31))
 223#define CXL_PSL_ID_An_L (1ull << (63-30))
 224
 225/****** CXL_PSL_SERR_An ****************************************************/
 226#define CXL_PSL_SERR_An_afuto   (1ull << (63-0))
 227#define CXL_PSL_SERR_An_afudis  (1ull << (63-1))
 228#define CXL_PSL_SERR_An_afuov   (1ull << (63-2))
 229#define CXL_PSL_SERR_An_badsrc  (1ull << (63-3))
 230#define CXL_PSL_SERR_An_badctx  (1ull << (63-4))
 231#define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
 232#define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
 233#define CXL_PSL_SERR_An_afupar  (1ull << (63-7))
 234#define CXL_PSL_SERR_An_afudup  (1ull << (63-8))
 235#define CXL_PSL_SERR_An_IRQS    ( \
 236        CXL_PSL_SERR_An_afuto | CXL_PSL_SERR_An_afudis | CXL_PSL_SERR_An_afuov | \
 237        CXL_PSL_SERR_An_badsrc | CXL_PSL_SERR_An_badctx | CXL_PSL_SERR_An_llcmdis | \
 238        CXL_PSL_SERR_An_llcmdto | CXL_PSL_SERR_An_afupar | CXL_PSL_SERR_An_afudup)
 239#define CXL_PSL_SERR_An_afuto_mask      (1ull << (63-32))
 240#define CXL_PSL_SERR_An_afudis_mask     (1ull << (63-33))
 241#define CXL_PSL_SERR_An_afuov_mask      (1ull << (63-34))
 242#define CXL_PSL_SERR_An_badsrc_mask     (1ull << (63-35))
 243#define CXL_PSL_SERR_An_badctx_mask     (1ull << (63-36))
 244#define CXL_PSL_SERR_An_llcmdis_mask    (1ull << (63-37))
 245#define CXL_PSL_SERR_An_llcmdto_mask    (1ull << (63-38))
 246#define CXL_PSL_SERR_An_afupar_mask     (1ull << (63-39))
 247#define CXL_PSL_SERR_An_afudup_mask     (1ull << (63-40))
 248#define CXL_PSL_SERR_An_IRQ_MASKS       ( \
 249        CXL_PSL_SERR_An_afuto_mask | CXL_PSL_SERR_An_afudis_mask | CXL_PSL_SERR_An_afuov_mask | \
 250        CXL_PSL_SERR_An_badsrc_mask | CXL_PSL_SERR_An_badctx_mask | CXL_PSL_SERR_An_llcmdis_mask | \
 251        CXL_PSL_SERR_An_llcmdto_mask | CXL_PSL_SERR_An_afupar_mask | CXL_PSL_SERR_An_afudup_mask)
 252
 253#define CXL_PSL_SERR_An_AE      (1ull << (63-30))
 254
 255/****** CXL_PSL_SCNTL_An ****************************************************/
 256#define CXL_PSL_SCNTL_An_CR          (0x1ull << (63-15))
 257/* Programming Modes: */
 258#define CXL_PSL_SCNTL_An_PM_MASK     (0xffffull << (63-31))
 259#define CXL_PSL_SCNTL_An_PM_Shared   (0x0000ull << (63-31))
 260#define CXL_PSL_SCNTL_An_PM_OS       (0x0001ull << (63-31))
 261#define CXL_PSL_SCNTL_An_PM_Process  (0x0002ull << (63-31))
 262#define CXL_PSL_SCNTL_An_PM_AFU      (0x0004ull << (63-31))
 263#define CXL_PSL_SCNTL_An_PM_AFU_PBT  (0x0104ull << (63-31))
 264/* Purge Status (ro) */
 265#define CXL_PSL_SCNTL_An_Ps_MASK     (0x3ull << (63-39))
 266#define CXL_PSL_SCNTL_An_Ps_Pending  (0x1ull << (63-39))
 267#define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
 268/* Purge */
 269#define CXL_PSL_SCNTL_An_Pc          (0x1ull << (63-48))
 270/* Suspend Status (ro) */
 271#define CXL_PSL_SCNTL_An_Ss_MASK     (0x3ull << (63-55))
 272#define CXL_PSL_SCNTL_An_Ss_Pending  (0x1ull << (63-55))
 273#define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
 274/* Suspend Control */
 275#define CXL_PSL_SCNTL_An_Sc          (0x1ull << (63-63))
 276
 277/* AFU Slice Enable Status (ro) */
 278#define CXL_AFU_Cntl_An_ES_MASK     (0x7ull << (63-2))
 279#define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
 280#define CXL_AFU_Cntl_An_ES_Enabled  (0x4ull << (63-2))
 281/* AFU Slice Enable */
 282#define CXL_AFU_Cntl_An_E           (0x1ull << (63-3))
 283/* AFU Slice Reset status (ro) */
 284#define CXL_AFU_Cntl_An_RS_MASK     (0x3ull << (63-5))
 285#define CXL_AFU_Cntl_An_RS_Pending  (0x1ull << (63-5))
 286#define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
 287/* AFU Slice Reset */
 288#define CXL_AFU_Cntl_An_RA          (0x1ull << (63-7))
 289
 290/****** CXL_SSTP0/1_An ******************************************************/
 291/* These top bits are for the segment that CONTAINS the segment table */
 292#define CXL_SSTP0_An_B_SHIFT    SLB_VSID_SSIZE_SHIFT
 293#define CXL_SSTP0_An_KS             (1ull << (63-2))
 294#define CXL_SSTP0_An_KP             (1ull << (63-3))
 295#define CXL_SSTP0_An_N              (1ull << (63-4))
 296#define CXL_SSTP0_An_L              (1ull << (63-5))
 297#define CXL_SSTP0_An_C              (1ull << (63-6))
 298#define CXL_SSTP0_An_TA             (1ull << (63-7))
 299#define CXL_SSTP0_An_LP_SHIFT                (63-9)  /* 2 Bits */
 300/* And finally, the virtual address & size of the segment table: */
 301#define CXL_SSTP0_An_SegTableSize_SHIFT      (63-31) /* 12 Bits */
 302#define CXL_SSTP0_An_SegTableSize_MASK \
 303        (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
 304#define CXL_SSTP0_An_STVA_U_MASK   ((1ull << (63-49))-1)
 305#define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
 306#define CXL_SSTP1_An_V              (1ull << (63-63))
 307
 308/****** CXL_PSL_SLBIE_[An] - CAIA 1 **************************************************/
 309/* write: */
 310#define CXL_SLBIE_C        PPC_BIT(36)         /* Class */
 311#define CXL_SLBIE_SS       PPC_BITMASK(37, 38) /* Segment Size */
 312#define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
 313#define CXL_SLBIE_TA       PPC_BIT(38)         /* Tags Active */
 314/* read: */
 315#define CXL_SLBIE_MAX      PPC_BITMASK(24, 31)
 316#define CXL_SLBIE_PENDING  PPC_BITMASK(56, 63)
 317
 318/****** Common to all CXL_TLBIA/SLBIA_[An] - CAIA 1 **********************************/
 319#define CXL_TLB_SLB_P          (1ull) /* Pending (read) */
 320
 321/****** Common to all CXL_TLB/SLB_IA/IE_[An] registers - CAIA 1 **********************/
 322#define CXL_TLB_SLB_IQ_ALL     (0ull) /* Inv qualifier */
 323#define CXL_TLB_SLB_IQ_LPID    (1ull) /* Inv qualifier */
 324#define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
 325
 326/****** CXL_PSL_AFUSEL ******************************************************/
 327#define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
 328
 329/****** CXL_PSL_DSISR_An - CAIA 1 ****************************************************/
 330#define CXL_PSL_DSISR_An_DS (1ull << (63-0))  /* Segment not found */
 331#define CXL_PSL_DSISR_An_DM (1ull << (63-1))  /* PTE not found (See also: M) or protection fault */
 332#define CXL_PSL_DSISR_An_ST (1ull << (63-2))  /* Segment Table PTE not found */
 333#define CXL_PSL_DSISR_An_UR (1ull << (63-3))  /* AURP PTE not found */
 334#define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
 335#define CXL_PSL_DSISR_An_PE (1ull << (63-4))  /* PSL Error (implementation specific) */
 336#define CXL_PSL_DSISR_An_AE (1ull << (63-5))  /* AFU Error */
 337#define CXL_PSL_DSISR_An_OC (1ull << (63-6))  /* OS Context Warning */
 338#define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC)
 339/* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
 340#define CXL_PSL_DSISR_An_M  DSISR_NOHPTE      /* PTE not found */
 341#define CXL_PSL_DSISR_An_P  DSISR_PROTFAULT   /* Storage protection violation */
 342#define CXL_PSL_DSISR_An_A  (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
 343#define CXL_PSL_DSISR_An_S  DSISR_ISSTORE     /* Access was afu_wr or afu_zero */
 344#define CXL_PSL_DSISR_An_K  DSISR_KEYFAULT    /* Access not permitted by virtual page class key protection */
 345
 346/****** CXL_PSL_DSISR_An - CAIA 2 ****************************************************/
 347#define CXL_PSL9_DSISR_An_TF (1ull << (63-3))  /* Translation fault */
 348#define CXL_PSL9_DSISR_An_PE (1ull << (63-4))  /* PSL Error (implementation specific) */
 349#define CXL_PSL9_DSISR_An_AE (1ull << (63-5))  /* AFU Error */
 350#define CXL_PSL9_DSISR_An_OC (1ull << (63-6))  /* OS Context Warning */
 351#define CXL_PSL9_DSISR_An_S (1ull << (63-38))  /* TF for a write operation */
 352#define CXL_PSL9_DSISR_PENDING (CXL_PSL9_DSISR_An_TF | CXL_PSL9_DSISR_An_PE | CXL_PSL9_DSISR_An_AE | CXL_PSL9_DSISR_An_OC)
 353/*
 354 * NOTE: Bits 56:63 (Checkout Response Status) are valid when DSISR_An[TF] = 1
 355 * Status (0:7) Encoding
 356 */
 357#define CXL_PSL9_DSISR_An_CO_MASK 0x00000000000000ffULL
 358#define CXL_PSL9_DSISR_An_SF      0x0000000000000080ULL  /* Segment Fault                        0b10000000 */
 359#define CXL_PSL9_DSISR_An_PF_SLR  0x0000000000000088ULL  /* PTE not found (Single Level Radix)   0b10001000 */
 360#define CXL_PSL9_DSISR_An_PF_RGC  0x000000000000008CULL  /* PTE not found (Radix Guest (child))  0b10001100 */
 361#define CXL_PSL9_DSISR_An_PF_RGP  0x0000000000000090ULL  /* PTE not found (Radix Guest (parent)) 0b10010000 */
 362#define CXL_PSL9_DSISR_An_PF_HRH  0x0000000000000094ULL  /* PTE not found (HPT/Radix Host)       0b10010100 */
 363#define CXL_PSL9_DSISR_An_PF_STEG 0x000000000000009CULL  /* PTE not found (STEG VA)              0b10011100 */
 364#define CXL_PSL9_DSISR_An_URTCH   0x00000000000000B4ULL  /* Unsupported Radix Tree Configuration 0b10110100 */
 365
 366/****** CXL_PSL_TFC_An ******************************************************/
 367#define CXL_PSL_TFC_An_A  (1ull << (63-28)) /* Acknowledge non-translation fault */
 368#define CXL_PSL_TFC_An_C  (1ull << (63-29)) /* Continue (abort transaction) */
 369#define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
 370#define CXL_PSL_TFC_An_R  (1ull << (63-31)) /* Restart PSL transaction */
 371
 372/****** CXL_PSL_DEBUG *****************************************************/
 373#define CXL_PSL_DEBUG_CDC  (1ull << (63-27)) /* Coherent Data cache support */
 374
 375/****** CXL_XSL9_IERAT_ERAT - CAIA 2 **********************************/
 376#define CXL_XSL9_IERAT_MLPID    (1ull << (63-0))  /* Match LPID */
 377#define CXL_XSL9_IERAT_MPID     (1ull << (63-1))  /* Match PID */
 378#define CXL_XSL9_IERAT_PRS      (1ull << (63-4))  /* PRS bit for Radix invalidations */
 379#define CXL_XSL9_IERAT_INVR     (1ull << (63-3))  /* Invalidate Radix */
 380#define CXL_XSL9_IERAT_IALL     (1ull << (63-8))  /* Invalidate All */
 381#define CXL_XSL9_IERAT_IINPROG  (1ull << (63-63)) /* Invalidate in progress */
 382
 383/* cxl_process_element->software_status */
 384#define CXL_PE_SOFTWARE_STATE_V (1ul << (31 -  0)) /* Valid */
 385#define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
 386#define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
 387#define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
 388
 389/****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
 390 * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
 391 * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
 392 * of the hang pulse frequency.
 393 */
 394#define CXL_PSL_RXCTL_AFUHP_4S      0x7000000000000000ULL
 395
 396/* SPA->sw_command_status */
 397#define CXL_SPA_SW_CMD_MASK         0xffff000000000000ULL
 398#define CXL_SPA_SW_CMD_TERMINATE    0x0001000000000000ULL
 399#define CXL_SPA_SW_CMD_REMOVE       0x0002000000000000ULL
 400#define CXL_SPA_SW_CMD_SUSPEND      0x0003000000000000ULL
 401#define CXL_SPA_SW_CMD_RESUME       0x0004000000000000ULL
 402#define CXL_SPA_SW_CMD_ADD          0x0005000000000000ULL
 403#define CXL_SPA_SW_CMD_UPDATE       0x0006000000000000ULL
 404#define CXL_SPA_SW_STATE_MASK       0x0000ffff00000000ULL
 405#define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
 406#define CXL_SPA_SW_STATE_REMOVED    0x0000000200000000ULL
 407#define CXL_SPA_SW_STATE_SUSPENDED  0x0000000300000000ULL
 408#define CXL_SPA_SW_STATE_RESUMED    0x0000000400000000ULL
 409#define CXL_SPA_SW_STATE_ADDED      0x0000000500000000ULL
 410#define CXL_SPA_SW_STATE_UPDATED    0x0000000600000000ULL
 411#define CXL_SPA_SW_PSL_ID_MASK      0x00000000ffff0000ULL
 412#define CXL_SPA_SW_LINK_MASK        0x000000000000ffffULL
 413
 414#define CXL_MAX_SLICES 4
 415#define MAX_AFU_MMIO_REGS 3
 416
 417#define CXL_MODE_TIME_SLICED 0x4
 418#define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
 419
 420#define CXL_DEV_MINORS 13   /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */
 421#define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
 422#define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS)
 423
 424#define CXL_PSL9_TRACEID_MAX 0xAU
 425#define CXL_PSL9_TRACESTATE_FIN 0x3U
 426
 427enum cxl_context_status {
 428        CLOSED,
 429        OPENED,
 430        STARTED
 431};
 432
 433enum prefault_modes {
 434        CXL_PREFAULT_NONE,
 435        CXL_PREFAULT_WED,
 436        CXL_PREFAULT_ALL,
 437};
 438
 439enum cxl_attrs {
 440        CXL_ADAPTER_ATTRS,
 441        CXL_AFU_MASTER_ATTRS,
 442        CXL_AFU_ATTRS,
 443};
 444
 445struct cxl_sste {
 446        __be64 esid_data;
 447        __be64 vsid_data;
 448};
 449
 450#define to_cxl_adapter(d) container_of(d, struct cxl, dev)
 451#define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
 452
 453struct cxl_afu_native {
 454        void __iomem *p1n_mmio;
 455        void __iomem *afu_desc_mmio;
 456        irq_hw_number_t psl_hwirq;
 457        unsigned int psl_virq;
 458        struct mutex spa_mutex;
 459        /*
 460         * Only the first part of the SPA is used for the process element
 461         * linked list. The only other part that software needs to worry about
 462         * is sw_command_status, which we store a separate pointer to.
 463         * Everything else in the SPA is only used by hardware
 464         */
 465        struct cxl_process_element *spa;
 466        __be64 *sw_command_status;
 467        unsigned int spa_size;
 468        int spa_order;
 469        int spa_max_procs;
 470        u64 pp_offset;
 471};
 472
 473struct cxl_afu_guest {
 474        struct cxl_afu *parent;
 475        u64 handle;
 476        phys_addr_t p2n_phys;
 477        u64 p2n_size;
 478        int max_ints;
 479        bool handle_err;
 480        struct delayed_work work_err;
 481        int previous_state;
 482};
 483
 484struct cxl_afu {
 485        struct cxl_afu_native *native;
 486        struct cxl_afu_guest *guest;
 487        irq_hw_number_t serr_hwirq;
 488        unsigned int serr_virq;
 489        char *psl_irq_name;
 490        char *err_irq_name;
 491        void __iomem *p2n_mmio;
 492        phys_addr_t psn_phys;
 493        u64 pp_size;
 494
 495        struct cxl *adapter;
 496        struct device dev;
 497        struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
 498        struct device *chardev_s, *chardev_m, *chardev_d;
 499        struct idr contexts_idr;
 500        struct dentry *debugfs;
 501        struct mutex contexts_lock;
 502        spinlock_t afu_cntl_lock;
 503
 504        /* -1: AFU deconfigured/locked, >= 0: number of readers */
 505        atomic_t configured_state;
 506
 507        /* AFU error buffer fields and bin attribute for sysfs */
 508        u64 eb_len, eb_offset;
 509        struct bin_attribute attr_eb;
 510
 511        /* pointer to the vphb */
 512        struct pci_controller *phb;
 513
 514        int pp_irqs;
 515        int irqs_max;
 516        int num_procs;
 517        int max_procs_virtualised;
 518        int slice;
 519        int modes_supported;
 520        int current_mode;
 521        int crs_num;
 522        u64 crs_len;
 523        u64 crs_offset;
 524        struct list_head crs;
 525        enum prefault_modes prefault_mode;
 526        bool psa;
 527        bool pp_psa;
 528        bool enabled;
 529};
 530
 531
 532struct cxl_irq_name {
 533        struct list_head list;
 534        char *name;
 535};
 536
 537struct irq_avail {
 538        irq_hw_number_t offset;
 539        irq_hw_number_t range;
 540        unsigned long   *bitmap;
 541};
 542
 543/*
 544 * This is a cxl context.  If the PSL is in dedicated mode, there will be one
 545 * of these per AFU.  If in AFU directed there can be lots of these.
 546 */
 547struct cxl_context {
 548        struct cxl_afu *afu;
 549
 550        /* Problem state MMIO */
 551        phys_addr_t psn_phys;
 552        u64 psn_size;
 553
 554        /* Used to unmap any mmaps when force detaching */
 555        struct address_space *mapping;
 556        struct mutex mapping_lock;
 557        struct page *ff_page;
 558        bool mmio_err_ff;
 559        bool kernelapi;
 560
 561        spinlock_t sste_lock; /* Protects segment table entries */
 562        struct cxl_sste *sstp;
 563        u64 sstp0, sstp1;
 564        unsigned int sst_size, sst_lru;
 565
 566        wait_queue_head_t wq;
 567        /* use mm context associated with this pid for ds faults */
 568        struct pid *pid;
 569        spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
 570        /* Only used in PR mode */
 571        u64 process_token;
 572
 573        /* driver private data */
 574        void *priv;
 575
 576        unsigned long *irq_bitmap; /* Accessed from IRQ context */
 577        struct cxl_irq_ranges irqs;
 578        struct list_head irq_names;
 579        u64 fault_addr;
 580        u64 fault_dsisr;
 581        u64 afu_err;
 582
 583        /*
 584         * This status and it's lock pretects start and detach context
 585         * from racing.  It also prevents detach from racing with
 586         * itself
 587         */
 588        enum cxl_context_status status;
 589        struct mutex status_mutex;
 590
 591
 592        /* XXX: Is it possible to need multiple work items at once? */
 593        struct work_struct fault_work;
 594        u64 dsisr;
 595        u64 dar;
 596
 597        struct cxl_process_element *elem;
 598
 599        /*
 600         * pe is the process element handle, assigned by this driver when the
 601         * context is initialized.
 602         *
 603         * external_pe is the PE shown outside of cxl.
 604         * On bare-metal, pe=external_pe, because we decide what the handle is.
 605         * In a guest, we only find out about the pe used by pHyp when the
 606         * context is attached, and that's the value we want to report outside
 607         * of cxl.
 608         */
 609        int pe;
 610        int external_pe;
 611
 612        u32 irq_count;
 613        bool pe_inserted;
 614        bool master;
 615        bool kernel;
 616        bool real_mode;
 617        bool pending_irq;
 618        bool pending_fault;
 619        bool pending_afu_err;
 620
 621        /* Used by AFU drivers for driver specific event delivery */
 622        struct cxl_afu_driver_ops *afu_driver_ops;
 623        atomic_t afu_driver_events;
 624
 625        struct rcu_head rcu;
 626
 627        /*
 628         * Only used when more interrupts are allocated via
 629         * pci_enable_msix_range than are supported in the default context, to
 630         * use additional contexts to overcome the limitation. i.e. Mellanox
 631         * CX4 only:
 632         */
 633        struct list_head extra_irq_contexts;
 634
 635        struct mm_struct *mm;
 636
 637        u16 tidr;
 638        bool assign_tidr;
 639};
 640
 641struct cxl_irq_info;
 642
 643struct cxl_service_layer_ops {
 644        int (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev);
 645        int (*invalidate_all)(struct cxl *adapter);
 646        int (*afu_regs_init)(struct cxl_afu *afu);
 647        int (*sanitise_afu_regs)(struct cxl_afu *afu);
 648        int (*register_serr_irq)(struct cxl_afu *afu);
 649        void (*release_serr_irq)(struct cxl_afu *afu);
 650        irqreturn_t (*handle_interrupt)(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
 651        irqreturn_t (*fail_irq)(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
 652        int (*activate_dedicated_process)(struct cxl_afu *afu);
 653        int (*attach_afu_directed)(struct cxl_context *ctx, u64 wed, u64 amr);
 654        int (*attach_dedicated_process)(struct cxl_context *ctx, u64 wed, u64 amr);
 655        void (*update_dedicated_ivtes)(struct cxl_context *ctx);
 656        void (*debugfs_add_adapter_regs)(struct cxl *adapter, struct dentry *dir);
 657        void (*debugfs_add_afu_regs)(struct cxl_afu *afu, struct dentry *dir);
 658        void (*psl_irq_dump_registers)(struct cxl_context *ctx);
 659        void (*err_irq_dump_registers)(struct cxl *adapter);
 660        void (*debugfs_stop_trace)(struct cxl *adapter);
 661        void (*write_timebase_ctrl)(struct cxl *adapter);
 662        u64 (*timebase_read)(struct cxl *adapter);
 663        int capi_mode;
 664        bool needs_reset_before_disable;
 665};
 666
 667struct cxl_native {
 668        u64 afu_desc_off;
 669        u64 afu_desc_size;
 670        void __iomem *p1_mmio;
 671        void __iomem *p2_mmio;
 672        irq_hw_number_t err_hwirq;
 673        unsigned int err_virq;
 674        u64 ps_off;
 675        bool no_data_cache; /* set if no data cache on the card */
 676        const struct cxl_service_layer_ops *sl_ops;
 677};
 678
 679struct cxl_guest {
 680        struct platform_device *pdev;
 681        int irq_nranges;
 682        struct cdev cdev;
 683        irq_hw_number_t irq_base_offset;
 684        struct irq_avail *irq_avail;
 685        spinlock_t irq_alloc_lock;
 686        u64 handle;
 687        char *status;
 688        u16 vendor;
 689        u16 device;
 690        u16 subsystem_vendor;
 691        u16 subsystem;
 692};
 693
 694struct cxl {
 695        struct cxl_native *native;
 696        struct cxl_guest *guest;
 697        spinlock_t afu_list_lock;
 698        struct cxl_afu *afu[CXL_MAX_SLICES];
 699        struct device dev;
 700        struct dentry *trace;
 701        struct dentry *psl_err_chk;
 702        struct dentry *debugfs;
 703        char *irq_name;
 704        struct bin_attribute cxl_attr;
 705        int adapter_num;
 706        int user_irqs;
 707        int min_pe;
 708        u64 ps_size;
 709        u16 psl_rev;
 710        u16 base_image;
 711        u8 vsec_status;
 712        u8 caia_major;
 713        u8 caia_minor;
 714        u8 slices;
 715        bool user_image_loaded;
 716        bool perst_loads_image;
 717        bool perst_select_user;
 718        bool perst_same_image;
 719        bool psl_timebase_synced;
 720        bool tunneled_ops_supported;
 721
 722        /*
 723         * number of contexts mapped on to this card. Possible values are:
 724         * >0: Number of contexts mapped and new one can be mapped.
 725         *  0: No active contexts and new ones can be mapped.
 726         * -1: No contexts mapped and new ones cannot be mapped.
 727         */
 728        atomic_t contexts_num;
 729};
 730
 731int cxl_pci_alloc_one_irq(struct cxl *adapter);
 732void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq);
 733int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
 734void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
 735int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
 736int cxl_update_image_control(struct cxl *adapter);
 737int cxl_pci_reset(struct cxl *adapter);
 738void cxl_pci_release_afu(struct device *dev);
 739ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
 740
 741/* common == phyp + powernv - CAIA 1&2 */
 742struct cxl_process_element_common {
 743        __be32 tid;
 744        __be32 pid;
 745        __be64 csrp;
 746        union {
 747                struct {
 748                        __be64 aurp0;
 749                        __be64 aurp1;
 750                        __be64 sstp0;
 751                        __be64 sstp1;
 752                } psl8;  /* CAIA 1 */
 753                struct {
 754                        u8     reserved2[8];
 755                        u8     reserved3[8];
 756                        u8     reserved4[8];
 757                        u8     reserved5[8];
 758                } psl9;  /* CAIA 2 */
 759        } u;
 760        __be64 amr;
 761        u8     reserved6[4];
 762        __be64 wed;
 763} __packed;
 764
 765/* just powernv - CAIA 1&2 */
 766struct cxl_process_element {
 767        __be64 sr;
 768        __be64 SPOffset;
 769        union {
 770                __be64 sdr;          /* CAIA 1 */
 771                u8     reserved1[8]; /* CAIA 2 */
 772        } u;
 773        __be64 haurp;
 774        __be32 ctxtime;
 775        __be16 ivte_offsets[4];
 776        __be16 ivte_ranges[4];
 777        __be32 lpid;
 778        struct cxl_process_element_common common;
 779        __be32 software_state;
 780} __packed;
 781
 782static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu)
 783{
 784        struct pci_dev *pdev;
 785
 786        if (cpu_has_feature(CPU_FTR_HVMODE)) {
 787                pdev = to_pci_dev(cxl->dev.parent);
 788                return !pci_channel_offline(pdev);
 789        }
 790        return true;
 791}
 792
 793static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
 794{
 795        WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
 796        return cxl->native->p1_mmio + cxl_reg_off(reg);
 797}
 798
 799static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
 800{
 801        if (likely(cxl_adapter_link_ok(cxl, NULL)))
 802                out_be64(_cxl_p1_addr(cxl, reg), val);
 803}
 804
 805static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
 806{
 807        if (likely(cxl_adapter_link_ok(cxl, NULL)))
 808                return in_be64(_cxl_p1_addr(cxl, reg));
 809        else
 810                return ~0ULL;
 811}
 812
 813static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
 814{
 815        WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
 816        return afu->native->p1n_mmio + cxl_reg_off(reg);
 817}
 818
 819static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
 820{
 821        if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 822                out_be64(_cxl_p1n_addr(afu, reg), val);
 823}
 824
 825static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
 826{
 827        if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 828                return in_be64(_cxl_p1n_addr(afu, reg));
 829        else
 830                return ~0ULL;
 831}
 832
 833static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
 834{
 835        return afu->p2n_mmio + cxl_reg_off(reg);
 836}
 837
 838static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
 839{
 840        if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 841                out_be64(_cxl_p2n_addr(afu, reg), val);
 842}
 843
 844static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
 845{
 846        if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 847                return in_be64(_cxl_p2n_addr(afu, reg));
 848        else
 849                return ~0ULL;
 850}
 851
 852static inline bool cxl_is_power8(void)
 853{
 854        if ((pvr_version_is(PVR_POWER8E)) ||
 855            (pvr_version_is(PVR_POWER8NVL)) ||
 856            (pvr_version_is(PVR_POWER8)))
 857                return true;
 858        return false;
 859}
 860
 861static inline bool cxl_is_power9(void)
 862{
 863        if (pvr_version_is(PVR_POWER9))
 864                return true;
 865        return false;
 866}
 867
 868ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
 869                                loff_t off, size_t count);
 870
 871/* Internal functions wrapped in cxl_base to allow PHB to call them */
 872bool _cxl_pci_associate_default_context(struct pci_dev *dev, struct cxl_afu *afu);
 873void _cxl_pci_disable_device(struct pci_dev *dev);
 874int _cxl_next_msi_hwirq(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
 875int _cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
 876void _cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
 877
 878struct cxl_calls {
 879        void (*cxl_slbia)(struct mm_struct *mm);
 880        bool (*cxl_pci_associate_default_context)(struct pci_dev *dev, struct cxl_afu *afu);
 881        void (*cxl_pci_disable_device)(struct pci_dev *dev);
 882        int (*cxl_next_msi_hwirq)(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
 883        int (*cxl_cx4_setup_msi_irqs)(struct pci_dev *pdev, int nvec, int type);
 884        void (*cxl_cx4_teardown_msi_irqs)(struct pci_dev *pdev);
 885
 886        struct module *owner;
 887};
 888int register_cxl_calls(struct cxl_calls *calls);
 889void unregister_cxl_calls(struct cxl_calls *calls);
 890int cxl_update_properties(struct device_node *dn, struct property *new_prop);
 891
 892void cxl_remove_adapter_nr(struct cxl *adapter);
 893
 894void cxl_release_spa(struct cxl_afu *afu);
 895
 896dev_t cxl_get_dev(void);
 897int cxl_file_init(void);
 898void cxl_file_exit(void);
 899int cxl_register_adapter(struct cxl *adapter);
 900int cxl_register_afu(struct cxl_afu *afu);
 901int cxl_chardev_d_afu_add(struct cxl_afu *afu);
 902int cxl_chardev_m_afu_add(struct cxl_afu *afu);
 903int cxl_chardev_s_afu_add(struct cxl_afu *afu);
 904void cxl_chardev_afu_remove(struct cxl_afu *afu);
 905
 906void cxl_context_detach_all(struct cxl_afu *afu);
 907void cxl_context_free(struct cxl_context *ctx);
 908void cxl_context_detach(struct cxl_context *ctx);
 909
 910int cxl_sysfs_adapter_add(struct cxl *adapter);
 911void cxl_sysfs_adapter_remove(struct cxl *adapter);
 912int cxl_sysfs_afu_add(struct cxl_afu *afu);
 913void cxl_sysfs_afu_remove(struct cxl_afu *afu);
 914int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
 915void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
 916
 917struct cxl *cxl_alloc_adapter(void);
 918struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice);
 919int cxl_afu_select_best_mode(struct cxl_afu *afu);
 920
 921int cxl_native_register_psl_irq(struct cxl_afu *afu);
 922void cxl_native_release_psl_irq(struct cxl_afu *afu);
 923int cxl_native_register_psl_err_irq(struct cxl *adapter);
 924void cxl_native_release_psl_err_irq(struct cxl *adapter);
 925int cxl_native_register_serr_irq(struct cxl_afu *afu);
 926void cxl_native_release_serr_irq(struct cxl_afu *afu);
 927int afu_register_irqs(struct cxl_context *ctx, u32 count);
 928void afu_release_irqs(struct cxl_context *ctx, void *cookie);
 929void afu_irq_name_free(struct cxl_context *ctx);
 930
 931int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
 932int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
 933int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu);
 934int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu);
 935int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
 936int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
 937void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx);
 938void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx);
 939
 940#ifdef CONFIG_DEBUG_FS
 941
 942int cxl_debugfs_init(void);
 943void cxl_debugfs_exit(void);
 944int cxl_debugfs_adapter_add(struct cxl *adapter);
 945void cxl_debugfs_adapter_remove(struct cxl *adapter);
 946int cxl_debugfs_afu_add(struct cxl_afu *afu);
 947void cxl_debugfs_afu_remove(struct cxl_afu *afu);
 948void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter, struct dentry *dir);
 949void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter, struct dentry *dir);
 950void cxl_debugfs_add_adapter_regs_xsl(struct cxl *adapter, struct dentry *dir);
 951void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir);
 952void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir);
 953
 954#else /* CONFIG_DEBUG_FS */
 955
 956static inline int __init cxl_debugfs_init(void)
 957{
 958        return 0;
 959}
 960
 961static inline void cxl_debugfs_exit(void)
 962{
 963}
 964
 965static inline int cxl_debugfs_adapter_add(struct cxl *adapter)
 966{
 967        return 0;
 968}
 969
 970static inline void cxl_debugfs_adapter_remove(struct cxl *adapter)
 971{
 972}
 973
 974static inline int cxl_debugfs_afu_add(struct cxl_afu *afu)
 975{
 976        return 0;
 977}
 978
 979static inline void cxl_debugfs_afu_remove(struct cxl_afu *afu)
 980{
 981}
 982
 983static inline void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter,
 984                                                    struct dentry *dir)
 985{
 986}
 987
 988static inline void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter,
 989                                                    struct dentry *dir)
 990{
 991}
 992
 993static inline void cxl_debugfs_add_adapter_regs_xsl(struct cxl *adapter,
 994                                                    struct dentry *dir)
 995{
 996}
 997
 998static inline void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir)
 999{
1000}

1001
1002static inline void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir)
1003{
1004}
1005
1006#endif /* CONFIG_DEBUG_FS */
1007
1008void cxl_handle_fault(struct work_struct *work);
1009void cxl_prefault(struct cxl_context *ctx, u64 wed);
1010int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar);
1011
1012struct cxl *get_cxl_adapter(int num);
1013int cxl_alloc_sst(struct cxl_context *ctx);
1014void cxl_dump_debug_buffer(void *addr, size_t size);
1015
1016void init_cxl_native(void);
1017
1018struct cxl_context *cxl_context_alloc(void);
1019int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master);
1020void cxl_context_set_mapping(struct cxl_context *ctx,
1021                        struct address_space *mapping);
1022void cxl_context_free(struct cxl_context *ctx);
1023int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
1024unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
1025                         irq_handler_t handler, void *cookie, const char *name);
1026void cxl_unmap_irq(unsigned int virq, void *cookie);
1027int __detach_context(struct cxl_context *ctx);
1028
1029/*
1030 * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined
1031 * in PAPR.
1032 * Field pid_tid is now 'reserved' because it's no more used on bare-metal.
1033 * On a guest environment, PSL_PID_An is located on the upper 32 bits and
1034 * PSL_TID_An register in the lower 32 bits.
1035 */
1036struct cxl_irq_info {
1037        u64 dsisr;
1038        u64 dar;
1039        u64 dsr;
1040        u64 reserved;
1041        u64 afu_err;
1042        u64 errstat;
1043        u64 proc_handle;
1044        u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */
1045};
1046
1047void cxl_assign_psn_space(struct cxl_context *ctx);
1048int cxl_invalidate_all_psl9(struct cxl *adapter);
1049int cxl_invalidate_all_psl8(struct cxl *adapter);
1050irqreturn_t cxl_irq_psl9(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
1051irqreturn_t cxl_irq_psl8(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
1052irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
1053int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
1054                        void *cookie, irq_hw_number_t *dest_hwirq,
1055                        unsigned int *dest_virq, const char *name);
1056
1057int cxl_check_error(struct cxl_afu *afu);
1058int cxl_afu_slbia(struct cxl_afu *afu);
1059int cxl_data_cache_flush(struct cxl *adapter);
1060int cxl_afu_disable(struct cxl_afu *afu);
1061int cxl_psl_purge(struct cxl_afu *afu);
1062int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
1063                          u32 *phb_index, u64 *capp_unit_id);
1064int cxl_slot_is_switched(struct pci_dev *dev);
1065int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg);
1066u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9);
1067
1068void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx);
1069void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx);
1070void cxl_native_err_irq_dump_regs_psl8(struct cxl *adapter);
1071void cxl_native_err_irq_dump_regs_psl9(struct cxl *adapter);
1072int cxl_pci_vphb_add(struct cxl_afu *afu);
1073void cxl_pci_vphb_remove(struct cxl_afu *afu);
1074void cxl_release_mapping(struct cxl_context *ctx);
1075
1076extern struct pci_driver cxl_pci_driver;
1077extern struct platform_driver cxl_of_driver;
1078int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
1079
1080int afu_open(struct inode *inode, struct file *file);
1081int afu_release(struct inode *inode, struct file *file);
1082long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
1083int afu_mmap(struct file *file, struct vm_area_struct *vm);
1084__poll_t afu_poll(struct file *file, struct poll_table_struct *poll);
1085ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
1086extern const struct file_operations afu_fops;
1087
1088struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev);
1089void cxl_guest_remove_adapter(struct cxl *adapter);
1090int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np);
1091int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np);
1092ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
1093ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len);
1094int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np);
1095void cxl_guest_remove_afu(struct cxl_afu *afu);
1096int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np);
1097int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np);
1098int cxl_guest_add_chardev(struct cxl *adapter);
1099void cxl_guest_remove_chardev(struct cxl *adapter);
1100void cxl_guest_reload_module(struct cxl *adapter);
1101int cxl_of_probe(struct platform_device *pdev);
1102
1103struct cxl_backend_ops {
1104        struct module *module;
1105        int (*adapter_reset)(struct cxl *adapter);
1106        int (*alloc_one_irq)(struct cxl *adapter);
1107        void (*release_one_irq)(struct cxl *adapter, int hwirq);
1108        int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs,
1109                                struct cxl *adapter, unsigned int num);
1110        void (*release_irq_ranges)(struct cxl_irq_ranges *irqs,
1111                                struct cxl *adapter);
1112        int (*setup_irq)(struct cxl *adapter, unsigned int hwirq,
1113                        unsigned int virq);
1114        irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx,
1115                                        u64 dsisr, u64 errstat);
1116        irqreturn_t (*psl_interrupt)(int irq, void *data);
1117        int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
1118        void (*irq_wait)(struct cxl_context *ctx);
1119        int (*attach_process)(struct cxl_context *ctx, bool kernel,
1120                        u64 wed, u64 amr);
1121        int (*detach_process)(struct cxl_context *ctx);
1122        void (*update_ivtes)(struct cxl_context *ctx);
1123        bool (*support_attributes)(const char *attr_name, enum cxl_attrs type);
1124        bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu);
1125        void (*release_afu)(struct device *dev);
1126        ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf,
1127                                loff_t off, size_t count);
1128        int (*afu_check_and_enable)(struct cxl_afu *afu);
1129        int (*afu_activate_mode)(struct cxl_afu *afu, int mode);
1130        int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode);
1131        int (*afu_reset)(struct cxl_afu *afu);
1132        int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
1133        int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
1134        int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
1135        int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
1136        int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
1137        int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
1138        int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
1139        ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count);
1140};
1141extern const struct cxl_backend_ops cxl_native_ops;
1142extern const struct cxl_backend_ops cxl_guest_ops;
1143extern const struct cxl_backend_ops *cxl_ops;
1144
1145/* check if the given pci_dev is on the the cxl vphb bus */
1146bool cxl_pci_is_vphb_device(struct pci_dev *dev);
1147
1148/* decode AFU error bits in the PSL register PSL_SERR_An */
1149void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr);
1150
1151/*
1152 * Increments the number of attached contexts on an adapter.
1153 * In case an adapter_context_lock is taken the return -EBUSY.
1154 */
1155int cxl_adapter_context_get(struct cxl *adapter);
1156
1157/* Decrements the number of attached contexts on an adapter */
1158void cxl_adapter_context_put(struct cxl *adapter);
1159
1160/* If no active contexts then prevents contexts from being attached */
1161int cxl_adapter_context_lock(struct cxl *adapter);
1162
1163/* Unlock the contexts-lock if taken. Warn and force unlock otherwise */
1164void cxl_adapter_context_unlock(struct cxl *adapter);
1165
1166/* Increases the reference count to "struct mm_struct" */
1167void cxl_context_mm_count_get(struct cxl_context *ctx);
1168
1169/* Decrements the reference count to "struct mm_struct" */
1170void cxl_context_mm_count_put(struct cxl_context *ctx);
1171
1172#endif
1173