linux/drivers/mmc/host/mmc_spi.c
<<
>>
Prefs
   1/*
   2 * mmc_spi.c - Access SD/MMC cards through SPI master controllers
   3 *
   4 * (C) Copyright 2005, Intec Automation,
   5 *              Mike Lavender (mike@steroidmicros)
   6 * (C) Copyright 2006-2007, David Brownell
   7 * (C) Copyright 2007, Axis Communications,
   8 *              Hans-Peter Nilsson (hp@axis.com)
   9 * (C) Copyright 2007, ATRON electronic GmbH,
  10 *              Jan Nikitenko <jan.nikitenko@gmail.com>
  11 *
  12 *
  13 * This program is free software; you can redistribute it and/or modify
  14 * it under the terms of the GNU General Public License as published by
  15 * the Free Software Foundation; either version 2 of the License, or
  16 * (at your option) any later version.
  17 *
  18 * This program is distributed in the hope that it will be useful,
  19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 * GNU General Public License for more details.
  22 *
  23 * You should have received a copy of the GNU General Public License
  24 * along with this program; if not, write to the Free Software
  25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26 */
  27#include <linux/sched.h>
  28#include <linux/delay.h>
  29#include <linux/slab.h>
  30#include <linux/module.h>
  31#include <linux/bio.h>
  32#include <linux/dma-mapping.h>
  33#include <linux/crc7.h>
  34#include <linux/crc-itu-t.h>
  35#include <linux/scatterlist.h>
  36
  37#include <linux/mmc/host.h>
  38#include <linux/mmc/mmc.h>              /* for R1_SPI_* bit values */
  39#include <linux/mmc/slot-gpio.h>
  40
  41#include <linux/spi/spi.h>
  42#include <linux/spi/mmc_spi.h>
  43
  44#include <asm/unaligned.h>
  45
  46
  47/* NOTES:
  48 *
  49 * - For now, we won't try to interoperate with a real mmc/sd/sdio
  50 *   controller, although some of them do have hardware support for
  51 *   SPI protocol.  The main reason for such configs would be mmc-ish
  52 *   cards like DataFlash, which don't support that "native" protocol.
  53 *
  54 *   We don't have a "DataFlash/MMC/SD/SDIO card slot" abstraction to
  55 *   switch between driver stacks, and in any case if "native" mode
  56 *   is available, it will be faster and hence preferable.
  57 *
  58 * - MMC depends on a different chipselect management policy than the
  59 *   SPI interface currently supports for shared bus segments:  it needs
  60 *   to issue multiple spi_message requests with the chipselect active,
  61 *   using the results of one message to decide the next one to issue.
  62 *
  63 *   Pending updates to the programming interface, this driver expects
  64 *   that it not share the bus with other drivers (precluding conflicts).
  65 *
  66 * - We tell the controller to keep the chipselect active from the
  67 *   beginning of an mmc_host_ops.request until the end.  So beware
  68 *   of SPI controller drivers that mis-handle the cs_change flag!
  69 *
  70 *   However, many cards seem OK with chipselect flapping up/down
  71 *   during that time ... at least on unshared bus segments.
  72 */
  73
  74
  75/*
  76 * Local protocol constants, internal to data block protocols.
  77 */
  78
  79/* Response tokens used to ack each block written: */
  80#define SPI_MMC_RESPONSE_CODE(x)        ((x) & 0x1f)
  81#define SPI_RESPONSE_ACCEPTED           ((2 << 1)|1)
  82#define SPI_RESPONSE_CRC_ERR            ((5 << 1)|1)
  83#define SPI_RESPONSE_WRITE_ERR          ((6 << 1)|1)
  84
  85/* Read and write blocks start with these tokens and end with crc;
  86 * on error, read tokens act like a subset of R2_SPI_* values.
  87 */
  88#define SPI_TOKEN_SINGLE        0xfe    /* single block r/w, multiblock read */
  89#define SPI_TOKEN_MULTI_WRITE   0xfc    /* multiblock write */
  90#define SPI_TOKEN_STOP_TRAN     0xfd    /* terminate multiblock write */
  91
  92#define MMC_SPI_BLOCKSIZE       512
  93
  94
  95/* These fixed timeouts come from the latest SD specs, which say to ignore
  96 * the CSD values.  The R1B value is for card erase (e.g. the "I forgot the
  97 * card's password" scenario); it's mostly applied to STOP_TRANSMISSION after
  98 * reads which takes nowhere near that long.  Older cards may be able to use
  99 * shorter timeouts ... but why bother?
 100 */
 101#define r1b_timeout             (HZ * 3)
 102
 103/* One of the critical speed parameters is the amount of data which may
 104 * be transferred in one command. If this value is too low, the SD card
 105 * controller has to do multiple partial block writes (argggh!). With
 106 * today (2008) SD cards there is little speed gain if we transfer more
 107 * than 64 KBytes at a time. So use this value until there is any indication
 108 * that we should do more here.
 109 */
 110#define MMC_SPI_BLOCKSATONCE    128
 111
 112/****************************************************************************/
 113
 114/*
 115 * Local Data Structures
 116 */
 117
 118/* "scratch" is per-{command,block} data exchanged with the card */
 119struct scratch {
 120        u8                      status[29];
 121        u8                      data_token;
 122        __be16                  crc_val;
 123};
 124
 125struct mmc_spi_host {
 126        struct mmc_host         *mmc;
 127        struct spi_device       *spi;
 128
 129        unsigned char           power_mode;
 130        u16                     powerup_msecs;
 131
 132        struct mmc_spi_platform_data    *pdata;
 133
 134        /* for bulk data transfers */
 135        struct spi_transfer     token, t, crc, early_status;
 136        struct spi_message      m;
 137
 138        /* for status readback */
 139        struct spi_transfer     status;
 140        struct spi_message      readback;
 141
 142        /* underlying DMA-aware controller, or null */
 143        struct device           *dma_dev;
 144
 145        /* buffer used for commands and for message "overhead" */
 146        struct scratch          *data;
 147        dma_addr_t              data_dma;
 148
 149        /* Specs say to write ones most of the time, even when the card
 150         * has no need to read its input data; and many cards won't care.
 151         * This is our source of those ones.
 152         */
 153        void                    *ones;
 154        dma_addr_t              ones_dma;
 155};
 156
 157
 158/****************************************************************************/
 159
 160/*
 161 * MMC-over-SPI protocol glue, used by the MMC stack interface
 162 */
 163
 164static inline int mmc_cs_off(struct mmc_spi_host *host)
 165{
 166        /* chipselect will always be inactive after setup() */
 167        return spi_setup(host->spi);
 168}
 169
 170static int
 171mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len)
 172{
 173        int status;
 174
 175        if (len > sizeof(*host->data)) {
 176                WARN_ON(1);
 177                return -EIO;
 178        }
 179
 180        host->status.len = len;
 181
 182        if (host->dma_dev)
 183                dma_sync_single_for_device(host->dma_dev,
 184                                host->data_dma, sizeof(*host->data),
 185                                DMA_FROM_DEVICE);
 186
 187        status = spi_sync_locked(host->spi, &host->readback);
 188
 189        if (host->dma_dev)
 190                dma_sync_single_for_cpu(host->dma_dev,
 191                                host->data_dma, sizeof(*host->data),
 192                                DMA_FROM_DEVICE);
 193
 194        return status;
 195}
 196
 197static int mmc_spi_skip(struct mmc_spi_host *host, unsigned long timeout,
 198                        unsigned n, u8 byte)
 199{
 200        u8              *cp = host->data->status;
 201        unsigned long start = jiffies;
 202
 203        while (1) {
 204                int             status;
 205                unsigned        i;
 206
 207                status = mmc_spi_readbytes(host, n);
 208                if (status < 0)
 209                        return status;
 210
 211                for (i = 0; i < n; i++) {
 212                        if (cp[i] != byte)
 213                                return cp[i];
 214                }
 215
 216                if (time_is_before_jiffies(start + timeout))
 217                        break;
 218
 219                /* If we need long timeouts, we may release the CPU.
 220                 * We use jiffies here because we want to have a relation
 221                 * between elapsed time and the blocking of the scheduler.
 222                 */
 223                if (time_is_before_jiffies(start+1))
 224                        schedule();
 225        }
 226        return -ETIMEDOUT;
 227}
 228
 229static inline int
 230mmc_spi_wait_unbusy(struct mmc_spi_host *host, unsigned long timeout)
 231{
 232        return mmc_spi_skip(host, timeout, sizeof(host->data->status), 0);
 233}
 234
 235static int mmc_spi_readtoken(struct mmc_spi_host *host, unsigned long timeout)
 236{
 237        return mmc_spi_skip(host, timeout, 1, 0xff);
 238}
 239
 240
 241/*
 242 * Note that for SPI, cmd->resp[0] is not the same data as "native" protocol
 243 * hosts return!  The low byte holds R1_SPI bits.  The next byte may hold
 244 * R2_SPI bits ... for SEND_STATUS, or after data read errors.
 245 *
 246 * cmd->resp[1] holds any four-byte response, for R3 (READ_OCR) and on
 247 * newer cards R7 (IF_COND).
 248 */
 249
 250static char *maptype(struct mmc_command *cmd)
 251{
 252        switch (mmc_spi_resp_type(cmd)) {
 253        case MMC_RSP_SPI_R1:    return "R1";
 254        case MMC_RSP_SPI_R1B:   return "R1B";
 255        case MMC_RSP_SPI_R2:    return "R2/R5";
 256        case MMC_RSP_SPI_R3:    return "R3/R4/R7";
 257        default:                return "?";
 258        }
 259}
 260
 261/* return zero, else negative errno after setting cmd->error */
 262static int mmc_spi_response_get(struct mmc_spi_host *host,
 263                struct mmc_command *cmd, int cs_on)
 264{
 265        u8      *cp = host->data->status;
 266        u8      *end = cp + host->t.len;
 267        int     value = 0;
 268        int     bitshift;
 269        u8      leftover = 0;
 270        unsigned short rotator;
 271        int     i;
 272        char    tag[32];
 273
 274        snprintf(tag, sizeof(tag), "  ... CMD%d response SPI_%s",
 275                cmd->opcode, maptype(cmd));
 276
 277        /* Except for data block reads, the whole response will already
 278         * be stored in the scratch buffer.  It's somewhere after the
 279         * command and the first byte we read after it.  We ignore that
 280         * first byte.  After STOP_TRANSMISSION command it may include
 281         * two data bits, but otherwise it's all ones.
 282         */
 283        cp += 8;
 284        while (cp < end && *cp == 0xff)
 285                cp++;
 286
 287        /* Data block reads (R1 response types) may need more data... */
 288        if (cp == end) {
 289                cp = host->data->status;
 290                end = cp+1;
 291
 292                /* Card sends N(CR) (== 1..8) bytes of all-ones then one
 293                 * status byte ... and we already scanned 2 bytes.
 294                 *
 295                 * REVISIT block read paths use nasty byte-at-a-time I/O
 296                 * so it can always DMA directly into the target buffer.
 297                 * It'd probably be better to memcpy() the first chunk and
 298                 * avoid extra i/o calls...
 299                 *
 300                 * Note we check for more than 8 bytes, because in practice,
 301                 * some SD cards are slow...
 302                 */
 303                for (i = 2; i < 16; i++) {
 304                        value = mmc_spi_readbytes(host, 1);
 305                        if (value < 0)
 306                                goto done;
 307                        if (*cp != 0xff)
 308                                goto checkstatus;
 309                }
 310                value = -ETIMEDOUT;
 311                goto done;
 312        }
 313
 314checkstatus:
 315        bitshift = 0;
 316        if (*cp & 0x80) {
 317                /* Houston, we have an ugly card with a bit-shifted response */
 318                rotator = *cp++ << 8;
 319                /* read the next byte */
 320                if (cp == end) {
 321                        value = mmc_spi_readbytes(host, 1);
 322                        if (value < 0)
 323                                goto done;
 324                        cp = host->data->status;
 325                        end = cp+1;
 326                }
 327                rotator |= *cp++;
 328                while (rotator & 0x8000) {
 329                        bitshift++;
 330                        rotator <<= 1;
 331                }
 332                cmd->resp[0] = rotator >> 8;
 333                leftover = rotator;
 334        } else {
 335                cmd->resp[0] = *cp++;
 336        }
 337        cmd->error = 0;
 338
 339        /* Status byte: the entire seven-bit R1 response.  */
 340        if (cmd->resp[0] != 0) {
 341                if ((R1_SPI_PARAMETER | R1_SPI_ADDRESS)
 342                                & cmd->resp[0])
 343                        value = -EFAULT; /* Bad address */
 344                else if (R1_SPI_ILLEGAL_COMMAND & cmd->resp[0])
 345                        value = -ENOSYS; /* Function not implemented */
 346                else if (R1_SPI_COM_CRC & cmd->resp[0])
 347                        value = -EILSEQ; /* Illegal byte sequence */
 348                else if ((R1_SPI_ERASE_SEQ | R1_SPI_ERASE_RESET)
 349                                & cmd->resp[0])
 350                        value = -EIO;    /* I/O error */
 351                /* else R1_SPI_IDLE, "it's resetting" */
 352        }
 353
 354        switch (mmc_spi_resp_type(cmd)) {
 355
 356        /* SPI R1B == R1 + busy; STOP_TRANSMISSION (for multiblock reads)
 357         * and less-common stuff like various erase operations.
 358         */
 359        case MMC_RSP_SPI_R1B:
 360                /* maybe we read all the busy tokens already */
 361                while (cp < end && *cp == 0)
 362                        cp++;
 363                if (cp == end)
 364                        mmc_spi_wait_unbusy(host, r1b_timeout);
 365                break;
 366
 367        /* SPI R2 == R1 + second status byte; SEND_STATUS
 368         * SPI R5 == R1 + data byte; IO_RW_DIRECT
 369         */
 370        case MMC_RSP_SPI_R2:
 371                /* read the next byte */
 372                if (cp == end) {
 373                        value = mmc_spi_readbytes(host, 1);
 374                        if (value < 0)
 375                                goto done;
 376                        cp = host->data->status;
 377                        end = cp+1;
 378                }
 379                if (bitshift) {
 380                        rotator = leftover << 8;
 381                        rotator |= *cp << bitshift;
 382                        cmd->resp[0] |= (rotator & 0xFF00);
 383                } else {
 384                        cmd->resp[0] |= *cp << 8;
 385                }
 386                break;
 387
 388        /* SPI R3, R4, or R7 == R1 + 4 bytes */
 389        case MMC_RSP_SPI_R3:
 390                rotator = leftover << 8;
 391                cmd->resp[1] = 0;
 392                for (i = 0; i < 4; i++) {
 393                        cmd->resp[1] <<= 8;
 394                        /* read the next byte */
 395                        if (cp == end) {
 396                                value = mmc_spi_readbytes(host, 1);
 397                                if (value < 0)
 398                                        goto done;
 399                                cp = host->data->status;
 400                                end = cp+1;
 401                        }
 402                        if (bitshift) {
 403                                rotator |= *cp++ << bitshift;
 404                                cmd->resp[1] |= (rotator >> 8);
 405                                rotator <<= 8;
 406                        } else {
 407                                cmd->resp[1] |= *cp++;
 408                        }
 409                }
 410                break;
 411
 412        /* SPI R1 == just one status byte */
 413        case MMC_RSP_SPI_R1:
 414                break;
 415
 416        default:
 417                dev_dbg(&host->spi->dev, "bad response type %04x\n",
 418                                mmc_spi_resp_type(cmd));
 419                if (value >= 0)
 420                        value = -EINVAL;
 421                goto done;
 422        }
 423
 424        if (value < 0)
 425                dev_dbg(&host->spi->dev, "%s: resp %04x %08x\n",
 426                        tag, cmd->resp[0], cmd->resp[1]);
 427
 428        /* disable chipselect on errors and some success cases */
 429        if (value >= 0 && cs_on)
 430                return value;
 431done:
 432        if (value < 0)
 433                cmd->error = value;
 434        mmc_cs_off(host);
 435        return value;
 436}
 437
 438/* Issue command and read its response.
 439 * Returns zero on success, negative for error.
 440 *
 441 * On error, caller must cope with mmc core retry mechanism.  That
 442 * means immediate low-level resubmit, which affects the bus lock...
 443 */
 444static int
 445mmc_spi_command_send(struct mmc_spi_host *host,
 446                struct mmc_request *mrq,
 447                struct mmc_command *cmd, int cs_on)
 448{
 449        struct scratch          *data = host->data;
 450        u8                      *cp = data->status;
 451        int                     status;
 452        struct spi_transfer     *t;
 453
 454        /* We can handle most commands (except block reads) in one full
 455         * duplex I/O operation before either starting the next transfer
 456         * (data block or command) or else deselecting the card.
 457         *
 458         * First, write 7 bytes:
 459         *  - an all-ones byte to ensure the card is ready
 460         *  - opcode byte (plus start and transmission bits)
 461         *  - four bytes of big-endian argument
 462         *  - crc7 (plus end bit) ... always computed, it's cheap
 463         *
 464         * We init the whole buffer to all-ones, which is what we need
 465         * to write while we're reading (later) response data.
 466         */
 467        memset(cp, 0xff, sizeof(data->status));
 468
 469        cp[1] = 0x40 | cmd->opcode;
 470        put_unaligned_be32(cmd->arg, cp+2);
 471        cp[6] = crc7_be(0, cp+1, 5) | 0x01;
 472        cp += 7;
 473
 474        /* Then, read up to 13 bytes (while writing all-ones):
 475         *  - N(CR) (== 1..8) bytes of all-ones
 476         *  - status byte (for all response types)
 477         *  - the rest of the response, either:
 478         *      + nothing, for R1 or R1B responses
 479         *      + second status byte, for R2 responses
 480         *      + four data bytes, for R3 and R7 responses
 481         *
 482         * Finally, read some more bytes ... in the nice cases we know in
 483         * advance how many, and reading 1 more is always OK:
 484         *  - N(EC) (== 0..N) bytes of all-ones, before deselect/finish
 485         *  - N(RC) (== 1..N) bytes of all-ones, before next command
 486         *  - N(WR) (== 1..N) bytes of all-ones, before data write
 487         *
 488         * So in those cases one full duplex I/O of at most 21 bytes will
 489         * handle the whole command, leaving the card ready to receive a
 490         * data block or new command.  We do that whenever we can, shaving
 491         * CPU and IRQ costs (especially when using DMA or FIFOs).
 492         *
 493         * There are two other cases, where it's not generally practical
 494         * to rely on a single I/O:
 495         *
 496         *  - R1B responses need at least N(EC) bytes of all-zeroes.
 497         *
 498         *    In this case we can *try* to fit it into one I/O, then
 499         *    maybe read more data later.
 500         *
 501         *  - Data block reads are more troublesome, since a variable
 502         *    number of padding bytes precede the token and data.
 503         *      + N(CX) (== 0..8) bytes of all-ones, before CSD or CID
 504         *      + N(AC) (== 1..many) bytes of all-ones
 505         *
 506         *    In this case we currently only have minimal speedups here:
 507         *    when N(CR) == 1 we can avoid I/O in response_get().
 508         */
 509        if (cs_on && (mrq->data->flags & MMC_DATA_READ)) {
 510                cp += 2;        /* min(N(CR)) + status */
 511                /* R1 */
 512        } else {
 513                cp += 10;       /* max(N(CR)) + status + min(N(RC),N(WR)) */
 514                if (cmd->flags & MMC_RSP_SPI_S2)        /* R2/R5 */
 515                        cp++;
 516                else if (cmd->flags & MMC_RSP_SPI_B4)   /* R3/R4/R7 */
 517                        cp += 4;
 518                else if (cmd->flags & MMC_RSP_BUSY)     /* R1B */
 519                        cp = data->status + sizeof(data->status);
 520                /* else:  R1 (most commands) */
 521        }
 522
 523        dev_dbg(&host->spi->dev, "  mmc_spi: CMD%d, resp %s\n",
 524                cmd->opcode, maptype(cmd));
 525
 526        /* send command, leaving chipselect active */
 527        spi_message_init(&host->m);
 528
 529        t = &host->t;
 530        memset(t, 0, sizeof(*t));
 531        t->tx_buf = t->rx_buf = data->status;
 532        t->tx_dma = t->rx_dma = host->data_dma;
 533        t->len = cp - data->status;
 534        t->cs_change = 1;
 535        spi_message_add_tail(t, &host->m);
 536
 537        if (host->dma_dev) {
 538                host->m.is_dma_mapped = 1;
 539                dma_sync_single_for_device(host->dma_dev,
 540                                host->data_dma, sizeof(*host->data),
 541                                DMA_BIDIRECTIONAL);
 542        }
 543        status = spi_sync_locked(host->spi, &host->m);
 544
 545        if (host->dma_dev)
 546                dma_sync_single_for_cpu(host->dma_dev,
 547                                host->data_dma, sizeof(*host->data),
 548                                DMA_BIDIRECTIONAL);
 549        if (status < 0) {
 550                dev_dbg(&host->spi->dev, "  ... write returned %d\n", status);
 551                cmd->error = status;
 552                return status;
 553        }
 554
 555        /* after no-data commands and STOP_TRANSMISSION, chipselect off */
 556        return mmc_spi_response_get(host, cmd, cs_on);
 557}
 558
 559/* Build data message with up to four separate transfers.  For TX, we
 560 * start by writing the data token.  And in most cases, we finish with
 561 * a status transfer.
 562 *
 563 * We always provide TX data for data and CRC.  The MMC/SD protocol
 564 * requires us to write ones; but Linux defaults to writing zeroes;
 565 * so we explicitly initialize it to all ones on RX paths.
 566 *
 567 * We also handle DMA mapping, so the underlying SPI controller does
 568 * not need to (re)do it for each message.
 569 */
 570static void
 571mmc_spi_setup_data_message(
 572        struct mmc_spi_host     *host,
 573        int                     multiple,
 574        enum dma_data_direction direction)
 575{
 576        struct spi_transfer     *t;
 577        struct scratch          *scratch = host->data;
 578        dma_addr_t              dma = host->data_dma;
 579
 580        spi_message_init(&host->m);
 581        if (dma)
 582                host->m.is_dma_mapped = 1;
 583
 584        /* for reads, readblock() skips 0xff bytes before finding
 585         * the token; for writes, this transfer issues that token.
 586         */
 587        if (direction == DMA_TO_DEVICE) {
 588                t = &host->token;
 589                memset(t, 0, sizeof(*t));
 590                t->len = 1;
 591                if (multiple)
 592                        scratch->data_token = SPI_TOKEN_MULTI_WRITE;
 593                else
 594                        scratch->data_token = SPI_TOKEN_SINGLE;
 595                t->tx_buf = &scratch->data_token;
 596                if (dma)
 597                        t->tx_dma = dma + offsetof(struct scratch, data_token);
 598                spi_message_add_tail(t, &host->m);
 599        }
 600
 601        /* Body of transfer is buffer, then CRC ...
 602         * either TX-only, or RX with TX-ones.
 603         */
 604        t = &host->t;
 605        memset(t, 0, sizeof(*t));
 606        t->tx_buf = host->ones;
 607        t->tx_dma = host->ones_dma;
 608        /* length and actual buffer info are written later */
 609        spi_message_add_tail(t, &host->m);
 610
 611        t = &host->crc;
 612        memset(t, 0, sizeof(*t));
 613        t->len = 2;
 614        if (direction == DMA_TO_DEVICE) {
 615                /* the actual CRC may get written later */
 616                t->tx_buf = &scratch->crc_val;
 617                if (dma)
 618                        t->tx_dma = dma + offsetof(struct scratch, crc_val);
 619        } else {
 620                t->tx_buf = host->ones;
 621                t->tx_dma = host->ones_dma;
 622                t->rx_buf = &scratch->crc_val;
 623                if (dma)
 624                        t->rx_dma = dma + offsetof(struct scratch, crc_val);
 625        }
 626        spi_message_add_tail(t, &host->m);
 627
 628        /*
 629         * A single block read is followed by N(EC) [0+] all-ones bytes
 630         * before deselect ... don't bother.
 631         *
 632         * Multiblock reads are followed by N(AC) [1+] all-ones bytes before
 633         * the next block is read, or a STOP_TRANSMISSION is issued.  We'll
 634         * collect that single byte, so readblock() doesn't need to.
 635         *
 636         * For a write, the one-byte data response follows immediately, then
 637         * come zero or more busy bytes, then N(WR) [1+] all-ones bytes.
 638         * Then single block reads may deselect, and multiblock ones issue
 639         * the next token (next data block, or STOP_TRAN).  We can try to
 640         * minimize I/O ops by using a single read to collect end-of-busy.
 641         */
 642        if (multiple || direction == DMA_TO_DEVICE) {
 643                t = &host->early_status;
 644                memset(t, 0, sizeof(*t));
 645                t->len = (direction == DMA_TO_DEVICE)
 646                                ? sizeof(scratch->status)
 647                                : 1;
 648                t->tx_buf = host->ones;
 649                t->tx_dma = host->ones_dma;
 650                t->rx_buf = scratch->status;
 651                if (dma)
 652                        t->rx_dma = dma + offsetof(struct scratch, status);
 653                t->cs_change = 1;
 654                spi_message_add_tail(t, &host->m);
 655        }
 656}
 657
 658/*
 659 * Write one block:
 660 *  - caller handled preceding N(WR) [1+] all-ones bytes
 661 *  - data block
 662 *      + token
 663 *      + data bytes
 664 *      + crc16
 665 *  - an all-ones byte ... card writes a data-response byte
 666 *  - followed by N(EC) [0+] all-ones bytes, card writes zero/'busy'
 667 *
 668 * Return negative errno, else success.
 669 */
 670static int
 671mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t,
 672        unsigned long timeout)
 673{
 674        struct spi_device       *spi = host->spi;
 675        int                     status, i;
 676        struct scratch          *scratch = host->data;
 677        u32                     pattern;
 678
 679        if (host->mmc->use_spi_crc)
 680                scratch->crc_val = cpu_to_be16(
 681                                crc_itu_t(0, t->tx_buf, t->len));
 682        if (host->dma_dev)
 683                dma_sync_single_for_device(host->dma_dev,
 684                                host->data_dma, sizeof(*scratch),
 685                                DMA_BIDIRECTIONAL);
 686
 687        status = spi_sync_locked(spi, &host->m);
 688
 689        if (status != 0) {
 690                dev_dbg(&spi->dev, "write error (%d)\n", status);
 691                return status;
 692        }
 693
 694        if (host->dma_dev)
 695                dma_sync_single_for_cpu(host->dma_dev,
 696                                host->data_dma, sizeof(*scratch),
 697                                DMA_BIDIRECTIONAL);
 698
 699        /*
 700         * Get the transmission data-response reply.  It must follow
 701         * immediately after the data block we transferred.  This reply
 702         * doesn't necessarily tell whether the write operation succeeded;
 703         * it just says if the transmission was ok and whether *earlier*
 704         * writes succeeded; see the standard.
 705         *
 706         * In practice, there are (even modern SDHC-)cards which are late
 707         * in sending the response, and miss the time frame by a few bits,
 708         * so we have to cope with this situation and check the response
 709         * bit-by-bit. Arggh!!!
 710         */
 711        pattern = get_unaligned_be32(scratch->status);
 712
 713        /* First 3 bit of pattern are undefined */
 714        pattern |= 0xE0000000;
 715
 716        /* left-adjust to leading 0 bit */
 717        while (pattern & 0x80000000)
 718                pattern <<= 1;
 719        /* right-adjust for pattern matching. Code is in bit 4..0 now. */
 720        pattern >>= 27;
 721
 722        switch (pattern) {
 723        case SPI_RESPONSE_ACCEPTED:
 724                status = 0;
 725                break;
 726        case SPI_RESPONSE_CRC_ERR:
 727                /* host shall then issue MMC_STOP_TRANSMISSION */
 728                status = -EILSEQ;
 729                break;
 730        case SPI_RESPONSE_WRITE_ERR:
 731                /* host shall then issue MMC_STOP_TRANSMISSION,
 732                 * and should MMC_SEND_STATUS to sort it out
 733                 */
 734                status = -EIO;
 735                break;
 736        default:
 737                status = -EPROTO;
 738                break;
 739        }
 740        if (status != 0) {
 741                dev_dbg(&spi->dev, "write error %02x (%d)\n",
 742                        scratch->status[0], status);
 743                return status;
 744        }
 745
 746        t->tx_buf += t->len;
 747        if (host->dma_dev)
 748                t->tx_dma += t->len;
 749
 750        /* Return when not busy.  If we didn't collect that status yet,
 751         * we'll need some more I/O.
 752         */
 753        for (i = 4; i < sizeof(scratch->status); i++) {
 754                /* card is non-busy if the most recent bit is 1 */
 755                if (scratch->status[i] & 0x01)
 756                        return 0;
 757        }
 758        return mmc_spi_wait_unbusy(host, timeout);
 759}
 760
 761/*
 762 * Read one block:
 763 *  - skip leading all-ones bytes ... either
 764 *      + N(AC) [1..f(clock,CSD)] usually, else
 765 *      + N(CX) [0..8] when reading CSD or CID
 766 *  - data block
 767 *      + token ... if error token, no data or crc
 768 *      + data bytes
 769 *      + crc16
 770 *
 771 * After single block reads, we're done; N(EC) [0+] all-ones bytes follow
 772 * before dropping chipselect.
 773 *
 774 * For multiblock reads, caller either reads the next block or issues a
 775 * STOP_TRANSMISSION command.
 776 */
 777static int
 778mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t,
 779        unsigned long timeout)
 780{
 781        struct spi_device       *spi = host->spi;
 782        int                     status;
 783        struct scratch          *scratch = host->data;
 784        unsigned int            bitshift;
 785        u8                      leftover;
 786
 787        /* At least one SD card sends an all-zeroes byte when N(CX)
 788         * applies, before the all-ones bytes ... just cope with that.
 789         */
 790        status = mmc_spi_readbytes(host, 1);
 791        if (status < 0)
 792                return status;
 793        status = scratch->status[0];
 794        if (status == 0xff || status == 0)
 795                status = mmc_spi_readtoken(host, timeout);
 796
 797        if (status < 0) {
 798                dev_dbg(&spi->dev, "read error %02x (%d)\n", status, status);
 799                return status;
 800        }
 801
 802        /* The token may be bit-shifted...
 803         * the first 0-bit precedes the data stream.
 804         */
 805        bitshift = 7;
 806        while (status & 0x80) {
 807                status <<= 1;
 808                bitshift--;
 809        }
 810        leftover = status << 1;
 811
 812        if (host->dma_dev) {
 813                dma_sync_single_for_device(host->dma_dev,
 814                                host->data_dma, sizeof(*scratch),
 815                                DMA_BIDIRECTIONAL);
 816                dma_sync_single_for_device(host->dma_dev,
 817                                t->rx_dma, t->len,
 818                                DMA_FROM_DEVICE);
 819        }
 820
 821        status = spi_sync_locked(spi, &host->m);
 822
 823        if (host->dma_dev) {
 824                dma_sync_single_for_cpu(host->dma_dev,
 825                                host->data_dma, sizeof(*scratch),
 826                                DMA_BIDIRECTIONAL);
 827                dma_sync_single_for_cpu(host->dma_dev,
 828                                t->rx_dma, t->len,
 829                                DMA_FROM_DEVICE);
 830        }
 831
 832        if (bitshift) {
 833                /* Walk through the data and the crc and do
 834                 * all the magic to get byte-aligned data.
 835                 */
 836                u8 *cp = t->rx_buf;
 837                unsigned int len;
 838                unsigned int bitright = 8 - bitshift;
 839                u8 temp;
 840                for (len = t->len; len; len--) {
 841                        temp = *cp;
 842                        *cp++ = leftover | (temp >> bitshift);
 843                        leftover = temp << bitright;
 844                }
 845                cp = (u8 *) &scratch->crc_val;
 846                temp = *cp;
 847                *cp++ = leftover | (temp >> bitshift);
 848                leftover = temp << bitright;
 849                temp = *cp;
 850                *cp = leftover | (temp >> bitshift);
 851        }
 852
 853        if (host->mmc->use_spi_crc) {
 854                u16 crc = crc_itu_t(0, t->rx_buf, t->len);
 855
 856                be16_to_cpus(&scratch->crc_val);
 857                if (scratch->crc_val != crc) {
 858                        dev_dbg(&spi->dev, "read - crc error: crc_val=0x%04x, "
 859                                        "computed=0x%04x len=%d\n",
 860                                        scratch->crc_val, crc, t->len);
 861                        return -EILSEQ;
 862                }
 863        }
 864
 865        t->rx_buf += t->len;
 866        if (host->dma_dev)
 867                t->rx_dma += t->len;
 868
 869        return 0;
 870}
 871
 872/*
 873 * An MMC/SD data stage includes one or more blocks, optional CRCs,
 874 * and inline handshaking.  That handhaking makes it unlike most
 875 * other SPI protocol stacks.
 876 */
 877static void
 878mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd,
 879                struct mmc_data *data, u32 blk_size)
 880{
 881        struct spi_device       *spi = host->spi;
 882        struct device           *dma_dev = host->dma_dev;
 883        struct spi_transfer     *t;
 884        enum dma_data_direction direction;
 885        struct scatterlist      *sg;
 886        unsigned                n_sg;
 887        int                     multiple = (data->blocks > 1);
 888        u32                     clock_rate;
 889        unsigned long           timeout;
 890
 891        direction = mmc_get_dma_dir(data);
 892        mmc_spi_setup_data_message(host, multiple, direction);
 893        t = &host->t;
 894
 895        if (t->speed_hz)
 896                clock_rate = t->speed_hz;
 897        else
 898                clock_rate = spi->max_speed_hz;
 899
 900        timeout = data->timeout_ns +
 901                  data->timeout_clks * 1000000 / clock_rate;
 902        timeout = usecs_to_jiffies((unsigned int)(timeout / 1000)) + 1;
 903
 904        /* Handle scatterlist segments one at a time, with synch for
 905         * each 512-byte block
 906         */
 907        for (sg = data->sg, n_sg = data->sg_len; n_sg; n_sg--, sg++) {
 908                int                     status = 0;
 909                dma_addr_t              dma_addr = 0;
 910                void                    *kmap_addr;
 911                unsigned                length = sg->length;
 912                enum dma_data_direction dir = direction;
 913
 914                /* set up dma mapping for controller drivers that might
 915                 * use DMA ... though they may fall back to PIO
 916                 */
 917                if (dma_dev) {
 918                        /* never invalidate whole *shared* pages ... */
 919                        if ((sg->offset != 0 || length != PAGE_SIZE)
 920                                        && dir == DMA_FROM_DEVICE)
 921                                dir = DMA_BIDIRECTIONAL;
 922
 923                        dma_addr = dma_map_page(dma_dev, sg_page(sg), 0,
 924                                                PAGE_SIZE, dir);
 925                        if (dma_mapping_error(dma_dev, dma_addr)) {
 926                                data->error = -EFAULT;
 927                                break;
 928                        }
 929                        if (direction == DMA_TO_DEVICE)
 930                                t->tx_dma = dma_addr + sg->offset;
 931                        else
 932                                t->rx_dma = dma_addr + sg->offset;
 933                }
 934
 935                /* allow pio too; we don't allow highmem */
 936                kmap_addr = kmap(sg_page(sg));
 937                if (direction == DMA_TO_DEVICE)
 938                        t->tx_buf = kmap_addr + sg->offset;
 939                else
 940                        t->rx_buf = kmap_addr + sg->offset;
 941
 942                /* transfer each block, and update request status */
 943                while (length) {
 944                        t->len = min(length, blk_size);
 945
 946                        dev_dbg(&host->spi->dev,
 947                                "    mmc_spi: %s block, %d bytes\n",
 948                                (direction == DMA_TO_DEVICE)
 949                                ? "write"
 950                                : "read",
 951                                t->len);
 952
 953                        if (direction == DMA_TO_DEVICE)
 954                                status = mmc_spi_writeblock(host, t, timeout);
 955                        else
 956                                status = mmc_spi_readblock(host, t, timeout);
 957                        if (status < 0)
 958                                break;
 959
 960                        data->bytes_xfered += t->len;
 961                        length -= t->len;
 962
 963                        if (!multiple)
 964                                break;
 965                }
 966
 967                /* discard mappings */
 968                if (direction == DMA_FROM_DEVICE)
 969                        flush_kernel_dcache_page(sg_page(sg));
 970                kunmap(sg_page(sg));
 971                if (dma_dev)
 972                        dma_unmap_page(dma_dev, dma_addr, PAGE_SIZE, dir);
 973
 974                if (status < 0) {
 975                        data->error = status;
 976                        dev_dbg(&spi->dev, "%s status %d\n",
 977                                (direction == DMA_TO_DEVICE)
 978                                        ? "write" : "read",
 979                                status);
 980                        break;
 981                }
 982        }
 983
 984        /* NOTE some docs describe an MMC-only SET_BLOCK_COUNT (CMD23) that
 985         * can be issued before multiblock writes.  Unlike its more widely
 986         * documented analogue for SD cards (SET_WR_BLK_ERASE_COUNT, ACMD23),
 987         * that can affect the STOP_TRAN logic.   Complete (and current)
 988         * MMC specs should sort that out before Linux starts using CMD23.
 989         */
 990        if (direction == DMA_TO_DEVICE && multiple) {
 991                struct scratch  *scratch = host->data;
 992                int             tmp;
 993                const unsigned  statlen = sizeof(scratch->status);
 994
 995                dev_dbg(&spi->dev, "    mmc_spi: STOP_TRAN\n");
 996
 997                /* Tweak the per-block message we set up earlier by morphing
 998                 * it to hold single buffer with the token followed by some
 999                 * all-ones bytes ... skip N(BR) (0..1), scan the rest for
1000                 * "not busy any longer" status, and leave chip selected.
1001                 */
1002                INIT_LIST_HEAD(&host->m.transfers);
1003                list_add(&host->early_status.transfer_list,
1004                                &host->m.transfers);
1005
1006                memset(scratch->status, 0xff, statlen);
1007                scratch->status[0] = SPI_TOKEN_STOP_TRAN;
1008
1009                host->early_status.tx_buf = host->early_status.rx_buf;
1010                host->early_status.tx_dma = host->early_status.rx_dma;
1011                host->early_status.len = statlen;
1012
1013                if (host->dma_dev)
1014                        dma_sync_single_for_device(host->dma_dev,
1015                                        host->data_dma, sizeof(*scratch),
1016                                        DMA_BIDIRECTIONAL);
1017
1018                tmp = spi_sync_locked(spi, &host->m);
1019
1020                if (host->dma_dev)
1021                        dma_sync_single_for_cpu(host->dma_dev,
1022                                        host->data_dma, sizeof(*scratch),
1023                                        DMA_BIDIRECTIONAL);
1024
1025                if (tmp < 0) {
1026                        if (!data->error)
1027                                data->error = tmp;
1028                        return;
1029                }
1030
1031                /* Ideally we collected "not busy" status with one I/O,
1032                 * avoiding wasteful byte-at-a-time scanning... but more
1033                 * I/O is often needed.
1034                 */
1035                for (tmp = 2; tmp < statlen; tmp++) {
1036                        if (scratch->status[tmp] != 0)
1037                                return;
1038                }
1039                tmp = mmc_spi_wait_unbusy(host, timeout);
1040                if (tmp < 0 && !data->error)
1041                        data->error = tmp;
1042        }
1043}
1044
1045/****************************************************************************/
1046
1047/*
1048 * MMC driver implementation -- the interface to the MMC stack
1049 */
1050
1051static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq)
1052{
1053        struct mmc_spi_host     *host = mmc_priv(mmc);
1054        int                     status = -EINVAL;
1055        int                     crc_retry = 5;
1056        struct mmc_command      stop;
1057
1058#ifdef DEBUG
1059        /* MMC core and layered drivers *MUST* issue SPI-aware commands */
1060        {
1061                struct mmc_command      *cmd;
1062                int                     invalid = 0;
1063
1064                cmd = mrq->cmd;
1065                if (!mmc_spi_resp_type(cmd)) {
1066                        dev_dbg(&host->spi->dev, "bogus command\n");
1067                        cmd->error = -EINVAL;
1068                        invalid = 1;
1069                }
1070
1071                cmd = mrq->stop;
1072                if (cmd && !mmc_spi_resp_type(cmd)) {
1073                        dev_dbg(&host->spi->dev, "bogus STOP command\n");
1074                        cmd->error = -EINVAL;
1075                        invalid = 1;
1076                }
1077
1078                if (invalid) {
1079                        dump_stack();
1080                        mmc_request_done(host->mmc, mrq);
1081                        return;
1082                }
1083        }
1084#endif
1085
1086        /* request exclusive bus access */
1087        spi_bus_lock(host->spi->master);
1088
1089crc_recover:
1090        /* issue command; then optionally data and stop */
1091        status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL);
1092        if (status == 0 && mrq->data) {
1093                mmc_spi_data_do(host, mrq->cmd, mrq->data, mrq->data->blksz);
1094
1095                /*
1096                 * The SPI bus is not always reliable for large data transfers.
1097                 * If an occasional crc error is reported by the SD device with
1098                 * data read/write over SPI, it may be recovered by repeating
1099                 * the last SD command again. The retry count is set to 5 to
1100                 * ensure the driver passes stress tests.
1101                 */
1102                if (mrq->data->error == -EILSEQ && crc_retry) {
1103                        stop.opcode = MMC_STOP_TRANSMISSION;
1104                        stop.arg = 0;
1105                        stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
1106                        status = mmc_spi_command_send(host, mrq, &stop, 0);
1107                        crc_retry--;
1108                        mrq->data->error = 0;
1109                        goto crc_recover;
1110                }
1111
1112                if (mrq->stop)
1113                        status = mmc_spi_command_send(host, mrq, mrq->stop, 0);
1114                else
1115                        mmc_cs_off(host);
1116        }
1117
1118        /* release the bus */
1119        spi_bus_unlock(host->spi->master);
1120
1121        mmc_request_done(host->mmc, mrq);
1122}
1123
1124/* See Section 6.4.1, in SD "Simplified Physical Layer Specification 2.0"
1125 *
1126 * NOTE that here we can't know that the card has just been powered up;
1127 * not all MMC/SD sockets support power switching.
1128 *
1129 * FIXME when the card is still in SPI mode, e.g. from a previous kernel,
1130 * this doesn't seem to do the right thing at all...
1131 */
1132static void mmc_spi_initsequence(struct mmc_spi_host *host)
1133{
1134        /* Try to be very sure any previous command has completed;
1135         * wait till not-busy, skip debris from any old commands.
1136         */
1137        mmc_spi_wait_unbusy(host, r1b_timeout);
1138        mmc_spi_readbytes(host, 10);
1139
1140        /*
1141         * Do a burst with chipselect active-high.  We need to do this to
1142         * meet the requirement of 74 clock cycles with both chipselect
1143         * and CMD (MOSI) high before CMD0 ... after the card has been
1144         * powered up to Vdd(min), and so is ready to take commands.
1145         *
1146         * Some cards are particularly needy of this (e.g. Viking "SD256")
1147         * while most others don't seem to care.
1148         *
1149         * Note that this is one of the places MMC/SD plays games with the
1150         * SPI protocol.  Another is that when chipselect is released while
1151         * the card returns BUSY status, the clock must issue several cycles
1152         * with chipselect high before the card will stop driving its output.
1153         */
1154        host->spi->mode |= SPI_CS_HIGH;
1155        if (spi_setup(host->spi) != 0) {
1156                /* Just warn; most cards work without it. */
1157                dev_warn(&host->spi->dev,
1158                                "can't change chip-select polarity\n");
1159                host->spi->mode &= ~SPI_CS_HIGH;
1160        } else {
1161                mmc_spi_readbytes(host, 18);
1162
1163                host->spi->mode &= ~SPI_CS_HIGH;
1164                if (spi_setup(host->spi) != 0) {
1165                        /* Wot, we can't get the same setup we had before? */
1166                        dev_err(&host->spi->dev,
1167                                        "can't restore chip-select polarity\n");
1168                }
1169        }
1170}
1171
1172static char *mmc_powerstring(u8 power_mode)
1173{
1174        switch (power_mode) {
1175        case MMC_POWER_OFF: return "off";
1176        case MMC_POWER_UP:  return "up";
1177        case MMC_POWER_ON:  return "on";
1178        }
1179        return "?";
1180}
1181
1182static void mmc_spi_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1183{
1184        struct mmc_spi_host *host = mmc_priv(mmc);
1185
1186        if (host->power_mode != ios->power_mode) {
1187                int             canpower;
1188
1189                canpower = host->pdata && host->pdata->setpower;
1190
1191                dev_dbg(&host->spi->dev, "mmc_spi: power %s (%d)%s\n",
1192                                mmc_powerstring(ios->power_mode),
1193                                ios->vdd,
1194                                canpower ? ", can switch" : "");
1195
1196                /* switch power on/off if possible, accounting for
1197                 * max 250msec powerup time if needed.
1198                 */
1199                if (canpower) {
1200                        switch (ios->power_mode) {
1201                        case MMC_POWER_OFF:
1202                        case MMC_POWER_UP:
1203                                host->pdata->setpower(&host->spi->dev,
1204                                                ios->vdd);
1205                                if (ios->power_mode == MMC_POWER_UP)
1206                                        msleep(host->powerup_msecs);
1207                        }
1208                }
1209
1210                /* See 6.4.1 in the simplified SD card physical spec 2.0 */
1211                if (ios->power_mode == MMC_POWER_ON)
1212                        mmc_spi_initsequence(host);
1213
1214                /* If powering down, ground all card inputs to avoid power
1215                 * delivery from data lines!  On a shared SPI bus, this
1216                 * will probably be temporary; 6.4.2 of the simplified SD
1217                 * spec says this must last at least 1msec.
1218                 *
1219                 *   - Clock low means CPOL 0, e.g. mode 0
1220                 *   - MOSI low comes from writing zero
1221                 *   - Chipselect is usually active low...
1222                 */
1223                if (canpower && ios->power_mode == MMC_POWER_OFF) {
1224                        int mres;
1225                        u8 nullbyte = 0;
1226
1227                        host->spi->mode &= ~(SPI_CPOL|SPI_CPHA);
1228                        mres = spi_setup(host->spi);
1229                        if (mres < 0)
1230                                dev_dbg(&host->spi->dev,
1231                                        "switch to SPI mode 0 failed\n");
1232
1233                        if (spi_write(host->spi, &nullbyte, 1) < 0)
1234                                dev_dbg(&host->spi->dev,
1235                                        "put spi signals to low failed\n");
1236
1237                        /*
1238                         * Now clock should be low due to spi mode 0;
1239                         * MOSI should be low because of written 0x00;
1240                         * chipselect should be low (it is active low)
1241                         * power supply is off, so now MMC is off too!
1242                         *
1243                         * FIXME no, chipselect can be high since the
1244                         * device is inactive and SPI_CS_HIGH is clear...
1245                         */
1246                        msleep(10);
1247                        if (mres == 0) {
1248                                host->spi->mode |= (SPI_CPOL|SPI_CPHA);
1249                                mres = spi_setup(host->spi);
1250                                if (mres < 0)
1251                                        dev_dbg(&host->spi->dev,
1252                                                "switch back to SPI mode 3"
1253                                                " failed\n");
1254                        }
1255                }
1256
1257                host->power_mode = ios->power_mode;
1258        }
1259
1260        if (host->spi->max_speed_hz != ios->clock && ios->clock != 0) {
1261                int             status;
1262
1263                host->spi->max_speed_hz = ios->clock;
1264                status = spi_setup(host->spi);
1265                dev_dbg(&host->spi->dev,
1266                        "mmc_spi:  clock to %d Hz, %d\n",
1267                        host->spi->max_speed_hz, status);
1268        }
1269}
1270
1271static const struct mmc_host_ops mmc_spi_ops = {
1272        .request        = mmc_spi_request,
1273        .set_ios        = mmc_spi_set_ios,
1274        .get_ro         = mmc_gpio_get_ro,
1275        .get_cd         = mmc_gpio_get_cd,
1276};
1277
1278
1279/****************************************************************************/
1280
1281/*
1282 * SPI driver implementation
1283 */
1284
1285static irqreturn_t
1286mmc_spi_detect_irq(int irq, void *mmc)
1287{
1288        struct mmc_spi_host *host = mmc_priv(mmc);
1289        u16 delay_msec = max(host->pdata->detect_delay, (u16)100);
1290
1291        mmc_detect_change(mmc, msecs_to_jiffies(delay_msec));
1292        return IRQ_HANDLED;
1293}
1294
1295static int mmc_spi_probe(struct spi_device *spi)
1296{
1297        void                    *ones;
1298        struct mmc_host         *mmc;
1299        struct mmc_spi_host     *host;
1300        int                     status;
1301        bool                    has_ro = false;
1302
1303        /* We rely on full duplex transfers, mostly to reduce
1304         * per-transfer overheads (by making fewer transfers).
1305         */
1306        if (spi->master->flags & SPI_MASTER_HALF_DUPLEX)
1307                return -EINVAL;
1308
1309        /* MMC and SD specs only seem to care that sampling is on the
1310         * rising edge ... meaning SPI modes 0 or 3.  So either SPI mode
1311         * should be legit.  We'll use mode 0 since the steady state is 0,
1312         * which is appropriate for hotplugging, unless the platform data
1313         * specify mode 3 (if hardware is not compatible to mode 0).
1314         */
1315        if (spi->mode != SPI_MODE_3)
1316                spi->mode = SPI_MODE_0;
1317        spi->bits_per_word = 8;
1318
1319        status = spi_setup(spi);
1320        if (status < 0) {
1321                dev_dbg(&spi->dev, "needs SPI mode %02x, %d KHz; %d\n",
1322                                spi->mode, spi->max_speed_hz / 1000,
1323                                status);
1324                return status;
1325        }
1326
1327        /* We need a supply of ones to transmit.  This is the only time
1328         * the CPU touches these, so cache coherency isn't a concern.
1329         *
1330         * NOTE if many systems use more than one MMC-over-SPI connector
1331         * it'd save some memory to share this.  That's evidently rare.
1332         */
1333        status = -ENOMEM;
1334        ones = kmalloc(MMC_SPI_BLOCKSIZE, GFP_KERNEL);
1335        if (!ones)
1336                goto nomem;
1337        memset(ones, 0xff, MMC_SPI_BLOCKSIZE);
1338
1339        mmc = mmc_alloc_host(sizeof(*host), &spi->dev);
1340        if (!mmc)
1341                goto nomem;
1342
1343        mmc->ops = &mmc_spi_ops;
1344        mmc->max_blk_size = MMC_SPI_BLOCKSIZE;
1345        mmc->max_segs = MMC_SPI_BLOCKSATONCE;
1346        mmc->max_req_size = MMC_SPI_BLOCKSATONCE * MMC_SPI_BLOCKSIZE;
1347        mmc->max_blk_count = MMC_SPI_BLOCKSATONCE;
1348
1349        mmc->caps = MMC_CAP_SPI;
1350
1351        /* SPI doesn't need the lowspeed device identification thing for
1352         * MMC or SD cards, since it never comes up in open drain mode.
1353         * That's good; some SPI masters can't handle very low speeds!
1354         *
1355         * However, low speed SDIO cards need not handle over 400 KHz;
1356         * that's the only reason not to use a few MHz for f_min (until
1357         * the upper layer reads the target frequency from the CSD).
1358         */
1359        mmc->f_min = 400000;
1360        mmc->f_max = spi->max_speed_hz;
1361
1362        host = mmc_priv(mmc);
1363        host->mmc = mmc;
1364        host->spi = spi;
1365
1366        host->ones = ones;
1367
1368        /* Platform data is used to hook up things like card sensing
1369         * and power switching gpios.
1370         */
1371        host->pdata = mmc_spi_get_pdata(spi);
1372        if (host->pdata)
1373                mmc->ocr_avail = host->pdata->ocr_mask;
1374        if (!mmc->ocr_avail) {
1375                dev_warn(&spi->dev, "ASSUMING 3.2-3.4 V slot power\n");
1376                mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
1377        }
1378        if (host->pdata && host->pdata->setpower) {
1379                host->powerup_msecs = host->pdata->powerup_msecs;
1380                if (!host->powerup_msecs || host->powerup_msecs > 250)
1381                        host->powerup_msecs = 250;
1382        }
1383
1384        dev_set_drvdata(&spi->dev, mmc);
1385
1386        /* preallocate dma buffers */
1387        host->data = kmalloc(sizeof(*host->data), GFP_KERNEL);
1388        if (!host->data)
1389                goto fail_nobuf1;
1390
1391        if (spi->master->dev.parent->dma_mask) {
1392                struct device   *dev = spi->master->dev.parent;
1393
1394                host->dma_dev = dev;
1395                host->ones_dma = dma_map_single(dev, ones,
1396                                MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE);
1397                if (dma_mapping_error(dev, host->ones_dma))
1398                        goto fail_ones_dma;
1399                host->data_dma = dma_map_single(dev, host->data,
1400                                sizeof(*host->data), DMA_BIDIRECTIONAL);
1401                if (dma_mapping_error(dev, host->data_dma))
1402                        goto fail_data_dma;
1403
1404                dma_sync_single_for_cpu(host->dma_dev,
1405                                host->data_dma, sizeof(*host->data),
1406                                DMA_BIDIRECTIONAL);
1407        }
1408
1409        /* setup message for status/busy readback */
1410        spi_message_init(&host->readback);
1411        host->readback.is_dma_mapped = (host->dma_dev != NULL);
1412
1413        spi_message_add_tail(&host->status, &host->readback);
1414        host->status.tx_buf = host->ones;
1415        host->status.tx_dma = host->ones_dma;
1416        host->status.rx_buf = &host->data->status;
1417        host->status.rx_dma = host->data_dma + offsetof(struct scratch, status);
1418        host->status.cs_change = 1;
1419
1420        /* register card detect irq */
1421        if (host->pdata && host->pdata->init) {
1422                status = host->pdata->init(&spi->dev, mmc_spi_detect_irq, mmc);
1423                if (status != 0)
1424                        goto fail_glue_init;
1425        }
1426
1427        /* pass platform capabilities, if any */
1428        if (host->pdata) {
1429                mmc->caps |= host->pdata->caps;
1430                mmc->caps2 |= host->pdata->caps2;
1431        }
1432
1433        status = mmc_add_host(mmc);
1434        if (status != 0)
1435                goto fail_add_host;
1436
1437        if (host->pdata && host->pdata->flags & MMC_SPI_USE_CD_GPIO) {
1438                status = mmc_gpio_request_cd(mmc, host->pdata->cd_gpio,
1439                                             host->pdata->cd_debounce);
1440                if (status != 0)
1441                        goto fail_add_host;
1442
1443                /* The platform has a CD GPIO signal that may support
1444                 * interrupts, so let mmc_gpiod_request_cd_irq() decide
1445                 * if polling is needed or not.
1446                 */
1447                mmc->caps &= ~MMC_CAP_NEEDS_POLL;
1448                mmc_gpiod_request_cd_irq(mmc);
1449        }
1450
1451        if (host->pdata && host->pdata->flags & MMC_SPI_USE_RO_GPIO) {
1452                has_ro = true;
1453                status = mmc_gpio_request_ro(mmc, host->pdata->ro_gpio);
1454                if (status != 0)
1455                        goto fail_add_host;
1456        }
1457
1458        dev_info(&spi->dev, "SD/MMC host %s%s%s%s%s\n",
1459                        dev_name(&mmc->class_dev),
1460                        host->dma_dev ? "" : ", no DMA",
1461                        has_ro ? "" : ", no WP",
1462                        (host->pdata && host->pdata->setpower)
1463                                ? "" : ", no poweroff",
1464                        (mmc->caps & MMC_CAP_NEEDS_POLL)
1465                                ? ", cd polling" : "");
1466        return 0;
1467
1468fail_add_host:
1469        mmc_remove_host (mmc);
1470fail_glue_init:
1471        if (host->dma_dev)
1472                dma_unmap_single(host->dma_dev, host->data_dma,
1473                                sizeof(*host->data), DMA_BIDIRECTIONAL);
1474fail_data_dma:
1475        if (host->dma_dev)
1476                dma_unmap_single(host->dma_dev, host->ones_dma,
1477                                MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE);
1478fail_ones_dma:
1479        kfree(host->data);
1480
1481fail_nobuf1:
1482        mmc_free_host(mmc);
1483        mmc_spi_put_pdata(spi);
1484        dev_set_drvdata(&spi->dev, NULL);
1485
1486nomem:
1487        kfree(ones);
1488        return status;
1489}
1490
1491
1492static int mmc_spi_remove(struct spi_device *spi)
1493{
1494        struct mmc_host         *mmc = dev_get_drvdata(&spi->dev);
1495        struct mmc_spi_host     *host;
1496
1497        if (mmc) {
1498                host = mmc_priv(mmc);
1499
1500                /* prevent new mmc_detect_change() calls */
1501                if (host->pdata && host->pdata->exit)
1502                        host->pdata->exit(&spi->dev, mmc);
1503
1504                mmc_remove_host(mmc);
1505
1506                if (host->dma_dev) {
1507                        dma_unmap_single(host->dma_dev, host->ones_dma,
1508                                MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE);
1509                        dma_unmap_single(host->dma_dev, host->data_dma,
1510                                sizeof(*host->data), DMA_BIDIRECTIONAL);
1511                }
1512
1513                kfree(host->data);
1514                kfree(host->ones);
1515
1516                spi->max_speed_hz = mmc->f_max;
1517                mmc_free_host(mmc);
1518                mmc_spi_put_pdata(spi);
1519                dev_set_drvdata(&spi->dev, NULL);
1520        }
1521        return 0;
1522}
1523
1524static const struct of_device_id mmc_spi_of_match_table[] = {
1525        { .compatible = "mmc-spi-slot", },
1526        {},
1527};
1528MODULE_DEVICE_TABLE(of, mmc_spi_of_match_table);
1529
1530static struct spi_driver mmc_spi_driver = {
1531        .driver = {
1532                .name =         "mmc_spi",
1533                .of_match_table = mmc_spi_of_match_table,
1534        },
1535        .probe =        mmc_spi_probe,
1536        .remove =       mmc_spi_remove,
1537};
1538
1539module_spi_driver(mmc_spi_driver);
1540
1541MODULE_AUTHOR("Mike Lavender, David Brownell, "
1542                "Hans-Peter Nilsson, Jan Nikitenko");
1543MODULE_DESCRIPTION("SPI SD/MMC host driver");
1544MODULE_LICENSE("GPL");
1545MODULE_ALIAS("spi:mmc_spi");
1546