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19#include <linux/bitops.h>
20#include <linux/clk.h>
21#include <linux/dma-mapping.h>
22#include <linux/iopoll.h>
23#include <linux/module.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/spi-nor.h>
26#include <linux/of.h>
27#include <linux/platform_device.h>
28#include <linux/slab.h>
29
30
31#define FMC_CFG 0x00
32#define FMC_CFG_OP_MODE_MASK BIT_MASK(0)
33#define FMC_CFG_OP_MODE_BOOT 0
34#define FMC_CFG_OP_MODE_NORMAL 1
35#define FMC_CFG_FLASH_SEL(type) (((type) & 0x3) << 1)
36#define FMC_CFG_FLASH_SEL_MASK 0x6
37#define FMC_ECC_TYPE(type) (((type) & 0x7) << 5)
38#define FMC_ECC_TYPE_MASK GENMASK(7, 5)
39#define SPI_NOR_ADDR_MODE_MASK BIT_MASK(10)
40#define SPI_NOR_ADDR_MODE_3BYTES (0x0 << 10)
41#define SPI_NOR_ADDR_MODE_4BYTES (0x1 << 10)
42#define FMC_GLOBAL_CFG 0x04
43#define FMC_GLOBAL_CFG_WP_ENABLE BIT(6)
44#define FMC_SPI_TIMING_CFG 0x08
45#define TIMING_CFG_TCSH(nr) (((nr) & 0xf) << 8)
46#define TIMING_CFG_TCSS(nr) (((nr) & 0xf) << 4)
47#define TIMING_CFG_TSHSL(nr) ((nr) & 0xf)
48#define CS_HOLD_TIME 0x6
49#define CS_SETUP_TIME 0x6
50#define CS_DESELECT_TIME 0xf
51#define FMC_INT 0x18
52#define FMC_INT_OP_DONE BIT(0)
53#define FMC_INT_CLR 0x20
54#define FMC_CMD 0x24
55#define FMC_CMD_CMD1(cmd) ((cmd) & 0xff)
56#define FMC_ADDRL 0x2c
57#define FMC_OP_CFG 0x30
58#define OP_CFG_FM_CS(cs) ((cs) << 11)
59#define OP_CFG_MEM_IF_TYPE(type) (((type) & 0x7) << 7)
60#define OP_CFG_ADDR_NUM(addr) (((addr) & 0x7) << 4)
61#define OP_CFG_DUMMY_NUM(dummy) ((dummy) & 0xf)
62#define FMC_DATA_NUM 0x38
63#define FMC_DATA_NUM_CNT(cnt) ((cnt) & GENMASK(13, 0))
64#define FMC_OP 0x3c
65#define FMC_OP_DUMMY_EN BIT(8)
66#define FMC_OP_CMD1_EN BIT(7)
67#define FMC_OP_ADDR_EN BIT(6)
68#define FMC_OP_WRITE_DATA_EN BIT(5)
69#define FMC_OP_READ_DATA_EN BIT(2)
70#define FMC_OP_READ_STATUS_EN BIT(1)
71#define FMC_OP_REG_OP_START BIT(0)
72#define FMC_DMA_LEN 0x40
73#define FMC_DMA_LEN_SET(len) ((len) & GENMASK(27, 0))
74#define FMC_DMA_SADDR_D0 0x4c
75#define HIFMC_DMA_MAX_LEN (4096)
76#define HIFMC_DMA_MASK (HIFMC_DMA_MAX_LEN - 1)
77#define FMC_OP_DMA 0x68
78#define OP_CTRL_RD_OPCODE(code) (((code) & 0xff) << 16)
79#define OP_CTRL_WR_OPCODE(code) (((code) & 0xff) << 8)
80#define OP_CTRL_RW_OP(op) ((op) << 1)
81#define OP_CTRL_DMA_OP_READY BIT(0)
82#define FMC_OP_READ 0x0
83#define FMC_OP_WRITE 0x1
84#define FMC_WAIT_TIMEOUT 1000000
85
86enum hifmc_iftype {
87 IF_TYPE_STD,
88 IF_TYPE_DUAL,
89 IF_TYPE_DIO,
90 IF_TYPE_QUAD,
91 IF_TYPE_QIO,
92};
93
94struct hifmc_priv {
95 u32 chipselect;
96 u32 clkrate;
97 struct hifmc_host *host;
98};
99
100#define HIFMC_MAX_CHIP_NUM 2
101struct hifmc_host {
102 struct device *dev;
103 struct mutex lock;
104
105 void __iomem *regbase;
106 void __iomem *iobase;
107 struct clk *clk;
108 void *buffer;
109 dma_addr_t dma_buffer;
110
111 struct spi_nor *nor[HIFMC_MAX_CHIP_NUM];
112 u32 num_chip;
113};
114
115static inline int hisi_spi_nor_wait_op_finish(struct hifmc_host *host)
116{
117 u32 reg;
118
119 return readl_poll_timeout(host->regbase + FMC_INT, reg,
120 (reg & FMC_INT_OP_DONE), 0, FMC_WAIT_TIMEOUT);
121}
122
123static int hisi_spi_nor_get_if_type(enum spi_nor_protocol proto)
124{
125 enum hifmc_iftype if_type;
126
127 switch (proto) {
128 case SNOR_PROTO_1_1_2:
129 if_type = IF_TYPE_DUAL;
130 break;
131 case SNOR_PROTO_1_2_2:
132 if_type = IF_TYPE_DIO;
133 break;
134 case SNOR_PROTO_1_1_4:
135 if_type = IF_TYPE_QUAD;
136 break;
137 case SNOR_PROTO_1_4_4:
138 if_type = IF_TYPE_QIO;
139 break;
140 case SNOR_PROTO_1_1_1:
141 default:
142 if_type = IF_TYPE_STD;
143 break;
144 }
145
146 return if_type;
147}
148
149static void hisi_spi_nor_init(struct hifmc_host *host)
150{
151 u32 reg;
152
153 reg = TIMING_CFG_TCSH(CS_HOLD_TIME)
154 | TIMING_CFG_TCSS(CS_SETUP_TIME)
155 | TIMING_CFG_TSHSL(CS_DESELECT_TIME);
156 writel(reg, host->regbase + FMC_SPI_TIMING_CFG);
157}
158
159static int hisi_spi_nor_prep(struct spi_nor *nor, enum spi_nor_ops ops)
160{
161 struct hifmc_priv *priv = nor->priv;
162 struct hifmc_host *host = priv->host;
163 int ret;
164
165 mutex_lock(&host->lock);
166
167 ret = clk_set_rate(host->clk, priv->clkrate);
168 if (ret)
169 goto out;
170
171 ret = clk_prepare_enable(host->clk);
172 if (ret)
173 goto out;
174
175 return 0;
176
177out:
178 mutex_unlock(&host->lock);
179 return ret;
180}
181
182static void hisi_spi_nor_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
183{
184 struct hifmc_priv *priv = nor->priv;
185 struct hifmc_host *host = priv->host;
186
187 clk_disable_unprepare(host->clk);
188 mutex_unlock(&host->lock);
189}
190
191static int hisi_spi_nor_op_reg(struct spi_nor *nor,
192 u8 opcode, int len, u8 optype)
193{
194 struct hifmc_priv *priv = nor->priv;
195 struct hifmc_host *host = priv->host;
196 u32 reg;
197
198 reg = FMC_CMD_CMD1(opcode);
199 writel(reg, host->regbase + FMC_CMD);
200
201 reg = FMC_DATA_NUM_CNT(len);
202 writel(reg, host->regbase + FMC_DATA_NUM);
203
204 reg = OP_CFG_FM_CS(priv->chipselect);
205 writel(reg, host->regbase + FMC_OP_CFG);
206
207 writel(0xff, host->regbase + FMC_INT_CLR);
208 reg = FMC_OP_CMD1_EN | FMC_OP_REG_OP_START | optype;
209 writel(reg, host->regbase + FMC_OP);
210
211 return hisi_spi_nor_wait_op_finish(host);
212}
213
214static int hisi_spi_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
215 int len)
216{
217 struct hifmc_priv *priv = nor->priv;
218 struct hifmc_host *host = priv->host;
219 int ret;
220
221 ret = hisi_spi_nor_op_reg(nor, opcode, len, FMC_OP_READ_DATA_EN);
222 if (ret)
223 return ret;
224
225 memcpy_fromio(buf, host->iobase, len);
226 return 0;
227}
228
229static int hisi_spi_nor_write_reg(struct spi_nor *nor, u8 opcode,
230 u8 *buf, int len)
231{
232 struct hifmc_priv *priv = nor->priv;
233 struct hifmc_host *host = priv->host;
234
235 if (len)
236 memcpy_toio(host->iobase, buf, len);
237
238 return hisi_spi_nor_op_reg(nor, opcode, len, FMC_OP_WRITE_DATA_EN);
239}
240
241static int hisi_spi_nor_dma_transfer(struct spi_nor *nor, loff_t start_off,
242 dma_addr_t dma_buf, size_t len, u8 op_type)
243{
244 struct hifmc_priv *priv = nor->priv;
245 struct hifmc_host *host = priv->host;
246 u8 if_type = 0;
247 u32 reg;
248
249 reg = readl(host->regbase + FMC_CFG);
250 reg &= ~(FMC_CFG_OP_MODE_MASK | SPI_NOR_ADDR_MODE_MASK);
251 reg |= FMC_CFG_OP_MODE_NORMAL;
252 reg |= (nor->addr_width == 4) ? SPI_NOR_ADDR_MODE_4BYTES
253 : SPI_NOR_ADDR_MODE_3BYTES;
254 writel(reg, host->regbase + FMC_CFG);
255
256 writel(start_off, host->regbase + FMC_ADDRL);
257 writel(dma_buf, host->regbase + FMC_DMA_SADDR_D0);
258 writel(FMC_DMA_LEN_SET(len), host->regbase + FMC_DMA_LEN);
259
260 reg = OP_CFG_FM_CS(priv->chipselect);
261 if (op_type == FMC_OP_READ)
262 if_type = hisi_spi_nor_get_if_type(nor->read_proto);
263 else
264 if_type = hisi_spi_nor_get_if_type(nor->write_proto);
265 reg |= OP_CFG_MEM_IF_TYPE(if_type);
266 if (op_type == FMC_OP_READ)
267 reg |= OP_CFG_DUMMY_NUM(nor->read_dummy >> 3);
268 writel(reg, host->regbase + FMC_OP_CFG);
269
270 writel(0xff, host->regbase + FMC_INT_CLR);
271 reg = OP_CTRL_RW_OP(op_type) | OP_CTRL_DMA_OP_READY;
272 reg |= (op_type == FMC_OP_READ)
273 ? OP_CTRL_RD_OPCODE(nor->read_opcode)
274 : OP_CTRL_WR_OPCODE(nor->program_opcode);
275 writel(reg, host->regbase + FMC_OP_DMA);
276
277 return hisi_spi_nor_wait_op_finish(host);
278}
279
280static ssize_t hisi_spi_nor_read(struct spi_nor *nor, loff_t from, size_t len,
281 u_char *read_buf)
282{
283 struct hifmc_priv *priv = nor->priv;
284 struct hifmc_host *host = priv->host;
285 size_t offset;
286 int ret;
287
288 for (offset = 0; offset < len; offset += HIFMC_DMA_MAX_LEN) {
289 size_t trans = min_t(size_t, HIFMC_DMA_MAX_LEN, len - offset);
290
291 ret = hisi_spi_nor_dma_transfer(nor,
292 from + offset, host->dma_buffer, trans, FMC_OP_READ);
293 if (ret) {
294 dev_warn(nor->dev, "DMA read timeout\n");
295 return ret;
296 }
297 memcpy(read_buf + offset, host->buffer, trans);
298 }
299
300 return len;
301}
302
303static ssize_t hisi_spi_nor_write(struct spi_nor *nor, loff_t to,
304 size_t len, const u_char *write_buf)
305{
306 struct hifmc_priv *priv = nor->priv;
307 struct hifmc_host *host = priv->host;
308 size_t offset;
309 int ret;
310
311 for (offset = 0; offset < len; offset += HIFMC_DMA_MAX_LEN) {
312 size_t trans = min_t(size_t, HIFMC_DMA_MAX_LEN, len - offset);
313
314 memcpy(host->buffer, write_buf + offset, trans);
315 ret = hisi_spi_nor_dma_transfer(nor,
316 to + offset, host->dma_buffer, trans, FMC_OP_WRITE);
317 if (ret) {
318 dev_warn(nor->dev, "DMA write timeout\n");
319 return ret;
320 }
321 }
322
323 return len;
324}
325
326
327
328
329static int hisi_spi_nor_register(struct device_node *np,
330 struct hifmc_host *host)
331{
332 const struct spi_nor_hwcaps hwcaps = {
333 .mask = SNOR_HWCAPS_READ |
334 SNOR_HWCAPS_READ_FAST |
335 SNOR_HWCAPS_READ_1_1_2 |
336 SNOR_HWCAPS_READ_1_1_4 |
337 SNOR_HWCAPS_PP,
338 };
339 struct device *dev = host->dev;
340 struct spi_nor *nor;
341 struct hifmc_priv *priv;
342 struct mtd_info *mtd;
343 int ret;
344
345 nor = devm_kzalloc(dev, sizeof(*nor), GFP_KERNEL);
346 if (!nor)
347 return -ENOMEM;
348
349 nor->dev = dev;
350 spi_nor_set_flash_node(nor, np);
351
352 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
353 if (!priv)
354 return -ENOMEM;
355
356 ret = of_property_read_u32(np, "reg", &priv->chipselect);
357 if (ret) {
358 dev_err(dev, "There's no reg property for %pOF\n",
359 np);
360 return ret;
361 }
362
363 ret = of_property_read_u32(np, "spi-max-frequency",
364 &priv->clkrate);
365 if (ret) {
366 dev_err(dev, "There's no spi-max-frequency property for %pOF\n",
367 np);
368 return ret;
369 }
370 priv->host = host;
371 nor->priv = priv;
372
373 nor->prepare = hisi_spi_nor_prep;
374 nor->unprepare = hisi_spi_nor_unprep;
375 nor->read_reg = hisi_spi_nor_read_reg;
376 nor->write_reg = hisi_spi_nor_write_reg;
377 nor->read = hisi_spi_nor_read;
378 nor->write = hisi_spi_nor_write;
379 nor->erase = NULL;
380 ret = spi_nor_scan(nor, NULL, &hwcaps);
381 if (ret)
382 return ret;
383
384 mtd = &nor->mtd;
385 mtd->name = np->name;
386 ret = mtd_device_register(mtd, NULL, 0);
387 if (ret)
388 return ret;
389
390 host->nor[host->num_chip] = nor;
391 host->num_chip++;
392 return 0;
393}
394
395static void hisi_spi_nor_unregister_all(struct hifmc_host *host)
396{
397 int i;
398
399 for (i = 0; i < host->num_chip; i++)
400 mtd_device_unregister(&host->nor[i]->mtd);
401}
402
403static int hisi_spi_nor_register_all(struct hifmc_host *host)
404{
405 struct device *dev = host->dev;
406 struct device_node *np;
407 int ret;
408
409 for_each_available_child_of_node(dev->of_node, np) {
410 ret = hisi_spi_nor_register(np, host);
411 if (ret)
412 goto fail;
413
414 if (host->num_chip == HIFMC_MAX_CHIP_NUM) {
415 dev_warn(dev, "Flash device number exceeds the maximum chipselect number\n");
416 break;
417 }
418 }
419
420 return 0;
421
422fail:
423 hisi_spi_nor_unregister_all(host);
424 return ret;
425}
426
427static int hisi_spi_nor_probe(struct platform_device *pdev)
428{
429 struct device *dev = &pdev->dev;
430 struct resource *res;
431 struct hifmc_host *host;
432 int ret;
433
434 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
435 if (!host)
436 return -ENOMEM;
437
438 platform_set_drvdata(pdev, host);
439 host->dev = dev;
440
441 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control");
442 host->regbase = devm_ioremap_resource(dev, res);
443 if (IS_ERR(host->regbase))
444 return PTR_ERR(host->regbase);
445
446 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory");
447 host->iobase = devm_ioremap_resource(dev, res);
448 if (IS_ERR(host->iobase))
449 return PTR_ERR(host->iobase);
450
451 host->clk = devm_clk_get(dev, NULL);
452 if (IS_ERR(host->clk))
453 return PTR_ERR(host->clk);
454
455 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
456 if (ret) {
457 dev_warn(dev, "Unable to set dma mask\n");
458 return ret;
459 }
460
461 host->buffer = dmam_alloc_coherent(dev, HIFMC_DMA_MAX_LEN,
462 &host->dma_buffer, GFP_KERNEL);
463 if (!host->buffer)
464 return -ENOMEM;
465
466 ret = clk_prepare_enable(host->clk);
467 if (ret)
468 return ret;
469
470 mutex_init(&host->lock);
471 hisi_spi_nor_init(host);
472 ret = hisi_spi_nor_register_all(host);
473 if (ret)
474 mutex_destroy(&host->lock);
475
476 clk_disable_unprepare(host->clk);
477 return ret;
478}
479
480static int hisi_spi_nor_remove(struct platform_device *pdev)
481{
482 struct hifmc_host *host = platform_get_drvdata(pdev);
483
484 hisi_spi_nor_unregister_all(host);
485 mutex_destroy(&host->lock);
486 clk_disable_unprepare(host->clk);
487 return 0;
488}
489
490static const struct of_device_id hisi_spi_nor_dt_ids[] = {
491 { .compatible = "hisilicon,fmc-spi-nor"},
492 { }
493};
494MODULE_DEVICE_TABLE(of, hisi_spi_nor_dt_ids);
495
496static struct platform_driver hisi_spi_nor_driver = {
497 .driver = {
498 .name = "hisi-sfc",
499 .of_match_table = hisi_spi_nor_dt_ids,
500 },
501 .probe = hisi_spi_nor_probe,
502 .remove = hisi_spi_nor_remove,
503};
504module_platform_driver(hisi_spi_nor_driver);
505
506MODULE_LICENSE("GPL v2");
507MODULE_DESCRIPTION("HiSilicon SPI Nor Flash Controller Driver");
508
