LXR linux/drivers/net/ethernet/sun/cassini.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* $Id: cassini.h,v 1.16 2004/08/17 21:15:16 zaumen Exp $
   3 * cassini.h: Definitions for Sun Microsystems Cassini(+) ethernet driver.
   4 *
   5 * Copyright (C) 2004 Sun Microsystems Inc.
   6 * Copyright (c) 2003 Adrian Sun (asun@darksunrising.com)
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of the
  11 * License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
  20 *
  21 * vendor id: 0x108E (Sun Microsystems, Inc.)
  22 * device id: 0xabba (Cassini)
  23 * revision ids: 0x01 = Cassini
  24 *               0x02 = Cassini rev 2
  25 *               0x10 = Cassini+
  26 *               0x11 = Cassini+ 0.2u
  27 *
  28 * vendor id: 0x100b (National Semiconductor)
  29 * device id: 0x0035 (DP83065/Saturn)
  30 * revision ids: 0x30 = Saturn B2
  31 *
  32 * rings are all offset from 0.
  33 *
  34 * there are two clock domains:
  35 * PCI:  33/66MHz clock
  36 * chip: 125MHz clock
  37 */
  38
  39#ifndef _CASSINI_H
  40#define _CASSINI_H
  41
  42/* cassini register map: 2M memory mapped in 32-bit memory space accessible as
  43 * 32-bit words. there is no i/o port access. REG_ addresses are
  44 * shared between cassini and cassini+. REG_PLUS_ addresses only
  45 * appear in cassini+. REG_MINUS_ addresses only appear in cassini.
  46 */
  47#define CAS_ID_REV2          0x02
  48#define CAS_ID_REVPLUS       0x10
  49#define CAS_ID_REVPLUS02u    0x11
  50#define CAS_ID_REVSATURNB2   0x30
  51
  52/** global resources **/
  53
  54/* this register sets the weights for the weighted round robin arbiter. e.g.,
  55 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
  56 * for its next turn to access the pci bus.
  57 * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8
  58 * DEFAULT: 0x0, SIZE: 5 bits
  59 */
  60#define  REG_CAWR                      0x0004  /* core arbitration weight */
  61#define    CAWR_RX_DMA_WEIGHT_SHIFT    0
  62#define    CAWR_RX_DMA_WEIGHT_MASK     0x03    /* [0:1] */
  63#define    CAWR_TX_DMA_WEIGHT_SHIFT    2
  64#define    CAWR_TX_DMA_WEIGHT_MASK     0x0C    /* [3:2] */
  65#define    CAWR_RR_DIS                 0x10    /* [4] */
  66
  67/* if enabled, BIM can send bursts across PCI bus > cacheline size. burst
  68 * sizes determined by length of packet or descriptor transfer and the
  69 * max length allowed by the target.
  70 * DEFAULT: 0x0, SIZE: 1 bit
  71 */
  72#define  REG_INF_BURST                 0x0008  /* infinite burst enable reg */
  73#define    INF_BURST_EN                0x1     /* enable */
  74
  75/* top level interrupts [0-9] are auto-cleared to 0 when the status
  76 * register is read. second level interrupts [13 - 18] are cleared at
  77 * the source. tx completion register 3 is replicated in [19 - 31]
  78 * DEFAULT: 0x00000000, SIZE: 29 bits
  79 */
  80#define  REG_INTR_STATUS               0x000C  /* interrupt status register */
  81#define    INTR_TX_INTME               0x00000001  /* frame w/ INT ME desc bit set
  82                                                      xferred from host queue to
  83                                                      TX FIFO */
  84#define    INTR_TX_ALL                 0x00000002  /* all xmit frames xferred into
  85                                                      TX FIFO. i.e.,
  86                                                      TX Kick == TX complete. if
  87                                                      PACED_MODE set, then TX FIFO
  88                                                      also empty */
  89#define    INTR_TX_DONE                0x00000004  /* any frame xferred into tx
  90                                                      FIFO */
  91#define    INTR_TX_TAG_ERROR           0x00000008  /* TX FIFO tag framing
  92                                                      corrupted. FATAL ERROR */
  93#define    INTR_RX_DONE                0x00000010  /* at least 1 frame xferred
  94                                                      from RX FIFO to host mem.
  95                                                      RX completion reg updated.
  96                                                      may be delayed by recv
  97                                                      intr blanking. */
  98#define    INTR_RX_BUF_UNAVAIL         0x00000020  /* no more receive buffers.
  99                                                      RX Kick == RX complete */
 100#define    INTR_RX_TAG_ERROR           0x00000040  /* RX FIFO tag framing
 101                                                      corrupted. FATAL ERROR */
 102#define    INTR_RX_COMP_FULL           0x00000080  /* no more room in completion
 103                                                      ring to post descriptors.
 104                                                      RX complete head incr to
 105                                                      almost reach RX complete
 106                                                      tail */
 107#define    INTR_RX_BUF_AE              0x00000100  /* less than the
 108                                                      programmable threshold #
 109                                                      of free descr avail for
 110                                                      hw use */
 111#define    INTR_RX_COMP_AF             0x00000200  /* less than the
 112                                                      programmable threshold #
 113                                                      of descr spaces for hw
 114                                                      use in completion descr
 115                                                      ring */
 116#define    INTR_RX_LEN_MISMATCH        0x00000400  /* len field from MAC !=
 117                                                      len of non-reassembly pkt
 118                                                      from fifo during DMA or
 119                                                      header parser provides TCP
 120                                                      header and payload size >
 121                                                      MAC packet size.
 122                                                      FATAL ERROR */
 123#define    INTR_SUMMARY                0x00001000  /* summary interrupt bit. this
 124                                                      bit will be set if an interrupt
 125                                                      generated on the pci bus. useful
 126                                                      when driver is polling for
 127                                                      interrupts */
 128#define    INTR_PCS_STATUS             0x00002000  /* PCS interrupt status register */
 129#define    INTR_TX_MAC_STATUS          0x00004000  /* TX MAC status register has at
 130                                                      least 1 unmasked interrupt set */
 131#define    INTR_RX_MAC_STATUS          0x00008000  /* RX MAC status register has at
 132                                                      least 1 unmasked interrupt set */
 133#define    INTR_MAC_CTRL_STATUS        0x00010000  /* MAC control status register has
 134                                                      at least 1 unmasked interrupt
 135                                                      set */
 136#define    INTR_MIF_STATUS             0x00020000  /* MIF status register has at least
 137                                                      1 unmasked interrupt set */
 138#define    INTR_PCI_ERROR_STATUS       0x00040000  /* PCI error status register in the
 139                                                      BIF has at least 1 unmasked
 140                                                      interrupt set */
 141#define    INTR_TX_COMP_3_MASK         0xFFF80000  /* mask for TX completion
 142                                                      3 reg data */
 143#define    INTR_TX_COMP_3_SHIFT        19
 144#define    INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \
 145                            INTR_PCS_STATUS | INTR_RX_LEN_MISMATCH | \
 146                            INTR_TX_MAC_STATUS | INTR_RX_MAC_STATUS | \
 147                            INTR_TX_TAG_ERROR | INTR_RX_TAG_ERROR | \
 148                            INTR_MAC_CTRL_STATUS)
 149
 150/* determines which status events will cause an interrupt. layout same
 151 * as REG_INTR_STATUS.
 152 * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits
 153 */
 154#define  REG_INTR_MASK                 0x0010  /* Interrupt mask */
 155
 156/* top level interrupt bits that are cleared during read of REG_INTR_STATUS_ALIAS.
 157 * useful when driver is polling for interrupts. layout same as REG_INTR_MASK.
 158 * DEFAULT: 0x00000000, SIZE: 12 bits
 159 */
 160#define  REG_ALIAS_CLEAR               0x0014  /* alias clear mask
 161                                                  (used w/ status alias) */
 162/* same as REG_INTR_STATUS except that only bits cleared are those selected by
 163 * REG_ALIAS_CLEAR
 164 * DEFAULT: 0x00000000, SIZE: 29 bits
 165 */
 166#define  REG_INTR_STATUS_ALIAS         0x001C  /* interrupt status alias
 167                                                  (selective clear) */
 168
 169/* DEFAULT: 0x0, SIZE: 3 bits */
 170#define  REG_PCI_ERR_STATUS            0x1000  /* PCI error status */
 171#define    PCI_ERR_BADACK              0x01    /* reserved in Cassini+.
 172                                                  set if no ACK64# during ABS64 cycle
 173                                                  in Cassini. */
 174#define    PCI_ERR_DTRTO               0x02    /* delayed xaction timeout. set if
 175                                                  no read retry after 2^15 clocks */
 176#define    PCI_ERR_OTHER               0x04    /* other PCI errors */
 177#define    PCI_ERR_BIM_DMA_WRITE       0x08    /* BIM received 0 count DMA write req.
 178                                                  unused in Cassini. */
 179#define    PCI_ERR_BIM_DMA_READ        0x10    /* BIM received 0 count DMA read req.
 180                                                  unused in Cassini. */
 181#define    PCI_ERR_BIM_DMA_TIMEOUT     0x20    /* BIM received 255 retries during
 182                                                  DMA. unused in cassini. */
 183
 184/* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event
 185 * causes an interrupt to be generated.
 186 * DEFAULT: 0x7, SIZE: 3 bits
 187 */
 188#define  REG_PCI_ERR_STATUS_MASK       0x1004  /* PCI Error status mask */
 189
 190/* used to configure PCI related parameters that are not in PCI config space.
 191 * DEFAULT: 0bxx000, SIZE: 5 bits
 192 */
 193#define  REG_BIM_CFG                0x1008  /* BIM Configuration */
 194#define    BIM_CFG_RESERVED0        0x001   /* reserved */
 195#define    BIM_CFG_RESERVED1        0x002   /* reserved */
 196#define    BIM_CFG_64BIT_DISABLE    0x004   /* disable 64-bit mode */
 197#define    BIM_CFG_66MHZ            0x008   /* (ro) 1 = 66MHz, 0 = < 66MHz */
 198#define    BIM_CFG_32BIT            0x010   /* (ro) 1 = 32-bit slot, 0 = 64-bit */
 199#define    BIM_CFG_DPAR_INTR_ENABLE 0x020   /* detected parity err enable */
 200#define    BIM_CFG_RMA_INTR_ENABLE  0x040   /* master abort intr enable */
 201#define    BIM_CFG_RTA_INTR_ENABLE  0x080   /* target abort intr enable */
 202#define    BIM_CFG_RESERVED2        0x100   /* reserved */
 203#define    BIM_CFG_BIM_DISABLE      0x200   /* stop BIM DMA. use before global
 204                                               reset. reserved in Cassini. */
 205#define    BIM_CFG_BIM_STATUS       0x400   /* (ro) 1 = BIM DMA suspended.
 206                                                  reserved in Cassini. */
 207#define    BIM_CFG_PERROR_BLOCK     0x800  /* block PERR# to pci bus. def: 0.
 208                                                 reserved in Cassini. */
 209
 210/* DEFAULT: 0x00000000, SIZE: 32 bits */
 211#define  REG_BIM_DIAG                  0x100C  /* BIM Diagnostic */
 212#define    BIM_DIAG_MSTR_SM_MASK       0x3FFFFF00 /* PCI master controller state
 213                                                     machine bits [21:0] */
 214#define    BIM_DIAG_BRST_SM_MASK       0x7F    /* PCI burst controller state
 215                                                  machine bits [6:0] */
 216
 217/* writing to SW_RESET_TX and SW_RESET_RX will issue a global
 218 * reset. poll until TX and RX read back as 0's for completion.
 219 */
 220#define  REG_SW_RESET                  0x1010  /* Software reset */
 221#define    SW_RESET_TX                 0x00000001  /* reset TX DMA engine. poll until
 222                                                      cleared to 0.  */
 223#define    SW_RESET_RX                 0x00000002  /* reset RX DMA engine. poll until
 224                                                      cleared to 0. */
 225#define    SW_RESET_RSTOUT             0x00000004  /* force RSTOUT# pin active (low).
 226                                                      resets PHY and anything else
 227                                                      connected to RSTOUT#. RSTOUT#
 228                                                      is also activated by local PCI
 229                                                      reset when hot-swap is being
 230                                                      done. */
 231#define    SW_RESET_BLOCK_PCS_SLINK    0x00000008  /* if a global reset is done with
 232                                                      this bit set, PCS and SLINK
 233                                                      modules won't be reset.
 234                                                      i.e., link won't drop. */
 235#define    SW_RESET_BREQ_SM_MASK       0x00007F00  /* breq state machine [6:0] */
 236#define    SW_RESET_PCIARB_SM_MASK     0x00070000  /* pci arbitration state bits:
 237                                                      0b000: ARB_IDLE1
 238                                                      0b001: ARB_IDLE2
 239                                                      0b010: ARB_WB_ACK
 240                                                      0b011: ARB_WB_WAT
 241                                                      0b100: ARB_RB_ACK
 242                                                      0b101: ARB_RB_WAT
 243                                                      0b110: ARB_RB_END
 244                                                      0b111: ARB_WB_END */
 245#define    SW_RESET_RDPCI_SM_MASK      0x00300000  /* read pci state bits:
 246                                                      0b00: RD_PCI_WAT
 247                                                      0b01: RD_PCI_RDY
 248                                                      0b11: RD_PCI_ACK */
 249#define    SW_RESET_RDARB_SM_MASK      0x00C00000  /* read arbitration state bits:
 250                                                      0b00: AD_IDL_RX
 251                                                      0b01: AD_ACK_RX
 252                                                      0b10: AD_ACK_TX
 253                                                      0b11: AD_IDL_TX */
 254#define    SW_RESET_WRPCI_SM_MASK      0x06000000  /* write pci state bits
 255                                                      0b00: WR_PCI_WAT
 256                                                      0b01: WR_PCI_RDY
 257                                                      0b11: WR_PCI_ACK */
 258#define    SW_RESET_WRARB_SM_MASK      0x38000000  /* write arbitration state bits:
 259                                                      0b000: ARB_IDLE1
 260                                                      0b001: ARB_IDLE2
 261                                                      0b010: ARB_TX_ACK
 262                                                      0b011: ARB_TX_WAT
 263                                                      0b100: ARB_RX_ACK
 264                                                      0b110: ARB_RX_WAT */
 265
 266/* Cassini only. 64-bit register used to check PCI datapath. when read,
 267 * value written has both lower and upper 32-bit halves rotated to the right
 268 * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF
 269 */
 270#define  REG_MINUS_BIM_DATAPATH_TEST   0x1018  /* Cassini: BIM datapath test
 271                                                  Cassini+: reserved */
 272
 273/* output enables are provided for each device's chip select and for the rest
 274 * of the outputs from cassini to its local bus devices. two sw programmable
 275 * bits are connected to general purpus control/status bits.
 276 * DEFAULT: 0x7
 277 */
 278#define  REG_BIM_LOCAL_DEV_EN          0x1020  /* BIM local device
 279                                                  output EN. default: 0x7 */
 280#define    BIM_LOCAL_DEV_PAD           0x01    /* address bus, RW signal, and
 281                                                  OE signal output enable on the
 282                                                  local bus interface. these
 283                                                  are shared between both local
 284                                                  bus devices. tristate when 0. */
 285#define    BIM_LOCAL_DEV_PROM          0x02    /* PROM chip select */
 286#define    BIM_LOCAL_DEV_EXT           0x04    /* secondary local bus device chip
 287                                                  select output enable */
 288#define    BIM_LOCAL_DEV_SOFT_0        0x08    /* sw programmable ctrl bit 0 */
 289#define    BIM_LOCAL_DEV_SOFT_1        0x10    /* sw programmable ctrl bit 1 */
 290#define    BIM_LOCAL_DEV_HW_RESET      0x20    /* internal hw reset. Cassini+ only. */
 291
 292/* access 24 entry BIM read and write buffers. put address in REG_BIM_BUFFER_ADDR
 293 * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI.
 294 * _DATA_HI should be the last access of the sequence.
 295 * DEFAULT: undefined
 296 */
 297#define  REG_BIM_BUFFER_ADDR           0x1024  /* BIM buffer address. for
 298                                                  purposes. */
 299#define    BIM_BUFFER_ADDR_MASK        0x3F    /* index (0 - 23) of buffer  */
 300#define    BIM_BUFFER_WR_SELECT        0x40    /* write buffer access = 1
 301                                                  read buffer access = 0 */
 302/* DEFAULT: undefined */
 303#define  REG_BIM_BUFFER_DATA_LOW       0x1028  /* BIM buffer data low */
 304#define  REG_BIM_BUFFER_DATA_HI        0x102C  /* BIM buffer data high */
 305
 306/* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer.
 307 * bit auto-clears when done with status read from _SUMMARY and _PASS bits.
 308 */
 309#define  REG_BIM_RAM_BIST              0x102C  /* BIM RAM (read buffer) BIST
 310                                                  control/status */
 311#define    BIM_RAM_BIST_RD_START       0x01    /* start BIST for BIM read buffer */
 312#define    BIM_RAM_BIST_WR_START       0x02    /* start BIST for BIM write buffer.
 313                                                  Cassini only. reserved in
 314                                                  Cassini+. */
 315#define    BIM_RAM_BIST_RD_PASS        0x04    /* summary BIST pass status for read
 316                                                  buffer. */
 317#define    BIM_RAM_BIST_WR_PASS        0x08    /* summary BIST pass status for write
 318                                                  buffer. Cassini only. reserved
 319                                                  in Cassini+. */
 320#define    BIM_RAM_BIST_RD_LOW_PASS    0x10    /* read low bank passes BIST */
 321#define    BIM_RAM_BIST_RD_HI_PASS     0x20    /* read high bank passes BIST */
 322#define    BIM_RAM_BIST_WR_LOW_PASS    0x40    /* write low bank passes BIST.
 323                                                  Cassini only. reserved in
 324                                                  Cassini+. */
 325#define    BIM_RAM_BIST_WR_HI_PASS     0x80    /* write high bank passes BIST.
 326                                                  Cassini only. reserved in
 327                                                  Cassini+. */
 328
 329/* ASUN: i'm not sure what this does as it's not in the spec.
 330 * DEFAULT: 0xFC
 331 */
 332#define  REG_BIM_DIAG_MUX              0x1030  /* BIM diagnostic probe mux
 333                                                  select register */
 334
 335/* enable probe monitoring mode and select data appearing on the P_A* bus. bit
 336 * values for _SEL_HI_MASK and _SEL_LOW_MASK:
 337 * 0x0: internal probe[7:0] (pci arb state, wtc empty w, wtc full w, wtc empty w,
 338 *                           wtc empty r, post pci)
 339 * 0x1: internal probe[15:8] (pci wbuf comp, pci wpkt comp, pci rbuf comp,
 340 *                            pci rpkt comp, txdma wr req, txdma wr ack,
 341 *                            txdma wr rdy, txdma wr xfr done)
 342 * 0x2: internal probe[23:16] (txdma rd req, txdma rd ack, txdma rd rdy, rxdma rd,
 343 *                             rd arb state, rd pci state)
 344 * 0x3: internal probe[31:24] (rxdma req, rxdma ack, rxdma rdy, wrarb state,
 345 *                             wrpci state)
 346 * 0x4: pci io probe[7:0]     0x5: pci io probe[15:8]
 347 * 0x6: pci io probe[23:16]   0x7: pci io probe[31:24]
 348 * 0x8: pci io probe[39:32]   0x9: pci io probe[47:40]
 349 * 0xa: pci io probe[55:48]   0xb: pci io probe[63:56]
 350 * the following are not available in Cassini:
 351 * 0xc: rx probe[7:0]         0xd: tx probe[7:0]
 352 * 0xe: hp probe[7:0]         0xf: mac probe[7:0]
 353 */
 354#define  REG_PLUS_PROBE_MUX_SELECT     0x1034 /* Cassini+: PROBE MUX SELECT */
 355#define    PROBE_MUX_EN                0x80000000 /* allow probe signals to be
 356                                                     driven on local bus P_A[15:0]
 357                                                     for debugging */
 358#define    PROBE_MUX_SUB_MUX_MASK      0x0000FF00 /* select sub module probe signals:
 359                                                     0x03 = mac[1:0]
 360                                                     0x0C = rx[1:0]
 361                                                     0x30 = tx[1:0]
 362                                                     0xC0 = hp[1:0] */
 363#define    PROBE_MUX_SEL_HI_MASK       0x000000F0 /* select which module to appear
 364                                                     on P_A[15:8]. see above for
 365                                                     values. */
 366#define    PROBE_MUX_SEL_LOW_MASK      0x0000000F /* select which module to appear
 367                                                     on P_A[7:0]. see above for
 368                                                     values. */
 369
 370/* values mean the same thing as REG_INTR_MASK excep that it's for INTB.
 371 DEFAULT: 0x1F */
 372#define  REG_PLUS_INTR_MASK_1          0x1038 /* Cassini+: interrupt mask
 373                                                 register 2 for INTB */
 374#define  REG_PLUS_INTRN_MASK(x)       (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16)
 375/* bits correspond to both _MASK and _STATUS registers. _ALT corresponds to
 376 * all of the alternate (2-4) INTR registers while _1 corresponds to only
 377 * _MASK_1 and _STATUS_1 registers.
 378 * DEFAULT: 0x7 for MASK registers, 0x0 for ALIAS_CLEAR registers
 379 */
 380#define    INTR_RX_DONE_ALT              0x01
 381#define    INTR_RX_COMP_FULL_ALT         0x02
 382#define    INTR_RX_COMP_AF_ALT           0x04
 383#define    INTR_RX_BUF_UNAVAIL_1         0x08
 384#define    INTR_RX_BUF_AE_1              0x10 /* almost empty */
 385#define    INTRN_MASK_RX_EN              0x80
 386#define    INTRN_MASK_CLEAR_ALL          (INTR_RX_DONE_ALT | \
 387                                          INTR_RX_COMP_FULL_ALT | \
 388                                          INTR_RX_COMP_AF_ALT | \
 389                                          INTR_RX_BUF_UNAVAIL_1 | \
 390                                          INTR_RX_BUF_AE_1)
 391#define  REG_PLUS_INTR_STATUS_1        0x103C /* Cassini+: interrupt status
 392                                                 register 2 for INTB. default: 0x1F */
 393#define  REG_PLUS_INTRN_STATUS(x)       (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16)
 394#define    INTR_STATUS_ALT_INTX_EN     0x80   /* generate INTX when one of the
 395                                                 flags are set. enables desc ring. */
 396
 397#define  REG_PLUS_ALIAS_CLEAR_1        0x1040 /* Cassini+: alias clear mask
 398                                                 register 2 for INTB */
 399#define  REG_PLUS_ALIASN_CLEAR(x)      (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16)
 400
 401#define  REG_PLUS_INTR_STATUS_ALIAS_1  0x1044 /* Cassini+: interrupt status
 402                                                 register alias 2 for INTB */
 403#define  REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16)
 404
 405#define REG_SATURN_PCFG               0x106c /* pin configuration register for
 406                                                integrated macphy */
 407
 408#define   SATURN_PCFG_TLA             0x00000001 /* 1 = phy actled */
 409#define   SATURN_PCFG_FLA             0x00000002 /* 1 = phy link10led */
 410#define   SATURN_PCFG_CLA             0x00000004 /* 1 = phy link100led */
 411#define   SATURN_PCFG_LLA             0x00000008 /* 1 = phy link1000led */
 412#define   SATURN_PCFG_RLA             0x00000010 /* 1 = phy duplexled */
 413#define   SATURN_PCFG_PDS             0x00000020 /* phy debug mode.
 414                                                    0 = normal */
 415#define   SATURN_PCFG_MTP             0x00000080 /* test point select */
 416#define   SATURN_PCFG_GMO             0x00000100 /* GMII observe. 1 =
 417                                                    GMII on SERDES pins for
 418                                                    monitoring. */
 419#define   SATURN_PCFG_FSI             0x00000200 /* 1 = freeze serdes/gmii. all
 420                                                    pins configed as outputs.
 421                                                    for power saving when using
 422                                                    internal phy. */
 423#define   SATURN_PCFG_LAD             0x00000800 /* 0 = mac core led ctrl
 424                                                    polarity from strapping
 425                                                    value.
 426                                                    1 = mac core led ctrl
 427                                                    polarity active low. */
 428
 429
 430/** transmit dma registers **/
 431#define MAX_TX_RINGS_SHIFT            2
 432#define MAX_TX_RINGS                  (1 << MAX_TX_RINGS_SHIFT)
 433#define MAX_TX_RINGS_MASK             (MAX_TX_RINGS - 1)
 434
 435/* TX configuration.
 436 * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8
 437 * DEFAULT: 0x3F000001
 438 */
 439#define  REG_TX_CFG                    0x2004  /* TX config */
 440#define    TX_CFG_DMA_EN               0x00000001  /* enable TX DMA. if cleared, DMA
 441                                                      will stop after xfer of current
 442                                                      buffer has been completed. */
 443#define    TX_CFG_FIFO_PIO_SEL         0x00000002  /* TX DMA FIFO can be
 444                                                      accessed w/ FIFO addr
 445                                                      and data registers.
 446                                                      TX DMA should be
 447                                                      disabled. */
 448#define    TX_CFG_DESC_RING0_MASK      0x0000003C  /* # desc entries in
 449                                                      ring 1. */
 450#define    TX_CFG_DESC_RING0_SHIFT     2
 451#define    TX_CFG_DESC_RINGN_MASK(a)   (TX_CFG_DESC_RING0_MASK << (a)*4)
 452#define    TX_CFG_DESC_RINGN_SHIFT(a)  (TX_CFG_DESC_RING0_SHIFT + (a)*4)
 453#define    TX_CFG_PACED_MODE           0x00100000  /* TX_ALL only set after
 454                                                      TX FIFO becomes empty.
 455                                                      if 0, TX_ALL set
 456                                                      if descr queue empty. */
 457#define    TX_CFG_DMA_RDPIPE_DIS       0x01000000  /* always set to 1 */
 458#define    TX_CFG_COMPWB_Q1            0x02000000  /* completion writeback happens at
 459                                                      the end of every packet kicked
 460                                                      through Q1. */
 461#define    TX_CFG_COMPWB_Q2            0x04000000  /* completion writeback happens at
 462                                                      the end of every packet kicked
 463                                                      through Q2. */
 464#define    TX_CFG_COMPWB_Q3            0x08000000  /* completion writeback happens at
 465                                                      the end of every packet kicked
 466                                                      through Q3 */
 467#define    TX_CFG_COMPWB_Q4            0x10000000  /* completion writeback happens at
 468                                                      the end of every packet kicked
 469                                                      through Q4 */
 470#define    TX_CFG_INTR_COMPWB_DIS      0x20000000  /* disable pre-interrupt completion
 471                                                      writeback */
 472#define    TX_CFG_CTX_SEL_MASK         0xC0000000  /* selects tx test port
 473                                                      connection
 474                                                      0b00: tx mac req,
 475                                                            tx mac retry req,
 476                                                            tx ack and tx tag.
 477                                                      0b01: txdma rd req,
 478                                                            txdma rd ack,
 479                                                            txdma rd rdy,
 480                                                            txdma rd type0
 481                                                      0b11: txdma wr req,
 482                                                            txdma wr ack,
 483                                                            txdma wr rdy,
 484                                                            txdma wr xfr done. */
 485#define    TX_CFG_CTX_SEL_SHIFT        30
 486
 487/* 11-bit counters that point to next location in FIFO to be loaded/retrieved.
 488 * used for diagnostics only.
 489 */
 490#define  REG_TX_FIFO_WRITE_PTR         0x2014  /* TX FIFO write pointer */
 491#define  REG_TX_FIFO_SHADOW_WRITE_PTR  0x2018  /* TX FIFO shadow write
 492                                                  pointer. temp hold reg.
 493                                                  diagnostics only. */
 494#define  REG_TX_FIFO_READ_PTR          0x201C  /* TX FIFO read pointer */
 495#define  REG_TX_FIFO_SHADOW_READ_PTR   0x2020  /* TX FIFO shadow read
 496                                                  pointer */
 497
 498/* (ro) 11-bit up/down counter w/ # of frames currently in TX FIFO */
 499#define  REG_TX_FIFO_PKT_CNT           0x2024  /* TX FIFO packet counter */
 500
 501/* current state of all state machines in TX */
 502#define  REG_TX_SM_1                   0x2028  /* TX state machine reg #1 */
 503#define    TX_SM_1_CHAIN_MASK          0x000003FF   /* chaining state machine */
 504#define    TX_SM_1_CSUM_MASK           0x00000C00   /* checksum state machine */
 505#define    TX_SM_1_FIFO_LOAD_MASK      0x0003F000   /* FIFO load state machine.
 506                                                       = 0x01 when TX disabled. */
 507#define    TX_SM_1_FIFO_UNLOAD_MASK    0x003C0000   /* FIFO unload state machine */
 508#define    TX_SM_1_CACHE_MASK          0x03C00000   /* desc. prefetch cache controller
 509                                                       state machine */
 510#define    TX_SM_1_CBQ_ARB_MASK        0xF8000000   /* CBQ arbiter state machine */
 511
 512#define  REG_TX_SM_2                   0x202C  /* TX state machine reg #2 */
 513#define    TX_SM_2_COMP_WB_MASK        0x07    /* completion writeback sm */
 514#define    TX_SM_2_SUB_LOAD_MASK       0x38    /* sub load state machine */
 515#define    TX_SM_2_KICK_MASK           0xC0    /* kick state machine */
 516
 517/* 64-bit pointer to the transmit data buffer. only the 50 LSB are incremented
 518 * while the upper 23 bits are taken from the TX descriptor
 519 */
 520#define  REG_TX_DATA_PTR_LOW           0x2030  /* TX data pointer low */
 521#define  REG_TX_DATA_PTR_HI            0x2034  /* TX data pointer high */
 522
 523/* 13 bit registers written by driver w/ descriptor value that follows
 524 * last valid xmit descriptor. kick # and complete # values are used by
 525 * the xmit dma engine to control tx descr fetching. if > 1 valid
 526 * tx descr is available within the cache line being read, cassini will
 527 * internally cache up to 4 of them. 0 on reset. _KICK = rw, _COMP = ro.
 528 */
 529#define  REG_TX_KICK0                  0x2038  /* TX kick reg #1 */
 530#define  REG_TX_KICKN(x)               (REG_TX_KICK0 + (x)*4)
 531#define  REG_TX_COMP0                  0x2048  /* TX completion reg #1 */
 532#define  REG_TX_COMPN(x)               (REG_TX_COMP0 + (x)*4)
 533
 534/* values of TX_COMPLETE_1-4 are written. each completion register
 535 * is 2bytes in size and contiguous. 8B allocation w/ 8B alignment.
 536 * NOTE: completion reg values are only written back prior to TX_INTME and
 537 * TX_ALL interrupts. at all other times, the most up-to-date index values
 538 * should be obtained from the REG_TX_COMPLETE_# registers.
 539 * here's the layout:
 540 * offset from base addr      completion # byte
 541 *           0                TX_COMPLETE_1_MSB
 542 *           1                TX_COMPLETE_1_LSB
 543 *           2                TX_COMPLETE_2_MSB
 544 *           3                TX_COMPLETE_2_LSB
 545 *           4                TX_COMPLETE_3_MSB
 546 *           5                TX_COMPLETE_3_LSB
 547 *           6                TX_COMPLETE_4_MSB
 548 *           7                TX_COMPLETE_4_LSB
 549 */
 550#define  TX_COMPWB_SIZE             8
 551#define  REG_TX_COMPWB_DB_LOW       0x2058  /* TX completion write back
 552                                               base low */
 553#define  REG_TX_COMPWB_DB_HI        0x205C  /* TX completion write back
 554                                               base high */
 555#define    TX_COMPWB_MSB_MASK       0x00000000000000FFULL
 556#define    TX_COMPWB_MSB_SHIFT      0
 557#define    TX_COMPWB_LSB_MASK       0x000000000000FF00ULL
 558#define    TX_COMPWB_LSB_SHIFT      8
 559#define    TX_COMPWB_NEXT(x)        ((x) >> 16)
 560
 561/* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must
 562 * be 2KB-aligned. */
 563#define  REG_TX_DB0_LOW         0x2060  /* TX descriptor base low #1 */
 564#define  REG_TX_DB0_HI          0x2064  /* TX descriptor base hi #1 */
 565#define  REG_TX_DBN_LOW(x)      (REG_TX_DB0_LOW + (x)*8)
 566#define  REG_TX_DBN_HI(x)       (REG_TX_DB0_HI + (x)*8)
 567
 568/* 16-bit registers hold weights for the weighted round-robin of the
 569 * four CBQ TX descr rings. weights correspond to # bytes xferred from
 570 * host to TXFIFO in a round of WRR arbitration. can be set
 571 * dynamically with new weights set upon completion of the current
 572 * packet transfer from host memory to TXFIFO. a dummy write to any of
 573 * these registers causes a queue1 pre-emption with all historical bw
 574 * deficit data reset to 0 (useful when congestion requires a
 575 * pre-emption/re-allocation of network bandwidth
 576 */
 577#define  REG_TX_MAXBURST_0             0x2080  /* TX MaxBurst #1 */
 578#define  REG_TX_MAXBURST_1             0x2084  /* TX MaxBurst #2 */
 579#define  REG_TX_MAXBURST_2             0x2088  /* TX MaxBurst #3 */
 580#define  REG_TX_MAXBURST_3             0x208C  /* TX MaxBurst #4 */
 581
 582/* diagnostics access to any TX FIFO location. every access is 65
 583 * bits.  _DATA_LOW = 32 LSB, _DATA_HI_T1/T0 = 32 MSB. _TAG = tag bit.
 584 * writing _DATA_HI_T0 sets tag bit low, writing _DATA_HI_T1 sets tag
 585 * bit high.  TX_FIFO_PIO_SEL must be set for TX FIFO PIO access. if
 586 * TX FIFO data integrity is desired, TX DMA should be
 587 * disabled. _DATA_HI_Tx should be the last access of the sequence.
 588 */
 589#define  REG_TX_FIFO_ADDR              0x2104  /* TX FIFO address */
 590#define  REG_TX_FIFO_TAG               0x2108  /* TX FIFO tag */
 591#define  REG_TX_FIFO_DATA_LOW          0x210C  /* TX FIFO data low */
 592#define  REG_TX_FIFO_DATA_HI_T1        0x2110  /* TX FIFO data high t1 */
 593#define  REG_TX_FIFO_DATA_HI_T0        0x2114  /* TX FIFO data high t0 */
 594#define  REG_TX_FIFO_SIZE              0x2118  /* (ro) TX FIFO size = 0x090 = 9KB */
 595
 596/* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST
 597 * passed for the specified memory
 598 */
 599#define  REG_TX_RAMBIST                0x211C /* TX RAMBIST control/status */
 600#define    TX_RAMBIST_STATE            0x01C0 /* progress state of RAMBIST
 601                                                 controller state machine */
 602#define    TX_RAMBIST_RAM33A_PASS      0x0020 /* RAM33A passed */
 603#define    TX_RAMBIST_RAM32A_PASS      0x0010 /* RAM32A passed */
 604#define    TX_RAMBIST_RAM33B_PASS      0x0008 /* RAM33B passed */
 605#define    TX_RAMBIST_RAM32B_PASS      0x0004 /* RAM32B passed */
 606#define    TX_RAMBIST_SUMMARY          0x0002 /* all RAM passed */
 607#define    TX_RAMBIST_START            0x0001 /* write 1 to start BIST. self
 608                                                 clears on completion. */
 609
 610/** receive dma registers **/
 611#define MAX_RX_DESC_RINGS              2
 612#define MAX_RX_COMP_RINGS              4
 613
 614/* receive DMA channel configuration. default: 0x80910
 615 * free ring size       = (1 << n)*32  -> [32 - 8k]
 616 * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9
 617 * DEFAULT: 0x80910
 618 */
 619#define  REG_RX_CFG                     0x4000  /* RX config */
 620#define    RX_CFG_DMA_EN                0x00000001 /* enable RX DMA. 0 stops
 621                                                         channel as soon as current
 622                                                         frame xfer has completed.
 623                                                         driver should disable MAC
 624                                                         for 200ms before disabling
 625                                                         RX */
 626#define    RX_CFG_DESC_RING_MASK        0x0000001E /* # desc entries in RX
 627                                                         free desc ring.
 628                                                         def: 0x8 = 8k */
 629#define    RX_CFG_DESC_RING_SHIFT       1
 630#define    RX_CFG_COMP_RING_MASK        0x000001E0 /* # desc entries in RX complete
 631                                                         ring. def: 0x8 = 32k */
 632#define    RX_CFG_COMP_RING_SHIFT       5
 633#define    RX_CFG_BATCH_DIS             0x00000200 /* disable receive desc
 634                                                      batching. def: 0x0 =
 635                                                      enabled */
 636#define    RX_CFG_SWIVEL_MASK           0x00001C00 /* byte offset of the 1st
 637                                                      data byte of the packet
 638                                                      w/in 8 byte boundares.
 639                                                      this swivels the data
 640                                                      DMA'ed to header
 641                                                      buffers, jumbo buffers
 642                                                      when header split is not
 643                                                      requested and MTU sized
 644                                                      buffers. def: 0x2 */
 645#define    RX_CFG_SWIVEL_SHIFT          10
 646
 647/* cassini+ only */
 648#define    RX_CFG_DESC_RING1_MASK       0x000F0000 /* # of desc entries in
 649                                                         RX free desc ring 2.
 650                                                         def: 0x8 = 8k */
 651#define    RX_CFG_DESC_RING1_SHIFT      16
 652
 653
 654/* the page size register allows cassini chips to do the following with
 655 * received data:
 656 * [--------------------------------------------------------------] page
 657 * [off][buf1][pad][off][buf2][pad][off][buf3][pad][off][buf4][pad]
 658 * |--------------| = PAGE_SIZE_BUFFER_STRIDE
 659 * page = PAGE_SIZE
 660 * offset = PAGE_SIZE_MTU_OFF
 661 * for the above example, MTU_BUFFER_COUNT = 4.
 662 * NOTE: as is apparent, you need to ensure that the following holds:
 663 * MTU_BUFFER_COUNT <= PAGE_SIZE/PAGE_SIZE_BUFFER_STRIDE
 664 * DEFAULT: 0x48002002 (8k pages)
 665 */
 666#define  REG_RX_PAGE_SIZE               0x4004  /* RX page size */
 667#define    RX_PAGE_SIZE_MASK            0x00000003 /* size of pages pointed to
 668                                                      by receive descriptors.
 669                                                      if jumbo buffers are
 670                                                      supported the page size
 671                                                      should not be < 8k.
 672                                                      0b00 = 2k, 0b01 = 4k
 673                                                      0b10 = 8k, 0b11 = 16k
 674                                                      DEFAULT: 8k */
 675#define    RX_PAGE_SIZE_SHIFT           0
 676#define    RX_PAGE_SIZE_MTU_COUNT_MASK  0x00007800 /* # of MTU buffers the hw
 677                                                      packs into a page.
 678                                                      DEFAULT: 4 */
 679#define    RX_PAGE_SIZE_MTU_COUNT_SHIFT 11
 680#define    RX_PAGE_SIZE_MTU_STRIDE_MASK 0x18000000 /* # of bytes that separate
 681                                                         each MTU buffer +
 682                                                         offset from each
 683                                                         other.
 684                                                         0b00 = 1k, 0b01 = 2k
 685                                                         0b10 = 4k, 0b11 = 8k
 686                                                         DEFAULT: 0x1 */
 687#define    RX_PAGE_SIZE_MTU_STRIDE_SHIFT 27
 688#define    RX_PAGE_SIZE_MTU_OFF_MASK    0xC0000000 /* offset in each page that
 689                                                      hw writes the MTU buffer
 690                                                      into.
 691                                                      0b00 = 0,
 692                                                      0b01 = 64 bytes
 693                                                      0b10 = 96, 0b11 = 128
 694                                                      DEFAULT: 0x1 */
 695#define    RX_PAGE_SIZE_MTU_OFF_SHIFT   30
 696
 697/* 11-bit counter points to next location in RX FIFO to be loaded/read.
 698 * shadow write pointers enable retries in case of early receive aborts.
 699 * DEFAULT: 0x0. generated on 64-bit boundaries.
 700 */
 701#define  REG_RX_FIFO_WRITE_PTR             0x4008  /* RX FIFO write pointer */
 702#define  REG_RX_FIFO_READ_PTR              0x400C  /* RX FIFO read pointer */
 703#define  REG_RX_IPP_FIFO_SHADOW_WRITE_PTR  0x4010  /* RX IPP FIFO shadow write
 704                                                      pointer */
 705#define  REG_RX_IPP_FIFO_SHADOW_READ_PTR   0x4014  /* RX IPP FIFO shadow read
 706                                                      pointer */
 707#define  REG_RX_IPP_FIFO_READ_PTR          0x400C  /* RX IPP FIFO read
 708                                                      pointer. (8-bit counter) */
 709
 710/* current state of RX DMA state engines + other info
 711 * DEFAULT: 0x0
 712 */
 713#define  REG_RX_DEBUG                      0x401C  /* RX debug */
 714#define    RX_DEBUG_LOAD_STATE_MASK        0x0000000F /* load state machine w/ MAC:
 715                                                         0x0 = idle,   0x1 = load_bop
 716                                                         0x2 = load 1, 0x3 = load 2
 717                                                         0x4 = load 3, 0x5 = load 4
 718                                                         0x6 = last detect
 719                                                         0x7 = wait req
 720                                                         0x8 = wait req statuss 1st
 721                                                         0x9 = load st
 722                                                         0xa = bubble mac
 723                                                         0xb = error */
 724#define    RX_DEBUG_LM_STATE_MASK          0x00000070 /* load state machine w/ HP and
 725                                                         RX FIFO:
 726                                                         0x0 = idle,   0x1 = hp xfr
 727                                                         0x2 = wait hp ready
 728                                                         0x3 = wait flow code
 729                                                         0x4 = fifo xfer
 730                                                         0x5 = make status
 731                                                         0x6 = csum ready
 732                                                         0x7 = error */
 733#define    RX_DEBUG_FC_STATE_MASK          0x000000180 /* flow control state machine
 734                                                         w/ MAC:
 735                                                         0x0 = idle
 736                                                         0x1 = wait xoff ack
 737                                                         0x2 = wait xon
 738                                                         0x3 = wait xon ack */
 739#define    RX_DEBUG_DATA_STATE_MASK        0x000001E00 /* unload data state machine
 740                                                         states:
 741                                                         0x0 = idle data
 742                                                         0x1 = header begin
 743                                                         0x2 = xfer header
 744                                                         0x3 = xfer header ld
 745                                                         0x4 = mtu begin
 746                                                         0x5 = xfer mtu
 747                                                         0x6 = xfer mtu ld
 748                                                         0x7 = jumbo begin
 749                                                         0x8 = xfer jumbo
 750                                                         0x9 = xfer jumbo ld
 751                                                         0xa = reas begin
 752                                                         0xb = xfer reas
 753                                                         0xc = flush tag
 754                                                         0xd = xfer reas ld
 755                                                         0xe = error
 756                                                         0xf = bubble idle */
 757#define    RX_DEBUG_DESC_STATE_MASK        0x0001E000 /* unload desc state machine
 758                                                         states:
 759                                                         0x0 = idle desc
 760                                                         0x1 = wait ack
 761                                                         0x9 = wait ack 2
 762                                                         0x2 = fetch desc 1
 763                                                         0xa = fetch desc 2
 764                                                         0x3 = load ptrs
 765                                                         0x4 = wait dma
 766                                                         0x5 = wait ack batch
 767                                                         0x6 = post batch
 768                                                         0x7 = xfr done */
 769#define    RX_DEBUG_INTR_READ_PTR_MASK     0x30000000 /* interrupt read ptr of the
 770                                                         interrupt queue */
 771#define    RX_DEBUG_INTR_WRITE_PTR_MASK    0xC0000000 /* interrupt write pointer
 772                                                         of the interrupt queue */
 773
 774/* flow control frames are emitted using two PAUSE thresholds:
 775 * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg
 776 * XON PAUSE uses a pause time of 0. granularity of threshold is 64bytes.
 777 * PAUSE thresholds defined in terms of FIFO occupancy and may be translated
 778 * into FIFO vacancy using RX_FIFO_SIZE. setting ON will trigger XON frames
 779 * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max
 780 * value is is 0x6F.
 781 * DEFAULT: 0x00078
 782 */
 783#define  REG_RX_PAUSE_THRESH               0x4020  /* RX pause thresholds */
 784#define    RX_PAUSE_THRESH_QUANTUM         64
 785#define    RX_PAUSE_THRESH_OFF_MASK        0x000001FF /* XOFF PAUSE emitted when
 786                                                         RX FIFO occupancy >
 787                                                         value*64B */
 788#define    RX_PAUSE_THRESH_OFF_SHIFT       0
 789#define    RX_PAUSE_THRESH_ON_MASK         0x001FF000 /* XON PAUSE emitted after
 790                                                         emitting XOFF PAUSE when RX
 791                                                         FIFO occupancy falls below
 792                                                         this value*64B. must be
 793                                                         < XOFF threshold. if =
 794                                                         RX_FIFO_SIZE< XON frames are
 795                                                         never emitted. */
 796#define    RX_PAUSE_THRESH_ON_SHIFT        12
 797
 798/* 13-bit register used to control RX desc fetching and intr generation. if 4+
 799 * valid RX descriptors are available, Cassini will read 4 at a time.
 800 * writing N means that all desc up to *but* excluding N are available. N must
 801 * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned.
 802 * DEFAULT: 0 on reset
 803 */
 804#define  REG_RX_KICK                    0x4024  /* RX kick reg */
 805
 806/* 8KB aligned 64-bit pointer to the base of the RX free/completion rings.
 807 * lower 13 bits of the low register are hard-wired to 0.
 808 */
 809#define  REG_RX_DB_LOW                     0x4028  /* RX descriptor ring
 810                                                         base low */
 811#define  REG_RX_DB_HI                      0x402C  /* RX descriptor ring
 812                                                         base hi */
 813#define  REG_RX_CB_LOW                     0x4030  /* RX completion ring
 814                                                         base low */
 815#define  REG_RX_CB_HI                      0x4034  /* RX completion ring
 816                                                         base hi */
 817/* 13-bit register indicate desc used by cassini for receive frames. used
 818 * for diagnostic purposes.
 819 * DEFAULT: 0 on reset
 820 */
 821#define  REG_RX_COMP                       0x4038  /* (ro) RX completion */
 822
 823/* HEAD and TAIL are used to control RX desc posting and interrupt
 824 * generation.  hw moves the head register to pass ownership to sw. sw
 825 * moves the tail register to pass ownership back to hw. to give all
 826 * entries to hw, set TAIL = HEAD.  if HEAD and TAIL indicate that no
 827 * more entries are available, DMA will pause and an interrupt will be
 828 * generated to indicate no more entries are available.  sw can use
 829 * this interrupt to reduce the # of times it must update the
 830 * completion tail register.
 831 * DEFAULT: 0 on reset
 832 */
 833#define  REG_RX_COMP_HEAD                  0x403C  /* RX completion head */
 834#define  REG_RX_COMP_TAIL                  0x4040  /* RX completion tail */
 835
 836/* values used for receive interrupt blanking. loaded each time the ISR is read
 837 * DEFAULT: 0x00000000
 838 */
 839#define  REG_RX_BLANK                      0x4044  /* RX blanking register
 840                                                         for ISR read */
 841#define    RX_BLANK_INTR_PKT_MASK          0x000001FF /* RX_DONE intr asserted if
 842                                                         this many sets of completion
 843                                                         writebacks (up to 2 packets)
 844                                                         occur since the last time
 845                                                         the ISR was read. 0 = no
 846                                                         packet blanking */
 847#define    RX_BLANK_INTR_PKT_SHIFT         0
 848#define    RX_BLANK_INTR_TIME_MASK         0x3FFFF000 /* RX_DONE interrupt asserted
 849                                                         if that many clocks were
 850                                                         counted since last time the
 851                                                         ISR was read.
 852                                                         each count is 512 core
 853                                                         clocks (125MHz). 0 = no
 854                                                         time blanking */
 855#define    RX_BLANK_INTR_TIME_SHIFT        12
 856
 857/* values used for interrupt generation based on threshold values of how
 858 * many free desc and completion entries are available for hw use.
 859 * DEFAULT: 0x00000000
 860 */
 861#define  REG_RX_AE_THRESH                  0x4048  /* RX almost empty
 862                                                         thresholds */
 863#define    RX_AE_THRESH_FREE_MASK          0x00001FFF /* RX_BUF_AE will be
 864                                                         generated if # desc
 865                                                         avail for hw use <=
 866                                                         # */
 867#define    RX_AE_THRESH_FREE_SHIFT         0
 868#define    RX_AE_THRESH_COMP_MASK          0x0FFFE000 /* RX_COMP_AE will be
 869                                                         generated if # of
 870                                                         completion entries
 871                                                         avail for hw use <=
 872                                                         # */
 873#define    RX_AE_THRESH_COMP_SHIFT         13
 874
 875/* probabilities for random early drop (RED) thresholds on a FIFO threshold
 876 * basis. probability should increase when the FIFO level increases. control
 877 * packets are never dropped and not counted in stats. probability programmed
 878 * on a 12.5% granularity. e.g., 0x1 = 1/8 packets dropped.
 879 * DEFAULT: 0x00000000
 880 */
 881#define  REG_RX_RED                      0x404C  /* RX random early detect enable */
 882#define    RX_RED_4K_6K_FIFO_MASK        0x000000FF /*  4KB < FIFO thresh < 6KB */
 883#define    RX_RED_6K_8K_FIFO_MASK        0x0000FF00 /*  6KB < FIFO thresh < 8KB */
 884#define    RX_RED_8K_10K_FIFO_MASK       0x00FF0000 /*  8KB < FIFO thresh < 10KB */
 885#define    RX_RED_10K_12K_FIFO_MASK      0xFF000000 /* 10KB < FIFO thresh < 12KB */
 886
 887/* FIFO fullness levels for RX FIFO, RX control FIFO, and RX IPP FIFO.
 888 * RX control FIFO = # of packets in RX FIFO.
 889 * DEFAULT: 0x0
 890 */
 891#define  REG_RX_FIFO_FULLNESS              0x4050  /* (ro) RX FIFO fullness */
 892#define    RX_FIFO_FULLNESS_RX_FIFO_MASK   0x3FF80000 /* level w/ 8B granularity */
 893#define    RX_FIFO_FULLNESS_IPP_FIFO_MASK  0x0007FF00 /* level w/ 8B granularity */
 894#define    RX_FIFO_FULLNESS_RX_PKT_MASK    0x000000FF /* # packets in RX FIFO */
 895#define  REG_RX_IPP_PACKET_COUNT           0x4054  /* RX IPP packet counter */
 896#define  REG_RX_WORK_DMA_PTR_LOW           0x4058  /* RX working DMA ptr low */
 897#define  REG_RX_WORK_DMA_PTR_HI            0x405C  /* RX working DMA ptr
 898                                                      high */
 899
 900/* BIST testing ro RX FIFO, RX control FIFO, and RX IPP FIFO. only RX BIST
 901 * START/COMPLETE is writeable. START will clear when the BIST has completed
 902 * checking all 17 RAMS.
 903 * DEFAULT: 0bxxxx xxxxx xxxx xxxx xxxx x000 0000 0000 00x0
 904 */
 905#define  REG_RX_BIST                       0x4060  /* (ro) RX BIST */
 906#define    RX_BIST_32A_PASS                0x80000000 /* RX FIFO 32A passed */
 907#define    RX_BIST_33A_PASS                0x40000000 /* RX FIFO 33A passed */
 908#define    RX_BIST_32B_PASS                0x20000000 /* RX FIFO 32B passed */
 909#define    RX_BIST_33B_PASS                0x10000000 /* RX FIFO 33B passed */
 910#define    RX_BIST_32C_PASS                0x08000000 /* RX FIFO 32C passed */
 911#define    RX_BIST_33C_PASS                0x04000000 /* RX FIFO 33C passed */
 912#define    RX_BIST_IPP_32A_PASS            0x02000000 /* RX IPP FIFO 33B passed */
 913#define    RX_BIST_IPP_33A_PASS            0x01000000 /* RX IPP FIFO 33A passed */
 914#define    RX_BIST_IPP_32B_PASS            0x00800000 /* RX IPP FIFO 32B passed */
 915#define    RX_BIST_IPP_33B_PASS            0x00400000 /* RX IPP FIFO 33B passed */
 916#define    RX_BIST_IPP_32C_PASS            0x00200000 /* RX IPP FIFO 32C passed */
 917#define    RX_BIST_IPP_33C_PASS            0x00100000 /* RX IPP FIFO 33C passed */
 918#define    RX_BIST_CTRL_32_PASS            0x00800000 /* RX CTRL FIFO 32 passed */
 919#define    RX_BIST_CTRL_33_PASS            0x00400000 /* RX CTRL FIFO 33 passed */
 920#define    RX_BIST_REAS_26A_PASS           0x00200000 /* RX Reas 26A passed */
 921#define    RX_BIST_REAS_26B_PASS           0x00100000 /* RX Reas 26B passed */
 922#define    RX_BIST_REAS_27_PASS            0x00080000 /* RX Reas 27 passed */
 923#define    RX_BIST_STATE_MASK              0x00078000 /* BIST state machine */
 924#define    RX_BIST_SUMMARY                 0x00000002 /* when BIST complete,
 925                                                         summary pass bit
 926                                                         contains AND of BIST
 927                                                         results of all 16
 928                                                         RAMS */
 929#define    RX_BIST_START                   0x00000001 /* write 1 to start
 930                                                         BIST. self clears
 931                                                         on completion. */
 932
 933/* next location in RX CTRL FIFO that will be loaded w/ data from RX IPP/read
 934 * from to retrieve packet control info.
 935 * DEFAULT: 0
 936 */
 937#define  REG_RX_CTRL_FIFO_WRITE_PTR        0x4064  /* (ro) RX control FIFO
 938                                                      write ptr */
 939#define  REG_RX_CTRL_FIFO_READ_PTR         0x4068  /* (ro) RX control FIFO read
 940                                                      ptr */
 941
 942/* receive interrupt blanking. loaded each time interrupt alias register is
 943 * read.
 944 * DEFAULT: 0x0
 945 */
 946#define  REG_RX_BLANK_ALIAS_READ           0x406C  /* RX blanking register for
 947                                                      alias read */
 948#define    RX_BAR_INTR_PACKET_MASK         0x000001FF /* assert RX_DONE if #
 949                                                         completion writebacks
 950                                                         > # since last ISR
 951                                                         read. 0 = no
 952                                                         blanking. up to 2
 953                                                         packets per
 954                                                         completion wb. */
 955#define    RX_BAR_INTR_TIME_MASK           0x3FFFF000 /* assert RX_DONE if #
 956                                                         clocks > # since last
 957                                                         ISR read. each count
 958                                                         is 512 core clocks
 959                                                         (125MHz). 0 = no
 960                                                         blanking. */
 961
 962/* diagnostic access to RX FIFO. 32 LSB accessed via DATA_LOW. 32 MSB accessed
 963 * via DATA_HI_T0 or DATA_HI_T1. TAG reads the tag bit. writing HI_T0
 964 * will unset the tag bit while writing HI_T1 will set the tag bit. to reset
 965 * to normal operation after diagnostics, write to address location 0x0.
 966 * RX_DMA_EN bit must be set to 0x0 for RX FIFO PIO access. DATA_HI should
 967 * be the last write access of a write sequence.
 968 * DEFAULT: undefined
 969 */
 970#define  REG_RX_FIFO_ADDR                  0x4080  /* RX FIFO address */
 971#define  REG_RX_FIFO_TAG                   0x4084  /* RX FIFO tag */
 972#define  REG_RX_FIFO_DATA_LOW              0x4088  /* RX FIFO data low */
 973#define  REG_RX_FIFO_DATA_HI_T0            0x408C  /* RX FIFO data high T0 */
 974#define  REG_RX_FIFO_DATA_HI_T1            0x4090  /* RX FIFO data high T1 */
 975
 976/* diagnostic assess to RX CTRL FIFO. 8-bit FIFO_ADDR holds address of
 977 * 81 bit control entry and 6 bit flow id. LOW and MID are both 32-bit
 978 * accesses. HI is 7-bits with 6-bit flow id and 1 bit control
 979 * word. RX_DMA_EN must be 0 for RX CTRL FIFO PIO access. DATA_HI
 980 * should be last write access of the write sequence.
 981 * DEFAULT: undefined
 982 */
 983#define  REG_RX_CTRL_FIFO_ADDR             0x4094  /* RX Control FIFO and
 984                                                      Batching FIFO addr */
 985#define  REG_RX_CTRL_FIFO_DATA_LOW         0x4098  /* RX Control FIFO data
 986                                                      low */
 987#define  REG_RX_CTRL_FIFO_DATA_MID         0x409C  /* RX Control FIFO data
 988                                                      mid */
 989#define  REG_RX_CTRL_FIFO_DATA_HI          0x4100  /* RX Control FIFO data
 990                                                      hi and flow id */
 991#define    RX_CTRL_FIFO_DATA_HI_CTRL       0x0001  /* upper bit of ctrl word */
 992#define    RX_CTRL_FIFO_DATA_HI_FLOW_MASK  0x007E  /* flow id */
 993
 994/* diagnostic access to RX IPP FIFO. same semantics as RX_FIFO.
 995 * DEFAULT: undefined
 996 */
 997#define  REG_RX_IPP_FIFO_ADDR              0x4104  /* RX IPP FIFO address */
 998#define  REG_RX_IPP_FIFO_TAG               0x4108  /* RX IPP FIFO tag */
 999#define  REG_RX_IPP_FIFO_DATA_LOW          0x410C  /* RX IPP FIFO data low */
1000#define  REG_RX_IPP_FIFO_DATA_HI_T0        0x4110  /* RX IPP FIFO data high

1001                                                      T0 */
1002#define  REG_RX_IPP_FIFO_DATA_HI_T1        0x4114  /* RX IPP FIFO data high
1003                                                      T1 */
1004
1005/* 64-bit pointer to receive data buffer in host memory used for headers and
1006 * small packets. MSB in high register. loaded by DMA state machine and
1007 * increments as DMA writes receive data. only 50 LSB are incremented. top
1008 * 13 bits taken from RX descriptor.
1009 * DEFAULT: undefined
1010 */
1011#define  REG_RX_HEADER_PAGE_PTR_LOW        0x4118  /* (ro) RX header page ptr
1012                                                      low */
1013#define  REG_RX_HEADER_PAGE_PTR_HI         0x411C  /* (ro) RX header page ptr
1014                                                      high */
1015#define  REG_RX_MTU_PAGE_PTR_LOW           0x4120  /* (ro) RX MTU page pointer
1016                                                      low */
1017#define  REG_RX_MTU_PAGE_PTR_HI            0x4124  /* (ro) RX MTU page pointer
1018                                                      high */
1019
1020/* PIO diagnostic access to RX reassembly DMA Table RAM. 6-bit register holds
1021 * one of 64 79-bit locations in the RX Reassembly DMA table and the addr of
1022 * one of the 64 byte locations in the Batching table. LOW holds 32 LSB.
1023 * MID holds the next 32 LSB. HIGH holds the 15 MSB. RX_DMA_EN must be set
1024 * to 0 for PIO access. DATA_HIGH should be last write of write sequence.
1025 * layout:
1026 * reassmbl ptr [78:15] | reassmbl index [14:1] | reassmbl entry valid [0]
1027 * DEFAULT: undefined
1028 */
1029#define  REG_RX_TABLE_ADDR             0x4128  /* RX reassembly DMA table
1030                                                  address */
1031#define    RX_TABLE_ADDR_MASK          0x0000003F /* address mask */
1032
1033#define  REG_RX_TABLE_DATA_LOW         0x412C  /* RX reassembly DMA table
1034                                                  data low */
1035#define  REG_RX_TABLE_DATA_MID         0x4130  /* RX reassembly DMA table
1036                                                  data mid */
1037#define  REG_RX_TABLE_DATA_HI          0x4134  /* RX reassembly DMA table
1038                                                  data high */
1039
1040/* cassini+ only */
1041/* 8KB aligned 64-bit pointer to base of RX rings. lower 13 bits hardwired to
1042 * 0. same semantics as primary desc/complete rings.
1043 */
1044#define  REG_PLUS_RX_DB1_LOW            0x4200  /* RX descriptor ring
1045                                                   2 base low */
1046#define  REG_PLUS_RX_DB1_HI             0x4204  /* RX descriptor ring
1047                                                   2 base high */
1048#define  REG_PLUS_RX_CB1_LOW            0x4208  /* RX completion ring
1049                                                   2 base low. 4 total */
1050#define  REG_PLUS_RX_CB1_HI             0x420C  /* RX completion ring
1051                                                   2 base high. 4 total */
1052#define  REG_PLUS_RX_CBN_LOW(x)        (REG_PLUS_RX_CB1_LOW + 8*((x) - 1))
1053#define  REG_PLUS_RX_CBN_HI(x)         (REG_PLUS_RX_CB1_HI + 8*((x) - 1))
1054#define  REG_PLUS_RX_KICK1             0x4220  /* RX Kick 2 register */
1055#define  REG_PLUS_RX_COMP1             0x4224  /* (ro) RX completion 2
1056                                                  reg */
1057#define  REG_PLUS_RX_COMP1_HEAD        0x4228  /* (ro) RX completion 2
1058                                                  head reg. 4 total. */
1059#define  REG_PLUS_RX_COMP1_TAIL        0x422C  /* RX completion 2
1060                                                  tail reg. 4 total. */
1061#define  REG_PLUS_RX_COMPN_HEAD(x)    (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1))
1062#define  REG_PLUS_RX_COMPN_TAIL(x)    (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1))
1063#define  REG_PLUS_RX_AE1_THRESH        0x4240  /* RX almost empty 2
1064                                                  thresholds */
1065#define    RX_AE1_THRESH_FREE_MASK     RX_AE_THRESH_FREE_MASK
1066#define    RX_AE1_THRESH_FREE_SHIFT    RX_AE_THRESH_FREE_SHIFT
1067
1068/** header parser registers **/
1069
1070/* RX parser configuration register.
1071 * DEFAULT: 0x1651004
1072 */
1073#define  REG_HP_CFG                       0x4140  /* header parser
1074                                                     configuration reg */
1075#define    HP_CFG_PARSE_EN                0x00000001 /* enab header parsing */
1076#define    HP_CFG_NUM_CPU_MASK            0x000000FC /* # processors
1077                                                      0 = 64. 0x3f = 63 */
1078#define    HP_CFG_NUM_CPU_SHIFT           2
1079#define    HP_CFG_SYN_INC_MASK            0x00000100 /* SYN bit won't increment
1080                                                        TCP seq # by one when
1081                                                        stored in FDBM */
1082#define    HP_CFG_TCP_THRESH_MASK         0x000FFE00 /* # bytes of TCP data
1083                                                        needed to be considered
1084                                                        for reassembly */
1085#define    HP_CFG_TCP_THRESH_SHIFT        9
1086
1087/* access to RX Instruction RAM. 5-bit register/counter holds addr
1088 * of 39 bit entry to be read/written. 32 LSB in _DATA_LOW. 7 MSB in _DATA_HI.
1089 * RX_DMA_EN must be 0 for RX instr PIO access. DATA_HI should be last access
1090 * of sequence.
1091 * DEFAULT: undefined
1092 */
1093#define  REG_HP_INSTR_RAM_ADDR             0x4144  /* HP instruction RAM
1094                                                      address */
1095#define    HP_INSTR_RAM_ADDR_MASK          0x01F   /* 5-bit mask */
1096#define  REG_HP_INSTR_RAM_DATA_LOW         0x4148  /* HP instruction RAM
1097                                                      data low */
1098#define    HP_INSTR_RAM_LOW_OUTMASK_MASK   0x0000FFFF
1099#define    HP_INSTR_RAM_LOW_OUTMASK_SHIFT  0
1100#define    HP_INSTR_RAM_LOW_OUTSHIFT_MASK  0x000F0000
1101#define    HP_INSTR_RAM_LOW_OUTSHIFT_SHIFT 16
1102#define    HP_INSTR_RAM_LOW_OUTEN_MASK     0x00300000
1103#define    HP_INSTR_RAM_LOW_OUTEN_SHIFT    20
1104#define    HP_INSTR_RAM_LOW_OUTARG_MASK    0xFFC00000
1105#define    HP_INSTR_RAM_LOW_OUTARG_SHIFT   22
1106#define  REG_HP_INSTR_RAM_DATA_MID         0x414C  /* HP instruction RAM
1107                                                      data mid */
1108#define    HP_INSTR_RAM_MID_OUTARG_MASK    0x00000003
1109#define    HP_INSTR_RAM_MID_OUTARG_SHIFT   0
1110#define    HP_INSTR_RAM_MID_OUTOP_MASK     0x0000003C
1111#define    HP_INSTR_RAM_MID_OUTOP_SHIFT    2
1112#define    HP_INSTR_RAM_MID_FNEXT_MASK     0x000007C0
1113#define    HP_INSTR_RAM_MID_FNEXT_SHIFT    6
1114#define    HP_INSTR_RAM_MID_FOFF_MASK      0x0003F800
1115#define    HP_INSTR_RAM_MID_FOFF_SHIFT     11
1116#define    HP_INSTR_RAM_MID_SNEXT_MASK     0x007C0000
1117#define    HP_INSTR_RAM_MID_SNEXT_SHIFT    18
1118#define    HP_INSTR_RAM_MID_SOFF_MASK      0x3F800000
1119#define    HP_INSTR_RAM_MID_SOFF_SHIFT     23
1120#define    HP_INSTR_RAM_MID_OP_MASK        0xC0000000
1121#define    HP_INSTR_RAM_MID_OP_SHIFT       30
1122#define  REG_HP_INSTR_RAM_DATA_HI          0x4150  /* HP instruction RAM
1123                                                      data high */
1124#define    HP_INSTR_RAM_HI_VAL_MASK        0x0000FFFF
1125#define    HP_INSTR_RAM_HI_VAL_SHIFT       0
1126#define    HP_INSTR_RAM_HI_MASK_MASK       0xFFFF0000
1127#define    HP_INSTR_RAM_HI_MASK_SHIFT      16
1128
1129/* PIO access into RX Header parser data RAM and flow database.
1130 * 11-bit register. Data fills the LSB portion of bus if less than 32 bits.
1131 * DATA_RAM: write RAM_FDB_DATA with index to access DATA_RAM.
1132 * RAM bytes = 4*(x - 1) + [3:0]. e.g., 0 -> [3:0], 31 -> [123:120]
1133 * FLOWDB: write DATA_RAM_FDB register and then read/write FDB1-12 to access
1134 * flow database.
1135 * RX_DMA_EN must be 0 for RX parser RAM PIO access. RX Parser RAM data reg
1136 * should be the last write access of the write sequence.
1137 * DEFAULT: undefined
1138 */
1139#define  REG_HP_DATA_RAM_FDB_ADDR          0x4154  /* HP data and FDB
1140                                                      RAM address */
1141#define    HP_DATA_RAM_FDB_DATA_MASK       0x001F  /* select 1 of 86 byte
1142                                                      locations in header
1143                                                      parser data ram to
1144                                                      read/write */
1145#define    HP_DATA_RAM_FDB_FDB_MASK        0x3F00  /* 1 of 64 353-bit locations
1146                                                      in the flow database */
1147#define  REG_HP_DATA_RAM_DATA              0x4158  /* HP data RAM data */
1148
1149/* HP flow database registers: 1 - 12, 0x415C - 0x4188, 4 8-bit bytes
1150 * FLOW_DB(1) = IP_SA[127:96], FLOW_DB(2) = IP_SA[95:64]
1151 * FLOW_DB(3) = IP_SA[63:32],  FLOW_DB(4) = IP_SA[31:0]
1152 * FLOW_DB(5) = IP_DA[127:96], FLOW_DB(6) = IP_DA[95:64]
1153 * FLOW_DB(7) = IP_DA[63:32],  FLOW_DB(8) = IP_DA[31:0]
1154 * FLOW_DB(9) = {TCP_SP[15:0],TCP_DP[15:0]}
1155 * FLOW_DB(10) = bit 0 has value for flow valid
1156 * FLOW_DB(11) = TCP_SEQ[63:32], FLOW_DB(12) = TCP_SEQ[31:0]
1157 */
1158#define  REG_HP_FLOW_DB0                   0x415C  /* HP flow database 1 reg */
1159#define  REG_HP_FLOW_DBN(x)                (REG_HP_FLOW_DB0 + (x)*4)
1160
1161/* diagnostics for RX Header Parser block.
1162 * ASUN: the header parser state machine register is used for diagnostics
1163 * purposes. however, the spec doesn't have any details on it.
1164 */
1165#define  REG_HP_STATE_MACHINE              0x418C  /* (ro) HP state machine */
1166#define  REG_HP_STATUS0                    0x4190  /* (ro) HP status 1 */
1167#define    HP_STATUS0_SAP_MASK             0xFFFF0000 /* SAP */
1168#define    HP_STATUS0_L3_OFF_MASK          0x0000FE00 /* L3 offset */
1169#define    HP_STATUS0_LB_CPUNUM_MASK       0x000001F8 /* load balancing CPU
1170                                                         number */
1171#define    HP_STATUS0_HRP_OPCODE_MASK      0x00000007 /* HRP opcode */
1172
1173#define  REG_HP_STATUS1                    0x4194  /* (ro) HP status 2 */
1174#define    HP_STATUS1_ACCUR2_MASK          0xE0000000 /* accu R2[6:4] */
1175#define    HP_STATUS1_FLOWID_MASK          0x1F800000 /* flow id */
1176#define    HP_STATUS1_TCP_OFF_MASK         0x007F0000 /* tcp payload offset */
1177#define    HP_STATUS1_TCP_SIZE_MASK        0x0000FFFF /* tcp payload size */
1178
1179#define  REG_HP_STATUS2                    0x4198  /* (ro) HP status 3 */
1180#define    HP_STATUS2_ACCUR2_MASK          0xF0000000 /* accu R2[3:0] */
1181#define    HP_STATUS2_CSUM_OFF_MASK        0x07F00000 /* checksum start
1182                                                         start offset */
1183#define    HP_STATUS2_ACCUR1_MASK          0x000FE000 /* accu R1 */
1184#define    HP_STATUS2_FORCE_DROP           0x00001000 /* force drop */
1185#define    HP_STATUS2_BWO_REASSM           0x00000800 /* batching w/o
1186                                                         reassembly */
1187#define    HP_STATUS2_JH_SPLIT_EN          0x00000400 /* jumbo header split
1188                                                         enable */
1189#define    HP_STATUS2_FORCE_TCP_NOCHECK    0x00000200 /* force tcp no payload
1190                                                         check */
1191#define    HP_STATUS2_DATA_MASK_ZERO       0x00000100 /* mask of data length
1192                                                         equal to zero */
1193#define    HP_STATUS2_FORCE_TCP_CHECK      0x00000080 /* force tcp payload
1194                                                         chk */
1195#define    HP_STATUS2_MASK_TCP_THRESH      0x00000040 /* mask of payload
1196                                                         threshold */
1197#define    HP_STATUS2_NO_ASSIST            0x00000020 /* no assist */
1198#define    HP_STATUS2_CTRL_PACKET_FLAG     0x00000010 /* control packet flag */
1199#define    HP_STATUS2_TCP_FLAG_CHECK       0x00000008 /* tcp flag check */
1200#define    HP_STATUS2_SYN_FLAG             0x00000004 /* syn flag */
1201#define    HP_STATUS2_TCP_CHECK            0x00000002 /* tcp payload chk */
1202#define    HP_STATUS2_TCP_NOCHECK          0x00000001 /* tcp no payload chk */
1203
1204/* BIST for header parser(HP) and flow database memories (FDBM). set _START
1205 * to start BIST. controller clears _START on completion. _START can also
1206 * be cleared to force termination of BIST. a bit set indicates that that
1207 * memory passed its BIST.
1208 */
1209#define  REG_HP_RAM_BIST                   0x419C  /* HP RAM BIST reg */
1210#define    HP_RAM_BIST_HP_DATA_PASS        0x80000000 /* HP data ram */
1211#define    HP_RAM_BIST_HP_INSTR0_PASS      0x40000000 /* HP instr ram 0 */
1212#define    HP_RAM_BIST_HP_INSTR1_PASS      0x20000000 /* HP instr ram 1 */
1213#define    HP_RAM_BIST_HP_INSTR2_PASS      0x10000000 /* HP instr ram 2 */
1214#define    HP_RAM_BIST_FDBM_AGE0_PASS      0x08000000 /* FDBM aging RAM0 */
1215#define    HP_RAM_BIST_FDBM_AGE1_PASS      0x04000000 /* FDBM aging RAM1 */
1216#define    HP_RAM_BIST_FDBM_FLOWID00_PASS  0x02000000 /* FDBM flowid RAM0
1217                                                         bank 0 */
1218#define    HP_RAM_BIST_FDBM_FLOWID10_PASS  0x01000000 /* FDBM flowid RAM1
1219                                                         bank 0 */
1220#define    HP_RAM_BIST_FDBM_FLOWID20_PASS  0x00800000 /* FDBM flowid RAM2
1221                                                         bank 0 */
1222#define    HP_RAM_BIST_FDBM_FLOWID30_PASS  0x00400000 /* FDBM flowid RAM3
1223                                                         bank 0 */
1224#define    HP_RAM_BIST_FDBM_FLOWID01_PASS  0x00200000 /* FDBM flowid RAM0
1225                                                         bank 1 */
1226#define    HP_RAM_BIST_FDBM_FLOWID11_PASS  0x00100000 /* FDBM flowid RAM1
1227                                                         bank 2 */
1228#define    HP_RAM_BIST_FDBM_FLOWID21_PASS  0x00080000 /* FDBM flowid RAM2
1229                                                         bank 1 */
1230#define    HP_RAM_BIST_FDBM_FLOWID31_PASS  0x00040000 /* FDBM flowid RAM3
1231                                                         bank 1 */
1232#define    HP_RAM_BIST_FDBM_TCPSEQ_PASS    0x00020000 /* FDBM tcp sequence
1233                                                         RAM */
1234#define    HP_RAM_BIST_SUMMARY             0x00000002 /* all BIST tests */
1235#define    HP_RAM_BIST_START               0x00000001 /* start/stop BIST */
1236
1237
1238/** MAC registers.  **/
1239/* reset bits are set using a PIO write and self-cleared after the command
1240 * execution has completed.
1241 */
1242#define  REG_MAC_TX_RESET                  0x6000  /* TX MAC software reset
1243                                                      command (default: 0x0) */
1244#define  REG_MAC_RX_RESET                  0x6004  /* RX MAC software reset
1245                                                      command (default: 0x0) */
1246/* execute a pause flow control frame transmission
1247 DEFAULT: 0x0XXXX */
1248#define  REG_MAC_SEND_PAUSE                0x6008  /* send pause command reg */
1249#define    MAC_SEND_PAUSE_TIME_MASK        0x0000FFFF /* value of pause time
1250                                                         to be sent on network
1251                                                         in units of slot
1252                                                         times */
1253#define    MAC_SEND_PAUSE_SEND             0x00010000 /* send pause flow ctrl
1254                                                         frame on network */
1255
1256/* bit set indicates that event occurred. auto-cleared when status register
1257 * is read and have corresponding mask bits in mask register. events will
1258 * trigger an interrupt if the corresponding mask bit is 0.
1259 * status register default: 0x00000000
1260 * mask register default = 0xFFFFFFFF on reset
1261 */
1262#define  REG_MAC_TX_STATUS                 0x6010  /* TX MAC status reg */
1263#define    MAC_TX_FRAME_XMIT               0x0001  /* successful frame
1264                                                      transmision */
1265#define    MAC_TX_UNDERRUN                 0x0002  /* terminated frame
1266                                                      transmission due to
1267                                                      data starvation in the
1268                                                      xmit data path */
1269#define    MAC_TX_MAX_PACKET_ERR           0x0004  /* frame exceeds max allowed
1270                                                      length passed to TX MAC
1271                                                      by the DMA engine */
1272#define    MAC_TX_COLL_NORMAL              0x0008  /* rollover of the normal
1273                                                      collision counter */
1274#define    MAC_TX_COLL_EXCESS              0x0010  /* rollover of the excessive
1275                                                      collision counter */
1276#define    MAC_TX_COLL_LATE                0x0020  /* rollover of the late
1277                                                      collision counter */
1278#define    MAC_TX_COLL_FIRST               0x0040  /* rollover of the first
1279                                                      collision counter */
1280#define    MAC_TX_DEFER_TIMER              0x0080  /* rollover of the defer
1281                                                      timer */
1282#define    MAC_TX_PEAK_ATTEMPTS            0x0100  /* rollover of the peak
1283                                                      attempts counter */
1284
1285#define  REG_MAC_RX_STATUS                 0x6014  /* RX MAC status reg */
1286#define    MAC_RX_FRAME_RECV               0x0001  /* successful receipt of
1287                                                      a frame */
1288#define    MAC_RX_OVERFLOW                 0x0002  /* dropped frame due to
1289                                                      RX FIFO overflow */
1290#define    MAC_RX_FRAME_COUNT              0x0004  /* rollover of receive frame
1291                                                      counter */
1292#define    MAC_RX_ALIGN_ERR                0x0008  /* rollover of alignment
1293                                                      error counter */
1294#define    MAC_RX_CRC_ERR                  0x0010  /* rollover of crc error
1295                                                      counter */
1296#define    MAC_RX_LEN_ERR                  0x0020  /* rollover of length
1297                                                      error counter */
1298#define    MAC_RX_VIOL_ERR                 0x0040  /* rollover of code
1299                                                      violation error */
1300
1301/* DEFAULT: 0xXXXX0000 on reset */
1302#define  REG_MAC_CTRL_STATUS               0x6018  /* MAC control status reg */
1303#define    MAC_CTRL_PAUSE_RECEIVED         0x00000001  /* successful
1304                                                          reception of a
1305                                                          pause control
1306                                                          frame */
1307#define    MAC_CTRL_PAUSE_STATE            0x00000002  /* MAC has made a
1308                                                          transition from
1309                                                          "not paused" to
1310                                                          "paused" */
1311#define    MAC_CTRL_NOPAUSE_STATE          0x00000004  /* MAC has made a
1312                                                          transition from
1313                                                          "paused" to "not
1314                                                          paused" */
1315#define    MAC_CTRL_PAUSE_TIME_MASK        0xFFFF0000  /* value of pause time
1316                                                          operand that was
1317                                                          received in the last
1318                                                          pause flow control
1319                                                          frame */
1320
1321/* layout identical to TX MAC[8:0] */
1322#define  REG_MAC_TX_MASK                   0x6020  /* TX MAC mask reg */
1323/* layout identical to RX MAC[6:0] */
1324#define  REG_MAC_RX_MASK                   0x6024  /* RX MAC mask reg */
1325/* layout identical to CTRL MAC[2:0] */
1326#define  REG_MAC_CTRL_MASK                 0x6028  /* MAC control mask reg */
1327
1328/* to ensure proper operation, CFG_EN must be cleared to 0 and a delay
1329 * imposed before writes to other bits in the TX_MAC_CFG register or any of
1330 * the MAC parameters is performed. delay dependent upon time required to
1331 * transmit a maximum size frame (= MAC_FRAMESIZE_MAX*8/Mbps). e.g.,
1332 * the delay for a 1518-byte frame on a 100Mbps network is 125us.
1333 * alternatively, just poll TX_CFG_EN until it reads back as 0.
1334 * NOTE: on half-duplex 1Gbps, TX_CFG_CARRIER_EXTEND and
1335 * RX_CFG_CARRIER_EXTEND should be set and the SLOT_TIME register should
1336 * be 0x200 (slot time of 512 bytes)
1337 */
1338#define  REG_MAC_TX_CFG                 0x6030  /* TX MAC config reg */
1339#define    MAC_TX_CFG_EN                0x0001  /* enable TX MAC. 0 will
1340                                                      force TXMAC state
1341                                                      machine to remain in
1342                                                      idle state or to
1343                                                      transition to idle state
1344                                                      on completion of an
1345                                                      ongoing packet. */
1346#define    MAC_TX_CFG_IGNORE_CARRIER    0x0002  /* disable CSMA/CD deferral
1347                                                   process. set to 1 when
1348                                                   full duplex and 0 when
1349                                                   half duplex */
1350#define    MAC_TX_CFG_IGNORE_COLL       0x0004  /* disable CSMA/CD backoff
1351                                                   algorithm. set to 1 when
1352                                                   full duplex and 0 when
1353                                                   half duplex */
1354#define    MAC_TX_CFG_IPG_EN            0x0008  /* enable extension of the
1355                                                   Rx-to-TX IPG. after
1356                                                   receiving a frame, TX
1357                                                   MAC will reset its
1358                                                   deferral process to
1359                                                   carrier sense for the
1360                                                   amount of time = IPG0 +
1361                                                   IPG1 and commit to
1362                                                   transmission for time
1363                                                   specified in IPG2. when
1364                                                   0 or when xmitting frames
1365                                                   back-to-pack (Tx-to-Tx
1366                                                   IPG), TX MAC ignores
1367                                                   IPG0 and will only use
1368                                                   IPG1 for deferral time.
1369                                                   IPG2 still used. */
1370#define    MAC_TX_CFG_NEVER_GIVE_UP_EN  0x0010  /* TX MAC will not easily
1371                                                   give up on frame
1372                                                   xmission. if backoff
1373                                                   algorithm reaches the
1374                                                   ATTEMPT_LIMIT, it will
1375                                                   clear attempts counter
1376                                                   and continue trying to
1377                                                   send the frame as
1378                                                   specified by
1379                                                   GIVE_UP_LIM. when 0,
1380                                                   TX MAC will execute
1381                                                   standard CSMA/CD prot. */
1382#define    MAC_TX_CFG_NEVER_GIVE_UP_LIM 0x0020  /* when set, TX MAC will
1383                                                   continue to try to xmit
1384                                                   until successful. when
1385                                                   0, TX MAC will continue
1386                                                   to try xmitting until
1387                                                   successful or backoff
1388                                                   algorithm reaches
1389                                                   ATTEMPT_LIMIT*16 */
1390#define    MAC_TX_CFG_NO_BACKOFF        0x0040  /* modify CSMA/CD to disable
1391                                                   backoff algorithm. TX
1392                                                   MAC will not back off
1393                                                   after a xmission attempt
1394                                                   that resulted in a
1395                                                   collision. */
1396#define    MAC_TX_CFG_SLOW_DOWN         0x0080  /* modify CSMA/CD so that
1397                                                   deferral process is reset
1398                                                   in response to carrier
1399                                                   sense during the entire
1400                                                   duration of IPG. TX MAC
1401                                                   will only commit to frame
1402                                                   xmission after frame
1403                                                   xmission has actually
1404                                                   begun. */
1405#define    MAC_TX_CFG_NO_FCS            0x0100  /* TX MAC will not generate
1406                                                   CRC for all xmitted
1407                                                   packets. when clear, CRC
1408                                                   generation is dependent
1409                                                   upon NO_CRC bit in the
1410                                                   xmit control word from
1411                                                   TX DMA */
1412#define    MAC_TX_CFG_CARRIER_EXTEND    0x0200  /* enables xmit part of the
1413                                                   carrier extension
1414                                                   feature. this allows for
1415                                                   longer collision domains
1416                                                   by extending the carrier
1417                                                   and collision window
1418                                                   from the end of FCS until
1419                                                   the end of the slot time
1420                                                   if necessary. Required
1421                                                   for half-duplex at 1Gbps,
1422                                                   clear otherwise. */
1423
1424/* when CRC is not stripped, reassembly packets will not contain the CRC.
1425 * these will be stripped by HRP because it reassembles layer 4 data, and the
1426 * CRC is layer 2. however, non-reassembly packets will still contain the CRC
1427 * when passed to the host. to ensure proper operation, need to wait 3.2ms
1428 * after clearing RX_CFG_EN before writing to any other RX MAC registers
1429 * or other MAC parameters. alternatively, poll RX_CFG_EN until it clears
1430 * to 0. similary, HASH_FILTER_EN and ADDR_FILTER_EN have the same
1431 * restrictions as CFG_EN.
1432 */
1433#define  REG_MAC_RX_CFG                 0x6034  /* RX MAC config reg */
1434#define    MAC_RX_CFG_EN                0x0001  /* enable RX MAC */
1435#define    MAC_RX_CFG_STRIP_PAD         0x0002  /* always program to 0.
1436                                                   feature not supported */
1437#define    MAC_RX_CFG_STRIP_FCS         0x0004  /* RX MAC will strip the
1438                                                   last 4 bytes of a
1439                                                   received frame. */
1440#define    MAC_RX_CFG_PROMISC_EN        0x0008  /* promiscuous mode */
1441#define    MAC_RX_CFG_PROMISC_GROUP_EN  0x0010  /* accept all valid
1442                                                   multicast frames (group
1443                                                   bit in DA field set) */
1444#define    MAC_RX_CFG_HASH_FILTER_EN    0x0020  /* use hash table to filter
1445                                                   multicast addresses */
1446#define    MAC_RX_CFG_ADDR_FILTER_EN    0x0040  /* cause RX MAC to use
1447                                                   address filtering regs
1448                                                   to filter both unicast
1449                                                   and multicast
1450                                                   addresses */
1451#define    MAC_RX_CFG_DISABLE_DISCARD   0x0080  /* pass errored frames to
1452                                                   RX DMA by setting BAD
1453                                                   bit but not Abort bit
1454                                                   in the status. CRC,
1455                                                   framing, and length errs
1456                                                   will not increment
1457                                                   error counters. frames
1458                                                   which don't match dest
1459                                                   addr will be passed up
1460                                                   w/ BAD bit set. */
1461#define    MAC_RX_CFG_CARRIER_EXTEND    0x0100  /* enable reception of
1462                                                   packet bursts generated
1463                                                   by carrier extension
1464                                                   with packet bursting
1465                                                   senders. only applies
1466                                                   to half-duplex 1Gbps */
1467
1468/* DEFAULT: 0x0 */
1469#define  REG_MAC_CTRL_CFG               0x6038  /* MAC control config reg */
1470#define    MAC_CTRL_CFG_SEND_PAUSE_EN   0x0001  /* respond to requests for
1471                                                   sending pause flow ctrl
1472                                                   frames */
1473#define    MAC_CTRL_CFG_RECV_PAUSE_EN   0x0002  /* respond to received
1474                                                   pause flow ctrl frames */
1475#define    MAC_CTRL_CFG_PASS_CTRL       0x0004  /* pass valid MAC ctrl
1476                                                   packets to RX DMA */
1477
1478/* to ensure proper operation, a global initialization sequence should be
1479 * performed when a loopback config is entered or exited. if programmed after
1480 * a hw or global sw reset, RX/TX MAC software reset and initialization
1481 * should be done to ensure stable clocking.
1482 * DEFAULT: 0x0
1483 */
1484#define  REG_MAC_XIF_CFG                0x603C  /* XIF config reg */
1485#define    MAC_XIF_TX_MII_OUTPUT_EN        0x0001  /* enable output drivers
1486                                                      on MII xmit bus */
1487#define    MAC_XIF_MII_INT_LOOPBACK        0x0002  /* loopback GMII xmit data
1488                                                      path to GMII recv data
1489                                                      path. phy mode register
1490                                                      clock selection must be
1491                                                      set to GMII mode and
1492                                                      GMII_MODE should be set
1493                                                      to 1. in loopback mode,
1494                                                      REFCLK will drive the
1495                                                      entire mac core. 0 for
1496                                                      normal operation. */
1497#define    MAC_XIF_DISABLE_ECHO            0x0004  /* disables receive data
1498                                                      path during packet
1499                                                      xmission. clear to 0
1500                                                      in any full duplex mode,
1501                                                      in any loopback mode,
1502                                                      or in half-duplex SERDES
1503                                                      or SLINK modes. set when
1504                                                      in half-duplex when
1505                                                      using external phy. */
1506#define    MAC_XIF_GMII_MODE               0x0008  /* MAC operates with GMII
1507                                                      clocks and datapath */
1508#define    MAC_XIF_MII_BUFFER_OUTPUT_EN    0x0010  /* MII_BUF_EN pin. enable
1509                                                      external tristate buffer
1510                                                      on the MII receive
1511                                                      bus. */
1512#define    MAC_XIF_LINK_LED                0x0020  /* LINKLED# active (low) */
1513#define    MAC_XIF_FDPLX_LED               0x0040  /* FDPLXLED# active (low) */
1514
1515#define  REG_MAC_IPG0                      0x6040  /* inter-packet gap0 reg.
1516                                                      recommended: 0x00 */
1517#define  REG_MAC_IPG1                      0x6044  /* inter-packet gap1 reg
1518                                                      recommended: 0x08 */
1519#define  REG_MAC_IPG2                      0x6048  /* inter-packet gap2 reg
1520                                                      recommended: 0x04 */
1521#define  REG_MAC_SLOT_TIME                 0x604C  /* slot time reg
1522                                                      recommended: 0x40 */
1523#define  REG_MAC_FRAMESIZE_MIN             0x6050  /* min frame size reg
1524                                                      recommended: 0x40 */
1525
1526/* FRAMESIZE_MAX holds both the max frame size as well as the max burst size.
1527 * recommended value:  0x2000.05EE
1528 */
1529#define  REG_MAC_FRAMESIZE_MAX             0x6054  /* max frame size reg */
1530#define    MAC_FRAMESIZE_MAX_BURST_MASK    0x3FFF0000 /* max burst size */
1531#define    MAC_FRAMESIZE_MAX_BURST_SHIFT   16
1532#define    MAC_FRAMESIZE_MAX_FRAME_MASK    0x00007FFF /* max frame size */
1533#define    MAC_FRAMESIZE_MAX_FRAME_SHIFT   0
1534#define  REG_MAC_PA_SIZE                   0x6058  /* PA size reg. number of
1535                                                      preamble bytes that the
1536                                                      TX MAC will xmit at the
1537                                                      beginning of each frame
1538                                                      value should be 2 or
1539                                                      greater. recommended
1540                                                      value: 0x07 */
1541#define  REG_MAC_JAM_SIZE                  0x605C  /* jam size reg. duration
1542                                                      of jam in units of media
1543                                                      byte time. recommended
1544                                                      value: 0x04 */
1545#define  REG_MAC_ATTEMPT_LIMIT             0x6060  /* attempt limit reg. #
1546                                                      of attempts TX MAC will
1547                                                      make to xmit a frame
1548                                                      before it resets its
1549                                                      attempts counter. after
1550                                                      the limit has been
1551                                                      reached, TX MAC may or
1552                                                      may not drop the frame
1553                                                      dependent upon value
1554                                                      in TX_MAC_CFG.
1555                                                      recommended
1556                                                      value: 0x10 */
1557#define  REG_MAC_CTRL_TYPE                 0x6064  /* MAC control type reg.
1558                                                      type field of a MAC
1559                                                      ctrl frame. recommended
1560                                                      value: 0x8808 */
1561
1562/* mac address registers: 0 - 44, 0x6080 - 0x6130, 4 8-bit bytes.
1563 * register           contains                   comparison
1564 *    0        16 MSB of primary MAC addr        [47:32] of DA field
1565 *    1        16 middle bits ""                 [31:16] of DA field
1566 *    2        16 LSB ""                         [15:0] of DA field
1567 *    3*x      16MSB of alt MAC addr 1-15        [47:32] of DA field
1568 *    4*x      16 middle bits ""                 [31:16]
1569 *    5*x      16 LSB ""                         [15:0]
1570 *    42       16 MSB of MAC CTRL addr           [47:32] of DA.
1571 *    43       16 middle bits ""                 [31:16]
1572 *    44       16 LSB ""                         [15:0]
1573 *    MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames.
1574 *    if there is a match, MAC will set the bit for alternative address
1575 *    filter pass [15]
1576
1577 *    here is the map of registers given MAC address notation: a:b:c:d:e:f
1578 *                     ab             cd             ef
1579 *    primary addr     reg 2          reg 1          reg 0
1580 *    alt addr 1       reg 5          reg 4          reg 3
1581 *    alt addr x       reg 5*x        reg 4*x        reg 3*x
1582 *    ctrl addr        reg 44         reg 43         reg 42
1583 */
1584#define  REG_MAC_ADDR0                     0x6080  /* MAC address 0 reg */
1585#define  REG_MAC_ADDRN(x)                  (REG_MAC_ADDR0 + (x)*4)
1586#define  REG_MAC_ADDR_FILTER0              0x614C  /* address filter 0 reg
1587                                                      [47:32] */
1588#define  REG_MAC_ADDR_FILTER1              0x6150  /* address filter 1 reg
1589                                                      [31:16] */
1590#define  REG_MAC_ADDR_FILTER2              0x6154  /* address filter 2 reg
1591                                                      [15:0] */
1592#define  REG_MAC_ADDR_FILTER2_1_MASK       0x6158  /* address filter 2 and 1
1593                                                      mask reg. 8-bit reg
1594                                                      contains nibble mask for
1595                                                      reg 2 and 1. */
1596#define  REG_MAC_ADDR_FILTER0_MASK         0x615C  /* address filter 0 mask
1597                                                      reg */
1598
1599/* hash table registers: 0 - 15, 0x6160 - 0x619C, 4 8-bit bytes
1600 * 16-bit registers contain bits of the hash table.
1601 * reg x  -> [16*(15 - x) + 15 : 16*(15 - x)].
1602 * e.g., 15 -> [15:0], 0 -> [255:240]
1603 */
1604#define  REG_MAC_HASH_TABLE0               0x6160  /* hash table 0 reg */
1605#define  REG_MAC_HASH_TABLEN(x)            (REG_MAC_HASH_TABLE0 + (x)*4)
1606
1607/* statistics registers. these registers generate an interrupt on
1608 * overflow. recommended initialization: 0x0000. most are 16-bits except
1609 * for PEAK_ATTEMPTS register which is 8 bits.
1610 */
1611#define  REG_MAC_COLL_NORMAL               0x61A0 /* normal collision
1612                                                     counter. */
1613#define  REG_MAC_COLL_FIRST                0x61A4 /* first attempt
1614                                                     successful collision
1615                                                     counter */
1616#define  REG_MAC_COLL_EXCESS               0x61A8 /* excessive collision
1617                                                     counter */
1618#define  REG_MAC_COLL_LATE                 0x61AC /* late collision counter */
1619#define  REG_MAC_TIMER_DEFER               0x61B0 /* defer timer. time base
1620                                                     is the media byte
1621                                                     clock/256 */
1622#define  REG_MAC_ATTEMPTS_PEAK             0x61B4 /* peak attempts reg */
1623#define  REG_MAC_RECV_FRAME                0x61B8 /* receive frame counter */
1624#define  REG_MAC_LEN_ERR                   0x61BC /* length error counter */
1625#define  REG_MAC_ALIGN_ERR                 0x61C0 /* alignment error counter */
1626#define  REG_MAC_FCS_ERR                   0x61C4 /* FCS error counter */
1627#define  REG_MAC_RX_CODE_ERR               0x61C8 /* RX code violation
1628                                                     error counter */
1629
1630/* misc registers */
1631#define  REG_MAC_RANDOM_SEED               0x61CC /* random number seed reg.
1632                                                   10-bit register used as a
1633                                                   seed  for the random number
1634                                                   generator for the CSMA/CD
1635                                                   backoff algorithm. only
1636                                                   programmed after power-on
1637                                                   reset and should be a
1638                                                   random value which has a
1639                                                   high likelihood of being
1640                                                   unique for each MAC
1641                                                   attached to a network
1642                                                   segment (e.g., 10 LSB of
1643                                                   MAC address) */
1644
1645/* ASUN: there's a PAUSE_TIMER (ro) described, but it's not in the address
1646 *       map
1647 */
1648
1649/* 27-bit register has the current state for key state machines in the MAC */
1650#define  REG_MAC_STATE_MACHINE             0x61D0 /* (ro) state machine reg */
1651#define    MAC_SM_RLM_MASK                 0x07800000
1652#define    MAC_SM_RLM_SHIFT                23
1653#define    MAC_SM_RX_FC_MASK               0x00700000
1654#define    MAC_SM_RX_FC_SHIFT              20
1655#define    MAC_SM_TLM_MASK                 0x000F0000
1656#define    MAC_SM_TLM_SHIFT                16
1657#define    MAC_SM_ENCAP_SM_MASK            0x0000F000
1658#define    MAC_SM_ENCAP_SM_SHIFT           12
1659#define    MAC_SM_TX_REQ_MASK              0x00000C00
1660#define    MAC_SM_TX_REQ_SHIFT             10
1661#define    MAC_SM_TX_FC_MASK               0x000003C0
1662#define    MAC_SM_TX_FC_SHIFT              6
1663#define    MAC_SM_FIFO_WRITE_SEL_MASK      0x00000038
1664#define    MAC_SM_FIFO_WRITE_SEL_SHIFT     3
1665#define    MAC_SM_TX_FIFO_EMPTY_MASK       0x00000007
1666#define    MAC_SM_TX_FIFO_EMPTY_SHIFT      0
1667
1668/** MIF registers. the MIF can be programmed in either bit-bang or
1669 *  frame mode.
1670 **/
1671#define  REG_MIF_BIT_BANG_CLOCK            0x6200 /* MIF bit-bang clock.
1672                                                   1 -> 0 will generate a
1673                                                   rising edge. 0 -> 1 will
1674                                                   generate a falling edge. */
1675#define  REG_MIF_BIT_BANG_DATA             0x6204 /* MIF bit-bang data. 1-bit
1676                                                     register generates data */
1677#define  REG_MIF_BIT_BANG_OUTPUT_EN        0x6208 /* MIF bit-bang output
1678                                                     enable. enable when
1679                                                     xmitting data from MIF to
1680                                                     transceiver. */
1681
1682/* 32-bit register serves as an instruction register when the MIF is
1683 * programmed in frame mode. load this register w/ a valid instruction
1684 * (as per IEEE 802.3u MII spec). poll this register to check for instruction
1685 * execution completion. during a read operation, this register will also
1686 * contain the 16-bit data returned by the tranceiver. unless specified
1687 * otherwise, fields are considered "don't care" when polling for
1688 * completion.
1689 */
1690#define  REG_MIF_FRAME                     0x620C /* MIF frame/output reg */
1691#define    MIF_FRAME_START_MASK            0xC0000000 /* start of frame.
1692                                                         load w/ 01 when
1693                                                         issuing an instr */
1694#define    MIF_FRAME_ST                    0x40000000 /* STart of frame */
1695#define    MIF_FRAME_OPCODE_MASK           0x30000000 /* opcode. 01 for a
1696                                                         write. 10 for a
1697                                                         read */
1698#define    MIF_FRAME_OP_READ               0x20000000 /* read OPcode */
1699#define    MIF_FRAME_OP_WRITE              0x10000000 /* write OPcode */
1700#define    MIF_FRAME_PHY_ADDR_MASK         0x0F800000 /* phy address. when
1701                                                         issuing an instr,
1702                                                         this field should be
1703                                                         loaded w/ the XCVR
1704                                                         addr */
1705#define    MIF_FRAME_PHY_ADDR_SHIFT        23
1706#define    MIF_FRAME_REG_ADDR_MASK         0x007C0000 /* register address.
1707                                                         when issuing an instr,
1708                                                         addr of register
1709                                                         to be read/written */
1710#define    MIF_FRAME_REG_ADDR_SHIFT        18
1711#define    MIF_FRAME_TURN_AROUND_MSB       0x00020000 /* turn around, MSB.
1712                                                         when issuing an instr,
1713                                                         set this bit to 1 */
1714#define    MIF_FRAME_TURN_AROUND_LSB       0x00010000 /* turn around, LSB.
1715                                                         when issuing an instr,
1716                                                         set this bit to 0.
1717                                                         when polling for
1718                                                         completion, 1 means
1719                                                         that instr execution
1720                                                         has been completed */
1721#define    MIF_FRAME_DATA_MASK             0x0000FFFF /* instruction payload
1722                                                         load with 16-bit data
1723                                                         to be written in
1724                                                         transceiver reg for a
1725                                                         write. doesn't matter
1726                                                         in a read. when
1727                                                         polling for
1728                                                         completion, field is
1729                                                         "don't care" for write
1730                                                         and 16-bit data
1731                                                         returned by the
1732                                                         transceiver for a
1733                                                         read (if valid bit
1734                                                         is set) */
1735#define  REG_MIF_CFG                    0x6210 /* MIF config reg */
1736#define    MIF_CFG_PHY_SELECT           0x0001 /* 1 -> select MDIO_1
1737                                                  0 -> select MDIO_0 */
1738#define    MIF_CFG_POLL_EN              0x0002 /* enable polling
1739                                                  mechanism. if set,
1740                                                  BB_MODE should be 0 */
1741#define    MIF_CFG_BB_MODE              0x0004 /* 1 -> bit-bang mode
1742                                                  0 -> frame mode */
1743#define    MIF_CFG_POLL_REG_MASK        0x00F8 /* register address to be
1744                                                  used by polling mode.
1745                                                  only meaningful if POLL_EN
1746                                                  is set to 1 */
1747#define    MIF_CFG_POLL_REG_SHIFT       3
1748#define    MIF_CFG_MDIO_0               0x0100 /* (ro) dual purpose.
1749                                                  when MDIO_0 is idle,
1750                                                  1 -> tranceiver is
1751                                                  connected to MDIO_0.
1752                                                  when MIF is communicating
1753                                                  w/ MDIO_0 in bit-bang
1754                                                  mode, this bit indicates
1755                                                  the incoming bit stream
1756                                                  during a read op */
1757#define    MIF_CFG_MDIO_1               0x0200 /* (ro) dual purpose.
1758                                                  when MDIO_1 is idle,
1759                                                  1 -> transceiver is
1760                                                  connected to MDIO_1.
1761                                                  when MIF is communicating
1762                                                  w/ MDIO_1 in bit-bang
1763                                                  mode, this bit indicates
1764                                                  the incoming bit stream
1765                                                  during a read op */
1766#define    MIF_CFG_POLL_PHY_MASK        0x7C00 /* tranceiver address to
1767                                                  be polled */
1768#define    MIF_CFG_POLL_PHY_SHIFT       10
1769
1770/* 16-bit register used to determine which bits in the POLL_STATUS portion of
1771 * the MIF_STATUS register will cause an interrupt. if a mask bit is 0,
1772 * corresponding bit of the POLL_STATUS will generate a MIF interrupt when
1773 * set. DEFAULT: 0xFFFF
1774 */
1775#define  REG_MIF_MASK                      0x6214 /* MIF mask reg */
1776
1777/* 32-bit register used when in poll mode. auto-cleared after being read */
1778#define  REG_MIF_STATUS                    0x6218 /* MIF status reg */
1779#define    MIF_STATUS_POLL_DATA_MASK       0xFFFF0000 /* poll data contains
1780                                                         the "latest image"
1781                                                         update of the XCVR
1782                                                         reg being read */
1783#define    MIF_STATUS_POLL_DATA_SHIFT      16
1784#define    MIF_STATUS_POLL_STATUS_MASK     0x0000FFFF /* poll status indicates
1785                                                         which bits in the
1786                                                         POLL_DATA field have
1787                                                         changed since the
1788                                                         MIF_STATUS reg was
1789                                                         last read */
1790#define    MIF_STATUS_POLL_STATUS_SHIFT    0
1791
1792/* 7-bit register has current state for all state machines in the MIF */
1793#define  REG_MIF_STATE_MACHINE             0x621C /* MIF state machine reg */
1794#define    MIF_SM_CONTROL_MASK             0x07   /* control state machine
1795                                                     state */
1796#define    MIF_SM_EXECUTION_MASK           0x60   /* execution state machine
1797                                                     state */
1798
1799/** PCS/Serialink. the following registers are equivalent to the standard
1800 *  MII management registers except that they're directly mapped in
1801 *  Cassini's register space.
1802 **/
1803
1804/* the auto-negotiation enable bit should be programmed the same at
1805 * the link partner as in the local device to enable auto-negotiation to
1806 * complete. when that bit is reprogrammed, auto-neg/manual config is
1807 * restarted automatically.
1808 * DEFAULT: 0x1040
1809 */
1810#define  REG_PCS_MII_CTRL                  0x9000 /* PCS MII control reg */
1811#define    PCS_MII_CTRL_1000_SEL           0x0040 /* reads 1. ignored on
1812                                                     writes */
1813#define    PCS_MII_CTRL_COLLISION_TEST     0x0080 /* COL signal at the PCS
1814                                                     to MAC interface is
1815                                                     activated regardless
1816                                                     of activity */
1817#define    PCS_MII_CTRL_DUPLEX             0x0100 /* forced 0x0. PCS
1818                                                     behaviour same for
1819                                                     half and full dplx */
1820#define    PCS_MII_RESTART_AUTONEG         0x0200 /* self clearing.
1821                                                     restart auto-
1822                                                     negotiation */
1823#define    PCS_MII_ISOLATE                 0x0400 /* read as 0. ignored
1824                                                     on writes */
1825#define    PCS_MII_POWER_DOWN              0x0800 /* read as 0. ignored
1826                                                     on writes */
1827#define    PCS_MII_AUTONEG_EN              0x1000 /* default 1. PCS goes
1828                                                     through automatic
1829                                                     link config before it
1830                                                     can be used. when 0,
1831                                                     link can be used
1832                                                     w/out any link config
1833                                                     phase */
1834#define    PCS_MII_10_100_SEL              0x2000 /* read as 0. ignored on
1835                                                     writes */
1836#define    PCS_MII_RESET                   0x8000 /* reset PCS. self-clears
1837                                                     when done */
1838
1839/* DEFAULT: 0x0108 */
1840#define  REG_PCS_MII_STATUS                0x9004 /* PCS MII status reg */
1841#define    PCS_MII_STATUS_EXTEND_CAP       0x0001 /* reads 0 */
1842#define    PCS_MII_STATUS_JABBER_DETECT    0x0002 /* reads 0 */
1843#define    PCS_MII_STATUS_LINK_STATUS      0x0004 /* 1 -> link up.
1844                                                     0 -> link down. 0 is
1845                                                     latched so that 0 is
1846                                                     kept until read. read
1847                                                     2x to determine if the
1848                                                     link has gone up again */
1849#define    PCS_MII_STATUS_AUTONEG_ABLE     0x0008 /* reads 1 (able to perform
1850                                                     auto-neg) */
1851#define    PCS_MII_STATUS_REMOTE_FAULT     0x0010 /* 1 -> remote fault detected
1852                                                     from received link code
1853                                                     word. only valid after
1854                                                     auto-neg completed */
1855#define    PCS_MII_STATUS_AUTONEG_COMP     0x0020 /* 1 -> auto-negotiation
1856                                                          completed
1857                                                     0 -> auto-negotiation not
1858                                                     completed */
1859#define    PCS_MII_STATUS_EXTEND_STATUS    0x0100 /* reads as 1. used as an
1860                                                     indication that this is
1861                                                     a 1000 Base-X PHY. writes
1862                                                     to it are ignored */
1863
1864/* used during auto-negotiation.
1865 * DEFAULT: 0x00E0
1866 */
1867#define  REG_PCS_MII_ADVERT                0x9008 /* PCS MII advertisement
1868                                                     reg */
1869#define    PCS_MII_ADVERT_FD               0x0020  /* advertise full duplex
1870                                                      1000 Base-X */
1871#define    PCS_MII_ADVERT_HD               0x0040  /* advertise half-duplex
1872                                                      1000 Base-X */
1873#define    PCS_MII_ADVERT_SYM_PAUSE        0x0080  /* advertise PAUSE
1874                                                      symmetric capability */
1875#define    PCS_MII_ADVERT_ASYM_PAUSE       0x0100  /* advertises PAUSE
1876                                                      asymmetric capability */
1877#define    PCS_MII_ADVERT_RF_MASK          0x3000 /* remote fault. write bit13
1878                                                     to optionally indicate to
1879                                                     link partner that chip is
1880                                                     going off-line. bit12 will
1881                                                     get set when signal
1882                                                     detect == FAIL and will
1883                                                     remain set until
1884                                                     successful negotiation */
1885#define    PCS_MII_ADVERT_ACK              0x4000 /* (ro) */
1886#define    PCS_MII_ADVERT_NEXT_PAGE        0x8000 /* (ro) forced 0x0 */
1887
1888/* contents updated as a result of autonegotiation. layout and definitions
1889 * identical to PCS_MII_ADVERT
1890 */
1891#define  REG_PCS_MII_LPA                   0x900C /* PCS MII link partner
1892                                                     ability reg */
1893#define    PCS_MII_LPA_FD             PCS_MII_ADVERT_FD
1894#define    PCS_MII_LPA_HD             PCS_MII_ADVERT_HD
1895#define    PCS_MII_LPA_SYM_PAUSE      PCS_MII_ADVERT_SYM_PAUSE
1896#define    PCS_MII_LPA_ASYM_PAUSE     PCS_MII_ADVERT_ASYM_PAUSE
1897#define    PCS_MII_LPA_RF_MASK        PCS_MII_ADVERT_RF_MASK
1898#define    PCS_MII_LPA_ACK            PCS_MII_ADVERT_ACK
1899#define    PCS_MII_LPA_NEXT_PAGE      PCS_MII_ADVERT_NEXT_PAGE
1900
1901/* DEFAULT: 0x0 */
1902#define  REG_PCS_CFG                       0x9010 /* PCS config reg */
1903#define    PCS_CFG_EN                      0x01   /* enable PCS. must be
1904                                                     0 when modifying
1905                                                     PCS_MII_ADVERT */
1906#define    PCS_CFG_SD_OVERRIDE             0x02   /* sets signal detect to
1907                                                     OK. bit is
1908                                                     non-resettable */
1909#define    PCS_CFG_SD_ACTIVE_LOW           0x04   /* changes interpretation
1910                                                     of optical signal to make
1911                                                     signal detect okay when
1912                                                     signal is low */
1913#define    PCS_CFG_JITTER_STUDY_MASK       0x18   /* used to make jitter
1914                                                     measurements. a single
1915                                                     code group is xmitted
1916                                                     regularly.
1917                                                     0x0 = normal operation
1918                                                     0x1 = high freq test
1919                                                           pattern, D21.5
1920                                                     0x2 = low freq test
1921                                                           pattern, K28.7
1922                                                     0x3 = reserved */
1923#define    PCS_CFG_10MS_TIMER_OVERRIDE     0x20   /* shortens 10-20ms auto-
1924                                                     negotiation timer to
1925                                                     a few cycles for test
1926                                                     purposes */
1927
1928/* used for diagnostic purposes. bits 20-22 autoclear on read */
1929#define  REG_PCS_STATE_MACHINE             0x9014 /* (ro) PCS state machine
1930                                                     and diagnostic reg */
1931#define    PCS_SM_TX_STATE_MASK            0x0000000F /* 0 and 1 indicate
1932                                                         xmission of idle.
1933                                                         otherwise, xmission of
1934                                                         a packet */
1935#define    PCS_SM_RX_STATE_MASK            0x000000F0 /* 0 indicates reception
1936                                                         of idle. otherwise,
1937                                                         reception of packet */
1938#define    PCS_SM_WORD_SYNC_STATE_MASK     0x00000700 /* 0 indicates loss of
1939                                                         sync */
1940#define    PCS_SM_SEQ_DETECT_STATE_MASK    0x00001800 /* cycling through 0-3
1941                                                         indicates reception of
1942                                                         Config codes. cycling
1943                                                         through 0-1 indicates
1944                                                         reception of idles */
1945#define    PCS_SM_LINK_STATE_MASK          0x0001E000
1946#define        SM_LINK_STATE_UP            0x00016000 /* link state is up */
1947
1948#define    PCS_SM_LOSS_LINK_C              0x00100000 /* loss of link due to
1949                                                         recept of Config
1950                                                         codes */
1951#define    PCS_SM_LOSS_LINK_SYNC           0x00200000 /* loss of link due to
1952                                                         loss of sync */
1953#define    PCS_SM_LOSS_SIGNAL_DETECT       0x00400000 /* signal detect goes
1954                                                         from OK to FAIL. bit29
1955                                                         will also be set if
1956                                                         this is set */
1957#define    PCS_SM_NO_LINK_BREAKLINK        0x01000000 /* link not up due to
1958                                                        receipt of breaklink
1959                                                        C codes from partner.
1960                                                        C codes w/ 0 content
1961                                                        received triggering
1962                                                        start/restart of
1963                                                        autonegotiation.
1964                                                        should be sent for
1965                                                        no longer than 20ms */
1966#define    PCS_SM_NO_LINK_SERDES           0x02000000 /* serdes being
1967                                                        initialized. see serdes
1968                                                        state reg */
1969#define    PCS_SM_NO_LINK_C                0x04000000 /* C codes not stable or
1970                                                         not received */
1971#define    PCS_SM_NO_LINK_SYNC             0x08000000 /* word sync not
1972                                                         achieved */
1973#define    PCS_SM_NO_LINK_WAIT_C           0x10000000 /* waiting for C codes
1974                                                         w/ ack bit set */
1975#define    PCS_SM_NO_LINK_NO_IDLE          0x20000000 /* link partner continues
1976                                                         to send C codes
1977                                                         instead of idle
1978                                                         symbols or pkt data */
1979
1980/* this register indicates interrupt changes in specific PCS MII status bits.
1981 * PCS_INT may be masked at the ISR level. only a single bit is implemented
1982 * for link status change.
1983 */
1984#define  REG_PCS_INTR_STATUS               0x9018 /* PCS interrupt status */
1985#define    PCS_INTR_STATUS_LINK_CHANGE     0x04   /* link status has changed
1986                                                     since last read */
1987
1988/* control which network interface is used. no more than one bit should
1989 * be set.
1990 * DEFAULT: none
1991 */
1992#define  REG_PCS_DATAPATH_MODE             0x9050 /* datapath mode reg */
1993#define    PCS_DATAPATH_MODE_MII           0x00 /* PCS is not used and
1994                                                   MII/GMII is selected.
1995                                                   selection between MII and
1996                                                   GMII is controlled by
1997                                                   XIF_CFG */
1998#define    PCS_DATAPATH_MODE_SERDES        0x02 /* PCS is used via the
1999                                                   10-bit interface */
2000

2001/* input to serdes chip or serialink block */
2002#define  REG_PCS_SERDES_CTRL              0x9054 /* serdes control reg */
2003#define    PCS_SERDES_CTRL_LOOPBACK       0x01   /* enable loopback on
2004                                                    serdes interface */
2005#define    PCS_SERDES_CTRL_SYNCD_EN       0x02   /* enable sync carrier
2006                                                    detection. should be
2007                                                    0x0 for normal
2008                                                    operation */
2009#define    PCS_SERDES_CTRL_LOCKREF       0x04   /* frequency-lock RBC[0:1]
2010                                                   to REFCLK when set.
2011                                                   when clear, receiver
2012                                                   clock locks to incoming
2013                                                   serial data */
2014
2015/* multiplex test outputs into the PROM address (PA_3 through PA_0) pins.
2016 * should be 0x0 for normal operations.
2017 * 0b000          normal operation, PROM address[3:0] selected
2018 * 0b001          rxdma req, rxdma ack, rxdma ready, rxdma read
2019 * 0b010          rxmac req, rx ack, rx tag, rx clk shared
2020 * 0b011          txmac req, tx ack, tx tag, tx retry req
2021 * 0b100          tx tp3, tx tp2, tx tp1, tx tp0
2022 * 0b101          R period RX, R period TX, R period HP, R period BIM
2023 * DEFAULT: 0x0
2024 */
2025#define  REG_PCS_SHARED_OUTPUT_SEL         0x9058 /* shared output select */
2026#define    PCS_SOS_PROM_ADDR_MASK          0x0007
2027
2028/* used for diagnostics. this register indicates progress of the SERDES
2029 * boot up.
2030 * 0b00       undergoing reset
2031 * 0b01       waiting 500us while lockrefn is asserted
2032 * 0b10       waiting for comma detect
2033 * 0b11       receive data is synchronized
2034 * DEFAULT: 0x0
2035 */
2036#define  REG_PCS_SERDES_STATE              0x905C /* (ro) serdes state */
2037#define    PCS_SERDES_STATE_MASK           0x03
2038
2039/* used for diagnostics. indicates number of packets transmitted or received.
2040 * counters rollover w/out generating an interrupt.
2041 * DEFAULT: 0x0
2042 */
2043#define  REG_PCS_PACKET_COUNT              0x9060 /* (ro) PCS packet counter */
2044#define    PCS_PACKET_COUNT_TX             0x000007FF /* pkts xmitted by PCS */
2045#define    PCS_PACKET_COUNT_RX             0x07FF0000 /* pkts recvd by PCS
2046                                                         whether they
2047                                                         encountered an error
2048                                                         or not */
2049
2050/** LocalBus Devices. the following provides run-time access to the
2051 *  Cassini's PROM
2052 ***/
2053#define  REG_EXPANSION_ROM_RUN_START       0x100000 /* expansion rom run time
2054                                                       access */
2055#define  REG_EXPANSION_ROM_RUN_END         0x17FFFF
2056
2057#define  REG_SECOND_LOCALBUS_START         0x180000 /* secondary local bus
2058                                                       device */
2059#define  REG_SECOND_LOCALBUS_END           0x1FFFFF
2060
2061/* entropy device */
2062#define  REG_ENTROPY_START                 REG_SECOND_LOCALBUS_START
2063#define  REG_ENTROPY_DATA                  (REG_ENTROPY_START + 0x00)
2064#define  REG_ENTROPY_STATUS                (REG_ENTROPY_START + 0x04)
2065#define      ENTROPY_STATUS_DRDY           0x01
2066#define      ENTROPY_STATUS_BUSY           0x02
2067#define      ENTROPY_STATUS_CIPHER         0x04
2068#define      ENTROPY_STATUS_BYPASS_MASK    0x18
2069#define  REG_ENTROPY_MODE                  (REG_ENTROPY_START + 0x05)
2070#define      ENTROPY_MODE_KEY_MASK         0x07
2071#define      ENTROPY_MODE_ENCRYPT          0x40
2072#define  REG_ENTROPY_RAND_REG              (REG_ENTROPY_START + 0x06)
2073#define  REG_ENTROPY_RESET                 (REG_ENTROPY_START + 0x07)
2074#define      ENTROPY_RESET_DES_IO          0x01
2075#define      ENTROPY_RESET_STC_MODE        0x02
2076#define      ENTROPY_RESET_KEY_CACHE       0x04
2077#define      ENTROPY_RESET_IV              0x08
2078#define  REG_ENTROPY_IV                    (REG_ENTROPY_START + 0x08)
2079#define  REG_ENTROPY_KEY0                  (REG_ENTROPY_START + 0x10)
2080#define  REG_ENTROPY_KEYN(x)               (REG_ENTROPY_KEY0 + 4*(x))
2081
2082/* phys of interest w/ their special mii registers */
2083#define PHY_LUCENT_B0     0x00437421
2084#define   LUCENT_MII_REG      0x1F
2085
2086#define PHY_NS_DP83065    0x20005c78
2087#define   DP83065_MII_MEM     0x16
2088#define   DP83065_MII_REGD    0x1D
2089#define   DP83065_MII_REGE    0x1E
2090
2091#define PHY_BROADCOM_5411 0x00206071
2092#define PHY_BROADCOM_B0   0x00206050
2093#define   BROADCOM_MII_REG4   0x14
2094#define   BROADCOM_MII_REG5   0x15
2095#define   BROADCOM_MII_REG7   0x17
2096#define   BROADCOM_MII_REG8   0x18
2097
2098#define   CAS_MII_ANNPTR          0x07
2099#define   CAS_MII_ANNPRR          0x08
2100#define   CAS_MII_1000_CTRL       0x09
2101#define   CAS_MII_1000_STATUS     0x0A
2102#define   CAS_MII_1000_EXTEND     0x0F
2103
2104#define   CAS_BMSR_1000_EXTEND    0x0100 /* supports 1000Base-T extended status */
2105/*
2106 * if autoneg is disabled, here's the table:
2107 * BMCR_SPEED100 = 100Mbps
2108 * BMCR_SPEED1000 = 1000Mbps
2109 * ~(BMCR_SPEED100 | BMCR_SPEED1000) = 10Mbps
2110 */
2111#define   CAS_BMCR_SPEED1000      0x0040  /* Select 1000Mbps */
2112
2113#define   CAS_ADVERTISE_1000HALF   0x0100
2114#define   CAS_ADVERTISE_1000FULL   0x0200
2115#define   CAS_ADVERTISE_PAUSE      0x0400
2116#define   CAS_ADVERTISE_ASYM_PAUSE 0x0800
2117
2118/* regular lpa register */
2119#define   CAS_LPA_PAUSE            CAS_ADVERTISE_PAUSE
2120#define   CAS_LPA_ASYM_PAUSE       CAS_ADVERTISE_ASYM_PAUSE
2121
2122/* 1000_STATUS register */
2123#define   CAS_LPA_1000HALF        0x0400
2124#define   CAS_LPA_1000FULL        0x0800
2125
2126#define   CAS_EXTEND_1000XFULL    0x8000
2127#define   CAS_EXTEND_1000XHALF    0x4000
2128#define   CAS_EXTEND_1000TFULL    0x2000
2129#define   CAS_EXTEND_1000THALF    0x1000
2130
2131/* cassini header parser firmware */
2132typedef struct cas_hp_inst {
2133        const char *note;
2134
2135        u16 mask, val;
2136
2137        u8 op;
2138        u8 soff, snext; /* if match succeeds, new offset and match */
2139        u8 foff, fnext; /* if match fails, new offset and match */
2140        /* output info */
2141        u8 outop;    /* output opcode */
2142
2143        u16 outarg;  /* output argument */
2144        u8 outenab;  /* output enable: 0 = not, 1 = if match
2145                         2 = if !match, 3 = always */
2146        u8 outshift; /* barrel shift right, 4 bits */
2147        u16 outmask;
2148} cas_hp_inst_t;
2149
2150/* comparison */
2151#define OP_EQ     0 /* packet == value */
2152#define OP_LT     1 /* packet < value */
2153#define OP_GT     2 /* packet > value */
2154#define OP_NP     3 /* new packet */
2155
2156/* output opcodes */
2157#define CL_REG  0
2158#define LD_FID  1
2159#define LD_SEQ  2
2160#define LD_CTL  3
2161#define LD_SAP  4
2162#define LD_R1   5
2163#define LD_L3   6
2164#define LD_SUM  7
2165#define LD_HDR  8
2166#define IM_FID  9
2167#define IM_SEQ  10
2168#define IM_SAP  11
2169#define IM_R1   12
2170#define IM_CTL  13
2171#define LD_LEN  14
2172#define ST_FLG  15
2173
2174/* match setp #s for IP4TCP4 */
2175#define S1_PCKT         0
2176#define S1_VLAN         1
2177#define S1_CFI          2
2178#define S1_8023         3
2179#define S1_LLC          4
2180#define S1_LLCc         5
2181#define S1_IPV4         6
2182#define S1_IPV4c        7
2183#define S1_IPV4F        8
2184#define S1_TCP44        9
2185#define S1_IPV6         10
2186#define S1_IPV6L        11
2187#define S1_IPV6c        12
2188#define S1_TCP64        13
2189#define S1_TCPSQ        14
2190#define S1_TCPFG        15
2191#define S1_TCPHL        16
2192#define S1_TCPHc        17
2193#define S1_CLNP         18
2194#define S1_CLNP2        19
2195#define S1_DROP         20
2196#define S2_HTTP         21
2197#define S1_ESP4         22
2198#define S1_AH4          23
2199#define S1_ESP6         24
2200#define S1_AH6          25
2201
2202#define CAS_PROG_IP46TCP4_PREAMBLE \
2203{ "packet arrival?", 0xffff, 0x0000, OP_NP,  6, S1_VLAN,  0, S1_PCKT,  \
2204  CL_REG, 0x3ff, 1, 0x0, 0x0000}, \
2205{ "VLAN?", 0xffff, 0x8100, OP_EQ,  1, S1_CFI,   0, S1_8023,  \
2206  IM_CTL, 0x00a,  3, 0x0, 0xffff}, \
2207{ "CFI?", 0x1000, 0x1000, OP_EQ,  0, S1_DROP,  1, S1_8023, \
2208  CL_REG, 0x000,  0, 0x0, 0x0000}, \
2209{ "8023?", 0xffff, 0x0600, OP_LT,  1, S1_LLC,   0, S1_IPV4, \
2210  CL_REG, 0x000,  0, 0x0, 0x0000}, \
2211{ "LLC?", 0xffff, 0xaaaa, OP_EQ,  1, S1_LLCc,  0, S1_CLNP, \
2212  CL_REG, 0x000,  0, 0x0, 0x0000}, \
2213{ "LLCc?", 0xff00, 0x0300, OP_EQ,  2, S1_IPV4,  0, S1_CLNP, \
2214  CL_REG, 0x000,  0, 0x0, 0x0000}, \
2215{ "IPV4?", 0xffff, 0x0800, OP_EQ,  1, S1_IPV4c, 0, S1_IPV6, \
2216  LD_SAP, 0x100,  3, 0x0, 0xffff}, \
2217{ "IPV4 cont?", 0xff00, 0x4500, OP_EQ,  3, S1_IPV4F, 0, S1_CLNP, \
2218  LD_SUM, 0x00a,  1, 0x0, 0x0000}, \
2219{ "IPV4 frag?", 0x3fff, 0x0000, OP_EQ,  1, S1_TCP44, 0, S1_CLNP, \
2220  LD_LEN, 0x03e,  1, 0x0, 0xffff}, \
2221{ "TCP44?", 0x00ff, 0x0006, OP_EQ,  7, S1_TCPSQ, 0, S1_CLNP, \
2222  LD_FID, 0x182,  1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ \
2223{ "IPV6?", 0xffff, 0x86dd, OP_EQ,  1, S1_IPV6L, 0, S1_CLNP,  \
2224  LD_SUM, 0x015,  1, 0x0, 0x0000}, \
2225{ "IPV6 len", 0xf000, 0x6000, OP_EQ,  0, S1_IPV6c, 0, S1_CLNP, \
2226  IM_R1,  0x128,  1, 0x0, 0xffff}, \
2227{ "IPV6 cont?", 0x0000, 0x0000, OP_EQ,  3, S1_TCP64, 0, S1_CLNP, \
2228  LD_FID, 0x484,  1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ \
2229{ "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP, \
2230  LD_LEN, 0x03f,  1, 0x0, 0xffff}
2231
2232#ifdef USE_HP_IP46TCP4
2233static cas_hp_inst_t cas_prog_ip46tcp4tab[] = {
2234        CAS_PROG_IP46TCP4_PREAMBLE,
2235        { "TCP seq", /* DADDR should point to dest port */
2236          0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ,
2237          0x081,  3, 0x0, 0xffff}, /* Load TCP seq # */
2238        { "TCP control flags", 0x0000, 0x0000, OP_EQ,  0, S1_TCPHL, 0,
2239          S1_TCPHL, ST_FLG, 0x045,  3, 0x0, 0x002f}, /* Load TCP flags */
2240        { "TCP length", 0x0000, 0x0000, OP_EQ,  0, S1_TCPHc, 0,
2241          S1_TCPHc, LD_R1,  0x205,  3, 0xB, 0xf000},
2242        { "TCP length cont", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0,
2243          S1_PCKT,  LD_HDR, 0x0ff,  3, 0x0, 0xffff},
2244        { "Cleanup", 0x0000, 0x0000, OP_EQ,  0, S1_CLNP2,  0, S1_CLNP2,
2245          IM_CTL, 0x001,  3, 0x0, 0x0001},
2246        { "Cleanup 2", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0, S1_PCKT,
2247          IM_CTL, 0x000,  0, 0x0, 0x0000},
2248        { "Drop packet", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0, S1_PCKT,
2249          IM_CTL, 0x080,  3, 0x0, 0xffff},
2250        { NULL },
2251};
2252#ifdef HP_IP46TCP4_DEFAULT
2253#define CAS_HP_FIRMWARE               cas_prog_ip46tcp4tab
2254#endif
2255#endif
2256
2257/*
2258 * Alternate table load which excludes HTTP server traffic from reassembly.
2259 * It is substantially similar to the basic table, with one extra state
2260 * and a few extra compares. */
2261#ifdef USE_HP_IP46TCP4NOHTTP
2262static cas_hp_inst_t cas_prog_ip46tcp4nohttptab[] = {
2263        CAS_PROG_IP46TCP4_PREAMBLE,
2264        { "TCP seq", /* DADDR should point to dest port */
2265          0xFFFF, 0x0080, OP_EQ,  0, S2_HTTP,  0, S1_TCPFG, LD_SEQ,
2266          0x081,  3, 0x0, 0xffff} , /* Load TCP seq # */
2267        { "TCP control flags", 0xFFFF, 0x8080, OP_EQ,  0, S2_HTTP,  0,
2268          S1_TCPHL, ST_FLG, 0x145,  2, 0x0, 0x002f, }, /* Load TCP flags */
2269        { "TCP length", 0x0000, 0x0000, OP_EQ,  0, S1_TCPHc, 0, S1_TCPHc,
2270          LD_R1,  0x205,  3, 0xB, 0xf000},
2271        { "TCP length cont", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0, S1_PCKT,
2272          LD_HDR, 0x0ff,  3, 0x0, 0xffff},
2273        { "Cleanup", 0x0000, 0x0000, OP_EQ,  0, S1_CLNP2,  0, S1_CLNP2,
2274          IM_CTL, 0x001,  3, 0x0, 0x0001},
2275        { "Cleanup 2", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0, S1_PCKT,
2276          CL_REG, 0x002,  3, 0x0, 0x0000},
2277        { "Drop packet", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0, S1_PCKT,
2278          IM_CTL, 0x080,  3, 0x0, 0xffff},
2279        { "No HTTP", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0, S1_PCKT,
2280          IM_CTL, 0x044,  3, 0x0, 0xffff},
2281        { NULL },
2282};
2283#ifdef HP_IP46TCP4NOHTTP_DEFAULT
2284#define CAS_HP_FIRMWARE               cas_prog_ip46tcp4nohttptab
2285#endif
2286#endif
2287
2288/* match step #s for IP4FRAG */
2289#define S3_IPV6c        11
2290#define S3_TCP64        12
2291#define S3_TCPSQ        13
2292#define S3_TCPFG        14
2293#define S3_TCPHL        15
2294#define S3_TCPHc        16
2295#define S3_FRAG         17
2296#define S3_FOFF         18
2297#define S3_CLNP         19
2298
2299#ifdef USE_HP_IP4FRAG
2300static cas_hp_inst_t cas_prog_ip4fragtab[] = {
2301        { "packet arrival?", 0xffff, 0x0000, OP_NP,  6, S1_VLAN,  0, S1_PCKT,
2302          CL_REG, 0x3ff, 1, 0x0, 0x0000},
2303        { "VLAN?", 0xffff, 0x8100, OP_EQ,  1, S1_CFI,   0, S1_8023,
2304          IM_CTL, 0x00a,  3, 0x0, 0xffff},
2305        { "CFI?", 0x1000, 0x1000, OP_EQ,  0, S3_CLNP,  1, S1_8023,
2306          CL_REG, 0x000,  0, 0x0, 0x0000},
2307        { "8023?", 0xffff, 0x0600, OP_LT,  1, S1_LLC,   0, S1_IPV4,
2308          CL_REG, 0x000,  0, 0x0, 0x0000},
2309        { "LLC?", 0xffff, 0xaaaa, OP_EQ,  1, S1_LLCc,  0, S3_CLNP,
2310          CL_REG, 0x000,  0, 0x0, 0x0000},
2311        { "LLCc?",0xff00, 0x0300, OP_EQ,  2, S1_IPV4,  0, S3_CLNP,
2312          CL_REG, 0x000,  0, 0x0, 0x0000},
2313        { "IPV4?", 0xffff, 0x0800, OP_EQ,  1, S1_IPV4c, 0, S1_IPV6,
2314          LD_SAP, 0x100,  3, 0x0, 0xffff},
2315        { "IPV4 cont?", 0xff00, 0x4500, OP_EQ,  3, S1_IPV4F, 0, S3_CLNP,
2316          LD_SUM, 0x00a,  1, 0x0, 0x0000},
2317        { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ,  1, S1_TCP44, 0, S3_FRAG,
2318          LD_LEN, 0x03e,  3, 0x0, 0xffff},
2319        { "TCP44?", 0x00ff, 0x0006, OP_EQ,  7, S3_TCPSQ, 0, S3_CLNP,
2320          LD_FID, 0x182,  3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
2321        { "IPV6?", 0xffff, 0x86dd, OP_EQ,  1, S3_IPV6c, 0, S3_CLNP,
2322          LD_SUM, 0x015,  1, 0x0, 0x0000},
2323        { "IPV6 cont?", 0xf000, 0x6000, OP_EQ,  3, S3_TCP64, 0, S3_CLNP,
2324          LD_FID, 0x484,  1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */
2325        { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S3_TCPSQ, 0, S3_CLNP,
2326          LD_LEN, 0x03f,  1, 0x0, 0xffff},
2327        { "TCP seq",    /* DADDR should point to dest port */
2328          0x0000, 0x0000, OP_EQ,  0, S3_TCPFG, 4, S3_TCPFG, LD_SEQ,
2329          0x081,  3, 0x0, 0xffff}, /* Load TCP seq # */
2330        { "TCP control flags", 0x0000, 0x0000, OP_EQ,  0, S3_TCPHL, 0,
2331          S3_TCPHL, ST_FLG, 0x045,  3, 0x0, 0x002f}, /* Load TCP flags */
2332        { "TCP length", 0x0000, 0x0000, OP_EQ,  0, S3_TCPHc, 0, S3_TCPHc,
2333          LD_R1,  0x205,  3, 0xB, 0xf000},
2334        { "TCP length cont", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0, S1_PCKT,
2335          LD_HDR, 0x0ff,  3, 0x0, 0xffff},
2336        { "IP4 Fragment", 0x0000, 0x0000, OP_EQ,  0, S3_FOFF,  0, S3_FOFF,
2337          LD_FID, 0x103,  3, 0x0, 0xffff}, /* FID IP4 src+dst */
2338        { "IP4 frag offset", 0x0000, 0x0000, OP_EQ,  0, S3_FOFF,  0, S3_FOFF,
2339          LD_SEQ, 0x040,  1, 0xD, 0xfff8},
2340        { "Cleanup", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0, S1_PCKT,
2341          IM_CTL, 0x001,  3, 0x0, 0x0001},
2342        { NULL },
2343};
2344#ifdef HP_IP4FRAG_DEFAULT
2345#define CAS_HP_FIRMWARE               cas_prog_ip4fragtab
2346#endif
2347#endif
2348
2349/*
2350 * Alternate table which does batching without reassembly
2351 */
2352#ifdef USE_HP_IP46TCP4BATCH
2353static cas_hp_inst_t cas_prog_ip46tcp4batchtab[] = {
2354        CAS_PROG_IP46TCP4_PREAMBLE,
2355        { "TCP seq",    /* DADDR should point to dest port */
2356          0x0000, 0x0000, OP_EQ,  0, S1_TCPFG, 0, S1_TCPFG, LD_SEQ,
2357          0x081,  3, 0x0, 0xffff}, /* Load TCP seq # */
2358        { "TCP control flags", 0x0000, 0x0000, OP_EQ,  0, S1_TCPHL, 0,
2359          S1_TCPHL, ST_FLG, 0x000,  3, 0x0, 0x0000}, /* Load TCP flags */
2360        { "TCP length", 0x0000, 0x0000, OP_EQ,  0, S1_TCPHc, 0,
2361          S1_TCPHc, LD_R1,  0x205,  3, 0xB, 0xf000},
2362        { "TCP length cont", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0,
2363          S1_PCKT,  IM_CTL, 0x040,  3, 0x0, 0xffff}, /* set batch bit */
2364        { "Cleanup", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0, S1_PCKT,
2365          IM_CTL, 0x001,  3, 0x0, 0x0001},
2366        { "Drop packet", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0,
2367          S1_PCKT,  IM_CTL, 0x080,  3, 0x0, 0xffff},
2368        { NULL },
2369};
2370#ifdef HP_IP46TCP4BATCH_DEFAULT
2371#define CAS_HP_FIRMWARE               cas_prog_ip46tcp4batchtab
2372#endif
2373#endif
2374
2375/* Workaround for Cassini rev2 descriptor corruption problem.
2376 * Does batching without reassembly, and sets the SAP to a known
2377 * data pattern for all packets.
2378 */
2379#ifdef USE_HP_WORKAROUND
2380static cas_hp_inst_t  cas_prog_workaroundtab[] = {
2381        { "packet arrival?", 0xffff, 0x0000, OP_NP,  6, S1_VLAN,  0,
2382          S1_PCKT,  CL_REG, 0x3ff,  1, 0x0, 0x0000} ,
2383        { "VLAN?", 0xffff, 0x8100, OP_EQ,  1, S1_CFI, 0, S1_8023,
2384          IM_CTL, 0x04a,  3, 0x0, 0xffff},
2385        { "CFI?", 0x1000, 0x1000, OP_EQ,  0, S1_CLNP,  1, S1_8023,
2386          CL_REG, 0x000,  0, 0x0, 0x0000},
2387        { "8023?", 0xffff, 0x0600, OP_LT,  1, S1_LLC,   0, S1_IPV4,
2388          CL_REG, 0x000,  0, 0x0, 0x0000},
2389        { "LLC?", 0xffff, 0xaaaa, OP_EQ,  1, S1_LLCc,  0, S1_CLNP,
2390          CL_REG, 0x000,  0, 0x0, 0x0000},
2391        { "LLCc?", 0xff00, 0x0300, OP_EQ,  2, S1_IPV4,  0, S1_CLNP,
2392          CL_REG, 0x000,  0, 0x0, 0x0000},
2393        { "IPV4?", 0xffff, 0x0800, OP_EQ,  1, S1_IPV4c, 0, S1_IPV6,
2394          IM_SAP, 0x6AE,  3, 0x0, 0xffff},
2395        { "IPV4 cont?", 0xff00, 0x4500, OP_EQ,  3, S1_IPV4F, 0, S1_CLNP,
2396          LD_SUM, 0x00a,  1, 0x0, 0x0000},
2397        { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ,  1, S1_TCP44, 0, S1_CLNP,
2398          LD_LEN, 0x03e,  1, 0x0, 0xffff},
2399        { "TCP44?", 0x00ff, 0x0006, OP_EQ,  7, S1_TCPSQ, 0, S1_CLNP,
2400          LD_FID, 0x182,  3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
2401        { "IPV6?", 0xffff, 0x86dd, OP_EQ,  1, S1_IPV6L, 0, S1_CLNP,
2402          LD_SUM, 0x015,  1, 0x0, 0x0000},
2403        { "IPV6 len", 0xf000, 0x6000, OP_EQ,  0, S1_IPV6c, 0, S1_CLNP,
2404          IM_R1,  0x128,  1, 0x0, 0xffff},
2405        { "IPV6 cont?", 0x0000, 0x0000, OP_EQ,  3, S1_TCP64, 0, S1_CLNP,
2406          LD_FID, 0x484,  1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */
2407        { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP,
2408          LD_LEN, 0x03f,  1, 0x0, 0xffff},
2409        { "TCP seq",      /* DADDR should point to dest port */
2410          0x0000, 0x0000, OP_EQ,  0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ,
2411          0x081,  3, 0x0, 0xffff}, /* Load TCP seq # */
2412        { "TCP control flags", 0x0000, 0x0000, OP_EQ,  0, S1_TCPHL, 0,
2413          S1_TCPHL, ST_FLG, 0x045,  3, 0x0, 0x002f}, /* Load TCP flags */
2414        { "TCP length", 0x0000, 0x0000, OP_EQ,  0, S1_TCPHc, 0, S1_TCPHc,
2415          LD_R1,  0x205,  3, 0xB, 0xf000},
2416        { "TCP length cont", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0,
2417          S1_PCKT,  LD_HDR, 0x0ff,  3, 0x0, 0xffff},
2418        { "Cleanup", 0x0000, 0x0000, OP_EQ,  0, S1_CLNP2, 0, S1_CLNP2,
2419          IM_SAP, 0x6AE,  3, 0x0, 0xffff} ,
2420        { "Cleanup 2", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0, S1_PCKT,
2421          IM_CTL, 0x001,  3, 0x0, 0x0001},
2422        { NULL },
2423};
2424#ifdef HP_WORKAROUND_DEFAULT
2425#define CAS_HP_FIRMWARE               cas_prog_workaroundtab
2426#endif
2427#endif
2428
2429#ifdef USE_HP_ENCRYPT
2430static cas_hp_inst_t  cas_prog_encryptiontab[] = {
2431        { "packet arrival?", 0xffff, 0x0000, OP_NP,  6, S1_VLAN,  0,
2432          S1_PCKT,  CL_REG, 0x3ff,  1, 0x0, 0x0000},
2433        { "VLAN?", 0xffff, 0x8100, OP_EQ,  1, S1_CFI,   0, S1_8023,
2434          IM_CTL, 0x00a,  3, 0x0, 0xffff},
2435#if 0
2436//"CFI?", /* 02 FIND CFI and If FIND go to S1_DROP */
2437//0x1000, 0x1000, OP_EQ,  0, S1_DROP,  1, S1_8023,  CL_REG, 0x000,  0, 0x0, 0x00
2438        00,
2439#endif
2440        { "CFI?", /* FIND CFI and If FIND go to CleanUP1 (ignore and send to host) */
2441          0x1000, 0x1000, OP_EQ,  0, S1_CLNP,  1, S1_8023,
2442          CL_REG, 0x000,  0, 0x0, 0x0000},
2443        { "8023?", 0xffff, 0x0600, OP_LT,  1, S1_LLC,   0, S1_IPV4,
2444          CL_REG, 0x000,  0, 0x0, 0x0000},
2445        { "LLC?", 0xffff, 0xaaaa, OP_EQ,  1, S1_LLCc,  0, S1_CLNP,
2446          CL_REG, 0x000,  0, 0x0, 0x0000},
2447        { "LLCc?", 0xff00, 0x0300, OP_EQ,  2, S1_IPV4,  0, S1_CLNP,
2448          CL_REG, 0x000,  0, 0x0, 0x0000},
2449        { "IPV4?", 0xffff, 0x0800, OP_EQ,  1, S1_IPV4c, 0, S1_IPV6,
2450          LD_SAP, 0x100,  3, 0x0, 0xffff},
2451        { "IPV4 cont?", 0xff00, 0x4500, OP_EQ,  3, S1_IPV4F, 0, S1_CLNP,
2452          LD_SUM, 0x00a,  1, 0x0, 0x0000},
2453        { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ,  1, S1_TCP44, 0, S1_CLNP,
2454          LD_LEN, 0x03e,  1, 0x0, 0xffff},
2455        { "TCP44?", 0x00ff, 0x0006, OP_EQ,  7, S1_TCPSQ, 0, S1_ESP4,
2456          LD_FID, 0x182,  1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
2457        { "IPV6?", 0xffff, 0x86dd, OP_EQ,  1, S1_IPV6L, 0, S1_CLNP,
2458          LD_SUM, 0x015,  1, 0x0, 0x0000},
2459        { "IPV6 len", 0xf000, 0x6000, OP_EQ,  0, S1_IPV6c, 0, S1_CLNP,
2460          IM_R1,  0x128,  1, 0x0, 0xffff},
2461        { "IPV6 cont?", 0x0000, 0x0000, OP_EQ,  3, S1_TCP64, 0, S1_CLNP,
2462          LD_FID, 0x484,  1, 0x0, 0xffff}, /*  FID IP6&TCP src+dst */
2463        { "TCP64?",
2464#if 0
2465//@@@0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_ESP6,  LD_LEN, 0x03f,  1, 0x0, 0xffff,
2466#endif
2467          0xff00, 0x0600, OP_EQ, 12, S1_TCPSQ, 0, S1_ESP6,  LD_LEN,
2468          0x03f,  1, 0x0, 0xffff},
2469        { "TCP seq", /* 14:DADDR should point to dest port */
2470          0xFFFF, 0x0080, OP_EQ,  0, S2_HTTP,  0, S1_TCPFG, LD_SEQ,
2471          0x081,  3, 0x0, 0xffff}, /* Load TCP seq # */
2472        { "TCP control flags", 0xFFFF, 0x8080, OP_EQ,  0, S2_HTTP,  0,
2473          S1_TCPHL, ST_FLG, 0x145,  2, 0x0, 0x002f}, /* Load TCP flags */
2474        { "TCP length", 0x0000, 0x0000, OP_EQ,  0, S1_TCPHc, 0, S1_TCPHc,
2475          LD_R1,  0x205,  3, 0xB, 0xf000} ,
2476        { "TCP length cont", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0,
2477          S1_PCKT,  LD_HDR, 0x0ff,  3, 0x0, 0xffff},
2478        { "Cleanup", 0x0000, 0x0000, OP_EQ,  0, S1_CLNP2,  0, S1_CLNP2,
2479          IM_CTL, 0x001,  3, 0x0, 0x0001},
2480        { "Cleanup 2", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0, S1_PCKT,
2481          CL_REG, 0x002,  3, 0x0, 0x0000},
2482        { "Drop packet", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0, S1_PCKT,
2483          IM_CTL, 0x080,  3, 0x0, 0xffff},
2484        { "No HTTP", 0x0000, 0x0000, OP_EQ,  0, S1_PCKT,  0, S1_PCKT,
2485          IM_CTL, 0x044,  3, 0x0, 0xffff},
2486        { "IPV4 ESP encrypted?",  /* S1_ESP4 */
2487          0x00ff, 0x0032, OP_EQ,  0, S1_CLNP2, 0, S1_AH4, IM_CTL,
2488          0x021, 1,  0x0, 0xffff},
2489        { "IPV4 AH encrypted?",   /* S1_AH4 */
2490          0x00ff, 0x0033, OP_EQ,  0, S1_CLNP2, 0, S1_CLNP, IM_CTL,
2491          0x021, 1,  0x0, 0xffff},
2492        { "IPV6 ESP encrypted?",  /* S1_ESP6 */
2493#if 0
2494//@@@0x00ff, 0x0032, OP_EQ,  0, S1_CLNP2, 0, S1_AH6, IM_CTL, 0x021, 1,  0x0, 0xffff,
2495#endif
2496          0xff00, 0x3200, OP_EQ,  0, S1_CLNP2, 0, S1_AH6, IM_CTL,
2497          0x021, 1,  0x0, 0xffff},
2498        { "IPV6 AH encrypted?",   /* S1_AH6 */
2499#if 0
2500//@@@0x00ff, 0x0033, OP_EQ,  0, S1_CLNP2, 0, S1_CLNP, IM_CTL, 0x021, 1,  0x0, 0xffff,
2501#endif
2502          0xff00, 0x3300, OP_EQ,  0, S1_CLNP2, 0, S1_CLNP, IM_CTL,
2503          0x021, 1,  0x0, 0xffff},
2504        { NULL },
2505};
2506#ifdef HP_ENCRYPT_DEFAULT
2507#define CAS_HP_FIRMWARE               cas_prog_encryptiontab
2508#endif
2509#endif
2510
2511static cas_hp_inst_t cas_prog_null[] = { {NULL} };
2512#ifdef HP_NULL_DEFAULT
2513#define CAS_HP_FIRMWARE               cas_prog_null
2514#endif
2515
2516/* phy types */
2517#define   CAS_PHY_UNKNOWN       0x00
2518#define   CAS_PHY_SERDES        0x01
2519#define   CAS_PHY_MII_MDIO0     0x02
2520#define   CAS_PHY_MII_MDIO1     0x04
2521#define   CAS_PHY_MII(x)        ((x) & (CAS_PHY_MII_MDIO0 | CAS_PHY_MII_MDIO1))
2522
2523/* _RING_INDEX is the index for the ring sizes to be used.  _RING_SIZE
2524 * is the actual size. the default index for the various rings is
2525 * 8. NOTE: there a bunch of alignment constraints for the rings. to
2526 * deal with that, i just allocate rings to create the desired
2527 * alignment. here are the constraints:
2528 *   RX DESC and COMP rings must be 8KB aligned
2529 *   TX DESC must be 2KB aligned.
2530 * if you change the numbers, be cognizant of how the alignment will change
2531 * in INIT_BLOCK as well.
2532 */
2533
2534#define DESC_RING_I_TO_S(x)  (32*(1 << (x)))
2535#define COMP_RING_I_TO_S(x)  (128*(1 << (x)))
2536#define TX_DESC_RING_INDEX 4  /* 512 = 8k */
2537#define RX_DESC_RING_INDEX 4  /* 512 = 8k */
2538#define RX_COMP_RING_INDEX 4  /* 2048 = 64k: should be 4x rx ring size */
2539
2540#if (TX_DESC_RING_INDEX > 8) || (TX_DESC_RING_INDEX < 0)
2541#error TX_DESC_RING_INDEX must be between 0 and 8
2542#endif
2543
2544#if (RX_DESC_RING_INDEX > 8) || (RX_DESC_RING_INDEX < 0)
2545#error RX_DESC_RING_INDEX must be between 0 and 8
2546#endif
2547
2548#if (RX_COMP_RING_INDEX > 8) || (RX_COMP_RING_INDEX < 0)
2549#error RX_COMP_RING_INDEX must be between 0 and 8
2550#endif
2551
2552#define N_TX_RINGS                    MAX_TX_RINGS      /* for QoS */
2553#define N_TX_RINGS_MASK               MAX_TX_RINGS_MASK
2554#define N_RX_DESC_RINGS               MAX_RX_DESC_RINGS /* 1 for ipsec */
2555#define N_RX_COMP_RINGS               0x1 /* for mult. PCI interrupts */
2556
2557/* number of flows that can go through re-assembly */
2558#define N_RX_FLOWS                    64
2559
2560#define TX_DESC_RING_SIZE  DESC_RING_I_TO_S(TX_DESC_RING_INDEX)
2561#define RX_DESC_RING_SIZE  DESC_RING_I_TO_S(RX_DESC_RING_INDEX)
2562#define RX_COMP_RING_SIZE  COMP_RING_I_TO_S(RX_COMP_RING_INDEX)
2563#define TX_DESC_RINGN_INDEX(x) TX_DESC_RING_INDEX
2564#define RX_DESC_RINGN_INDEX(x) RX_DESC_RING_INDEX
2565#define RX_COMP_RINGN_INDEX(x) RX_COMP_RING_INDEX
2566#define TX_DESC_RINGN_SIZE(x)  TX_DESC_RING_SIZE
2567#define RX_DESC_RINGN_SIZE(x)  RX_DESC_RING_SIZE
2568#define RX_COMP_RINGN_SIZE(x)  RX_COMP_RING_SIZE
2569
2570/* convert values */
2571#define CAS_BASE(x, y)                (((y) << (x ## _SHIFT)) & (x ## _MASK))
2572#define CAS_VAL(x, y)                 (((y) & (x ## _MASK)) >> (x ## _SHIFT))
2573#define CAS_TX_RINGN_BASE(y)          ((TX_DESC_RINGN_INDEX(y) << \
2574                                        TX_CFG_DESC_RINGN_SHIFT(y)) & \
2575                                        TX_CFG_DESC_RINGN_MASK(y))
2576
2577/* min is 2k, but we can't do jumbo frames unless it's at least 8k */
2578#define CAS_MIN_PAGE_SHIFT            11 /* 2048 */
2579#define CAS_JUMBO_PAGE_SHIFT          13 /* 8192 */
2580#define CAS_MAX_PAGE_SHIFT            14 /* 16384 */
2581
2582#define TX_DESC_BUFLEN_MASK         0x0000000000003FFFULL /* buffer length in
2583                                                             bytes. 0 - 9256 */
2584#define TX_DESC_BUFLEN_SHIFT        0
2585#define TX_DESC_CSUM_START_MASK     0x00000000001F8000ULL /* checksum start. #
2586                                                             of bytes to be
2587                                                             skipped before
2588                                                             csum calc begins.
2589                                                             value must be
2590                                                             even */
2591#define TX_DESC_CSUM_START_SHIFT    15
2592#define TX_DESC_CSUM_STUFF_MASK     0x000000001FE00000ULL /* checksum stuff.
2593                                                             byte offset w/in
2594                                                             the pkt for the
2595                                                             1st csum byte.
2596                                                             must be > 8 */
2597#define TX_DESC_CSUM_STUFF_SHIFT    21
2598#define TX_DESC_CSUM_EN             0x0000000020000000ULL /* enable checksum */
2599#define TX_DESC_EOF                 0x0000000040000000ULL /* end of frame */
2600#define TX_DESC_SOF                 0x0000000080000000ULL /* start of frame */
2601#define TX_DESC_INTME               0x0000000100000000ULL /* interrupt me */
2602#define TX_DESC_NO_CRC              0x0000000200000000ULL /* debugging only.
2603                                                             CRC will not be
2604                                                             inserted into
2605                                                             outgoing frame. */
2606struct cas_tx_desc {
2607        __le64     control;
2608        __le64     buffer;
2609};
2610
2611/* descriptor ring for free buffers contains page-sized buffers. the index
2612 * value is not used by the hw in any way. it's just stored and returned in
2613 * the completion ring.
2614 */
2615struct cas_rx_desc {
2616        __le64     index;
2617        __le64     buffer;
2618};
2619
2620/* received packets are put on the completion ring. */
2621/* word 1 */
2622#define RX_COMP1_DATA_SIZE_MASK           0x0000000007FFE000ULL
2623#define RX_COMP1_DATA_SIZE_SHIFT          13
2624#define RX_COMP1_DATA_OFF_MASK            0x000001FFF8000000ULL
2625#define RX_COMP1_DATA_OFF_SHIFT           27
2626#define RX_COMP1_DATA_INDEX_MASK          0x007FFE0000000000ULL
2627#define RX_COMP1_DATA_INDEX_SHIFT         41
2628#define RX_COMP1_SKIP_MASK                0x0180000000000000ULL
2629#define RX_COMP1_SKIP_SHIFT               55
2630#define RX_COMP1_RELEASE_NEXT             0x0200000000000000ULL
2631#define RX_COMP1_SPLIT_PKT                0x0400000000000000ULL
2632#define RX_COMP1_RELEASE_FLOW             0x0800000000000000ULL
2633#define RX_COMP1_RELEASE_DATA             0x1000000000000000ULL
2634#define RX_COMP1_RELEASE_HDR              0x2000000000000000ULL
2635#define RX_COMP1_TYPE_MASK                0xC000000000000000ULL
2636#define RX_COMP1_TYPE_SHIFT               62
2637
2638/* word 2 */
2639#define RX_COMP2_NEXT_INDEX_MASK          0x00000007FFE00000ULL
2640#define RX_COMP2_NEXT_INDEX_SHIFT         21
2641#define RX_COMP2_HDR_SIZE_MASK            0x00000FF800000000ULL
2642#define RX_COMP2_HDR_SIZE_SHIFT           35
2643#define RX_COMP2_HDR_OFF_MASK             0x0003F00000000000ULL
2644#define RX_COMP2_HDR_OFF_SHIFT            44
2645#define RX_COMP2_HDR_INDEX_MASK           0xFFFC000000000000ULL
2646#define RX_COMP2_HDR_INDEX_SHIFT          50
2647
2648/* word 3 */
2649#define RX_COMP3_SMALL_PKT                0x0000000000000001ULL
2650#define RX_COMP3_JUMBO_PKT                0x0000000000000002ULL
2651#define RX_COMP3_JUMBO_HDR_SPLIT_EN       0x0000000000000004ULL
2652#define RX_COMP3_CSUM_START_MASK          0x000000000007F000ULL
2653#define RX_COMP3_CSUM_START_SHIFT         12
2654#define RX_COMP3_FLOWID_MASK              0x0000000001F80000ULL
2655#define RX_COMP3_FLOWID_SHIFT             19
2656#define RX_COMP3_OPCODE_MASK              0x000000000E000000ULL
2657#define RX_COMP3_OPCODE_SHIFT             25
2658#define RX_COMP3_FORCE_FLAG               0x0000000010000000ULL
2659#define RX_COMP3_NO_ASSIST                0x0000000020000000ULL
2660#define RX_COMP3_LOAD_BAL_MASK            0x000001F800000000ULL
2661#define RX_COMP3_LOAD_BAL_SHIFT           35
2662#define RX_PLUS_COMP3_ENC_PKT             0x0000020000000000ULL /* cas+ */
2663#define RX_COMP3_L3_HEAD_OFF_MASK         0x0000FE0000000000ULL /* cas */
2664#define RX_COMP3_L3_HEAD_OFF_SHIFT        41
2665#define RX_PLUS_COMP_L3_HEAD_OFF_MASK     0x0000FC0000000000ULL /* cas+ */
2666#define RX_PLUS_COMP_L3_HEAD_OFF_SHIFT    42
2667#define RX_COMP3_SAP_MASK                 0xFFFF000000000000ULL
2668#define RX_COMP3_SAP_SHIFT                48
2669
2670/* word 4 */
2671#define RX_COMP4_TCP_CSUM_MASK            0x000000000000FFFFULL
2672#define RX_COMP4_TCP_CSUM_SHIFT           0
2673#define RX_COMP4_PKT_LEN_MASK             0x000000003FFF0000ULL
2674#define RX_COMP4_PKT_LEN_SHIFT            16
2675#define RX_COMP4_PERFECT_MATCH_MASK       0x00000003C0000000ULL
2676#define RX_COMP4_PERFECT_MATCH_SHIFT      30
2677#define RX_COMP4_ZERO                     0x0000080000000000ULL
2678#define RX_COMP4_HASH_VAL_MASK            0x0FFFF00000000000ULL
2679#define RX_COMP4_HASH_VAL_SHIFT           44
2680#define RX_COMP4_HASH_PASS                0x1000000000000000ULL
2681#define RX_COMP4_BAD                      0x4000000000000000ULL
2682#define RX_COMP4_LEN_MISMATCH             0x8000000000000000ULL
2683
2684/* we encode the following: ring/index/release. only 14 bits
2685 * are usable.
2686 * NOTE: the encoding is dependent upon RX_DESC_RING_SIZE and
2687 *       MAX_RX_DESC_RINGS. */
2688#define RX_INDEX_NUM_MASK                 0x0000000000000FFFULL
2689#define RX_INDEX_NUM_SHIFT                0
2690#define RX_INDEX_RING_MASK                0x0000000000001000ULL
2691#define RX_INDEX_RING_SHIFT               12
2692#define RX_INDEX_RELEASE                  0x0000000000002000ULL
2693
2694struct cas_rx_comp {
2695        __le64     word1;
2696        __le64     word2;
2697        __le64     word3;
2698        __le64     word4;
2699};
2700
2701enum link_state {
2702        link_down = 0,  /* No link, will retry */
2703        link_aneg,      /* Autoneg in progress */
2704        link_force_try, /* Try Forced link speed */
2705        link_force_ret, /* Forced mode worked, retrying autoneg */
2706        link_force_ok,  /* Stay in forced mode */
2707        link_up         /* Link is up */
2708};
2709
2710typedef struct cas_page {
2711        struct list_head list;
2712        struct page *buffer;
2713        dma_addr_t dma_addr;
2714        int used;
2715} cas_page_t;
2716
2717
2718/* some alignment constraints:
2719 * TX DESC, RX DESC, and RX COMP must each be 8K aligned.
2720 * TX COMPWB must be 8-byte aligned.
2721 * to accomplish this, here's what we do:
2722 *
2723 * INIT_BLOCK_RX_COMP  = 64k (already aligned)
2724 * INIT_BLOCK_RX_DESC  = 8k
2725 * INIT_BLOCK_TX       = 8k
2726 * INIT_BLOCK_RX1_DESC = 8k
2727 * TX COMPWB
2728 */
2729#define INIT_BLOCK_TX           (TX_DESC_RING_SIZE)
2730#define INIT_BLOCK_RX_DESC      (RX_DESC_RING_SIZE)
2731#define INIT_BLOCK_RX_COMP      (RX_COMP_RING_SIZE)
2732
2733struct cas_init_block {
2734        struct cas_rx_comp rxcs[N_RX_COMP_RINGS][INIT_BLOCK_RX_COMP];
2735        struct cas_rx_desc rxds[N_RX_DESC_RINGS][INIT_BLOCK_RX_DESC];
2736        struct cas_tx_desc txds[N_TX_RINGS][INIT_BLOCK_TX];
2737        __le64 tx_compwb;
2738};
2739
2740/* tiny buffers to deal with target abort issue. we allocate a bit
2741 * over so that we don't have target abort issues with these buffers
2742 * as well.
2743 */
2744#define TX_TINY_BUF_LEN    0x100
2745#define TX_TINY_BUF_BLOCK  ((INIT_BLOCK_TX + 1)*TX_TINY_BUF_LEN)
2746
2747struct cas_tiny_count {
2748        int nbufs;
2749        int used;
2750};
2751
2752struct cas {
2753        spinlock_t lock; /* for most bits */
2754        spinlock_t tx_lock[N_TX_RINGS]; /* tx bits */
2755        spinlock_t stat_lock[N_TX_RINGS + 1]; /* for stat gathering */
2756        spinlock_t rx_inuse_lock; /* rx inuse list */
2757        spinlock_t rx_spare_lock; /* rx spare list */
2758
2759        void __iomem *regs;
2760        int tx_new[N_TX_RINGS], tx_old[N_TX_RINGS];
2761        int rx_old[N_RX_DESC_RINGS];
2762        int rx_cur[N_RX_COMP_RINGS], rx_new[N_RX_COMP_RINGS];
2763        int rx_last[N_RX_DESC_RINGS];
2764
2765        struct napi_struct napi;
2766
2767        /* Set when chip is actually in operational state
2768         * (ie. not power managed) */
2769        int hw_running;
2770        int opened;
2771        struct mutex pm_mutex; /* open/close/suspend/resume */
2772
2773        struct cas_init_block *init_block;
2774        struct cas_tx_desc *init_txds[MAX_TX_RINGS];
2775        struct cas_rx_desc *init_rxds[MAX_RX_DESC_RINGS];
2776        struct cas_rx_comp *init_rxcs[MAX_RX_COMP_RINGS];
2777
2778        /* we use sk_buffs for tx and pages for rx. the rx skbuffs
2779         * are there for flow re-assembly. */
2780        struct sk_buff      *tx_skbs[N_TX_RINGS][TX_DESC_RING_SIZE];
2781        struct sk_buff_head  rx_flows[N_RX_FLOWS];
2782        cas_page_t          *rx_pages[N_RX_DESC_RINGS][RX_DESC_RING_SIZE];
2783        struct list_head     rx_spare_list, rx_inuse_list;
2784        int                  rx_spares_needed;
2785
2786        /* for small packets when copying would be quicker than
2787           mapping */
2788        struct cas_tiny_count tx_tiny_use[N_TX_RINGS][TX_DESC_RING_SIZE];
2789        u8 *tx_tiny_bufs[N_TX_RINGS];
2790
2791        u32                     msg_enable;
2792
2793        /* N_TX_RINGS must be >= N_RX_DESC_RINGS */
2794        struct net_device_stats net_stats[N_TX_RINGS + 1];
2795
2796        u32                     pci_cfg[64 >> 2];
2797        u8                      pci_revision;
2798
2799        int                     phy_type;
2800        int                     phy_addr;
2801        u32                     phy_id;
2802#define CAS_FLAG_1000MB_CAP     0x00000001
2803#define CAS_FLAG_REG_PLUS       0x00000002
2804#define CAS_FLAG_TARGET_ABORT   0x00000004
2805#define CAS_FLAG_SATURN         0x00000008
2806#define CAS_FLAG_RXD_POST_MASK  0x000000F0
2807#define CAS_FLAG_RXD_POST_SHIFT 4
2808#define CAS_FLAG_RXD_POST(x)    ((1 << (CAS_FLAG_RXD_POST_SHIFT + (x))) & \
2809                                 CAS_FLAG_RXD_POST_MASK)
2810#define CAS_FLAG_ENTROPY_DEV    0x00000100
2811#define CAS_FLAG_NO_HW_CSUM     0x00000200
2812        u32                     cas_flags;
2813        int                     packet_min; /* minimum packet size */
2814        int                     tx_fifo_size;
2815        int                     rx_fifo_size;
2816        int                     rx_pause_off;
2817        int                     rx_pause_on;
2818        int                     crc_size;      /* 4 if half-duplex */
2819
2820        int                     pci_irq_INTC;
2821        int                     min_frame_size; /* for tx fifo workaround */
2822
2823        /* page size allocation */
2824        int                     page_size;
2825        int                     page_order;
2826        int                     mtu_stride;
2827
2828        u32                     mac_rx_cfg;
2829
2830        /* Autoneg & PHY control */
2831        int                     link_cntl;
2832        int                     link_fcntl;
2833        enum link_state         lstate;
2834        struct timer_list       link_timer;
2835        int                     timer_ticks;
2836        struct work_struct      reset_task;
2837#if 0
2838        atomic_t                reset_task_pending;
2839#else
2840        atomic_t                reset_task_pending;
2841        atomic_t                reset_task_pending_mtu;
2842        atomic_t                reset_task_pending_spare;
2843        atomic_t                reset_task_pending_all;
2844#endif
2845
2846        /* Link-down problem workaround */
2847#define LINK_TRANSITION_UNKNOWN         0
2848#define LINK_TRANSITION_ON_FAILURE      1
2849#define LINK_TRANSITION_STILL_FAILED    2
2850#define LINK_TRANSITION_LINK_UP         3
2851#define LINK_TRANSITION_LINK_CONFIG     4
2852#define LINK_TRANSITION_LINK_DOWN       5
2853#define LINK_TRANSITION_REQUESTED_RESET 6
2854        int                     link_transition;
2855        int                     link_transition_jiffies_valid;
2856        unsigned long           link_transition_jiffies;
2857
2858        /* Tuning */
2859        u8 orig_cacheline_size; /* value when loaded */
2860#define CAS_PREF_CACHELINE_SIZE  0x20   /* Minimum desired */
2861
2862        /* Diagnostic counters and state. */
2863        int                     casreg_len; /* reg-space size for dumping */
2864        u64                     pause_entered;
2865        u16                     pause_last_time_recvd;
2866
2867        dma_addr_t block_dvma, tx_tiny_dvma[N_TX_RINGS];
2868        struct pci_dev *pdev;
2869        struct net_device *dev;
2870#if defined(CONFIG_OF)
2871        struct device_node      *of_node;
2872#endif
2873
2874        /* Firmware Info */
2875        u16                     fw_load_addr;
2876        u32                     fw_size;
2877        u8                      *fw_data;
2878};
2879
2880#define TX_DESC_NEXT(r, x)  (((x) + 1) & (TX_DESC_RINGN_SIZE(r) - 1))
2881#define RX_DESC_ENTRY(r, x) ((x) & (RX_DESC_RINGN_SIZE(r) - 1))
2882#define RX_COMP_ENTRY(r, x) ((x) & (RX_COMP_RINGN_SIZE(r) - 1))
2883
2884#define TX_BUFF_COUNT(r, x, y)    ((x) <= (y) ? ((y) - (x)) : \
2885        (TX_DESC_RINGN_SIZE(r) - (x) + (y)))
2886
2887#define TX_BUFFS_AVAIL(cp, i)   ((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \
2888        (cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \
2889        (cp)->tx_old[(i)] - (cp)->tx_new[(i)] - 1)
2890
2891#define CAS_ALIGN(addr, align) \
2892     (((unsigned long) (addr) + ((align) - 1UL)) & ~((align) - 1))
2893
2894#define RX_FIFO_SIZE                  16384
2895#define EXPANSION_ROM_SIZE            65536
2896
2897#define CAS_MC_EXACT_MATCH_SIZE       15
2898#define CAS_MC_HASH_SIZE              256
2899#define CAS_MC_HASH_MAX              (CAS_MC_EXACT_MATCH_SIZE + \
2900                                      CAS_MC_HASH_SIZE)
2901
2902#define TX_TARGET_ABORT_LEN           0x20
2903#define RX_SWIVEL_OFF_VAL             0x2
2904#define RX_AE_FREEN_VAL(x)            (RX_DESC_RINGN_SIZE(x) >> 1)
2905#define RX_AE_COMP_VAL                (RX_COMP_RING_SIZE >> 1)
2906#define RX_BLANK_INTR_PKT_VAL         0x05
2907#define RX_BLANK_INTR_TIME_VAL        0x0F
2908#define HP_TCP_THRESH_VAL             1530 /* reduce to enable reassembly */
2909
2910#define RX_SPARE_COUNT                (RX_DESC_RING_SIZE >> 1)
2911#define RX_SPARE_RECOVER_VAL          (RX_SPARE_COUNT >> 2)
2912
2913#endif /* _CASSINI_H */
2914