1/****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright (C) 2018 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34 * Copyright (C) 2018 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64#ifndef __iwl_fw_api_debug_h__ 65#define __iwl_fw_api_debug_h__ 66 67/** 68 * enum iwl_debug_cmds - debug commands 69 */ 70enum iwl_debug_cmds { 71 /** 72 * @LMAC_RD_WR: 73 * LMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and 74 * &struct iwl_dbg_mem_access_rsp 75 */ 76 LMAC_RD_WR = 0x0, 77 /** 78 * @UMAC_RD_WR: 79 * UMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and 80 * &struct iwl_dbg_mem_access_rsp 81 */ 82 UMAC_RD_WR = 0x1, 83 /** 84 * @MFU_ASSERT_DUMP_NTF: 85 * &struct iwl_mfu_assert_dump_notif 86 */ 87 MFU_ASSERT_DUMP_NTF = 0xFE, 88}; 89 90/* Error response/notification */ 91enum { 92 FW_ERR_UNKNOWN_CMD = 0x0, 93 FW_ERR_INVALID_CMD_PARAM = 0x1, 94 FW_ERR_SERVICE = 0x2, 95 FW_ERR_ARC_MEMORY = 0x3, 96 FW_ERR_ARC_CODE = 0x4, 97 FW_ERR_WATCH_DOG = 0x5, 98 FW_ERR_WEP_GRP_KEY_INDX = 0x10, 99 FW_ERR_WEP_KEY_SIZE = 0x11, 100 FW_ERR_OBSOLETE_FUNC = 0x12, 101 FW_ERR_UNEXPECTED = 0xFE, 102 FW_ERR_FATAL = 0xFF 103}; 104 105/** 106 * struct iwl_error_resp - FW error indication 107 * ( REPLY_ERROR = 0x2 ) 108 * @error_type: one of FW_ERR_* 109 * @cmd_id: the command ID for which the error occurred 110 * @reserved1: reserved 111 * @bad_cmd_seq_num: sequence number of the erroneous command 112 * @error_service: which service created the error, applicable only if 113 * error_type = 2, otherwise 0 114 * @timestamp: TSF in usecs. 115 */ 116struct iwl_error_resp { 117 __le32 error_type; 118 u8 cmd_id; 119 u8 reserved1; 120 __le16 bad_cmd_seq_num; 121 __le32 error_service; 122 __le64 timestamp; 123} __packed; 124 125#define TX_FIFO_MAX_NUM_9000 8 126#define TX_FIFO_MAX_NUM 15 127#define RX_FIFO_MAX_NUM 2 128#define TX_FIFO_INTERNAL_MAX_NUM 6 129 130/** 131 * struct iwl_shared_mem_cfg_v2 - Shared memory configuration information 132 * 133 * @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not 134 * accessible) 135 * @shared_mem_size: shared memory size 136 * @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to 137 * 0x0 as accessible only via DBGM RDAT) 138 * @sample_buff_size: internal sample buff size 139 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre 140 * 8000 HW set to 0x0 as not accessible) 141 * @txfifo_size: size of TXF0 ... TXF7 142 * @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0 143 * @page_buff_addr: used by UMAC and performance debug (page miss analysis), 144 * when paging is not supported this should be 0 145 * @page_buff_size: size of %page_buff_addr 146 * @rxfifo_addr: Start address of rxFifo 147 * @internal_txfifo_addr: start address of internalFifo 148 * @internal_txfifo_size: internal fifos' size 149 * 150 * NOTE: on firmware that don't have IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 151 * set, the last 3 members don't exist. 152 */ 153struct iwl_shared_mem_cfg_v2 { 154 __le32 shared_mem_addr; 155 __le32 shared_mem_size; 156 __le32 sample_buff_addr; 157 __le32 sample_buff_size; 158 __le32 txfifo_addr; 159 __le32 txfifo_size[TX_FIFO_MAX_NUM_9000]; 160 __le32 rxfifo_size[RX_FIFO_MAX_NUM]; 161 __le32 page_buff_addr; 162 __le32 page_buff_size; 163 __le32 rxfifo_addr; 164 __le32 internal_txfifo_addr; 165 __le32 internal_txfifo_size[TX_FIFO_INTERNAL_MAX_NUM]; 166} __packed; /* SHARED_MEM_ALLOC_API_S_VER_2 */ 167 168/** 169 * struct iwl_shared_mem_lmac_cfg - LMAC shared memory configuration 170 * 171 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB) 172 * @txfifo_size: size of TX FIFOs 173 * @rxfifo1_addr: RXF1 addr 174 * @rxfifo1_size: RXF1 size 175 */ 176struct iwl_shared_mem_lmac_cfg { 177 __le32 txfifo_addr; 178 __le32 txfifo_size[TX_FIFO_MAX_NUM]; 179 __le32 rxfifo1_addr; 180 __le32 rxfifo1_size; 181 182} __packed; /* SHARED_MEM_ALLOC_LMAC_API_S_VER_1 */ 183 184/** 185 * struct iwl_shared_mem_cfg - Shared memory configuration information 186 * 187 * @shared_mem_addr: shared memory address 188 * @shared_mem_size: shared memory size 189 * @sample_buff_addr: internal sample (mon/adc) buff addr 190 * @sample_buff_size: internal sample buff size 191 * @rxfifo2_addr: start addr of RXF2 192 * @rxfifo2_size: size of RXF2 193 * @page_buff_addr: used by UMAC and performance debug (page miss analysis), 194 * when paging is not supported this should be 0 195 * @page_buff_size: size of %page_buff_addr 196 * @lmac_num: number of LMACs (1 or 2) 197 * @lmac_smem: per - LMAC smem data 198 */ 199struct iwl_shared_mem_cfg { 200 __le32 shared_mem_addr; 201 __le32 shared_mem_size; 202 __le32 sample_buff_addr; 203 __le32 sample_buff_size; 204 __le32 rxfifo2_addr; 205 __le32 rxfifo2_size; 206 __le32 page_buff_addr; 207 __le32 page_buff_size; 208 __le32 lmac_num; 209 struct iwl_shared_mem_lmac_cfg lmac_smem[2]; 210} __packed; /* SHARED_MEM_ALLOC_API_S_VER_3 */ 211 212/** 213 * struct iwl_mfuart_load_notif - mfuart image version & status 214 * ( MFUART_LOAD_NOTIFICATION = 0xb1 ) 215 * @installed_ver: installed image version 216 * @external_ver: external image version 217 * @status: MFUART loading status 218 * @duration: MFUART loading time 219 * @image_size: MFUART image size in bytes 220*/ 221struct iwl_mfuart_load_notif { 222 __le32 installed_ver; 223 __le32 external_ver; 224 __le32 status; 225 __le32 duration; 226 /* image size valid only in v2 of the command */ 227 __le32 image_size; 228} __packed; /* MFU_LOADER_NTFY_API_S_VER_2 */ 229 230/** 231 * struct iwl_mfu_assert_dump_notif - mfuart dump logs 232 * ( MFU_ASSERT_DUMP_NTF = 0xfe ) 233 * @assert_id: mfuart assert id that cause the notif 234 * @curr_reset_num: number of asserts since uptime 235 * @index_num: current chunk id 236 * @parts_num: total number of chunks 237 * @data_size: number of data bytes sent 238 * @data: data buffer 239 */ 240struct iwl_mfu_assert_dump_notif { 241 __le32 assert_id; 242 __le32 curr_reset_num; 243 __le16 index_num; 244 __le16 parts_num; 245 __le32 data_size; 246 __le32 data[0]; 247} __packed; /* MFU_DUMP_ASSERT_API_S_VER_1 */ 248 249/** 250 * enum iwl_mvm_marker_id - marker ids 251 * 252 * The ids for different type of markers to insert into the usniffer logs 253 * 254 * @MARKER_ID_TX_FRAME_LATENCY: TX latency marker 255 * @MARKER_ID_SYNC_CLOCK: sync FW time and systime 256 */ 257enum iwl_mvm_marker_id { 258 MARKER_ID_TX_FRAME_LATENCY = 1, 259 MARKER_ID_SYNC_CLOCK = 2, 260}; /* MARKER_ID_API_E_VER_2 */ 261 262/** 263 * struct iwl_mvm_marker - mark info into the usniffer logs 264 * 265 * (MARKER_CMD = 0xcb) 266 * 267 * Mark the UTC time stamp into the usniffer logs together with additional 268 * metadata, so the usniffer output can be parsed. 269 * In the command response the ucode will return the GP2 time. 270 * 271 * @dw_len: The amount of dwords following this byte including this byte. 272 * @marker_id: A unique marker id (iwl_mvm_marker_id). 273 * @reserved: reserved. 274 * @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC 275 * @metadata: additional meta data that will be written to the unsiffer log 276 */ 277struct iwl_mvm_marker { 278 u8 dw_len; 279 u8 marker_id; 280 __le16 reserved; 281 __le64 timestamp; 282 __le32 metadata[0]; 283} __packed; /* MARKER_API_S_VER_1 */ 284 285/** 286 * struct iwl_mvm_marker_rsp - Response to marker cmd 287 * 288 * @gp2: The gp2 clock value in the FW 289 */ 290struct iwl_mvm_marker_rsp { 291 __le32 gp2; 292} __packed; 293 294/* Operation types for the debug mem access */ 295enum { 296 DEBUG_MEM_OP_READ = 0, 297 DEBUG_MEM_OP_WRITE = 1, 298 DEBUG_MEM_OP_WRITE_BYTES = 2, 299}; 300 301#define DEBUG_MEM_MAX_SIZE_DWORDS 32 302 303/** 304 * struct iwl_dbg_mem_access_cmd - Request the device to read/write memory 305 * @op: DEBUG_MEM_OP_* 306 * @addr: address to read/write from/to 307 * @len: in dwords, to read/write 308 * @data: for write opeations, contains the source buffer 309 */ 310struct iwl_dbg_mem_access_cmd { 311 __le32 op; 312 __le32 addr; 313 __le32 len; 314 __le32 data[]; 315} __packed; /* DEBUG_(U|L)MAC_RD_WR_CMD_API_S_VER_1 */ 316 317/* Status responses for the debug mem access */ 318enum { 319 DEBUG_MEM_STATUS_SUCCESS = 0x0, 320 DEBUG_MEM_STATUS_FAILED = 0x1, 321 DEBUG_MEM_STATUS_LOCKED = 0x2, 322 DEBUG_MEM_STATUS_HIDDEN = 0x3, 323 DEBUG_MEM_STATUS_LENGTH = 0x4, 324}; 325 326/** 327 * struct iwl_dbg_mem_access_rsp - Response to debug mem commands 328 * @status: DEBUG_MEM_STATUS_* 329 * @len: read dwords (0 for write operations) 330 * @data: contains the read DWs 331 */ 332struct iwl_dbg_mem_access_rsp { 333 __le32 status; 334 __le32 len; 335 __le32 data[]; 336} __packed; /* DEBUG_(U|L)MAC_RD_WR_RSP_API_S_VER_1 */ 337 338#define LDBG_CFG_COMMAND_SIZE 80 339#define BUFFER_ALLOCATION 0x27 340#define START_DEBUG_RECORDING 0x29 341#define STOP_DEBUG_RECORDING 0x2A 342 343/* maximum fragments to be allocated per target of allocationId */ 344#define IWL_BUFFER_LOCATION_MAX_FRAGS 2 345 346/** 347 * struct iwl_fragment_data single fragment structure 348 * @address: 64bit start address 349 * @size: size in bytes 350 */ 351struct iwl_fragment_data { 352 __le64 address; 353 __le32 size; 354} __packed; /* FRAGMENT_STRUCTURE_API_S_VER_1 */ 355 356/** 357 * struct iwl_buffer_allocation_cmd - buffer allocation command structure 358 * @allocation_id: id of the allocation 359 * @buffer_location: location of the buffer 360 * @num_frags: number of fragments 361 * @fragments: memory fragments 362 */ 363struct iwl_buffer_allocation_cmd { 364 __le32 allocation_id; 365 __le32 buffer_location; 366 __le32 num_frags; 367 struct iwl_fragment_data fragments[IWL_BUFFER_LOCATION_MAX_FRAGS]; 368} __packed; /* BUFFER_ALLOCATION_CMD_API_S_VER_1 */ 369 370/** 371 * struct iwl_ldbg_config_cmd - LDBG config command 372 * @type: configuration type 373 * @pad: reserved space for type-dependent data 374 */ 375struct iwl_ldbg_config_cmd { 376 __le32 type; 377 union { 378 u8 pad[LDBG_CFG_COMMAND_SIZE - sizeof(__le32)]; 379 struct iwl_buffer_allocation_cmd buffer_allocation; 380 }; /* LDBG_CFG_BODY_API_U_VER_2 (partially) */ 381} __packed; /* LDBG_CFG_CMD_API_S_VER_2 */ 382 383#endif /* __iwl_fw_api_debug_h__ */ 384