1
2
3
4#include "../wifi.h"
5#include "../pci.h"
6#include "../ps.h"
7#include "../core.h"
8#include "reg.h"
9#include "def.h"
10#include "phy.h"
11#include "rf.h"
12#include "dm.h"
13#include "table.h"
14#include "sw.h"
15#include "hw.h"
16
17#define MAX_RF_IMR_INDEX 12
18#define MAX_RF_IMR_INDEX_NORMAL 13
19#define RF_REG_NUM_FOR_C_CUT_5G 6
20#define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA 7
21#define RF_REG_NUM_FOR_C_CUT_2G 5
22#define RF_CHNL_NUM_5G 19
23#define RF_CHNL_NUM_5G_40M 17
24#define TARGET_CHNL_NUM_5G 221
25#define TARGET_CHNL_NUM_2G 14
26#define CV_CURVE_CNT 64
27
28static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = {
29 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
30};
31
32static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = {
33 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6
34};
35
36static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
37 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8
38};
39
40static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
41 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
42};
43
44static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
45 BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1),
46 BIT(10) | BIT(9),
47 BIT(18) | BIT(17) | BIT(16) | BIT(1),
48 BIT(2) | BIT(1),
49 BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11)
50};
51
52static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = {
53 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108,
54 112, 116, 120, 124, 128, 132, 136, 140
55};
56
57static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = {
58 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114,
59 118, 122, 126, 130, 134, 138
60};
61static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = {
62 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
63 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
64 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
65 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
66 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
67};
68
69static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = {
70 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
71 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
72 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
73};
74
75static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
76
77static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
78 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
79 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
80 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
81};
82
83
84static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = {
85 {
86
87 {
88 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
89 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
90 },
91
92 {
93 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
94 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
95 0x32c9a
96 },
97
98 {
99 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
100 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
101 }
102 }
103};
104
105static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
106
107static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
108
109static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = {
110 25141, 25116, 25091, 25066, 25041,
111 25016, 24991, 24966, 24941, 24917,
112 24892, 24867, 24843, 24818, 24794,
113 24770, 24765, 24721, 24697, 24672,
114 24648, 24624, 24600, 24576, 24552,
115 24528, 24504, 24480, 24457, 24433,
116 24409, 24385, 24362, 24338, 24315,
117 24291, 24268, 24245, 24221, 24198,
118 24175, 24151, 24128, 24105, 24082,
119 24059, 24036, 24013, 23990, 23967,
120 23945, 23922, 23899, 23876, 23854,
121 23831, 23809, 23786, 23764, 23741,
122 23719, 23697, 23674, 23652, 23630,
123 23608, 23586, 23564, 23541, 23519,
124 23498, 23476, 23454, 23432, 23410,
125 23388, 23367, 23345, 23323, 23302,
126 23280, 23259, 23237, 23216, 23194,
127 23173, 23152, 23130, 23109, 23088,
128 23067, 23046, 23025, 23003, 22982,
129 22962, 22941, 22920, 22899, 22878,
130 22857, 22837, 22816, 22795, 22775,
131 22754, 22733, 22713, 22692, 22672,
132 22652, 22631, 22611, 22591, 22570,
133 22550, 22530, 22510, 22490, 22469,
134 22449, 22429, 22409, 22390, 22370,
135 22350, 22336, 22310, 22290, 22271,
136 22251, 22231, 22212, 22192, 22173,
137 22153, 22134, 22114, 22095, 22075,
138 22056, 22037, 22017, 21998, 21979,
139 21960, 21941, 21921, 21902, 21883,
140 21864, 21845, 21826, 21807, 21789,
141 21770, 21751, 21732, 21713, 21695,
142 21676, 21657, 21639, 21620, 21602,
143 21583, 21565, 21546, 21528, 21509,
144 21491, 21473, 21454, 21436, 21418,
145 21400, 21381, 21363, 21345, 21327,
146 21309, 21291, 21273, 21255, 21237,
147 21219, 21201, 21183, 21166, 21148,
148 21130, 21112, 21095, 21077, 21059,
149 21042, 21024, 21007, 20989, 20972,
150 25679, 25653, 25627, 25601, 25575,
151 25549, 25523, 25497, 25471, 25446,
152 25420, 25394, 25369, 25343, 25318,
153 25292, 25267, 25242, 25216, 25191,
154 25166
155};
156
157
158static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = {
159 26084, 26030, 25976, 25923, 25869, 25816, 25764,
160 25711, 25658, 25606, 25554, 25502, 25451, 25328
161};
162
163static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask)
164{
165 u32 i;
166
167 for (i = 0; i <= 31; i++) {
168 if (((bitmask >> i) & 0x1) == 1)
169 break;
170 }
171
172 return i;
173}
174
175u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
176{
177 struct rtl_priv *rtlpriv = rtl_priv(hw);
178 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
179 u32 returnvalue, originalvalue, bitshift;
180
181 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
182 regaddr, bitmask);
183 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) {
184 u8 dbi_direct = 0;
185
186
187
188 if (rtlhal->during_mac1init_radioa)
189 dbi_direct = BIT(3);
190 else if (rtlhal->during_mac0init_radiob)
191 dbi_direct = BIT(3) | BIT(2);
192 originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr,
193 dbi_direct);
194 } else {
195 originalvalue = rtl_read_dword(rtlpriv, regaddr);
196 }
197 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
198 returnvalue = (originalvalue & bitmask) >> bitshift;
199 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
200 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
201 bitmask, regaddr, originalvalue);
202 return returnvalue;
203}
204
205void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
206 u32 regaddr, u32 bitmask, u32 data)
207{
208 struct rtl_priv *rtlpriv = rtl_priv(hw);
209 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
210 u8 dbi_direct = 0;
211 u32 originalvalue, bitshift;
212
213 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
214 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
215 regaddr, bitmask, data);
216 if (rtlhal->during_mac1init_radioa)
217 dbi_direct = BIT(3);
218 else if (rtlhal->during_mac0init_radiob)
219
220 dbi_direct = BIT(3) | BIT(2);
221 if (bitmask != MASKDWORD) {
222 if (rtlhal->during_mac1init_radioa ||
223 rtlhal->during_mac0init_radiob)
224 originalvalue = rtl92de_read_dword_dbi(hw,
225 (u16) regaddr,
226 dbi_direct);
227 else
228 originalvalue = rtl_read_dword(rtlpriv, regaddr);
229 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
230 data = ((originalvalue & (~bitmask)) | (data << bitshift));
231 }
232 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob)
233 rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct);
234 else
235 rtl_write_dword(rtlpriv, regaddr, data);
236 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
237 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
238 regaddr, bitmask, data);
239}
240
241static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
242 enum radio_path rfpath, u32 offset)
243{
244
245 struct rtl_priv *rtlpriv = rtl_priv(hw);
246 struct rtl_phy *rtlphy = &(rtlpriv->phy);
247 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
248 u32 newoffset;
249 u32 tmplong, tmplong2;
250 u8 rfpi_enable = 0;
251 u32 retvalue;
252
253 newoffset = offset;
254 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
255 if (rfpath == RF90_PATH_A)
256 tmplong2 = tmplong;
257 else
258 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
259 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
260 (newoffset << 23) | BLSSIREADEDGE;
261 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
262 tmplong & (~BLSSIREADEDGE));
263 udelay(10);
264 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
265 udelay(50);
266 udelay(50);
267 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
268 tmplong | BLSSIREADEDGE);
269 udelay(10);
270 if (rfpath == RF90_PATH_A)
271 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
272 BIT(8));
273 else if (rfpath == RF90_PATH_B)
274 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
275 BIT(8));
276 if (rfpi_enable)
277 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
278 BLSSIREADBACKDATA);
279 else
280 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
281 BLSSIREADBACKDATA);
282 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n",
283 rfpath, pphyreg->rf_rb, retvalue);
284 return retvalue;
285}
286
287static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
288 enum radio_path rfpath,
289 u32 offset, u32 data)
290{
291 u32 data_and_addr;
292 u32 newoffset;
293 struct rtl_priv *rtlpriv = rtl_priv(hw);
294 struct rtl_phy *rtlphy = &(rtlpriv->phy);
295 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
296
297 newoffset = offset;
298
299 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
300 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
301 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
302 rfpath, pphyreg->rf3wire_offset, data_and_addr);
303}
304
305u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
306 enum radio_path rfpath, u32 regaddr, u32 bitmask)
307{
308 struct rtl_priv *rtlpriv = rtl_priv(hw);
309 u32 original_value, readback_value, bitshift;
310 unsigned long flags;
311
312 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
313 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
314 regaddr, rfpath, bitmask);
315 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
316 original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);
317 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
318 readback_value = (original_value & bitmask) >> bitshift;
319 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
320 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
321 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
322 regaddr, rfpath, bitmask, original_value);
323 return readback_value;
324}
325
326void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
327 u32 regaddr, u32 bitmask, u32 data)
328{
329 struct rtl_priv *rtlpriv = rtl_priv(hw);
330 struct rtl_phy *rtlphy = &(rtlpriv->phy);
331 u32 original_value, bitshift;
332 unsigned long flags;
333
334 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
335 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
336 regaddr, bitmask, data, rfpath);
337 if (bitmask == 0)
338 return;
339 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
340 if (rtlphy->rf_mode != RF_OP_BY_FW) {
341 if (bitmask != RFREG_OFFSET_MASK) {
342 original_value = _rtl92d_phy_rf_serial_read(hw,
343 rfpath, regaddr);
344 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
345 data = ((original_value & (~bitmask)) |
346 (data << bitshift));
347 }
348 _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);
349 }
350 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
351 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
352 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
353 regaddr, bitmask, data, rfpath);
354}
355
356bool rtl92d_phy_mac_config(struct ieee80211_hw *hw)
357{
358 struct rtl_priv *rtlpriv = rtl_priv(hw);
359 u32 i;
360 u32 arraylength;
361 u32 *ptrarray;
362
363 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
364 arraylength = MAC_2T_ARRAYLENGTH;
365 ptrarray = rtl8192de_mac_2tarray;
366 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n");
367 for (i = 0; i < arraylength; i = i + 2)
368 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
369 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
370
371
372
373
374 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B);
375 } else {
376
377 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07);
378 }
379 return true;
380}
381
382static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
383{
384 struct rtl_priv *rtlpriv = rtl_priv(hw);
385 struct rtl_phy *rtlphy = &(rtlpriv->phy);
386
387
388
389 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
390
391 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
392
393 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
394
395
396 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
397
398
399 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
400
401 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
402
403 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
404
405 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
406
407
408
409 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
410
411 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
412
413
414
415 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
416
417 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
418
419
420
421 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
422 RFPGA0_XA_LSSIPARAMETER;
423 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
424 RFPGA0_XB_LSSIPARAMETER;
425
426
427
428 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
429 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
430 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
431 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
432
433
434
435 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
436
437 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
438
439 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
440
441 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
442
443
444
445 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
446
447 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
448
449
450
451 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
452
453 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
454
455
456
457 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
458 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
459 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
460 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
461
462
463 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
464 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
465 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
466 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
467
468
469 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
470 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
471 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
472 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
473
474
475 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
476 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
477 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
478 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
479
480
481 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
482 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
483 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
484 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
485
486
487 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
488 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
489 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
490 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
491
492
493 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
494 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
495 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
496 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
497
498
499 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
500 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
501 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
502 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
503
504
505 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
506 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
507}
508
509static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
510 u8 configtype)
511{
512 int i;
513 u32 *phy_regarray_table;
514 u32 *agctab_array_table = NULL;
515 u32 *agctab_5garray_table;
516 u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen;
517 struct rtl_priv *rtlpriv = rtl_priv(hw);
518 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
519
520
521 if (rtlhal->interfaceindex == 0) {
522 agctab_arraylen = AGCTAB_ARRAYLENGTH;
523 agctab_array_table = rtl8192de_agctab_array;
524 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
525 " ===> phy:MAC0, Rtl819XAGCTAB_Array\n");
526 } else {
527 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
528 agctab_arraylen = AGCTAB_2G_ARRAYLENGTH;
529 agctab_array_table = rtl8192de_agctab_2garray;
530 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
531 " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n");
532 } else {
533 agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH;
534 agctab_5garray_table = rtl8192de_agctab_5garray;
535 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
536 " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n");
537
538 }
539 }
540 phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH;
541 phy_regarray_table = rtl8192de_phy_reg_2tarray;
542 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
543 " ===> phy:Rtl819XPHY_REG_Array_PG\n");
544 if (configtype == BASEBAND_CONFIG_PHY_REG) {
545 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
546 rtl_addr_delay(phy_regarray_table[i]);
547 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
548 phy_regarray_table[i + 1]);
549 udelay(1);
550 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
551 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
552 phy_regarray_table[i],
553 phy_regarray_table[i + 1]);
554 }
555 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
556 if (rtlhal->interfaceindex == 0) {
557 for (i = 0; i < agctab_arraylen; i = i + 2) {
558 rtl_set_bbreg(hw, agctab_array_table[i],
559 MASKDWORD,
560 agctab_array_table[i + 1]);
561
562
563 udelay(1);
564 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
565 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
566 agctab_array_table[i],
567 agctab_array_table[i + 1]);
568 }
569 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
570 "Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n");
571 } else {
572 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
573 for (i = 0; i < agctab_arraylen; i = i + 2) {
574 rtl_set_bbreg(hw, agctab_array_table[i],
575 MASKDWORD,
576 agctab_array_table[i + 1]);
577
578
579 udelay(1);
580 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
581 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
582 agctab_array_table[i],
583 agctab_array_table[i + 1]);
584 }
585 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
586 "Load Rtl819XAGCTAB_2GArray\n");
587 } else {
588 for (i = 0; i < agctab_5garraylen; i = i + 2) {
589 rtl_set_bbreg(hw,
590 agctab_5garray_table[i],
591 MASKDWORD,
592 agctab_5garray_table[i + 1]);
593
594
595 udelay(1);
596 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
597 "The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
598 agctab_5garray_table[i],
599 agctab_5garray_table[i + 1]);
600 }
601 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
602 "Load Rtl819XAGCTAB_5GArray\n");
603 }
604 }
605 }
606 return true;
607}
608
609static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
610 u32 regaddr, u32 bitmask,
611 u32 data)
612{
613 struct rtl_priv *rtlpriv = rtl_priv(hw);
614 struct rtl_phy *rtlphy = &(rtlpriv->phy);
615 int index;
616
617 if (regaddr == RTXAGC_A_RATE18_06)
618 index = 0;
619 else if (regaddr == RTXAGC_A_RATE54_24)
620 index = 1;
621 else if (regaddr == RTXAGC_A_CCK1_MCS32)
622 index = 6;
623 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
624 index = 7;
625 else if (regaddr == RTXAGC_A_MCS03_MCS00)
626 index = 2;
627 else if (regaddr == RTXAGC_A_MCS07_MCS04)
628 index = 3;
629 else if (regaddr == RTXAGC_A_MCS11_MCS08)
630 index = 4;
631 else if (regaddr == RTXAGC_A_MCS15_MCS12)
632 index = 5;
633 else if (regaddr == RTXAGC_B_RATE18_06)
634 index = 8;
635 else if (regaddr == RTXAGC_B_RATE54_24)
636 index = 9;
637 else if (regaddr == RTXAGC_B_CCK1_55_MCS32)
638 index = 14;
639 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
640 index = 15;
641 else if (regaddr == RTXAGC_B_MCS03_MCS00)
642 index = 10;
643 else if (regaddr == RTXAGC_B_MCS07_MCS04)
644 index = 11;
645 else if (regaddr == RTXAGC_B_MCS11_MCS08)
646 index = 12;
647 else if (regaddr == RTXAGC_B_MCS15_MCS12)
648 index = 13;
649 else
650 return;
651
652 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
653 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
654 "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
655 rtlphy->pwrgroup_cnt, index,
656 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]);
657 if (index == 13)
658 rtlphy->pwrgroup_cnt++;
659}
660
661static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
662 u8 configtype)
663{
664 struct rtl_priv *rtlpriv = rtl_priv(hw);
665 int i;
666 u32 *phy_regarray_table_pg;
667 u16 phy_regarray_pg_len;
668
669 phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH;
670 phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
671 if (configtype == BASEBAND_CONFIG_PHY_REG) {
672 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
673 rtl_addr_delay(phy_regarray_table_pg[i]);
674 _rtl92d_store_pwrindex_diffrate_offset(hw,
675 phy_regarray_table_pg[i],
676 phy_regarray_table_pg[i + 1],
677 phy_regarray_table_pg[i + 2]);
678 }
679 } else {
680 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
681 "configtype != BaseBand_Config_PHY_REG\n");
682 }
683 return true;
684}
685
686static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw)
687{
688 struct rtl_priv *rtlpriv = rtl_priv(hw);
689 struct rtl_phy *rtlphy = &(rtlpriv->phy);
690 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
691 bool rtstatus = true;
692
693 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
694 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
695 BASEBAND_CONFIG_PHY_REG);
696 if (!rtstatus) {
697 pr_err("Write BB Reg Fail!!\n");
698 return false;
699 }
700
701
702
703
704
705
706 if (rtlefuse->autoload_failflag == false) {
707 rtlphy->pwrgroup_cnt = 0;
708 rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw,
709 BASEBAND_CONFIG_PHY_REG);
710 }
711 if (!rtstatus) {
712 pr_err("BB_PG Reg Fail!!\n");
713 return false;
714 }
715 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
716 BASEBAND_CONFIG_AGC_TAB);
717 if (!rtstatus) {
718 pr_err("AGC Table Fail\n");
719 return false;
720 }
721 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
722 RFPGA0_XA_HSSIPARAMETER2, 0x200));
723
724 return true;
725}
726
727bool rtl92d_phy_bb_config(struct ieee80211_hw *hw)
728{
729 struct rtl_priv *rtlpriv = rtl_priv(hw);
730 u16 regval;
731 u32 regvaldw;
732 u8 value;
733
734 _rtl92d_phy_init_bb_rf_register_definition(hw);
735 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
736 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
737 regval | BIT(13) | BIT(0) | BIT(1));
738 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
739 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
740
741 value = rtl_read_byte(rtlpriv, REG_RF_CTRL);
742 rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
743 RF_SDMRSTB);
744 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
745 FEN_DIO_PCIE | FEN_BB_GLB_RSTN | FEN_BBRSTB);
746 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
747 if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
748 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
749 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
750 }
751
752 return _rtl92d_phy_bb_config(hw);
753}
754
755bool rtl92d_phy_rf_config(struct ieee80211_hw *hw)
756{
757 return rtl92d_phy_rf6052_config(hw);
758}
759
760bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
761 enum rf_content content,
762 enum radio_path rfpath)
763{
764 int i;
765 u32 *radioa_array_table;
766 u32 *radiob_array_table;
767 u16 radioa_arraylen, radiob_arraylen;
768 struct rtl_priv *rtlpriv = rtl_priv(hw);
769
770 radioa_arraylen = RADIOA_2T_ARRAYLENGTH;
771 radioa_array_table = rtl8192de_radioa_2tarray;
772 radiob_arraylen = RADIOB_2T_ARRAYLENGTH;
773 radiob_array_table = rtl8192de_radiob_2tarray;
774 if (rtlpriv->efuse.internal_pa_5g[0]) {
775 radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH;
776 radioa_array_table = rtl8192de_radioa_2t_int_paarray;
777 }
778 if (rtlpriv->efuse.internal_pa_5g[1]) {
779 radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH;
780 radiob_array_table = rtl8192de_radiob_2t_int_paarray;
781 }
782 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
783 "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n");
784 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
785 "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n");
786 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
787
788
789
790
791 if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) {
792 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
793 " ===> althougth Path A, we load radiob.txt\n");
794 radioa_arraylen = radiob_arraylen;
795 radioa_array_table = radiob_array_table;
796 }
797 switch (rfpath) {
798 case RF90_PATH_A:
799 for (i = 0; i < radioa_arraylen; i = i + 2) {
800 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
801 RFREG_OFFSET_MASK,
802 radioa_array_table[i + 1]);
803 }
804 break;
805 case RF90_PATH_B:
806 for (i = 0; i < radiob_arraylen; i = i + 2) {
807 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
808 RFREG_OFFSET_MASK,
809 radiob_array_table[i + 1]);
810 }
811 break;
812 case RF90_PATH_C:
813 case RF90_PATH_D:
814 pr_err("switch case %#x not processed\n", rfpath);
815 break;
816 }
817 return true;
818}
819
820void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
821{
822 struct rtl_priv *rtlpriv = rtl_priv(hw);
823 struct rtl_phy *rtlphy = &(rtlpriv->phy);
824
825 rtlphy->default_initialgain[0] =
826 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
827 rtlphy->default_initialgain[1] =
828 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
829 rtlphy->default_initialgain[2] =
830 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
831 rtlphy->default_initialgain[3] =
832 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
833 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
834 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
835 rtlphy->default_initialgain[0],
836 rtlphy->default_initialgain[1],
837 rtlphy->default_initialgain[2],
838 rtlphy->default_initialgain[3]);
839 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
840 MASKBYTE0);
841 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
842 MASKDWORD);
843 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
844 "Default framesync (0x%x) = 0x%x\n",
845 ROFDM0_RXDETECTOR3, rtlphy->framesync);
846}
847
848static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
849 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
850{
851 struct rtl_priv *rtlpriv = rtl_priv(hw);
852 struct rtl_phy *rtlphy = &(rtlpriv->phy);
853 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
854 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
855 u8 index = (channel - 1);
856
857
858 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
859
860 cckpowerlevel[RF90_PATH_A] =
861 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
862
863 cckpowerlevel[RF90_PATH_B] =
864 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
865 } else {
866 cckpowerlevel[RF90_PATH_A] = 0;
867 cckpowerlevel[RF90_PATH_B] = 0;
868 }
869
870 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
871
872 ofdmpowerlevel[RF90_PATH_A] =
873 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
874 ofdmpowerlevel[RF90_PATH_B] =
875 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
876 } else if (rtlphy->rf_type == RF_2T2R) {
877
878 ofdmpowerlevel[RF90_PATH_A] =
879 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
880 ofdmpowerlevel[RF90_PATH_B] =
881 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
882 }
883}
884
885static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw,
886 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
887{
888 struct rtl_priv *rtlpriv = rtl_priv(hw);
889 struct rtl_phy *rtlphy = &(rtlpriv->phy);
890
891 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
892 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
893}
894
895static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl)
896{
897 u8 place = chnl;
898
899 if (chnl > 14) {
900 for (place = 14; place < sizeof(channel5g); place++) {
901 if (channel5g[place] == chnl) {
902 place++;
903 break;
904 }
905 }
906 }
907 return place;
908}
909
910void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
911{
912 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
913 struct rtl_priv *rtlpriv = rtl_priv(hw);
914 u8 cckpowerlevel[2], ofdmpowerlevel[2];
915
916 if (!rtlefuse->txpwr_fromeprom)
917 return;
918 channel = _rtl92c_phy_get_rightchnlplace(channel);
919 _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0],
920 &ofdmpowerlevel[0]);
921 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
922 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
923 &ofdmpowerlevel[0]);
924 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
925 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
926 rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
927}
928
929void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
930 enum nl80211_channel_type ch_type)
931{
932 struct rtl_priv *rtlpriv = rtl_priv(hw);
933 struct rtl_phy *rtlphy = &(rtlpriv->phy);
934 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
935 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
936 unsigned long flag = 0;
937 u8 reg_prsr_rsc;
938 u8 reg_bw_opmode;
939
940 if (rtlphy->set_bwmode_inprogress)
941 return;
942 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
943 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
944 "FALSE driver sleep or unload\n");
945 return;
946 }
947 rtlphy->set_bwmode_inprogress = true;
948 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
949 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
950 "20MHz" : "40MHz");
951 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
952 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
953 switch (rtlphy->current_chan_bw) {
954 case HT_CHANNEL_WIDTH_20:
955 reg_bw_opmode |= BW_OPMODE_20MHZ;
956 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
957 break;
958 case HT_CHANNEL_WIDTH_20_40:
959 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
960 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
961
962 reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
963 (mac->cur_40_prime_sc << 5);
964 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
965 break;
966 default:
967 pr_err("unknown bandwidth: %#X\n",
968 rtlphy->current_chan_bw);
969 break;
970 }
971 switch (rtlphy->current_chan_bw) {
972 case HT_CHANNEL_WIDTH_20:
973 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
974 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
975
976 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
977 BIT(11), 3);
978 break;
979 case HT_CHANNEL_WIDTH_20_40:
980 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
981 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
982
983
984 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
985 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
986 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND,
987 (mac->cur_40_prime_sc >> 1));
988 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
989 }
990 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
991
992 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
993 BIT(11), 0);
994 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
995 (mac->cur_40_prime_sc ==
996 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
997 break;
998 default:
999 pr_err("unknown bandwidth: %#X\n",
1000 rtlphy->current_chan_bw);
1001 break;
1002
1003 }
1004 rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1005 rtlphy->set_bwmode_inprogress = false;
1006 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
1007}
1008
1009static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
1010{
1011 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
1012 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
1013 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00);
1014 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
1015}
1016
1017static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
1018{
1019 struct rtl_priv *rtlpriv = rtl_priv(hw);
1020 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1021 u8 value8;
1022
1023 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
1024 rtlhal->bandset = band;
1025 rtlhal->current_bandtype = band;
1026 if (IS_92D_SINGLEPHY(rtlhal->version))
1027 rtlhal->bandset = BAND_ON_BOTH;
1028
1029 _rtl92d_phy_stop_trx_before_changeband(hw);
1030
1031 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1032
1033 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n");
1034 if (rtlhal->interfaceindex == 1)
1035 _rtl92d_phy_config_bb_with_headerfile(hw,
1036 BASEBAND_CONFIG_AGC_TAB);
1037 } else {
1038
1039 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n");
1040 if (rtlhal->interfaceindex == 1)
1041 _rtl92d_phy_config_bb_with_headerfile(hw,
1042 BASEBAND_CONFIG_AGC_TAB);
1043 }
1044 rtl92d_update_bbrf_configuration(hw);
1045 if (rtlhal->current_bandtype == BAND_ON_2_4G)
1046 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1047 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1048
1049
1050
1051 rtlhal->reloadtxpowerindex = true;
1052
1053 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1054 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1055 0 ? REG_MAC0 : REG_MAC1));
1056 value8 |= BIT(1);
1057 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1058 0 ? REG_MAC0 : REG_MAC1), value8);
1059 } else {
1060 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1061 0 ? REG_MAC0 : REG_MAC1));
1062 value8 &= (~BIT(1));
1063 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1064 0 ? REG_MAC0 : REG_MAC1), value8);
1065 }
1066 mdelay(1);
1067 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n");
1068}
1069
1070static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1071 u8 channel, u8 rfpath)
1072{
1073 struct rtl_priv *rtlpriv = rtl_priv(hw);
1074 u32 imr_num = MAX_RF_IMR_INDEX;
1075 u32 rfmask = RFREG_OFFSET_MASK;
1076 u8 group, i;
1077 unsigned long flag = 0;
1078
1079 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath);
1080 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
1081 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1082 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1083 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1084
1085 if (channel > 99)
1086 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1087 BIT(14), 2);
1088 else
1089 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1090 BIT(14), 1);
1091
1092 group = channel <= 64 ? 1 : 2;
1093 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1094 for (i = 0; i < imr_num; i++)
1095 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1096 rf_reg_for_5g_swchnl_normal[i], rfmask,
1097 rf_imr_param_normal[0][group][i]);
1098 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
1099 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1);
1100 } else {
1101
1102 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1103 "Load RF IMR parameters for G band. IMR already setting %d\n",
1104 rtlpriv->rtlhal.load_imrandiqk_setting_for2g);
1105 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1106 if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) {
1107 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1108 "Load RF IMR parameters for G band. %d\n",
1109 rfpath);
1110 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1111 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1112 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1113 0x00f00000, 0xf);
1114 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1115 for (i = 0; i < imr_num; i++) {
1116 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1117 rf_reg_for_5g_swchnl_normal[i],
1118 RFREG_OFFSET_MASK,
1119 rf_imr_param_normal[0][0][i]);
1120 }
1121 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1122 0x00f00000, 0);
1123 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3);
1124 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1125 }
1126 }
1127 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1128}
1129
1130static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw,
1131 u8 rfpath, u32 *pu4_regval)
1132{
1133 struct rtl_priv *rtlpriv = rtl_priv(hw);
1134 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1135 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1136
1137 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "====>\n");
1138
1139 switch (rfpath) {
1140 case RF90_PATH_A:
1141 case RF90_PATH_C:
1142 *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV);
1143 break;
1144 case RF90_PATH_B:
1145 case RF90_PATH_D:
1146 *pu4_regval =
1147 rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16);
1148 break;
1149 }
1150
1151 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
1152 udelay(1);
1153
1154 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
1155 udelay(1);
1156
1157
1158 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0);
1159 udelay(1);
1160
1161 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
1162 udelay(1);
1163 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<====\n");
1164}
1165
1166static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath,
1167 u32 *pu4_regval)
1168{
1169 struct rtl_priv *rtlpriv = rtl_priv(hw);
1170 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1171 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1172
1173 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n");
1174
1175 switch (rfpath) {
1176 case RF90_PATH_A:
1177 case RF90_PATH_C:
1178 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval);
1179 break;
1180 case RF90_PATH_B:
1181 case RF90_PATH_D:
1182 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
1183 *pu4_regval);
1184 break;
1185 }
1186 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n");
1187}
1188
1189static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1190{
1191 struct rtl_priv *rtlpriv = rtl_priv(hw);
1192 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1193 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1194 u8 path = rtlhal->current_bandtype ==
1195 BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B;
1196 u8 index = 0, i = 0, rfpath = RF90_PATH_A;
1197 bool need_pwr_down = false, internal_pa = false;
1198 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2;
1199
1200 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n");
1201
1202 if (rtlhal->current_bandtype == BAND_ON_5G) {
1203 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1204 u4tmp = curveindex_5g[channel - 1];
1205 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1206 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
1207 for (i = 0; i < RF_CHNL_NUM_5G; i++) {
1208 if (channel == rf_chnl_5g[i] && channel <= 140)
1209 index = 0;
1210 }
1211 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) {
1212 if (channel == rf_chnl_5g_40m[i] && channel <= 140)
1213 index = 1;
1214 }
1215 if (channel == 149 || channel == 155 || channel == 161)
1216 index = 2;
1217 else if (channel == 151 || channel == 153 || channel == 163
1218 || channel == 165)
1219 index = 3;
1220 else if (channel == 157 || channel == 159)
1221 index = 4;
1222
1223 if (rtlhal->macphymode == DUALMAC_DUALPHY
1224 && rtlhal->interfaceindex == 1) {
1225 need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false);
1226 rtlhal->during_mac1init_radioa = true;
1227
1228 if (need_pwr_down)
1229 _rtl92d_phy_enable_rf_env(hw, path,
1230 &u4regvalue);
1231 }
1232 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) {
1233 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
1234 rtl_set_rfreg(hw, (enum radio_path)path,
1235 rf_reg_for_c_cut_5g[i],
1236 RFREG_OFFSET_MASK, 0xE439D);
1237 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
1238 u4tmp2 = (rf_reg_pram_c_5g[index][i] &
1239 0x7FF) | (u4tmp << 11);
1240 if (channel == 36)
1241 u4tmp2 &= ~(BIT(7) | BIT(6));
1242 rtl_set_rfreg(hw, (enum radio_path)path,
1243 rf_reg_for_c_cut_5g[i],
1244 RFREG_OFFSET_MASK, u4tmp2);
1245 } else {
1246 rtl_set_rfreg(hw, (enum radio_path)path,
1247 rf_reg_for_c_cut_5g[i],
1248 RFREG_OFFSET_MASK,
1249 rf_reg_pram_c_5g[index][i]);
1250 }
1251 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1252 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n",
1253 rf_reg_for_c_cut_5g[i],
1254 rf_reg_pram_c_5g[index][i],
1255 path, index,
1256 rtl_get_rfreg(hw, (enum radio_path)path,
1257 rf_reg_for_c_cut_5g[i],
1258 RFREG_OFFSET_MASK));
1259 }
1260 if (need_pwr_down)
1261 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1262 if (rtlhal->during_mac1init_radioa)
1263 rtl92d_phy_powerdown_anotherphy(hw, false);
1264 if (channel < 149)
1265 value = 0x07;
1266 else if (channel >= 149)
1267 value = 0x02;
1268 if (channel >= 36 && channel <= 64)
1269 index = 0;
1270 else if (channel >= 100 && channel <= 140)
1271 index = 1;
1272 else
1273 index = 2;
1274 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1275 rfpath++) {
1276 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
1277 rtlhal->interfaceindex == 1)
1278 internal_pa = rtlpriv->efuse.internal_pa_5g[1];
1279 else
1280 internal_pa =
1281 rtlpriv->efuse.internal_pa_5g[rfpath];
1282 if (internal_pa) {
1283 for (i = 0;
1284 i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA;
1285 i++) {
1286 rtl_set_rfreg(hw, rfpath,
1287 rf_for_c_cut_5g_internal_pa[i],
1288 RFREG_OFFSET_MASK,
1289 rf_pram_c_5g_int_pa[index][i]);
1290 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
1291 "offset 0x%x value 0x%x path %d index %d\n",
1292 rf_for_c_cut_5g_internal_pa[i],
1293 rf_pram_c_5g_int_pa[index][i],
1294 rfpath, index);
1295 }
1296 } else {
1297 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
1298 mask, value);
1299 }
1300 }
1301 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1302 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1303 u4tmp = curveindex_2g[channel - 1];
1304 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1305 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
1306 if (channel == 1 || channel == 2 || channel == 4 || channel == 9
1307 || channel == 10 || channel == 11 || channel == 12)
1308 index = 0;
1309 else if (channel == 3 || channel == 13 || channel == 14)
1310 index = 1;
1311 else if (channel >= 5 && channel <= 8)
1312 index = 2;
1313 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1314 path = RF90_PATH_A;
1315 if (rtlhal->interfaceindex == 0) {
1316 need_pwr_down =
1317 rtl92d_phy_enable_anotherphy(hw, true);
1318 rtlhal->during_mac0init_radiob = true;
1319
1320 if (need_pwr_down)
1321 _rtl92d_phy_enable_rf_env(hw, path,
1322 &u4regvalue);
1323 }
1324 }
1325 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) {
1326 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
1327 rtl_set_rfreg(hw, (enum radio_path)path,
1328 rf_reg_for_c_cut_2g[i],
1329 RFREG_OFFSET_MASK,
1330 (rf_reg_param_for_c_cut_2g[index][i] |
1331 BIT(17)));
1332 else
1333 rtl_set_rfreg(hw, (enum radio_path)path,
1334 rf_reg_for_c_cut_2g[i],
1335 RFREG_OFFSET_MASK,
1336 rf_reg_param_for_c_cut_2g
1337 [index][i]);
1338 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1339 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n",
1340 rf_reg_for_c_cut_2g[i],
1341 rf_reg_param_for_c_cut_2g[index][i],
1342 rf_reg_mask_for_c_cut_2g[i], path, index,
1343 rtl_get_rfreg(hw, (enum radio_path)path,
1344 rf_reg_for_c_cut_2g[i],
1345 RFREG_OFFSET_MASK));
1346 }
1347 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1348 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1349 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1350
1351 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1352 RFREG_OFFSET_MASK,
1353 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1354 if (need_pwr_down)
1355 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1356 if (rtlhal->during_mac0init_radiob)
1357 rtl92d_phy_powerdown_anotherphy(hw, true);
1358 }
1359 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1360}
1361
1362u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl)
1363{
1364 u8 channel_all[59] = {
1365 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
1366 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
1367 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
1368 114, 116, 118, 120, 122, 124, 126, 128, 130,
1369 132, 134, 136, 138, 140, 149, 151, 153, 155,
1370 157, 159, 161, 163, 165
1371 };
1372 u8 place = chnl;
1373
1374 if (chnl > 14) {
1375 for (place = 14; place < sizeof(channel_all); place++) {
1376 if (channel_all[place] == chnl)
1377 return place - 13;
1378 }
1379 }
1380
1381 return 0;
1382}
1383
1384#define MAX_TOLERANCE 5
1385#define IQK_DELAY_TIME 1
1386#define MAX_TOLERANCE_92D 3
1387
1388
1389static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1390{
1391 struct rtl_priv *rtlpriv = rtl_priv(hw);
1392 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1393 u32 regeac, rege94, rege9c, regea4;
1394 u8 result = 0;
1395
1396 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n");
1397
1398 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1399 if (rtlhal->interfaceindex == 0) {
1400 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1401 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1402 } else {
1403 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22);
1404 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22);
1405 }
1406 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1407 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206);
1408
1409 if (configpathb) {
1410 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1411 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1412 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1413 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206);
1414 }
1415
1416 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1417 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1418
1419 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n");
1420 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1421 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1422
1423 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1424 "Delay %d ms for One shot, path A LOK & IQK\n",
1425 IQK_DELAY_TIME);
1426 mdelay(IQK_DELAY_TIME);
1427
1428 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1429 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1430 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1431 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
1432 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1433 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
1434 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1435 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
1436 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1437 (((rege9c & 0x03FF0000) >> 16) != 0x42))
1438 result |= 0x01;
1439 else
1440 return result;
1441
1442 if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) &&
1443 (((regeac & 0x03FF0000) >> 16) != 0x36))
1444 result |= 0x02;
1445 else
1446 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A Rx IQK fail!!\n");
1447 return result;
1448}
1449
1450
1451static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1452 bool configpathb)
1453{
1454 struct rtl_priv *rtlpriv = rtl_priv(hw);
1455 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1456 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1457 u32 regeac, rege94, rege9c, regea4;
1458 u8 result = 0;
1459 u8 i;
1460 u8 retrycount = 2;
1461 u32 TXOKBIT = BIT(28), RXOKBIT = BIT(27);
1462
1463 if (rtlhal->interfaceindex == 1) {
1464 TXOKBIT = BIT(31);
1465 RXOKBIT = BIT(30);
1466 }
1467 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n");
1468
1469 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1470 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1471 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1472 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307);
1473 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960);
1474
1475 if (configpathb) {
1476 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1477 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1478 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000);
1479 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000);
1480 }
1481
1482 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1483 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1484
1485 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60);
1486 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30);
1487 for (i = 0; i < retrycount; i++) {
1488
1489 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1490 "One shot, path A LOK & IQK!\n");
1491 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1492 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1493
1494 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1495 "Delay %d ms for One shot, path A LOK & IQK.\n",
1496 IQK_DELAY_TIME);
1497 mdelay(IQK_DELAY_TIME * 10);
1498
1499 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1500 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1501 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1502 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
1503 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1504 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
1505 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1506 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
1507 if (!(regeac & TXOKBIT) &&
1508 (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1509 result |= 0x01;
1510 } else {
1511 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1512 "Path A Tx IQK fail!!\n");
1513 continue;
1514 }
1515
1516
1517 if (!(regeac & RXOKBIT) &&
1518 (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1519 result |= 0x02;
1520 break;
1521 } else {
1522 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1523 "Path A Rx IQK fail!!\n");
1524 }
1525 }
1526
1527 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1528 rtlphy->iqk_bb_backup[0]);
1529 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD,
1530 rtlphy->iqk_bb_backup[1]);
1531 return result;
1532}
1533
1534
1535static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1536{
1537 struct rtl_priv *rtlpriv = rtl_priv(hw);
1538 u32 regeac, regeb4, regebc, regec4, regecc;
1539 u8 result = 0;
1540
1541 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n");
1542
1543 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n");
1544 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1545 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1546
1547 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1548 "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME);
1549 mdelay(IQK_DELAY_TIME);
1550
1551 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1552 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1553 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1554 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
1555 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1556 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
1557 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1558 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
1559 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1560 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
1561 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1562 (((regebc & 0x03FF0000) >> 16) != 0x42))
1563 result |= 0x01;
1564 else
1565 return result;
1566 if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
1567 (((regecc & 0x03FF0000) >> 16) != 0x36))
1568 result |= 0x02;
1569 else
1570 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B Rx IQK fail!!\n");
1571 return result;
1572}
1573
1574
1575static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1576{
1577 struct rtl_priv *rtlpriv = rtl_priv(hw);
1578 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1579 u32 regeac, regeb4, regebc, regec4, regecc;
1580 u8 result = 0;
1581 u8 i;
1582 u8 retrycount = 2;
1583
1584 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n");
1585
1586 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1587 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1588 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1589 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000);
1590 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000);
1591
1592
1593 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1594 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1595 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307);
1596 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960);
1597
1598
1599 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1600 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1601
1602
1603 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700);
1604 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30);
1605
1606 for (i = 0; i < retrycount; i++) {
1607
1608 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1609 "One shot, path A LOK & IQK!\n");
1610 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000);
1611 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1612
1613
1614 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1615 "Delay %d ms for One shot, path B LOK & IQK.\n", 10);
1616 mdelay(IQK_DELAY_TIME * 10);
1617
1618
1619 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1620 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1621 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1622 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
1623 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1624 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
1625 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1626 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
1627 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1628 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
1629 if (!(regeac & BIT(31)) &&
1630 (((regeb4 & 0x03FF0000) >> 16) != 0x142))
1631 result |= 0x01;
1632 else
1633 continue;
1634 if (!(regeac & BIT(30)) &&
1635 (((regec4 & 0x03FF0000) >> 16) != 0x132)) {
1636 result |= 0x02;
1637 break;
1638 } else {
1639 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1640 "Path B Rx IQK fail!!\n");
1641 }
1642 }
1643
1644
1645 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1646 rtlphy->iqk_bb_backup[0]);
1647 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD,
1648 rtlphy->iqk_bb_backup[2]);
1649 return result;
1650}
1651
1652static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1653 u32 *adda_reg, u32 *adda_backup,
1654 u32 regnum)
1655{
1656 struct rtl_priv *rtlpriv = rtl_priv(hw);
1657 u32 i;
1658
1659 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n");
1660 for (i = 0; i < regnum; i++)
1661 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD);
1662}
1663
1664static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
1665 u32 *macreg, u32 *macbackup)
1666{
1667 struct rtl_priv *rtlpriv = rtl_priv(hw);
1668 u32 i;
1669
1670 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save MAC parameters.\n");
1671 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1672 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1673 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1674}
1675
1676static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1677 u32 *adda_reg, u32 *adda_backup,
1678 u32 regnum)
1679{
1680 struct rtl_priv *rtlpriv = rtl_priv(hw);
1681 u32 i;
1682
1683 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1684 "Reload ADDA power saving parameters !\n");
1685 for (i = 0; i < regnum; i++)
1686 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]);
1687}
1688
1689static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
1690 u32 *macreg, u32 *macbackup)
1691{
1692 struct rtl_priv *rtlpriv = rtl_priv(hw);
1693 u32 i;
1694
1695 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Reload MAC parameters !\n");
1696 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1697 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1698 rtl_write_byte(rtlpriv, macreg[i], macbackup[i]);
1699}
1700
1701static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1702 u32 *adda_reg, bool patha_on, bool is2t)
1703{
1704 struct rtl_priv *rtlpriv = rtl_priv(hw);
1705 u32 pathon;
1706 u32 i;
1707
1708 RTPRINT(rtlpriv, FINIT, INIT_IQK, "ADDA ON.\n");
1709 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;
1710 if (patha_on)
1711 pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
1712 0x04db25a4 : 0x0b1b25a4;
1713 for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1714 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon);
1715}
1716
1717static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1718 u32 *macreg, u32 *macbackup)
1719{
1720 struct rtl_priv *rtlpriv = rtl_priv(hw);
1721 u32 i;
1722
1723 RTPRINT(rtlpriv, FINIT, INIT_IQK, "MAC settings for Calibration.\n");
1724 rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1725
1726 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1727 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] &
1728 (~BIT(3))));
1729 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1730}
1731
1732static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1733{
1734 struct rtl_priv *rtlpriv = rtl_priv(hw);
1735 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n");
1736
1737 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1738 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000);
1739 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1740}
1741
1742static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
1743{
1744 struct rtl_priv *rtlpriv = rtl_priv(hw);
1745 u32 mode;
1746
1747 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1748 "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI");
1749 mode = pi_mode ? 0x01000100 : 0x01000000;
1750 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1751 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1752}
1753
1754static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1755 u8 t, bool is2t)
1756{
1757 struct rtl_priv *rtlpriv = rtl_priv(hw);
1758 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1759 u32 i;
1760 u8 patha_ok, pathb_ok;
1761 static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1762 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1763 0xe78, 0xe7c, 0xe80, 0xe84,
1764 0xe88, 0xe8c, 0xed0, 0xed4,
1765 0xed8, 0xedc, 0xee0, 0xeec
1766 };
1767 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1768 0x522, 0x550, 0x551, 0x040
1769 };
1770 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1771 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1772 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1773 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1774 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1775 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1776 };
1777 const u32 retrycount = 2;
1778 u32 bbvalue;
1779
1780 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n");
1781 if (t == 0) {
1782 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1783 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
1784 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1785 is2t ? "2T2R" : "1T1R");
1786
1787
1788 _rtl92d_phy_save_adda_registers(hw, adda_reg,
1789 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1790 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1791 rtlphy->iqk_mac_backup);
1792 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1793 rtlphy->iqk_bb_backup, IQK_BB_REG_NUM);
1794 }
1795 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1796 if (t == 0)
1797 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1798 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1799
1800
1801 if (!rtlphy->rfpi_enable)
1802 _rtl92d_phy_pimode_switch(hw, true);
1803
1804 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1805 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1806 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1807 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000);
1808 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1809 if (is2t) {
1810 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD,
1811 0x00010000);
1812 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD,
1813 0x00010000);
1814 }
1815
1816 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1817 rtlphy->iqk_mac_backup);
1818
1819 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1820 if (is2t)
1821 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1822
1823 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n");
1824 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1825 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1826 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1827 for (i = 0; i < retrycount; i++) {
1828 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
1829 if (patha_ok == 0x03) {
1830 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1831 "Path A IQK Success!!\n");
1832 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1833 0x3FF0000) >> 16;
1834 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1835 0x3FF0000) >> 16;
1836 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1837 0x3FF0000) >> 16;
1838 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1839 0x3FF0000) >> 16;
1840 break;
1841 } else if (i == (retrycount - 1) && patha_ok == 0x01) {
1842
1843 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1844 "Path A IQK Only Tx Success!!\n");
1845
1846 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1847 0x3FF0000) >> 16;
1848 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1849 0x3FF0000) >> 16;
1850 }
1851 }
1852 if (0x00 == patha_ok)
1853 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK failed!!\n");
1854 if (is2t) {
1855 _rtl92d_phy_patha_standby(hw);
1856
1857 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
1858 for (i = 0; i < retrycount; i++) {
1859 pathb_ok = _rtl92d_phy_pathb_iqk(hw);
1860 if (pathb_ok == 0x03) {
1861 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1862 "Path B IQK Success!!\n");
1863 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1864 MASKDWORD) & 0x3FF0000) >> 16;
1865 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1866 MASKDWORD) & 0x3FF0000) >> 16;
1867 result[t][6] = (rtl_get_bbreg(hw, 0xec4,
1868 MASKDWORD) & 0x3FF0000) >> 16;
1869 result[t][7] = (rtl_get_bbreg(hw, 0xecc,
1870 MASKDWORD) & 0x3FF0000) >> 16;
1871 break;
1872 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1873
1874 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1875 "Path B Only Tx IQK Success!!\n");
1876 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1877 MASKDWORD) & 0x3FF0000) >> 16;
1878 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1879 MASKDWORD) & 0x3FF0000) >> 16;
1880 }
1881 }
1882 if (0x00 == pathb_ok)
1883 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1884 "Path B IQK failed!!\n");
1885 }
1886
1887
1888 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1889 "IQK:Back to BB mode, load original value!\n");
1890
1891 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1892 if (t != 0) {
1893
1894 if (!rtlphy->rfpi_enable)
1895 _rtl92d_phy_pimode_switch(hw, false);
1896
1897 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
1898 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1899
1900 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
1901 rtlphy->iqk_mac_backup);
1902 if (is2t)
1903 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
1904 rtlphy->iqk_bb_backup,
1905 IQK_BB_REG_NUM);
1906 else
1907 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
1908 rtlphy->iqk_bb_backup,
1909 IQK_BB_REG_NUM - 1);
1910
1911 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
1912 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
1913 }
1914 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n");
1915}
1916
1917static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
1918 long result[][8], u8 t)
1919{
1920 struct rtl_priv *rtlpriv = rtl_priv(hw);
1921 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1922 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1923 u8 patha_ok, pathb_ok;
1924 static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1925 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1926 0xe78, 0xe7c, 0xe80, 0xe84,
1927 0xe88, 0xe8c, 0xed0, 0xed4,
1928 0xed8, 0xedc, 0xee0, 0xeec
1929 };
1930 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1931 0x522, 0x550, 0x551, 0x040
1932 };
1933 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1934 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1935 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1936 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1937 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1938 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1939 };
1940 u32 bbvalue;
1941 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
1942
1943
1944
1945
1946 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n");
1947 mdelay(IQK_DELAY_TIME * 20);
1948 if (t == 0) {
1949 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1950 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
1951 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1952 is2t ? "2T2R" : "1T1R");
1953
1954 _rtl92d_phy_save_adda_registers(hw, adda_reg,
1955 rtlphy->adda_backup,
1956 IQK_ADDA_REG_NUM);
1957 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1958 rtlphy->iqk_mac_backup);
1959 if (is2t)
1960 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1961 rtlphy->iqk_bb_backup,
1962 IQK_BB_REG_NUM);
1963 else
1964 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1965 rtlphy->iqk_bb_backup,
1966 IQK_BB_REG_NUM - 1);
1967 }
1968 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1969
1970 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1971 rtlphy->iqk_mac_backup);
1972 if (t == 0)
1973 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1974 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1975
1976 if (!rtlphy->rfpi_enable)
1977 _rtl92d_phy_pimode_switch(hw, true);
1978 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1979 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1980 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1981 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000);
1982 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1983
1984
1985 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1986 if (is2t)
1987 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1988
1989 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n");
1990 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1991 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00);
1992 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1993 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
1994 if (patha_ok == 0x03) {
1995 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n");
1996 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1997 0x3FF0000) >> 16;
1998 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1999 0x3FF0000) >> 16;
2000 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
2001 0x3FF0000) >> 16;
2002 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
2003 0x3FF0000) >> 16;
2004 } else if (patha_ok == 0x01) {
2005 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2006 "Path A IQK Only Tx Success!!\n");
2007
2008 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
2009 0x3FF0000) >> 16;
2010 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
2011 0x3FF0000) >> 16;
2012 } else {
2013 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n");
2014 }
2015 if (is2t) {
2016
2017
2018 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2019 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw);
2020 if (pathb_ok == 0x03) {
2021 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2022 "Path B IQK Success!!\n");
2023 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2024 0x3FF0000) >> 16;
2025 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2026 0x3FF0000) >> 16;
2027 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
2028 0x3FF0000) >> 16;
2029 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
2030 0x3FF0000) >> 16;
2031 } else if (pathb_ok == 0x01) {
2032 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2033 "Path B Only Tx IQK Success!!\n");
2034 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2035 0x3FF0000) >> 16;
2036 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2037 0x3FF0000) >> 16;
2038 } else {
2039 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2040 "Path B IQK failed!!\n");
2041 }
2042 }
2043
2044
2045 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2046 "IQK:Back to BB mode, load original value!\n");
2047 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
2048 if (t != 0) {
2049 if (is2t)
2050 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2051 rtlphy->iqk_bb_backup,
2052 IQK_BB_REG_NUM);
2053 else
2054 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2055 rtlphy->iqk_bb_backup,
2056 IQK_BB_REG_NUM - 1);
2057
2058 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2059 rtlphy->iqk_mac_backup);
2060
2061 if (!rtlphy->rfpi_enable)
2062 _rtl92d_phy_pimode_switch(hw, false);
2063
2064 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
2065 rtlphy->adda_backup,
2066 IQK_ADDA_REG_NUM);
2067 }
2068 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n");
2069}
2070
2071static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw,
2072 long result[][8], u8 c1, u8 c2)
2073{
2074 struct rtl_priv *rtlpriv = rtl_priv(hw);
2075 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2076 u32 i, j, diff, sim_bitmap, bound;
2077 u8 final_candidate[2] = {0xFF, 0xFF};
2078 bool bresult = true;
2079 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2080
2081 if (is2t)
2082 bound = 8;
2083 else
2084 bound = 4;
2085 sim_bitmap = 0;
2086 for (i = 0; i < bound; i++) {
2087 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] -
2088 result[c2][i]) : (result[c2][i] - result[c1][i]);
2089 if (diff > MAX_TOLERANCE_92D) {
2090 if ((i == 2 || i == 6) && !sim_bitmap) {
2091 if (result[c1][i] + result[c1][i + 1] == 0)
2092 final_candidate[(i / 4)] = c2;
2093 else if (result[c2][i] + result[c2][i + 1] == 0)
2094 final_candidate[(i / 4)] = c1;
2095 else
2096 sim_bitmap = sim_bitmap | (1 << i);
2097 } else {
2098 sim_bitmap = sim_bitmap | (1 << i);
2099 }
2100 }
2101 }
2102 if (sim_bitmap == 0) {
2103 for (i = 0; i < (bound / 4); i++) {
2104 if (final_candidate[i] != 0xFF) {
2105 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2106 result[3][j] =
2107 result[final_candidate[i]][j];
2108 bresult = false;
2109 }
2110 }
2111 return bresult;
2112 }
2113 if (!(sim_bitmap & 0x0F)) {
2114 for (i = 0; i < 4; i++)
2115 result[3][i] = result[c1][i];
2116 } else if (!(sim_bitmap & 0x03)) {
2117 for (i = 0; i < 2; i++)
2118 result[3][i] = result[c1][i];
2119 }
2120 if (!(sim_bitmap & 0xF0) && is2t) {
2121 for (i = 4; i < 8; i++)
2122 result[3][i] = result[c1][i];
2123 } else if (!(sim_bitmap & 0x30)) {
2124 for (i = 4; i < 6; i++)
2125 result[3][i] = result[c1][i];
2126 }
2127 return false;
2128}
2129
2130static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2131 bool iqk_ok, long result[][8],
2132 u8 final_candidate, bool txonly)
2133{
2134 struct rtl_priv *rtlpriv = rtl_priv(hw);
2135 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2136 u32 oldval_0, val_x, tx0_a, reg;
2137 long val_y, tx0_c;
2138 bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
2139 rtlhal->macphymode == DUALMAC_DUALPHY;
2140
2141 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2142 "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed");
2143 if (final_candidate == 0xFF) {
2144 return;
2145 } else if (iqk_ok) {
2146 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2147 MASKDWORD) >> 22) & 0x3FF;
2148 val_x = result[final_candidate][0];
2149 if ((val_x & 0x00000200) != 0)
2150 val_x = val_x | 0xFFFFFC00;
2151 tx0_a = (val_x * oldval_0) >> 8;
2152 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2153 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n",
2154 val_x, tx0_a, oldval_0);
2155 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
2156 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2157 ((val_x * oldval_0 >> 7) & 0x1));
2158 val_y = result[final_candidate][1];
2159 if ((val_y & 0x00000200) != 0)
2160 val_y = val_y | 0xFFFFFC00;
2161
2162 if (rtlhal->interfaceindex == 1 &&
2163 rtlhal->current_bandtype == BAND_ON_5G)
2164 val_y += 3;
2165 tx0_c = (val_y * oldval_0) >> 8;
2166 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2167 "Y = 0x%lx, tx0_c = 0x%lx\n",
2168 val_y, tx0_c);
2169 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
2170 ((tx0_c & 0x3C0) >> 6));
2171 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
2172 (tx0_c & 0x3F));
2173 if (is2t)
2174 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2175 ((val_y * oldval_0 >> 7) & 0x1));
2176 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
2177 rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2178 MASKDWORD));
2179 if (txonly) {
2180 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n");
2181 return;
2182 }
2183 reg = result[final_candidate][2];
2184 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2185 reg = result[final_candidate][3] & 0x3F;
2186 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2187 reg = (result[final_candidate][3] >> 6) & 0xF;
2188 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
2189 }
2190}
2191
2192static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2193 bool iqk_ok, long result[][8], u8 final_candidate, bool txonly)
2194{
2195 struct rtl_priv *rtlpriv = rtl_priv(hw);
2196 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2197 u32 oldval_1, val_x, tx1_a, reg;
2198 long val_y, tx1_c;
2199
2200 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n",
2201 iqk_ok ? "Success" : "Failed");
2202 if (final_candidate == 0xFF) {
2203 return;
2204 } else if (iqk_ok) {
2205 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
2206 MASKDWORD) >> 22) & 0x3FF;
2207 val_x = result[final_candidate][4];
2208 if ((val_x & 0x00000200) != 0)
2209 val_x = val_x | 0xFFFFFC00;
2210 tx1_a = (val_x * oldval_1) >> 8;
2211 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n",
2212 val_x, tx1_a);
2213 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
2214 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2215 ((val_x * oldval_1 >> 7) & 0x1));
2216 val_y = result[final_candidate][5];
2217 if ((val_y & 0x00000200) != 0)
2218 val_y = val_y | 0xFFFFFC00;
2219 if (rtlhal->current_bandtype == BAND_ON_5G)
2220 val_y += 3;
2221 tx1_c = (val_y * oldval_1) >> 8;
2222 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n",
2223 val_y, tx1_c);
2224 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
2225 ((tx1_c & 0x3C0) >> 6));
2226 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
2227 (tx1_c & 0x3F));
2228 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
2229 ((val_y * oldval_1 >> 7) & 0x1));
2230 if (txonly)
2231 return;
2232 reg = result[final_candidate][6];
2233 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2234 reg = result[final_candidate][7] & 0x3F;
2235 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2236 reg = (result[final_candidate][7] >> 6) & 0xF;
2237 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
2238 }
2239}
2240
2241void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2242{
2243 struct rtl_priv *rtlpriv = rtl_priv(hw);
2244 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2245 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2246 long result[4][8];
2247 u8 i, final_candidate, indexforchannel;
2248 bool patha_ok, pathb_ok;
2249 long rege94, rege9c, regea4, regeac, regeb4;
2250 long regebc, regec4, regecc, regtmp = 0;
2251 bool is12simular, is13simular, is23simular;
2252 unsigned long flag = 0;
2253
2254 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2255 "IQK:Start!!!channel %d\n", rtlphy->current_channel);
2256 for (i = 0; i < 8; i++) {
2257 result[0][i] = 0;
2258 result[1][i] = 0;
2259 result[2][i] = 0;
2260 result[3][i] = 0;
2261 }
2262 final_candidate = 0xff;
2263 patha_ok = false;
2264 pathb_ok = false;
2265 is12simular = false;
2266 is23simular = false;
2267 is13simular = false;
2268 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2269 "IQK !!!currentband %d\n", rtlhal->current_bandtype);
2270 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
2271 for (i = 0; i < 3; i++) {
2272 if (rtlhal->current_bandtype == BAND_ON_5G) {
2273 _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i);
2274 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2275 if (IS_92D_SINGLEPHY(rtlhal->version))
2276 _rtl92d_phy_iq_calibrate(hw, result, i, true);
2277 else
2278 _rtl92d_phy_iq_calibrate(hw, result, i, false);
2279 }
2280 if (i == 1) {
2281 is12simular = _rtl92d_phy_simularity_compare(hw, result,
2282 0, 1);
2283 if (is12simular) {
2284 final_candidate = 0;
2285 break;
2286 }
2287 }
2288 if (i == 2) {
2289 is13simular = _rtl92d_phy_simularity_compare(hw, result,
2290 0, 2);
2291 if (is13simular) {
2292 final_candidate = 0;
2293 break;
2294 }
2295 is23simular = _rtl92d_phy_simularity_compare(hw, result,
2296 1, 2);
2297 if (is23simular) {
2298 final_candidate = 1;
2299 } else {
2300 for (i = 0; i < 8; i++)
2301 regtmp += result[3][i];
2302
2303 if (regtmp != 0)
2304 final_candidate = 3;
2305 else
2306 final_candidate = 0xFF;
2307 }
2308 }
2309 }
2310 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
2311 for (i = 0; i < 4; i++) {
2312 rege94 = result[i][0];
2313 rege9c = result[i][1];
2314 regea4 = result[i][2];
2315 regeac = result[i][3];
2316 regeb4 = result[i][4];
2317 regebc = result[i][5];
2318 regec4 = result[i][6];
2319 regecc = result[i][7];
2320 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2321 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2322 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2323 regecc);
2324 }
2325 if (final_candidate != 0xff) {
2326 rtlphy->reg_e94 = rege94 = result[final_candidate][0];
2327 rtlphy->reg_e9c = rege9c = result[final_candidate][1];
2328 regea4 = result[final_candidate][2];
2329 regeac = result[final_candidate][3];
2330 rtlphy->reg_eb4 = regeb4 = result[final_candidate][4];
2331 rtlphy->reg_ebc = regebc = result[final_candidate][5];
2332 regec4 = result[final_candidate][6];
2333 regecc = result[final_candidate][7];
2334 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2335 "IQK: final_candidate is %x\n", final_candidate);
2336 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2337 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2338 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2339 regecc);
2340 patha_ok = pathb_ok = true;
2341 } else {
2342 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
2343 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
2344 }
2345 if ((rege94 != 0) )
2346 _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result,
2347 final_candidate, (regea4 == 0));
2348 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2349 if ((regeb4 != 0) )
2350 _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result,
2351 final_candidate, (regec4 == 0));
2352 }
2353 if (final_candidate != 0xFF) {
2354 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(
2355 rtlphy->current_channel);
2356
2357 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2358 rtlphy->iqk_matrix[indexforchannel].
2359 value[0][i] = result[final_candidate][i];
2360 rtlphy->iqk_matrix[indexforchannel].iqk_done =
2361 true;
2362
2363 RT_TRACE(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD,
2364 "IQK OK indexforchannel %d\n", indexforchannel);
2365 }
2366}
2367
2368void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel)
2369{
2370 struct rtl_priv *rtlpriv = rtl_priv(hw);
2371 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2372 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2373 u8 indexforchannel;
2374
2375 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel);
2376
2377 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
2378 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n",
2379 indexforchannel,
2380 rtlphy->iqk_matrix[indexforchannel].iqk_done);
2381 if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done &&
2382 rtlphy->need_iqk) {
2383
2384 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD,
2385 "Do IQK Matrix reg for channel:%d....\n", channel);
2386 rtl92d_phy_iq_calibrate(hw);
2387 } else {
2388
2389
2390 if (((!rtlhal->load_imrandiqk_setting_for2g) &&
2391 indexforchannel == 0) || indexforchannel > 0) {
2392 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
2393 "Just Read IQK Matrix reg for channel:%d....\n",
2394 channel);
2395 if ((rtlphy->iqk_matrix[indexforchannel].
2396 value[0] != NULL)
2397 )
2398 _rtl92d_phy_patha_fill_iqk_matrix(hw, true,
2399 rtlphy->iqk_matrix[
2400 indexforchannel].value, 0,
2401 (rtlphy->iqk_matrix[
2402 indexforchannel].value[0][2] == 0));
2403 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2404 if ((rtlphy->iqk_matrix[
2405 indexforchannel].value[0][4] != 0)
2406 )
2407 _rtl92d_phy_pathb_fill_iqk_matrix(hw,
2408 true,
2409 rtlphy->iqk_matrix[
2410 indexforchannel].value, 0,
2411 (rtlphy->iqk_matrix[
2412 indexforchannel].value[0][6]
2413 == 0));
2414 }
2415 }
2416 }
2417 rtlphy->need_iqk = false;
2418 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2419}
2420
2421static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2)
2422{
2423 u32 ret;
2424
2425 if (val1 >= val2)
2426 ret = val1 - val2;
2427 else
2428 ret = val2 - val1;
2429 return ret;
2430}
2431
2432static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel)
2433{
2434
2435 int i;
2436
2437 for (i = 0; i < sizeof(channel5g); i++)
2438 if (channel == channel5g[i])
2439 return true;
2440 return false;
2441}
2442
2443static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw,
2444 u32 *targetchnl, u32 * curvecount_val,
2445 bool is5g, u32 *curveindex)
2446{
2447 struct rtl_priv *rtlpriv = rtl_priv(hw);
2448 u32 smallest_abs_val = 0xffffffff, u4tmp;
2449 u8 i, j;
2450 u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G;
2451
2452 for (i = 0; i < chnl_num; i++) {
2453 if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1))
2454 continue;
2455 curveindex[i] = 0;
2456 for (j = 0; j < (CV_CURVE_CNT * 2); j++) {
2457 u4tmp = _rtl92d_phy_get_abs(targetchnl[i],
2458 curvecount_val[j]);
2459
2460 if (u4tmp < smallest_abs_val) {
2461 curveindex[i] = j;
2462 smallest_abs_val = u4tmp;
2463 }
2464 }
2465 smallest_abs_val = 0xffffffff;
2466 RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n",
2467 i, curveindex[i]);
2468 }
2469}
2470
2471static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2472 u8 channel)
2473{
2474 struct rtl_priv *rtlpriv = rtl_priv(hw);
2475 u8 erfpath = rtlpriv->rtlhal.current_bandtype ==
2476 BAND_ON_5G ? RF90_PATH_A :
2477 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ?
2478 RF90_PATH_B : RF90_PATH_A;
2479 u32 u4tmp = 0, u4regvalue = 0;
2480 bool bneed_powerdown_radio = false;
2481
2482 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath);
2483 RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n",
2484 rtlpriv->rtlhal.current_bandtype);
2485 RTPRINT(rtlpriv, FINIT, INIT_IQK, "channel = %d\n", channel);
2486 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
2487 u4tmp = curveindex_5g[channel-1];
2488 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2489 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
2490 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2491 rtlpriv->rtlhal.interfaceindex == 1) {
2492 bneed_powerdown_radio =
2493 rtl92d_phy_enable_anotherphy(hw, false);
2494 rtlpriv->rtlhal.during_mac1init_radioa = true;
2495
2496 if (bneed_powerdown_radio)
2497 _rtl92d_phy_enable_rf_env(hw, erfpath,
2498 &u4regvalue);
2499 }
2500 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2501 if (bneed_powerdown_radio)
2502 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2503 if (rtlpriv->rtlhal.during_mac1init_radioa)
2504 rtl92d_phy_powerdown_anotherphy(hw, false);
2505 } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) {
2506 u4tmp = curveindex_2g[channel-1];
2507 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2508 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
2509 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2510 rtlpriv->rtlhal.interfaceindex == 0) {
2511 bneed_powerdown_radio =
2512 rtl92d_phy_enable_anotherphy(hw, true);
2513 rtlpriv->rtlhal.during_mac0init_radiob = true;
2514 if (bneed_powerdown_radio)
2515 _rtl92d_phy_enable_rf_env(hw, erfpath,
2516 &u4regvalue);
2517 }
2518 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2519 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2520 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
2521 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800));
2522 if (bneed_powerdown_radio)
2523 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2524 if (rtlpriv->rtlhal.during_mac0init_radiob)
2525 rtl92d_phy_powerdown_anotherphy(hw, true);
2526 }
2527 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2528}
2529
2530static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2531{
2532 struct rtl_priv *rtlpriv = rtl_priv(hw);
2533 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2534 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2535 u8 tmpreg, index, rf_mode[2];
2536 u8 path = is2t ? 2 : 1;
2537 u8 i;
2538 u32 u4tmp, offset;
2539 u32 curvecount_val[CV_CURVE_CNT * 2] = {0};
2540 u16 timeout = 800, timecount = 0;
2541
2542
2543 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2544
2545
2546 if ((tmpreg & 0x70) != 0)
2547 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2548 else
2549 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2550 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F);
2551 for (index = 0; index < path; index++) {
2552
2553 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2554 rf_mode[index] = rtl_read_byte(rtlpriv, offset);
2555
2556 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
2557 RFREG_OFFSET_MASK, 0x010000);
2558 if (rtlpci->init_ready) {
2559
2560 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2561 BIT(17), 0x0);
2562
2563 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2564 0x08000, 0x01);
2565 }
2566 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
2567 RFREG_OFFSET_MASK);
2568 while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
2569 mdelay(50);
2570 timecount += 50;
2571 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
2572 RF_SYN_G6, RFREG_OFFSET_MASK);
2573 }
2574 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2575 "PHY_LCK finish delay for %d ms=2\n", timecount);
2576 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK);
2577 if (index == 0 && rtlhal->interfaceindex == 0) {
2578 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2579 "path-A / 5G LCK\n");
2580 } else {
2581 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2582 "path-B / 2.4G LCK\n");
2583 }
2584 memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2);
2585
2586 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2587 0x08000, 0x0);
2588 RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n");
2589
2590 for (i = 0; i < CV_CURVE_CNT; i++) {
2591 u32 readval = 0, readval2 = 0;
2592 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F,
2593 0x7f, i);
2594
2595 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2596 RFREG_OFFSET_MASK, 0x0);
2597 readval = rtl_get_rfreg(hw, (enum radio_path)index,
2598 0x4F, RFREG_OFFSET_MASK);
2599 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2600
2601
2602 readval2 = rtl_get_rfreg(hw, (enum radio_path)index,
2603 0x50, 0xffc00);
2604 curvecount_val[2 * i] = (((readval & 0x1F) << 10) |
2605 readval2);
2606 }
2607 if (index == 0 && rtlhal->interfaceindex == 0)
2608 _rtl92d_phy_calc_curvindex(hw, targetchnl_5g,
2609 curvecount_val,
2610 true, curveindex_5g);
2611 else
2612 _rtl92d_phy_calc_curvindex(hw, targetchnl_2g,
2613 curvecount_val,
2614 false, curveindex_2g);
2615
2616 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2617 BIT(17), 0x1);
2618 }
2619
2620
2621 for (index = 0; index < path; index++) {
2622 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2623 rtl_write_byte(rtlpriv, offset, 0x50);
2624 rtl_write_byte(rtlpriv, offset, rf_mode[index]);
2625 }
2626 if ((tmpreg & 0x70) != 0)
2627 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2628 else
2629 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2630 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00);
2631 _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel);
2632}
2633
2634static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2635{
2636 struct rtl_priv *rtlpriv = rtl_priv(hw);
2637
2638 RTPRINT(rtlpriv, FINIT, INIT_IQK, "cosa PHY_LCK ver=2\n");
2639 _rtl92d_phy_lc_calibrate_sw(hw, is2t);
2640}
2641
2642void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw)
2643{
2644 struct rtl_priv *rtlpriv = rtl_priv(hw);
2645 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2646 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2647 u32 timeout = 2000, timecount = 0;
2648
2649 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2650 udelay(50);
2651 timecount += 50;
2652 }
2653
2654 rtlphy->lck_inprogress = true;
2655 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2656 "LCK:Start!!! currentband %x delay %d ms\n",
2657 rtlhal->current_bandtype, timecount);
2658 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2659 _rtl92d_phy_lc_calibrate(hw, true);
2660 } else {
2661
2662 _rtl92d_phy_lc_calibrate(hw, false);
2663 }
2664 rtlphy->lck_inprogress = false;
2665 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LCK:Finish!!!\n");
2666}
2667
2668void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
2669{
2670 return;
2671}
2672
2673static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
2674 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
2675 u32 para1, u32 para2, u32 msdelay)
2676{
2677 struct swchnlcmd *pcmd;
2678
2679 if (cmdtable == NULL) {
2680 WARN_ONCE(true, "rtl8192de: cmdtable cannot be NULL\n");
2681 return false;
2682 }
2683 if (cmdtableidx >= cmdtablesz)
2684 return false;
2685
2686 pcmd = cmdtable + cmdtableidx;
2687 pcmd->cmdid = cmdid;
2688 pcmd->para1 = para1;
2689 pcmd->para2 = para2;
2690 pcmd->msdelay = msdelay;
2691 return true;
2692}
2693
2694void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw)
2695{
2696 struct rtl_priv *rtlpriv = rtl_priv(hw);
2697 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2698 u8 i;
2699
2700 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2701 "settings regs %d default regs %d\n",
2702 (int)(sizeof(rtlphy->iqk_matrix) /
2703 sizeof(struct iqk_matrix_regs)),
2704 IQK_MATRIX_REG_NUM);
2705
2706 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
2707 rtlphy->iqk_matrix[i].value[0][0] = 0x100;
2708 rtlphy->iqk_matrix[i].value[0][2] = 0x100;
2709 rtlphy->iqk_matrix[i].value[0][4] = 0x100;
2710 rtlphy->iqk_matrix[i].value[0][6] = 0x100;
2711 rtlphy->iqk_matrix[i].value[0][1] = 0x0;
2712 rtlphy->iqk_matrix[i].value[0][3] = 0x0;
2713 rtlphy->iqk_matrix[i].value[0][5] = 0x0;
2714 rtlphy->iqk_matrix[i].value[0][7] = 0x0;
2715 rtlphy->iqk_matrix[i].iqk_done = false;
2716 }
2717}
2718
2719static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
2720 u8 channel, u8 *stage, u8 *step,
2721 u32 *delay)
2722{
2723 struct rtl_priv *rtlpriv = rtl_priv(hw);
2724 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2725 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
2726 u32 precommoncmdcnt;
2727 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
2728 u32 postcommoncmdcnt;
2729 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
2730 u32 rfdependcmdcnt;
2731 struct swchnlcmd *currentcmd = NULL;
2732 u8 rfpath;
2733 u8 num_total_rfpath = rtlphy->num_total_rfpath;
2734
2735 precommoncmdcnt = 0;
2736 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2737 MAX_PRECMD_CNT,
2738 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
2739 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2740 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
2741 postcommoncmdcnt = 0;
2742 _rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
2743 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
2744 rfdependcmdcnt = 0;
2745 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2746 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
2747 RF_CHNLBW, channel, 0);
2748 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2749 MAX_RFDEPENDCMD_CNT, CMDID_END,
2750 0, 0, 0);
2751
2752 do {
2753 switch (*stage) {
2754 case 0:
2755 currentcmd = &precommoncmd[*step];
2756 break;
2757 case 1:
2758 currentcmd = &rfdependcmd[*step];
2759 break;
2760 case 2:
2761 currentcmd = &postcommoncmd[*step];
2762 break;
2763 }
2764 if (currentcmd->cmdid == CMDID_END) {
2765 if ((*stage) == 2) {
2766 return true;
2767 } else {
2768 (*stage)++;
2769 (*step) = 0;
2770 continue;
2771 }
2772 }
2773 switch (currentcmd->cmdid) {
2774 case CMDID_SET_TXPOWEROWER_LEVEL:
2775 rtl92d_phy_set_txpower_level(hw, channel);
2776 break;
2777 case CMDID_WRITEPORT_ULONG:
2778 rtl_write_dword(rtlpriv, currentcmd->para1,
2779 currentcmd->para2);
2780 break;
2781 case CMDID_WRITEPORT_USHORT:
2782 rtl_write_word(rtlpriv, currentcmd->para1,
2783 (u16)currentcmd->para2);
2784 break;
2785 case CMDID_WRITEPORT_UCHAR:
2786 rtl_write_byte(rtlpriv, currentcmd->para1,
2787 (u8)currentcmd->para2);
2788 break;
2789 case CMDID_RF_WRITEREG:
2790 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
2791 rtlphy->rfreg_chnlval[rfpath] =
2792 ((rtlphy->rfreg_chnlval[rfpath] &
2793 0xffffff00) | currentcmd->para2);
2794 if (rtlpriv->rtlhal.current_bandtype ==
2795 BAND_ON_5G) {
2796 if (currentcmd->para2 > 99)
2797 rtlphy->rfreg_chnlval[rfpath] =
2798 rtlphy->rfreg_chnlval
2799 [rfpath] | (BIT(18));
2800 else
2801 rtlphy->rfreg_chnlval[rfpath] =
2802 rtlphy->rfreg_chnlval
2803 [rfpath] & (~BIT(18));
2804 rtlphy->rfreg_chnlval[rfpath] |=
2805 (BIT(16) | BIT(8));
2806 } else {
2807 rtlphy->rfreg_chnlval[rfpath] &=
2808 ~(BIT(8) | BIT(16) | BIT(18));
2809 }
2810 rtl_set_rfreg(hw, (enum radio_path)rfpath,
2811 currentcmd->para1,
2812 RFREG_OFFSET_MASK,
2813 rtlphy->rfreg_chnlval[rfpath]);
2814 _rtl92d_phy_reload_imr_setting(hw, channel,
2815 rfpath);
2816 }
2817 _rtl92d_phy_switch_rf_setting(hw, channel);
2818
2819 rtl92d_phy_reload_iqk_setting(hw, channel);
2820 break;
2821 default:
2822 pr_err("switch case %#x not processed\n",
2823 currentcmd->cmdid);
2824 break;
2825 }
2826 break;
2827 } while (true);
2828 (*delay) = currentcmd->msdelay;
2829 (*step)++;
2830 return false;
2831}
2832
2833u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
2834{
2835 struct rtl_priv *rtlpriv = rtl_priv(hw);
2836 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2837 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2838 u32 delay;
2839 u32 timeout = 1000, timecount = 0;
2840 u8 channel = rtlphy->current_channel;
2841 u32 ret_value;
2842
2843 if (rtlphy->sw_chnl_inprogress)
2844 return 0;
2845 if (rtlphy->set_bwmode_inprogress)
2846 return 0;
2847
2848 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
2849 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
2850 "sw_chnl_inprogress false driver sleep or unload\n");
2851 return 0;
2852 }
2853 while (rtlphy->lck_inprogress && timecount < timeout) {
2854 mdelay(50);
2855 timecount += 50;
2856 }
2857 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
2858 rtlhal->bandset == BAND_ON_BOTH) {
2859 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
2860 MASKDWORD);
2861 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
2862 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
2863 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
2864 rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G);
2865 }
2866 switch (rtlhal->current_bandtype) {
2867 case BAND_ON_5G:
2868
2869
2870 if (channel <= 14)
2871 return 0;
2872 WARN_ONCE((channel <= 14), "rtl8192de: 5G but channel<=14\n");
2873 break;
2874 case BAND_ON_2_4G:
2875
2876
2877 if (channel > 14)
2878 return 0;
2879 WARN_ONCE((channel > 14), "rtl8192de: 2G but channel>14\n");
2880 break;
2881 default:
2882 WARN_ONCE(true, "rtl8192de: Invalid WirelessMode(%#x)!!\n",
2883 rtlpriv->mac80211.mode);
2884 break;
2885 }
2886 rtlphy->sw_chnl_inprogress = true;
2887 if (channel == 0)
2888 channel = 1;
2889 rtlphy->sw_chnl_stage = 0;
2890 rtlphy->sw_chnl_step = 0;
2891 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
2892 "switch to channel%d\n", rtlphy->current_channel);
2893
2894 do {
2895 if (!rtlphy->sw_chnl_inprogress)
2896 break;
2897 if (!_rtl92d_phy_sw_chnl_step_by_step(hw,
2898 rtlphy->current_channel,
2899 &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) {
2900 if (delay > 0)
2901 mdelay(delay);
2902 else
2903 continue;
2904 } else {
2905 rtlphy->sw_chnl_inprogress = false;
2906 }
2907 break;
2908 } while (true);
2909 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
2910 rtlphy->sw_chnl_inprogress = false;
2911 return 1;
2912}
2913
2914static void rtl92d_phy_set_io(struct ieee80211_hw *hw)
2915{
2916 struct rtl_priv *rtlpriv = rtl_priv(hw);
2917 struct dig_t *de_digtable = &rtlpriv->dm_digtable;
2918 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2919
2920 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2921 "--->Cmd(%#x), set_io_inprogress(%d)\n",
2922 rtlphy->current_io_type, rtlphy->set_io_inprogress);
2923 switch (rtlphy->current_io_type) {
2924 case IO_CMD_RESUME_DM_BY_SCAN:
2925 de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
2926 rtl92d_dm_write_dig(hw);
2927 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
2928 break;
2929 case IO_CMD_PAUSE_DM_BY_SCAN:
2930 rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue;
2931 de_digtable->cur_igvalue = 0x37;
2932 rtl92d_dm_write_dig(hw);
2933 break;
2934 default:
2935 pr_err("switch case %#x not processed\n",
2936 rtlphy->current_io_type);
2937 break;
2938 }
2939 rtlphy->set_io_inprogress = false;
2940 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n",
2941 rtlphy->current_io_type);
2942}
2943
2944bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2945{
2946 struct rtl_priv *rtlpriv = rtl_priv(hw);
2947 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2948 bool postprocessing = false;
2949
2950 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2951 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2952 iotype, rtlphy->set_io_inprogress);
2953 do {
2954 switch (iotype) {
2955 case IO_CMD_RESUME_DM_BY_SCAN:
2956 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2957 "[IO CMD] Resume DM after scan\n");
2958 postprocessing = true;
2959 break;
2960 case IO_CMD_PAUSE_DM_BY_SCAN:
2961 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2962 "[IO CMD] Pause DM before scan\n");
2963 postprocessing = true;
2964 break;
2965 default:
2966 pr_err("switch case %#x not processed\n",
2967 iotype);
2968 break;
2969 }
2970 } while (false);
2971 if (postprocessing && !rtlphy->set_io_inprogress) {
2972 rtlphy->set_io_inprogress = true;
2973 rtlphy->current_io_type = iotype;
2974 } else {
2975 return false;
2976 }
2977 rtl92d_phy_set_io(hw);
2978 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
2979 return true;
2980}
2981
2982static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw)
2983{
2984 struct rtl_priv *rtlpriv = rtl_priv(hw);
2985
2986
2987
2988 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
2989 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
2990
2991 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2992
2993
2994 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2995
2996
2997 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2998 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2999
3000 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3001}
3002
3003static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
3004{
3005 struct rtl_priv *rtlpriv = rtl_priv(hw);
3006 u32 u4btmp;
3007 u8 delay = 5;
3008
3009
3010 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3011
3012 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3013
3014 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3015
3016
3017
3018
3019
3020 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3021 while (u4btmp != 0 && delay > 0) {
3022 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
3023 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3024 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3025 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3026 delay--;
3027 }
3028 if (delay == 0) {
3029
3030 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3031
3032 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3033 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3034 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3035 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3036 "Fail !!! Switch RF timeout\n");
3037 return;
3038 }
3039
3040 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3041
3042 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3043 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3044
3045}
3046
3047bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
3048 enum rf_pwrstate rfpwr_state)
3049{
3050
3051 bool bresult = true;
3052 struct rtl_priv *rtlpriv = rtl_priv(hw);
3053 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3054 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3055 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3056 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3057 u8 i, queue_id;
3058 struct rtl8192_tx_ring *ring = NULL;
3059
3060 if (rfpwr_state == ppsc->rfpwr_state)
3061 return false;
3062 switch (rfpwr_state) {
3063 case ERFON:
3064 if ((ppsc->rfpwr_state == ERFOFF) &&
3065 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3066 bool rtstatus;
3067 u32 initializecount = 0;
3068 do {
3069 initializecount++;
3070 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3071 "IPS Set eRf nic enable\n");
3072 rtstatus = rtl_ps_enable_nic(hw);
3073 } while (!rtstatus && (initializecount < 10));
3074
3075 RT_CLEAR_PS_LEVEL(ppsc,
3076 RT_RF_OFF_LEVL_HALT_NIC);
3077 } else {
3078 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3079 "awake, sleeped:%d ms state_inap:%x\n",
3080 jiffies_to_msecs(jiffies -
3081 ppsc->last_sleep_jiffies),
3082 rtlpriv->psc.state_inap);
3083 ppsc->last_awake_jiffies = jiffies;
3084 _rtl92d_phy_set_rfon(hw);
3085 }
3086
3087 if (mac->link_state == MAC80211_LINKED)
3088 rtlpriv->cfg->ops->led_control(hw,
3089 LED_CTL_LINK);
3090 else
3091 rtlpriv->cfg->ops->led_control(hw,
3092 LED_CTL_NO_LINK);
3093 break;
3094 case ERFOFF:
3095 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3096 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3097 "IPS Set eRf nic disable\n");
3098 rtl_ps_disable_nic(hw);
3099 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3100 } else {
3101 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
3102 rtlpriv->cfg->ops->led_control(hw,
3103 LED_CTL_NO_LINK);
3104 else
3105 rtlpriv->cfg->ops->led_control(hw,
3106 LED_CTL_POWER_OFF);
3107 }
3108 break;
3109 case ERFSLEEP:
3110 if (ppsc->rfpwr_state == ERFOFF)
3111 return false;
3112
3113 for (queue_id = 0, i = 0;
3114 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3115 ring = &pcipriv->dev.tx_ring[queue_id];
3116 if (skb_queue_len(&ring->queue) == 0 ||
3117 queue_id == BEACON_QUEUE) {
3118 queue_id++;
3119 continue;
3120 } else if (rtlpci->pdev->current_state != PCI_D0) {
3121 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3122 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n",
3123 i + 1, queue_id);
3124 break;
3125 } else {
3126 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3127 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3128 i + 1, queue_id,
3129 skb_queue_len(&ring->queue));
3130 udelay(10);
3131 i++;
3132 }
3133
3134 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3135 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3136 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
3137 MAX_DOZE_WAITING_TIMES_9x, queue_id,
3138 skb_queue_len(&ring->queue));
3139 break;
3140 }
3141 }
3142 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3143 "Set rfsleep awaked:%d ms\n",
3144 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
3145 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3146 "sleep awaked:%d ms state_inap:%x\n",
3147 jiffies_to_msecs(jiffies -
3148 ppsc->last_awake_jiffies),
3149 rtlpriv->psc.state_inap);
3150 ppsc->last_sleep_jiffies = jiffies;
3151 _rtl92d_phy_set_rfsleep(hw);
3152 break;
3153 default:
3154 pr_err("switch case %#x not processed\n",
3155 rfpwr_state);
3156 bresult = false;
3157 break;
3158 }
3159 if (bresult)
3160 ppsc->rfpwr_state = rfpwr_state;
3161 return bresult;
3162}
3163
3164void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw)
3165{
3166 struct rtl_priv *rtlpriv = rtl_priv(hw);
3167 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3168 u8 offset = REG_MAC_PHY_CTRL_NORMAL;
3169
3170 switch (rtlhal->macphymode) {
3171 case DUALMAC_DUALPHY:
3172 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3173 "MacPhyMode: DUALMAC_DUALPHY\n");
3174 rtl_write_byte(rtlpriv, offset, 0xF3);
3175 break;
3176 case SINGLEMAC_SINGLEPHY:
3177 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3178 "MacPhyMode: SINGLEMAC_SINGLEPHY\n");
3179 rtl_write_byte(rtlpriv, offset, 0xF4);
3180 break;
3181 case DUALMAC_SINGLEPHY:
3182 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3183 "MacPhyMode: DUALMAC_SINGLEPHY\n");
3184 rtl_write_byte(rtlpriv, offset, 0xF1);
3185 break;
3186 }
3187}
3188
3189void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw)
3190{
3191 struct rtl_priv *rtlpriv = rtl_priv(hw);
3192 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3193 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3194
3195 switch (rtlhal->macphymode) {
3196 case DUALMAC_SINGLEPHY:
3197 rtlphy->rf_type = RF_2T2R;
3198 rtlhal->version |= RF_TYPE_2T2R;
3199 rtlhal->bandset = BAND_ON_BOTH;
3200 rtlhal->current_bandtype = BAND_ON_2_4G;
3201 break;
3202
3203 case SINGLEMAC_SINGLEPHY:
3204 rtlphy->rf_type = RF_2T2R;
3205 rtlhal->version |= RF_TYPE_2T2R;
3206 rtlhal->bandset = BAND_ON_BOTH;
3207 rtlhal->current_bandtype = BAND_ON_2_4G;
3208 break;
3209
3210 case DUALMAC_DUALPHY:
3211 rtlphy->rf_type = RF_1T1R;
3212 rtlhal->version &= RF_TYPE_1T1R;
3213
3214 if (rtlhal->interfaceindex == 0) {
3215 rtlhal->bandset = BAND_ON_5G;
3216 rtlhal->current_bandtype = BAND_ON_5G;
3217 } else {
3218 rtlhal->bandset = BAND_ON_2_4G;
3219 rtlhal->current_bandtype = BAND_ON_2_4G;
3220 }
3221 break;
3222 default:
3223 break;
3224 }
3225}
3226
3227u8 rtl92d_get_chnlgroup_fromarray(u8 chnl)
3228{
3229 u8 group;
3230 u8 channel_info[59] = {
3231 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
3232 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56,
3233 58, 60, 62, 64, 100, 102, 104, 106, 108,
3234 110, 112, 114, 116, 118, 120, 122, 124,
3235 126, 128, 130, 132, 134, 136, 138, 140,
3236 149, 151, 153, 155, 157, 159, 161, 163,
3237 165
3238 };
3239
3240 if (channel_info[chnl] <= 3)
3241 group = 0;
3242 else if (channel_info[chnl] <= 9)
3243 group = 1;
3244 else if (channel_info[chnl] <= 14)
3245 group = 2;
3246 else if (channel_info[chnl] <= 44)
3247 group = 3;
3248 else if (channel_info[chnl] <= 54)
3249 group = 4;
3250 else if (channel_info[chnl] <= 64)
3251 group = 5;
3252 else if (channel_info[chnl] <= 112)
3253 group = 6;
3254 else if (channel_info[chnl] <= 126)
3255 group = 7;
3256 else if (channel_info[chnl] <= 140)
3257 group = 8;
3258 else if (channel_info[chnl] <= 153)
3259 group = 9;
3260 else if (channel_info[chnl] <= 159)
3261 group = 10;
3262 else
3263 group = 11;
3264 return group;
3265}
3266
3267void rtl92d_phy_set_poweron(struct ieee80211_hw *hw)
3268{
3269 struct rtl_priv *rtlpriv = rtl_priv(hw);
3270 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3271 unsigned long flags;
3272 u8 value8;
3273 u16 i;
3274 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
3275
3276
3277 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3278 value8 = rtl_read_byte(rtlpriv, mac_reg);
3279 value8 |= BIT(1);
3280 rtl_write_byte(rtlpriv, mac_reg, value8);
3281 } else {
3282 value8 = rtl_read_byte(rtlpriv, mac_reg);
3283 value8 &= (~BIT(1));
3284 rtl_write_byte(rtlpriv, mac_reg, value8);
3285 }
3286
3287 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3288 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3289 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3290 } else {
3291 spin_lock_irqsave(&globalmutex_power, flags);
3292 if (rtlhal->interfaceindex == 0) {
3293 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3294 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3295 } else {
3296 value8 = rtl_read_byte(rtlpriv, REG_MAC1);
3297 rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON);
3298 }
3299 value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3300 spin_unlock_irqrestore(&globalmutex_power, flags);
3301 for (i = 0; i < 200; i++) {
3302 if ((value8 & BIT(7)) == 0) {
3303 break;
3304 } else {
3305 udelay(500);
3306 spin_lock_irqsave(&globalmutex_power, flags);
3307 value8 = rtl_read_byte(rtlpriv,
3308 REG_POWER_OFF_IN_PROCESS);
3309 spin_unlock_irqrestore(&globalmutex_power,
3310 flags);
3311 }
3312 }
3313 if (i == 200)
3314 WARN_ONCE(true, "rtl8192de: Another mac power off over time\n");
3315 }
3316}
3317
3318void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw)
3319{
3320 struct rtl_priv *rtlpriv = rtl_priv(hw);
3321
3322 switch (rtlpriv->rtlhal.macphymode) {
3323 case DUALMAC_DUALPHY:
3324 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3325 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3326 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3327 break;
3328 case DUALMAC_SINGLEPHY:
3329 rtl_write_byte(rtlpriv, REG_DMC, 0xf8);
3330 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3331 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3332 break;
3333 case SINGLEMAC_SINGLEPHY:
3334 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3335 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10);
3336 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
3337 break;
3338 default:
3339 break;
3340 }
3341}
3342
3343void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3344{
3345 struct rtl_priv *rtlpriv = rtl_priv(hw);
3346 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3347 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3348 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3349 u8 rfpath, i;
3350
3351 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
3352
3353 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3354
3355 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0);
3356 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0);
3357 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3358 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0);
3359 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0);
3360 }
3361
3362 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
3363
3364 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
3365
3366 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3367
3368 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3369 0x40000100);
3370 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3371 0x40000100);
3372 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3373 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3374 BIT(10) | BIT(6) | BIT(5),
3375 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3376 (rtlefuse->eeprom_c9 & BIT(1)) |
3377 ((rtlefuse->eeprom_cc & BIT(1)) << 4));
3378 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3379 BIT(10) | BIT(6) | BIT(5),
3380 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3381 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3382 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3383 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0);
3384 } else {
3385 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3386 BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3387 BIT(6) | BIT(5),
3388 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3389 (rtlefuse->eeprom_c9 & BIT(1)) |
3390 ((rtlefuse->eeprom_cc & BIT(1)) << 4) |
3391 ((rtlefuse->eeprom_c9 & BIT(7)) << 9) |
3392 ((rtlefuse->eeprom_c9 & BIT(5)) << 12) |
3393 ((rtlefuse->eeprom_cc & BIT(3)) << 18));
3394 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3395 BIT(10) | BIT(6) | BIT(5),
3396 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3397 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3398 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3399 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
3400 BIT(10) | BIT(6) | BIT(5),
3401 ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) |
3402 ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) |
3403 ((rtlefuse->eeprom_cc & BIT(2)) << 3));
3404 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3405 BIT(31) | BIT(15), 0);
3406 }
3407
3408 } else {
3409
3410 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1);
3411 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1);
3412 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3413 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1);
3414 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1);
3415 }
3416
3417 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
3418
3419 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
3420
3421 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3422
3423 if (rtlefuse->internal_pa_5g[0])
3424 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3425 0x2d4000b5);
3426 else
3427 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3428 0x20000080);
3429 if (rtlefuse->internal_pa_5g[1])
3430 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3431 0x2d4000b5);
3432 else
3433 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3434 0x20000080);
3435 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3436 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3437 BIT(10) | BIT(6) | BIT(5),
3438 (rtlefuse->eeprom_cc & BIT(5)));
3439 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3440 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3441 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15),
3442 (rtlefuse->eeprom_cc & BIT(4)) >> 4);
3443 } else {
3444 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3445 BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3446 BIT(6) | BIT(5),
3447 (rtlefuse->eeprom_cc & BIT(5)) |
3448 ((rtlefuse->eeprom_cc & BIT(7)) << 14));
3449 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3450 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3451 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10),
3452 ((rtlefuse->eeprom_cc & BIT(6)) >> 6));
3453 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3454 BIT(31) | BIT(15),
3455 ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
3456 ((rtlefuse->eeprom_cc & BIT(6)) << 10));
3457 }
3458 }
3459
3460 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
3461 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
3462 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00);
3463 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3464 BIT(26) | BIT(24), 0x00);
3465 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00);
3466 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
3467 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
3468
3469
3470 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3471 rfpath++) {
3472 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3473
3474 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) |
3475 BIT(18), 0);
3476
3477 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
3478 0x1c000, 0x07);
3479 } else {
3480
3481 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) |
3482 BIT(16) | BIT(18),
3483 (BIT(16) | BIT(8)) >> 8);
3484 }
3485 }
3486
3487
3488 if (rtlphy->rf_type == RF_1T1R) {
3489
3490 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11);
3491 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
3492
3493
3494 if (rtlhal->interfaceindex == 0) {
3495 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) |
3496 BIT(13), 0x3);
3497 } else {
3498 rtl92d_phy_enable_anotherphy(hw, false);
3499 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3500 "MAC1 use DBI to update 0x888\n");
3501
3502 rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN,
3503 rtl92de_read_dword_dbi(hw,
3504 RFPGA0_ADDALLOCKEN,
3505 BIT(3)) | BIT(12) | BIT(13),
3506 BIT(3));
3507 rtl92d_phy_powerdown_anotherphy(hw, false);
3508 }
3509 } else {
3510
3511
3512 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33);
3513 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
3514
3515 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
3516 }
3517 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3518 rfpath++) {
3519 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
3520 RF_CHNLBW, RFREG_OFFSET_MASK);
3521 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
3522 RFREG_OFFSET_MASK);
3523 }
3524 for (i = 0; i < 2; i++)
3525 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n",
3526 rtlphy->rfreg_chnlval[i]);
3527 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n");
3528
3529}
3530
3531bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw)
3532{
3533 struct rtl_priv *rtlpriv = rtl_priv(hw);
3534 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3535 u8 u1btmp;
3536 unsigned long flags;
3537
3538 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3539 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3540 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3541 return true;
3542 }
3543 spin_lock_irqsave(&globalmutex_power, flags);
3544 if (rtlhal->interfaceindex == 0) {
3545 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3546 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3547 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3548 u1btmp &= MAC1_ON;
3549 } else {
3550 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3551 rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON));
3552 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3553 u1btmp &= MAC0_ON;
3554 }
3555 if (u1btmp) {
3556 spin_unlock_irqrestore(&globalmutex_power, flags);
3557 return false;
3558 }
3559 u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3560 u1btmp |= BIT(7);
3561 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp);
3562 spin_unlock_irqrestore(&globalmutex_power, flags);
3563 return true;
3564}
3565
