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20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/of.h>
23#include <linux/io.h>
24#include <linux/err.h>
25#include <linux/clk.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/phy/phy.h>
29
30#define PHY_28NM_HSIC_CTRL 0x08
31#define PHY_28NM_HSIC_IMPCAL_CAL 0x18
32#define PHY_28NM_HSIC_PLL_CTRL01 0x1c
33#define PHY_28NM_HSIC_PLL_CTRL2 0x20
34#define PHY_28NM_HSIC_INT 0x28
35
36#define PHY_28NM_HSIC_PLL_SELLPFR_SHIFT 26
37#define PHY_28NM_HSIC_PLL_FBDIV_SHIFT 0
38#define PHY_28NM_HSIC_PLL_REFDIV_SHIFT 9
39
40#define PHY_28NM_HSIC_S2H_PU_PLL BIT(10)
41#define PHY_28NM_HSIC_H2S_PLL_LOCK BIT(15)
42#define PHY_28NM_HSIC_S2H_HSIC_EN BIT(7)
43#define S2H_DRV_SE0_4RESUME BIT(14)
44#define PHY_28NM_HSIC_H2S_IMPCAL_DONE BIT(27)
45
46#define PHY_28NM_HSIC_CONNECT_INT BIT(1)
47#define PHY_28NM_HSIC_HS_READY_INT BIT(2)
48
49struct mv_hsic_phy {
50 struct phy *phy;
51 struct platform_device *pdev;
52 void __iomem *base;
53 struct clk *clk;
54};
55
56static bool wait_for_reg(void __iomem *reg, u32 mask, unsigned long timeout)
57{
58 timeout += jiffies;
59 while (time_is_after_eq_jiffies(timeout)) {
60 if ((readl(reg) & mask) == mask)
61 return true;
62 msleep(1);
63 }
64 return false;
65}
66
67static int mv_hsic_phy_init(struct phy *phy)
68{
69 struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy);
70 struct platform_device *pdev = mv_phy->pdev;
71 void __iomem *base = mv_phy->base;
72
73 clk_prepare_enable(mv_phy->clk);
74
75
76 writel(0x1 << PHY_28NM_HSIC_PLL_SELLPFR_SHIFT |
77 0xf0 << PHY_28NM_HSIC_PLL_FBDIV_SHIFT |
78 0xd << PHY_28NM_HSIC_PLL_REFDIV_SHIFT,
79 base + PHY_28NM_HSIC_PLL_CTRL01);
80
81
82 writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) |
83 PHY_28NM_HSIC_S2H_PU_PLL,
84 base + PHY_28NM_HSIC_PLL_CTRL2);
85
86
87 if (!wait_for_reg(base + PHY_28NM_HSIC_PLL_CTRL2,
88 PHY_28NM_HSIC_H2S_PLL_LOCK, HZ / 10)) {
89 dev_err(&pdev->dev, "HSIC PHY PLL not locked after 100mS.");
90 clk_disable_unprepare(mv_phy->clk);
91 return -ETIMEDOUT;
92 }
93
94 return 0;
95}
96
97static int mv_hsic_phy_power_on(struct phy *phy)
98{
99 struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy);
100 struct platform_device *pdev = mv_phy->pdev;
101 void __iomem *base = mv_phy->base;
102 u32 reg;
103
104 reg = readl(base + PHY_28NM_HSIC_CTRL);
105
106 reg &= ~S2H_DRV_SE0_4RESUME;
107 reg |= PHY_28NM_HSIC_S2H_HSIC_EN;
108 writel(reg, base + PHY_28NM_HSIC_CTRL);
109
110
111
112
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114
115
116
117
118
119
120 if (!wait_for_reg(base + PHY_28NM_HSIC_IMPCAL_CAL,
121 PHY_28NM_HSIC_H2S_IMPCAL_DONE, HZ / 10)) {
122 dev_warn(&pdev->dev, "HSIC PHY READY not set after 100mS.");
123 return -ETIMEDOUT;
124 }
125
126
127 if (!wait_for_reg(base + PHY_28NM_HSIC_INT,
128 PHY_28NM_HSIC_CONNECT_INT, HZ / 5)) {
129 dev_warn(&pdev->dev, "HSIC wait for connect interrupt timeout.");
130 return -ETIMEDOUT;
131 }
132
133 return 0;
134}
135
136static int mv_hsic_phy_power_off(struct phy *phy)
137{
138 struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy);
139 void __iomem *base = mv_phy->base;
140
141 writel(readl(base + PHY_28NM_HSIC_CTRL) & ~PHY_28NM_HSIC_S2H_HSIC_EN,
142 base + PHY_28NM_HSIC_CTRL);
143
144 return 0;
145}
146
147static int mv_hsic_phy_exit(struct phy *phy)
148{
149 struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy);
150 void __iomem *base = mv_phy->base;
151
152
153 writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) &
154 ~PHY_28NM_HSIC_S2H_PU_PLL,
155 base + PHY_28NM_HSIC_PLL_CTRL2);
156
157 clk_disable_unprepare(mv_phy->clk);
158 return 0;
159}
160
161
162static const struct phy_ops hsic_ops = {
163 .init = mv_hsic_phy_init,
164 .power_on = mv_hsic_phy_power_on,
165 .power_off = mv_hsic_phy_power_off,
166 .exit = mv_hsic_phy_exit,
167 .owner = THIS_MODULE,
168};
169
170static int mv_hsic_phy_probe(struct platform_device *pdev)
171{
172 struct phy_provider *phy_provider;
173 struct mv_hsic_phy *mv_phy;
174 struct resource *r;
175
176 mv_phy = devm_kzalloc(&pdev->dev, sizeof(*mv_phy), GFP_KERNEL);
177 if (!mv_phy)
178 return -ENOMEM;
179
180 mv_phy->pdev = pdev;
181
182 mv_phy->clk = devm_clk_get(&pdev->dev, NULL);
183 if (IS_ERR(mv_phy->clk)) {
184 dev_err(&pdev->dev, "failed to get clock.\n");
185 return PTR_ERR(mv_phy->clk);
186 }
187
188 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
189 mv_phy->base = devm_ioremap_resource(&pdev->dev, r);
190 if (IS_ERR(mv_phy->base))
191 return PTR_ERR(mv_phy->base);
192
193 mv_phy->phy = devm_phy_create(&pdev->dev, pdev->dev.of_node, &hsic_ops);
194 if (IS_ERR(mv_phy->phy))
195 return PTR_ERR(mv_phy->phy);
196
197 phy_set_drvdata(mv_phy->phy, mv_phy);
198
199 phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
200 return PTR_ERR_OR_ZERO(phy_provider);
201}
202
203static const struct of_device_id mv_hsic_phy_dt_match[] = {
204 { .compatible = "marvell,pxa1928-hsic-phy", },
205 {},
206};
207MODULE_DEVICE_TABLE(of, mv_hsic_phy_dt_match);
208
209static struct platform_driver mv_hsic_phy_driver = {
210 .probe = mv_hsic_phy_probe,
211 .driver = {
212 .name = "mv-hsic-phy",
213 .of_match_table = of_match_ptr(mv_hsic_phy_dt_match),
214 },
215};
216module_platform_driver(mv_hsic_phy_driver);
217
218MODULE_AUTHOR("Rob Herring <robh@kernel.org>");
219MODULE_DESCRIPTION("Marvell HSIC phy driver");
220MODULE_LICENSE("GPL v2");
221
