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10
11#undef DEBUG
12#undef DEBUGDATA
13#undef DEBUGCCW
14
15#define KMSG_COMPONENT "ctcm"
16#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
17
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/slab.h>
22#include <linux/errno.h>
23#include <linux/types.h>
24#include <linux/interrupt.h>
25#include <linux/timer.h>
26#include <linux/bitops.h>
27
28#include <linux/signal.h>
29#include <linux/string.h>
30
31#include <linux/ip.h>
32#include <linux/if_arp.h>
33#include <linux/tcp.h>
34#include <linux/skbuff.h>
35#include <linux/ctype.h>
36#include <net/dst.h>
37
38#include <linux/io.h>
39#include <asm/ccwdev.h>
40#include <asm/ccwgroup.h>
41#include <linux/uaccess.h>
42
43#include <asm/idals.h>
44
45#include "fsm.h"
46
47#include "ctcm_dbug.h"
48#include "ctcm_main.h"
49#include "ctcm_fsms.h"
50
51const char *dev_state_names[] = {
52 [DEV_STATE_STOPPED] = "Stopped",
53 [DEV_STATE_STARTWAIT_RXTX] = "StartWait RXTX",
54 [DEV_STATE_STARTWAIT_RX] = "StartWait RX",
55 [DEV_STATE_STARTWAIT_TX] = "StartWait TX",
56 [DEV_STATE_STOPWAIT_RXTX] = "StopWait RXTX",
57 [DEV_STATE_STOPWAIT_RX] = "StopWait RX",
58 [DEV_STATE_STOPWAIT_TX] = "StopWait TX",
59 [DEV_STATE_RUNNING] = "Running",
60};
61
62const char *dev_event_names[] = {
63 [DEV_EVENT_START] = "Start",
64 [DEV_EVENT_STOP] = "Stop",
65 [DEV_EVENT_RXUP] = "RX up",
66 [DEV_EVENT_TXUP] = "TX up",
67 [DEV_EVENT_RXDOWN] = "RX down",
68 [DEV_EVENT_TXDOWN] = "TX down",
69 [DEV_EVENT_RESTART] = "Restart",
70};
71
72const char *ctc_ch_event_names[] = {
73 [CTC_EVENT_IO_SUCCESS] = "ccw_device success",
74 [CTC_EVENT_IO_EBUSY] = "ccw_device busy",
75 [CTC_EVENT_IO_ENODEV] = "ccw_device enodev",
76 [CTC_EVENT_IO_UNKNOWN] = "ccw_device unknown",
77 [CTC_EVENT_ATTNBUSY] = "Status ATTN & BUSY",
78 [CTC_EVENT_ATTN] = "Status ATTN",
79 [CTC_EVENT_BUSY] = "Status BUSY",
80 [CTC_EVENT_UC_RCRESET] = "Unit check remote reset",
81 [CTC_EVENT_UC_RSRESET] = "Unit check remote system reset",
82 [CTC_EVENT_UC_TXTIMEOUT] = "Unit check TX timeout",
83 [CTC_EVENT_UC_TXPARITY] = "Unit check TX parity",
84 [CTC_EVENT_UC_HWFAIL] = "Unit check Hardware failure",
85 [CTC_EVENT_UC_RXPARITY] = "Unit check RX parity",
86 [CTC_EVENT_UC_ZERO] = "Unit check ZERO",
87 [CTC_EVENT_UC_UNKNOWN] = "Unit check Unknown",
88 [CTC_EVENT_SC_UNKNOWN] = "SubChannel check Unknown",
89 [CTC_EVENT_MC_FAIL] = "Machine check failure",
90 [CTC_EVENT_MC_GOOD] = "Machine check operational",
91 [CTC_EVENT_IRQ] = "IRQ normal",
92 [CTC_EVENT_FINSTAT] = "IRQ final",
93 [CTC_EVENT_TIMER] = "Timer",
94 [CTC_EVENT_START] = "Start",
95 [CTC_EVENT_STOP] = "Stop",
96
97
98
99 [CTC_EVENT_SEND_XID] = "XID Exchange",
100 [CTC_EVENT_RSWEEP_TIMER] = "MPC Group Sweep Timer",
101};
102
103const char *ctc_ch_state_names[] = {
104 [CTC_STATE_IDLE] = "Idle",
105 [CTC_STATE_STOPPED] = "Stopped",
106 [CTC_STATE_STARTWAIT] = "StartWait",
107 [CTC_STATE_STARTRETRY] = "StartRetry",
108 [CTC_STATE_SETUPWAIT] = "SetupWait",
109 [CTC_STATE_RXINIT] = "RX init",
110 [CTC_STATE_TXINIT] = "TX init",
111 [CTC_STATE_RX] = "RX",
112 [CTC_STATE_TX] = "TX",
113 [CTC_STATE_RXIDLE] = "RX idle",
114 [CTC_STATE_TXIDLE] = "TX idle",
115 [CTC_STATE_RXERR] = "RX error",
116 [CTC_STATE_TXERR] = "TX error",
117 [CTC_STATE_TERM] = "Terminating",
118 [CTC_STATE_DTERM] = "Restarting",
119 [CTC_STATE_NOTOP] = "Not operational",
120
121
122
123 [CH_XID0_PENDING] = "Pending XID0 Start",
124 [CH_XID0_INPROGRESS] = "In XID0 Negotiations ",
125 [CH_XID7_PENDING] = "Pending XID7 P1 Start",
126 [CH_XID7_PENDING1] = "Active XID7 P1 Exchange ",
127 [CH_XID7_PENDING2] = "Pending XID7 P2 Start ",
128 [CH_XID7_PENDING3] = "Active XID7 P2 Exchange ",
129 [CH_XID7_PENDING4] = "XID7 Complete - Pending READY ",
130};
131
132static void ctcm_action_nop(fsm_instance *fi, int event, void *arg);
133
134
135
136
137
138static void chx_txdone(fsm_instance *fi, int event, void *arg);
139static void chx_rx(fsm_instance *fi, int event, void *arg);
140static void chx_rxidle(fsm_instance *fi, int event, void *arg);
141static void chx_firstio(fsm_instance *fi, int event, void *arg);
142static void ctcm_chx_setmode(fsm_instance *fi, int event, void *arg);
143static void ctcm_chx_start(fsm_instance *fi, int event, void *arg);
144static void ctcm_chx_haltio(fsm_instance *fi, int event, void *arg);
145static void ctcm_chx_stopped(fsm_instance *fi, int event, void *arg);
146static void ctcm_chx_stop(fsm_instance *fi, int event, void *arg);
147static void ctcm_chx_fail(fsm_instance *fi, int event, void *arg);
148static void ctcm_chx_setuperr(fsm_instance *fi, int event, void *arg);
149static void ctcm_chx_restart(fsm_instance *fi, int event, void *arg);
150static void ctcm_chx_rxiniterr(fsm_instance *fi, int event, void *arg);
151static void ctcm_chx_rxinitfail(fsm_instance *fi, int event, void *arg);
152static void ctcm_chx_rxdisc(fsm_instance *fi, int event, void *arg);
153static void ctcm_chx_txiniterr(fsm_instance *fi, int event, void *arg);
154static void ctcm_chx_txretry(fsm_instance *fi, int event, void *arg);
155static void ctcm_chx_iofatal(fsm_instance *fi, int event, void *arg);
156
157
158
159
160
161static void ctcmpc_chx_txdone(fsm_instance *fi, int event, void *arg);
162static void ctcmpc_chx_rx(fsm_instance *fi, int event, void *arg);
163static void ctcmpc_chx_firstio(fsm_instance *fi, int event, void *arg);
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180static void ctcmpc_chx_attn(fsm_instance *fsm, int event, void *arg);
181static void ctcmpc_chx_attnbusy(fsm_instance *, int, void *);
182static void ctcmpc_chx_resend(fsm_instance *, int, void *);
183static void ctcmpc_chx_send_sweep(fsm_instance *fsm, int event, void *arg);
184
185
186
187
188
189
190
191void ctcm_ccw_check_rc(struct channel *ch, int rc, char *msg)
192{
193 CTCM_DBF_TEXT_(ERROR, CTC_DBF_ERROR,
194 "%s(%s): %s: %04x\n",
195 CTCM_FUNTAIL, ch->id, msg, rc);
196 switch (rc) {
197 case -EBUSY:
198 pr_info("%s: The communication peer is busy\n",
199 ch->id);
200 fsm_event(ch->fsm, CTC_EVENT_IO_EBUSY, ch);
201 break;
202 case -ENODEV:
203 pr_err("%s: The specified target device is not valid\n",
204 ch->id);
205 fsm_event(ch->fsm, CTC_EVENT_IO_ENODEV, ch);
206 break;
207 default:
208 pr_err("An I/O operation resulted in error %04x\n",
209 rc);
210 fsm_event(ch->fsm, CTC_EVENT_IO_UNKNOWN, ch);
211 }
212}
213
214void ctcm_purge_skb_queue(struct sk_buff_head *q)
215{
216 struct sk_buff *skb;
217
218 CTCM_DBF_TEXT(TRACE, CTC_DBF_DEBUG, __func__);
219
220 while ((skb = skb_dequeue(q))) {
221 refcount_dec(&skb->users);
222 dev_kfree_skb_any(skb);
223 }
224}
225
226
227
228
229static void ctcm_action_nop(fsm_instance *fi, int event, void *arg)
230{
231}
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246static void chx_txdone(fsm_instance *fi, int event, void *arg)
247{
248 struct channel *ch = arg;
249 struct net_device *dev = ch->netdev;
250 struct ctcm_priv *priv = dev->ml_priv;
251 struct sk_buff *skb;
252 int first = 1;
253 int i;
254 unsigned long duration;
255 unsigned long done_stamp = jiffies;
256
257 CTCM_PR_DEBUG("%s(%s): %s\n", __func__, ch->id, dev->name);
258
259 duration = done_stamp - ch->prof.send_stamp;
260 if (duration > ch->prof.tx_time)
261 ch->prof.tx_time = duration;
262
263 if (ch->irb->scsw.cmd.count != 0)
264 CTCM_DBF_TEXT_(TRACE, CTC_DBF_DEBUG,
265 "%s(%s): TX not complete, remaining %d bytes",
266 CTCM_FUNTAIL, dev->name, ch->irb->scsw.cmd.count);
267 fsm_deltimer(&ch->timer);
268 while ((skb = skb_dequeue(&ch->io_queue))) {
269 priv->stats.tx_packets++;
270 priv->stats.tx_bytes += skb->len - LL_HEADER_LENGTH;
271 if (first) {
272 priv->stats.tx_bytes += 2;
273 first = 0;
274 }
275 refcount_dec(&skb->users);
276 dev_kfree_skb_irq(skb);
277 }
278 spin_lock(&ch->collect_lock);
279 clear_normalized_cda(&ch->ccw[4]);
280 if (ch->collect_len > 0) {
281 int rc;
282
283 if (ctcm_checkalloc_buffer(ch)) {
284 spin_unlock(&ch->collect_lock);
285 return;
286 }
287 ch->trans_skb->data = ch->trans_skb_data;
288 skb_reset_tail_pointer(ch->trans_skb);
289 ch->trans_skb->len = 0;
290 if (ch->prof.maxmulti < (ch->collect_len + 2))
291 ch->prof.maxmulti = ch->collect_len + 2;
292 if (ch->prof.maxcqueue < skb_queue_len(&ch->collect_queue))
293 ch->prof.maxcqueue = skb_queue_len(&ch->collect_queue);
294 *((__u16 *)skb_put(ch->trans_skb, 2)) = ch->collect_len + 2;
295 i = 0;
296 while ((skb = skb_dequeue(&ch->collect_queue))) {
297 skb_copy_from_linear_data(skb,
298 skb_put(ch->trans_skb, skb->len), skb->len);
299 priv->stats.tx_packets++;
300 priv->stats.tx_bytes += skb->len - LL_HEADER_LENGTH;
301 refcount_dec(&skb->users);
302 dev_kfree_skb_irq(skb);
303 i++;
304 }
305 ch->collect_len = 0;
306 spin_unlock(&ch->collect_lock);
307 ch->ccw[1].count = ch->trans_skb->len;
308 fsm_addtimer(&ch->timer, CTCM_TIME_5_SEC, CTC_EVENT_TIMER, ch);
309 ch->prof.send_stamp = jiffies;
310 rc = ccw_device_start(ch->cdev, &ch->ccw[0],
311 (unsigned long)ch, 0xff, 0);
312 ch->prof.doios_multi++;
313 if (rc != 0) {
314 priv->stats.tx_dropped += i;
315 priv->stats.tx_errors += i;
316 fsm_deltimer(&ch->timer);
317 ctcm_ccw_check_rc(ch, rc, "chained TX");
318 }
319 } else {
320 spin_unlock(&ch->collect_lock);
321 fsm_newstate(fi, CTC_STATE_TXIDLE);
322 }
323 ctcm_clear_busy_do(dev);
324}
325
326
327
328
329
330
331
332
333
334
335void ctcm_chx_txidle(fsm_instance *fi, int event, void *arg)
336{
337 struct channel *ch = arg;
338 struct net_device *dev = ch->netdev;
339 struct ctcm_priv *priv = dev->ml_priv;
340
341 CTCM_PR_DEBUG("%s(%s): %s\n", __func__, ch->id, dev->name);
342
343 fsm_deltimer(&ch->timer);
344 fsm_newstate(fi, CTC_STATE_TXIDLE);
345 fsm_event(priv->fsm, DEV_EVENT_TXUP, ch->netdev);
346}
347
348
349
350
351
352
353
354
355
356static void chx_rx(fsm_instance *fi, int event, void *arg)
357{
358 struct channel *ch = arg;
359 struct net_device *dev = ch->netdev;
360 struct ctcm_priv *priv = dev->ml_priv;
361 int len = ch->max_bufsize - ch->irb->scsw.cmd.count;
362 struct sk_buff *skb = ch->trans_skb;
363 __u16 block_len = *((__u16 *)skb->data);
364 int check_len;
365 int rc;
366
367 fsm_deltimer(&ch->timer);
368 if (len < 8) {
369 CTCM_DBF_TEXT_(TRACE, CTC_DBF_NOTICE,
370 "%s(%s): got packet with length %d < 8\n",
371 CTCM_FUNTAIL, dev->name, len);
372 priv->stats.rx_dropped++;
373 priv->stats.rx_length_errors++;
374 goto again;
375 }
376 if (len > ch->max_bufsize) {
377 CTCM_DBF_TEXT_(TRACE, CTC_DBF_NOTICE,
378 "%s(%s): got packet with length %d > %d\n",
379 CTCM_FUNTAIL, dev->name, len, ch->max_bufsize);
380 priv->stats.rx_dropped++;
381 priv->stats.rx_length_errors++;
382 goto again;
383 }
384
385
386
387
388 switch (ch->protocol) {
389 case CTCM_PROTO_S390:
390 case CTCM_PROTO_OS390:
391 check_len = block_len + 2;
392 break;
393 default:
394 check_len = block_len;
395 break;
396 }
397 if ((len < block_len) || (len > check_len)) {
398 CTCM_DBF_TEXT_(TRACE, CTC_DBF_NOTICE,
399 "%s(%s): got block length %d != rx length %d\n",
400 CTCM_FUNTAIL, dev->name, block_len, len);
401 if (do_debug)
402 ctcmpc_dump_skb(skb, 0);
403
404 *((__u16 *)skb->data) = len;
405 priv->stats.rx_dropped++;
406 priv->stats.rx_length_errors++;
407 goto again;
408 }
409 if (block_len > 2) {
410 *((__u16 *)skb->data) = block_len - 2;
411 ctcm_unpack_skb(ch, skb);
412 }
413 again:
414 skb->data = ch->trans_skb_data;
415 skb_reset_tail_pointer(skb);
416 skb->len = 0;
417 if (ctcm_checkalloc_buffer(ch))
418 return;
419 ch->ccw[1].count = ch->max_bufsize;
420 rc = ccw_device_start(ch->cdev, &ch->ccw[0],
421 (unsigned long)ch, 0xff, 0);
422 if (rc != 0)
423 ctcm_ccw_check_rc(ch, rc, "normal RX");
424}
425
426
427
428
429
430
431
432
433static void chx_firstio(fsm_instance *fi, int event, void *arg)
434{
435 int rc;
436 struct channel *ch = arg;
437 int fsmstate = fsm_getstate(fi);
438
439 CTCM_DBF_TEXT_(TRACE, CTC_DBF_NOTICE,
440 "%s(%s) : %02x",
441 CTCM_FUNTAIL, ch->id, fsmstate);
442
443 ch->sense_rc = 0;
444 if (fsmstate == CTC_STATE_TXIDLE)
445 CTCM_DBF_TEXT_(TRACE, CTC_DBF_DEBUG,
446 "%s(%s): remote side issued READ?, init.\n",
447 CTCM_FUNTAIL, ch->id);
448 fsm_deltimer(&ch->timer);
449 if (ctcm_checkalloc_buffer(ch))
450 return;
451 if ((fsmstate == CTC_STATE_SETUPWAIT) &&
452 (ch->protocol == CTCM_PROTO_OS390)) {
453
454 if (CHANNEL_DIRECTION(ch->flags) == CTCM_READ) {
455 *((__u16 *)ch->trans_skb->data) = CTCM_INITIAL_BLOCKLEN;
456 fsm_addtimer(&ch->timer, CTCM_TIME_5_SEC,
457 CTC_EVENT_TIMER, ch);
458 chx_rxidle(fi, event, arg);
459 } else {
460 struct net_device *dev = ch->netdev;
461 struct ctcm_priv *priv = dev->ml_priv;
462 fsm_newstate(fi, CTC_STATE_TXIDLE);
463 fsm_event(priv->fsm, DEV_EVENT_TXUP, dev);
464 }
465 return;
466 }
467
468
469
470
471
472 if ((CHANNEL_DIRECTION(ch->flags) == CTCM_WRITE) ||
473 (ch->protocol != CTCM_PROTO_S390))
474 fsm_addtimer(&ch->timer, CTCM_TIME_5_SEC, CTC_EVENT_TIMER, ch);
475
476 *((__u16 *)ch->trans_skb->data) = CTCM_INITIAL_BLOCKLEN;
477 ch->ccw[1].count = 2;
478
479 fsm_newstate(fi, (CHANNEL_DIRECTION(ch->flags) == CTCM_READ)
480 ? CTC_STATE_RXINIT : CTC_STATE_TXINIT);
481 rc = ccw_device_start(ch->cdev, &ch->ccw[0],
482 (unsigned long)ch, 0xff, 0);
483 if (rc != 0) {
484 fsm_deltimer(&ch->timer);
485 fsm_newstate(fi, CTC_STATE_SETUPWAIT);
486 ctcm_ccw_check_rc(ch, rc, "init IO");
487 }
488
489
490
491
492
493
494
495 if ((CHANNEL_DIRECTION(ch->flags) == CTCM_READ) &&
496 (ch->protocol == CTCM_PROTO_S390)) {
497 struct net_device *dev = ch->netdev;
498 struct ctcm_priv *priv = dev->ml_priv;
499 fsm_event(priv->fsm, DEV_EVENT_RXUP, dev);
500 }
501}
502
503
504
505
506
507
508
509
510
511
512static void chx_rxidle(fsm_instance *fi, int event, void *arg)
513{
514 struct channel *ch = arg;
515 struct net_device *dev = ch->netdev;
516 struct ctcm_priv *priv = dev->ml_priv;
517 __u16 buflen;
518 int rc;
519
520 fsm_deltimer(&ch->timer);
521 buflen = *((__u16 *)ch->trans_skb->data);
522 CTCM_PR_DEBUG("%s: %s: Initial RX count = %d\n",
523 __func__, dev->name, buflen);
524
525 if (buflen >= CTCM_INITIAL_BLOCKLEN) {
526 if (ctcm_checkalloc_buffer(ch))
527 return;
528 ch->ccw[1].count = ch->max_bufsize;
529 fsm_newstate(fi, CTC_STATE_RXIDLE);
530 rc = ccw_device_start(ch->cdev, &ch->ccw[0],
531 (unsigned long)ch, 0xff, 0);
532 if (rc != 0) {
533 fsm_newstate(fi, CTC_STATE_RXINIT);
534 ctcm_ccw_check_rc(ch, rc, "initial RX");
535 } else
536 fsm_event(priv->fsm, DEV_EVENT_RXUP, dev);
537 } else {
538 CTCM_PR_DEBUG("%s: %s: Initial RX count %d not %d\n",
539 __func__, dev->name,
540 buflen, CTCM_INITIAL_BLOCKLEN);
541 chx_firstio(fi, event, arg);
542 }
543}
544
545
546
547
548
549
550
551
552static void ctcm_chx_setmode(fsm_instance *fi, int event, void *arg)
553{
554 struct channel *ch = arg;
555 int rc;
556 unsigned long saveflags = 0;
557 int timeout = CTCM_TIME_5_SEC;
558
559 fsm_deltimer(&ch->timer);
560 if (IS_MPC(ch)) {
561 timeout = 1500;
562 CTCM_PR_DEBUG("enter %s: cp=%i ch=0x%p id=%s\n",
563 __func__, smp_processor_id(), ch, ch->id);
564 }
565 fsm_addtimer(&ch->timer, timeout, CTC_EVENT_TIMER, ch);
566 fsm_newstate(fi, CTC_STATE_SETUPWAIT);
567 CTCM_CCW_DUMP((char *)&ch->ccw[6], sizeof(struct ccw1) * 2);
568
569 if (event == CTC_EVENT_TIMER)
570 spin_lock_irqsave(get_ccwdev_lock(ch->cdev), saveflags);
571
572
573
574 rc = ccw_device_start(ch->cdev, &ch->ccw[6],
575 (unsigned long)ch, 0xff, 0);
576 if (event == CTC_EVENT_TIMER)
577 spin_unlock_irqrestore(get_ccwdev_lock(ch->cdev), saveflags);
578 if (rc != 0) {
579 fsm_deltimer(&ch->timer);
580 fsm_newstate(fi, CTC_STATE_STARTWAIT);
581 ctcm_ccw_check_rc(ch, rc, "set Mode");
582 } else
583 ch->retry = 0;
584}
585
586
587
588
589
590
591
592
593static void ctcm_chx_start(fsm_instance *fi, int event, void *arg)
594{
595 struct channel *ch = arg;
596 unsigned long saveflags;
597 int rc;
598
599 CTCM_DBF_TEXT_(SETUP, CTC_DBF_INFO, "%s(%s): %s",
600 CTCM_FUNTAIL, ch->id,
601 (CHANNEL_DIRECTION(ch->flags) == CTCM_READ) ? "RX" : "TX");
602
603 if (ch->trans_skb != NULL) {
604 clear_normalized_cda(&ch->ccw[1]);
605 dev_kfree_skb(ch->trans_skb);
606 ch->trans_skb = NULL;
607 }
608 if (CHANNEL_DIRECTION(ch->flags) == CTCM_READ) {
609 ch->ccw[1].cmd_code = CCW_CMD_READ;
610 ch->ccw[1].flags = CCW_FLAG_SLI;
611 ch->ccw[1].count = 0;
612 } else {
613 ch->ccw[1].cmd_code = CCW_CMD_WRITE;
614 ch->ccw[1].flags = CCW_FLAG_SLI | CCW_FLAG_CC;
615 ch->ccw[1].count = 0;
616 }
617 if (ctcm_checkalloc_buffer(ch)) {
618 CTCM_DBF_TEXT_(TRACE, CTC_DBF_DEBUG,
619 "%s(%s): %s trans_skb alloc delayed "
620 "until first transfer",
621 CTCM_FUNTAIL, ch->id,
622 (CHANNEL_DIRECTION(ch->flags) == CTCM_READ) ?
623 "RX" : "TX");
624 }
625 ch->ccw[0].cmd_code = CCW_CMD_PREPARE;
626 ch->ccw[0].flags = CCW_FLAG_SLI | CCW_FLAG_CC;
627 ch->ccw[0].count = 0;
628 ch->ccw[0].cda = 0;
629 ch->ccw[2].cmd_code = CCW_CMD_NOOP;
630 ch->ccw[2].flags = CCW_FLAG_SLI;
631 ch->ccw[2].count = 0;
632 ch->ccw[2].cda = 0;
633 memcpy(&ch->ccw[3], &ch->ccw[0], sizeof(struct ccw1) * 3);
634 ch->ccw[4].cda = 0;
635 ch->ccw[4].flags &= ~CCW_FLAG_IDA;
636
637 fsm_newstate(fi, CTC_STATE_STARTWAIT);
638 fsm_addtimer(&ch->timer, 1000, CTC_EVENT_TIMER, ch);
639 spin_lock_irqsave(get_ccwdev_lock(ch->cdev), saveflags);
640 rc = ccw_device_halt(ch->cdev, (unsigned long)ch);
641 spin_unlock_irqrestore(get_ccwdev_lock(ch->cdev), saveflags);
642 if (rc != 0) {
643 if (rc != -EBUSY)
644 fsm_deltimer(&ch->timer);
645 ctcm_ccw_check_rc(ch, rc, "initial HaltIO");
646 }
647}
648
649
650
651
652
653
654
655
656static void ctcm_chx_haltio(fsm_instance *fi, int event, void *arg)
657{
658 struct channel *ch = arg;
659 unsigned long saveflags = 0;
660 int rc;
661 int oldstate;
662
663 fsm_deltimer(&ch->timer);
664 if (IS_MPC(ch))
665 fsm_deltimer(&ch->sweep_timer);
666
667 fsm_addtimer(&ch->timer, CTCM_TIME_5_SEC, CTC_EVENT_TIMER, ch);
668
669 if (event == CTC_EVENT_STOP)
670 spin_lock_irqsave(get_ccwdev_lock(ch->cdev), saveflags);
671
672
673 oldstate = fsm_getstate(fi);
674 fsm_newstate(fi, CTC_STATE_TERM);
675 rc = ccw_device_halt(ch->cdev, (unsigned long)ch);
676
677 if (event == CTC_EVENT_STOP)
678 spin_unlock_irqrestore(get_ccwdev_lock(ch->cdev), saveflags);
679
680
681 if (rc != 0 && rc != -EBUSY) {
682 fsm_deltimer(&ch->timer);
683 if (event != CTC_EVENT_STOP) {
684 fsm_newstate(fi, oldstate);
685 ctcm_ccw_check_rc(ch, rc, (char *)__func__);
686 }
687 }
688}
689
690
691
692
693
694
695
696
697
698static void ctcm_chx_cleanup(fsm_instance *fi, int state,
699 struct channel *ch)
700{
701 struct net_device *dev = ch->netdev;
702 struct ctcm_priv *priv = dev->ml_priv;
703
704 CTCM_DBF_TEXT_(SETUP, CTC_DBF_NOTICE,
705 "%s(%s): %s[%d]\n",
706 CTCM_FUNTAIL, dev->name, ch->id, state);
707
708 fsm_deltimer(&ch->timer);
709 if (IS_MPC(ch))
710 fsm_deltimer(&ch->sweep_timer);
711
712 fsm_newstate(fi, state);
713 if (state == CTC_STATE_STOPPED && ch->trans_skb != NULL) {
714 clear_normalized_cda(&ch->ccw[1]);
715 dev_kfree_skb_any(ch->trans_skb);
716 ch->trans_skb = NULL;
717 }
718
719 ch->th_seg = 0x00;
720 ch->th_seq_num = 0x00;
721 if (CHANNEL_DIRECTION(ch->flags) == CTCM_READ) {
722 skb_queue_purge(&ch->io_queue);
723 fsm_event(priv->fsm, DEV_EVENT_RXDOWN, dev);
724 } else {
725 ctcm_purge_skb_queue(&ch->io_queue);
726 if (IS_MPC(ch))
727 ctcm_purge_skb_queue(&ch->sweep_queue);
728 spin_lock(&ch->collect_lock);
729 ctcm_purge_skb_queue(&ch->collect_queue);
730 ch->collect_len = 0;
731 spin_unlock(&ch->collect_lock);
732 fsm_event(priv->fsm, DEV_EVENT_TXDOWN, dev);
733 }
734}
735
736
737
738
739
740
741
742
743
744static void ctcm_chx_stopped(fsm_instance *fi, int event, void *arg)
745{
746 ctcm_chx_cleanup(fi, CTC_STATE_STOPPED, arg);
747}
748
749
750
751
752
753
754
755
756
757static void ctcm_chx_stop(fsm_instance *fi, int event, void *arg)
758{
759 fsm_newstate(fi, CTC_STATE_STOPPED);
760}
761
762
763
764
765
766
767
768
769
770
771static void ctcm_chx_fail(fsm_instance *fi, int event, void *arg)
772{
773 ctcm_chx_cleanup(fi, CTC_STATE_NOTOP, arg);
774}
775
776
777
778
779
780
781
782
783static void ctcm_chx_setuperr(fsm_instance *fi, int event, void *arg)
784{
785 struct channel *ch = arg;
786 struct net_device *dev = ch->netdev;
787 struct ctcm_priv *priv = dev->ml_priv;
788
789
790
791
792
793
794 if ((fsm_getstate(fi) == CTC_STATE_SETUPWAIT) &&
795 ((event == CTC_EVENT_UC_RCRESET) ||
796 (event == CTC_EVENT_UC_RSRESET))) {
797 fsm_newstate(fi, CTC_STATE_STARTRETRY);
798 fsm_deltimer(&ch->timer);
799 fsm_addtimer(&ch->timer, CTCM_TIME_5_SEC, CTC_EVENT_TIMER, ch);
800 if (!IS_MPC(ch) &&
801 (CHANNEL_DIRECTION(ch->flags) == CTCM_READ)) {
802 int rc = ccw_device_halt(ch->cdev, (unsigned long)ch);
803 if (rc != 0)
804 ctcm_ccw_check_rc(ch, rc,
805 "HaltIO in chx_setuperr");
806 }
807 return;
808 }
809
810 CTCM_DBF_TEXT_(ERROR, CTC_DBF_CRIT,
811 "%s(%s) : %s error during %s channel setup state=%s\n",
812 CTCM_FUNTAIL, dev->name, ctc_ch_event_names[event],
813 (CHANNEL_DIRECTION(ch->flags) == CTCM_READ) ? "RX" : "TX",
814 fsm_getstate_str(fi));
815
816 if (CHANNEL_DIRECTION(ch->flags) == CTCM_READ) {
817 fsm_newstate(fi, CTC_STATE_RXERR);
818 fsm_event(priv->fsm, DEV_EVENT_RXDOWN, dev);
819 } else {
820 fsm_newstate(fi, CTC_STATE_TXERR);
821 fsm_event(priv->fsm, DEV_EVENT_TXDOWN, dev);
822 }
823}
824
825
826
827
828
829
830
831
832static void ctcm_chx_restart(fsm_instance *fi, int event, void *arg)
833{
834 struct channel *ch = arg;
835 struct net_device *dev = ch->netdev;
836 unsigned long saveflags = 0;
837 int oldstate;
838 int rc;
839
840 CTCM_DBF_TEXT_(TRACE, CTC_DBF_NOTICE,
841 "%s: %s[%d] of %s\n",
842 CTCM_FUNTAIL, ch->id, event, dev->name);
843
844 fsm_deltimer(&ch->timer);
845
846 fsm_addtimer(&ch->timer, CTCM_TIME_5_SEC, CTC_EVENT_TIMER, ch);
847 oldstate = fsm_getstate(fi);
848 fsm_newstate(fi, CTC_STATE_STARTWAIT);
849 if (event == CTC_EVENT_TIMER)
850 spin_lock_irqsave(get_ccwdev_lock(ch->cdev), saveflags);
851
852
853
854 rc = ccw_device_halt(ch->cdev, (unsigned long)ch);
855 if (event == CTC_EVENT_TIMER)
856 spin_unlock_irqrestore(get_ccwdev_lock(ch->cdev), saveflags);
857 if (rc != 0) {
858 if (rc != -EBUSY) {
859 fsm_deltimer(&ch->timer);
860 fsm_newstate(fi, oldstate);
861 }
862 ctcm_ccw_check_rc(ch, rc, "HaltIO in ctcm_chx_restart");
863 }
864}
865
866
867
868
869
870
871
872
873
874static void ctcm_chx_rxiniterr(fsm_instance *fi, int event, void *arg)
875{
876 struct channel *ch = arg;
877 struct net_device *dev = ch->netdev;
878 struct ctcm_priv *priv = dev->ml_priv;
879
880 if (event == CTC_EVENT_TIMER) {
881 if (!IS_MPCDEV(dev))
882
883 fsm_deltimer(&ch->timer);
884 if (ch->retry++ < 3)
885 ctcm_chx_restart(fi, event, arg);
886 else {
887 fsm_newstate(fi, CTC_STATE_RXERR);
888 fsm_event(priv->fsm, DEV_EVENT_RXDOWN, dev);
889 }
890 } else {
891 CTCM_DBF_TEXT_(ERROR, CTC_DBF_ERROR,
892 "%s(%s): %s in %s", CTCM_FUNTAIL, ch->id,
893 ctc_ch_event_names[event], fsm_getstate_str(fi));
894
895 dev_warn(&dev->dev,
896 "Initialization failed with RX/TX init handshake "
897 "error %s\n", ctc_ch_event_names[event]);
898 }
899}
900
901
902
903
904
905
906
907
908
909static void ctcm_chx_rxinitfail(fsm_instance *fi, int event, void *arg)
910{
911 struct channel *ch = arg;
912 struct net_device *dev = ch->netdev;
913 struct ctcm_priv *priv = dev->ml_priv;
914
915 CTCM_DBF_TEXT_(ERROR, CTC_DBF_ERROR,
916 "%s(%s): RX %s busy, init. fail",
917 CTCM_FUNTAIL, dev->name, ch->id);
918 fsm_newstate(fi, CTC_STATE_RXERR);
919 fsm_event(priv->fsm, DEV_EVENT_RXDOWN, dev);
920}
921
922
923
924
925
926
927
928
929static void ctcm_chx_rxdisc(fsm_instance *fi, int event, void *arg)
930{
931 struct channel *ch = arg;
932 struct channel *ch2;
933 struct net_device *dev = ch->netdev;
934 struct ctcm_priv *priv = dev->ml_priv;
935
936 CTCM_DBF_TEXT_(TRACE, CTC_DBF_NOTICE,
937 "%s: %s: remote disconnect - re-init ...",
938 CTCM_FUNTAIL, dev->name);
939 fsm_deltimer(&ch->timer);
940
941
942
943 fsm_event(priv->fsm, DEV_EVENT_RXDOWN, dev);
944 fsm_event(priv->fsm, DEV_EVENT_TXDOWN, dev);
945
946 fsm_newstate(fi, CTC_STATE_DTERM);
947 ch2 = priv->channel[CTCM_WRITE];
948 fsm_newstate(ch2->fsm, CTC_STATE_DTERM);
949
950 ccw_device_halt(ch->cdev, (unsigned long)ch);
951 ccw_device_halt(ch2->cdev, (unsigned long)ch2);
952}
953
954
955
956
957
958
959
960
961static void ctcm_chx_txiniterr(fsm_instance *fi, int event, void *arg)
962{
963 struct channel *ch = arg;
964 struct net_device *dev = ch->netdev;
965 struct ctcm_priv *priv = dev->ml_priv;
966
967 if (event == CTC_EVENT_TIMER) {
968 fsm_deltimer(&ch->timer);
969 if (ch->retry++ < 3)
970 ctcm_chx_restart(fi, event, arg);
971 else {
972 fsm_newstate(fi, CTC_STATE_TXERR);
973 fsm_event(priv->fsm, DEV_EVENT_TXDOWN, dev);
974 }
975 } else {
976 CTCM_DBF_TEXT_(ERROR, CTC_DBF_ERROR,
977 "%s(%s): %s in %s", CTCM_FUNTAIL, ch->id,
978 ctc_ch_event_names[event], fsm_getstate_str(fi));
979
980 dev_warn(&dev->dev,
981 "Initialization failed with RX/TX init handshake "
982 "error %s\n", ctc_ch_event_names[event]);
983 }
984}
985
986
987
988
989
990
991
992
993static void ctcm_chx_txretry(fsm_instance *fi, int event, void *arg)
994{
995 struct channel *ch = arg;
996 struct net_device *dev = ch->netdev;
997 struct ctcm_priv *priv = dev->ml_priv;
998 struct sk_buff *skb;
999
1000 CTCM_PR_DEBUG("Enter: %s: cp=%i ch=0x%p id=%s\n",
1001 __func__, smp_processor_id(), ch, ch->id);
1002
1003 fsm_deltimer(&ch->timer);
1004 if (ch->retry++ > 3) {
1005 struct mpc_group *gptr = priv->mpcg;
1006 CTCM_DBF_TEXT_(TRACE, CTC_DBF_INFO,
1007 "%s: %s: retries exceeded",
1008 CTCM_FUNTAIL, ch->id);
1009 fsm_event(priv->fsm, DEV_EVENT_TXDOWN, dev);
1010
1011
1012 if (!(gptr && (fsm_getstate(gptr->fsm) != MPCG_STATE_READY)))
1013 ctcm_chx_restart(fi, event, arg);
1014 goto done;
1015 }
1016
1017 CTCM_DBF_TEXT_(TRACE, CTC_DBF_DEBUG,
1018 "%s : %s: retry %d",
1019 CTCM_FUNTAIL, ch->id, ch->retry);
1020 skb = skb_peek(&ch->io_queue);
1021 if (skb) {
1022 int rc = 0;
1023 unsigned long saveflags = 0;
1024 clear_normalized_cda(&ch->ccw[4]);
1025 ch->ccw[4].count = skb->len;
1026 if (set_normalized_cda(&ch->ccw[4], skb->data)) {
1027 CTCM_DBF_TEXT_(TRACE, CTC_DBF_INFO,
1028 "%s: %s: IDAL alloc failed",
1029 CTCM_FUNTAIL, ch->id);
1030 fsm_event(priv->fsm, DEV_EVENT_TXDOWN, dev);
1031 ctcm_chx_restart(fi, event, arg);
1032 goto done;
1033 }
1034 fsm_addtimer(&ch->timer, 1000, CTC_EVENT_TIMER, ch);
1035 if (event == CTC_EVENT_TIMER)
1036 spin_lock_irqsave(get_ccwdev_lock(ch->cdev), saveflags);
1037
1038
1039
1040 if (do_debug_ccw)
1041 ctcmpc_dumpit((char *)&ch->ccw[3],
1042 sizeof(struct ccw1) * 3);
1043
1044 rc = ccw_device_start(ch->cdev, &ch->ccw[3],
1045 (unsigned long)ch, 0xff, 0);
1046 if (event == CTC_EVENT_TIMER)
1047 spin_unlock_irqrestore(get_ccwdev_lock(ch->cdev),
1048 saveflags);
1049 if (rc != 0) {
1050 fsm_deltimer(&ch->timer);
1051 ctcm_ccw_check_rc(ch, rc, "TX in chx_txretry");
1052 ctcm_purge_skb_queue(&ch->io_queue);
1053 }
1054 }
1055done:
1056 return;
1057}
1058
1059
1060
1061
1062
1063
1064
1065
1066static void ctcm_chx_iofatal(fsm_instance *fi, int event, void *arg)
1067{
1068 struct channel *ch = arg;
1069 struct net_device *dev = ch->netdev;
1070 struct ctcm_priv *priv = dev->ml_priv;
1071 int rd = CHANNEL_DIRECTION(ch->flags);
1072
1073 fsm_deltimer(&ch->timer);
1074 CTCM_DBF_TEXT_(ERROR, CTC_DBF_ERROR,
1075 "%s: %s: %s unrecoverable channel error",
1076 CTCM_FUNTAIL, ch->id, rd == CTCM_READ ? "RX" : "TX");
1077
1078 if (IS_MPC(ch)) {
1079 priv->stats.tx_dropped++;
1080 priv->stats.tx_errors++;
1081 }
1082 if (rd == CTCM_READ) {
1083 fsm_newstate(fi, CTC_STATE_RXERR);
1084 fsm_event(priv->fsm, DEV_EVENT_RXDOWN, dev);
1085 } else {
1086 fsm_newstate(fi, CTC_STATE_TXERR);
1087 fsm_event(priv->fsm, DEV_EVENT_TXDOWN, dev);
1088 }
1089}
1090
1091
1092
1093
1094const fsm_node ch_fsm[] = {
1095 { CTC_STATE_STOPPED, CTC_EVENT_STOP, ctcm_action_nop },
1096 { CTC_STATE_STOPPED, CTC_EVENT_START, ctcm_chx_start },
1097 { CTC_STATE_STOPPED, CTC_EVENT_FINSTAT, ctcm_action_nop },
1098 { CTC_STATE_STOPPED, CTC_EVENT_MC_FAIL, ctcm_action_nop },
1099
1100 { CTC_STATE_NOTOP, CTC_EVENT_STOP, ctcm_chx_stop },
1101 { CTC_STATE_NOTOP, CTC_EVENT_START, ctcm_action_nop },
1102 { CTC_STATE_NOTOP, CTC_EVENT_FINSTAT, ctcm_action_nop },
1103 { CTC_STATE_NOTOP, CTC_EVENT_MC_FAIL, ctcm_action_nop },
1104 { CTC_STATE_NOTOP, CTC_EVENT_MC_GOOD, ctcm_chx_start },
1105
1106 { CTC_STATE_STARTWAIT, CTC_EVENT_STOP, ctcm_chx_haltio },
1107 { CTC_STATE_STARTWAIT, CTC_EVENT_START, ctcm_action_nop },
1108 { CTC_STATE_STARTWAIT, CTC_EVENT_FINSTAT, ctcm_chx_setmode },
1109 { CTC_STATE_STARTWAIT, CTC_EVENT_TIMER, ctcm_chx_setuperr },
1110 { CTC_STATE_STARTWAIT, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1111 { CTC_STATE_STARTWAIT, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1112
1113 { CTC_STATE_STARTRETRY, CTC_EVENT_STOP, ctcm_chx_haltio },
1114 { CTC_STATE_STARTRETRY, CTC_EVENT_TIMER, ctcm_chx_setmode },
1115 { CTC_STATE_STARTRETRY, CTC_EVENT_FINSTAT, ctcm_action_nop },
1116 { CTC_STATE_STARTRETRY, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1117
1118 { CTC_STATE_SETUPWAIT, CTC_EVENT_STOP, ctcm_chx_haltio },
1119 { CTC_STATE_SETUPWAIT, CTC_EVENT_START, ctcm_action_nop },
1120 { CTC_STATE_SETUPWAIT, CTC_EVENT_FINSTAT, chx_firstio },
1121 { CTC_STATE_SETUPWAIT, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1122 { CTC_STATE_SETUPWAIT, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1123 { CTC_STATE_SETUPWAIT, CTC_EVENT_TIMER, ctcm_chx_setmode },
1124 { CTC_STATE_SETUPWAIT, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1125 { CTC_STATE_SETUPWAIT, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1126
1127 { CTC_STATE_RXINIT, CTC_EVENT_STOP, ctcm_chx_haltio },
1128 { CTC_STATE_RXINIT, CTC_EVENT_START, ctcm_action_nop },
1129 { CTC_STATE_RXINIT, CTC_EVENT_FINSTAT, chx_rxidle },
1130 { CTC_STATE_RXINIT, CTC_EVENT_UC_RCRESET, ctcm_chx_rxiniterr },
1131 { CTC_STATE_RXINIT, CTC_EVENT_UC_RSRESET, ctcm_chx_rxiniterr },
1132 { CTC_STATE_RXINIT, CTC_EVENT_TIMER, ctcm_chx_rxiniterr },
1133 { CTC_STATE_RXINIT, CTC_EVENT_ATTNBUSY, ctcm_chx_rxinitfail },
1134 { CTC_STATE_RXINIT, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1135 { CTC_STATE_RXINIT, CTC_EVENT_UC_ZERO, chx_firstio },
1136 { CTC_STATE_RXINIT, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1137
1138 { CTC_STATE_RXIDLE, CTC_EVENT_STOP, ctcm_chx_haltio },
1139 { CTC_STATE_RXIDLE, CTC_EVENT_START, ctcm_action_nop },
1140 { CTC_STATE_RXIDLE, CTC_EVENT_FINSTAT, chx_rx },
1141 { CTC_STATE_RXIDLE, CTC_EVENT_UC_RCRESET, ctcm_chx_rxdisc },
1142 { CTC_STATE_RXIDLE, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1143 { CTC_STATE_RXIDLE, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1144 { CTC_STATE_RXIDLE, CTC_EVENT_UC_ZERO, chx_rx },
1145
1146 { CTC_STATE_TXINIT, CTC_EVENT_STOP, ctcm_chx_haltio },
1147 { CTC_STATE_TXINIT, CTC_EVENT_START, ctcm_action_nop },
1148 { CTC_STATE_TXINIT, CTC_EVENT_FINSTAT, ctcm_chx_txidle },
1149 { CTC_STATE_TXINIT, CTC_EVENT_UC_RCRESET, ctcm_chx_txiniterr },
1150 { CTC_STATE_TXINIT, CTC_EVENT_UC_RSRESET, ctcm_chx_txiniterr },
1151 { CTC_STATE_TXINIT, CTC_EVENT_TIMER, ctcm_chx_txiniterr },
1152 { CTC_STATE_TXINIT, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1153 { CTC_STATE_TXINIT, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1154
1155 { CTC_STATE_TXIDLE, CTC_EVENT_STOP, ctcm_chx_haltio },
1156 { CTC_STATE_TXIDLE, CTC_EVENT_START, ctcm_action_nop },
1157 { CTC_STATE_TXIDLE, CTC_EVENT_FINSTAT, chx_firstio },
1158 { CTC_STATE_TXIDLE, CTC_EVENT_UC_RCRESET, ctcm_action_nop },
1159 { CTC_STATE_TXIDLE, CTC_EVENT_UC_RSRESET, ctcm_action_nop },
1160 { CTC_STATE_TXIDLE, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1161 { CTC_STATE_TXIDLE, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1162
1163 { CTC_STATE_TERM, CTC_EVENT_STOP, ctcm_action_nop },
1164 { CTC_STATE_TERM, CTC_EVENT_START, ctcm_chx_restart },
1165 { CTC_STATE_TERM, CTC_EVENT_FINSTAT, ctcm_chx_stopped },
1166 { CTC_STATE_TERM, CTC_EVENT_UC_RCRESET, ctcm_action_nop },
1167 { CTC_STATE_TERM, CTC_EVENT_UC_RSRESET, ctcm_action_nop },
1168 { CTC_STATE_TERM, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1169
1170 { CTC_STATE_DTERM, CTC_EVENT_STOP, ctcm_chx_haltio },
1171 { CTC_STATE_DTERM, CTC_EVENT_START, ctcm_chx_restart },
1172 { CTC_STATE_DTERM, CTC_EVENT_FINSTAT, ctcm_chx_setmode },
1173 { CTC_STATE_DTERM, CTC_EVENT_UC_RCRESET, ctcm_action_nop },
1174 { CTC_STATE_DTERM, CTC_EVENT_UC_RSRESET, ctcm_action_nop },
1175 { CTC_STATE_DTERM, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1176
1177 { CTC_STATE_TX, CTC_EVENT_STOP, ctcm_chx_haltio },
1178 { CTC_STATE_TX, CTC_EVENT_START, ctcm_action_nop },
1179 { CTC_STATE_TX, CTC_EVENT_FINSTAT, chx_txdone },
1180 { CTC_STATE_TX, CTC_EVENT_UC_RCRESET, ctcm_chx_txretry },
1181 { CTC_STATE_TX, CTC_EVENT_UC_RSRESET, ctcm_chx_txretry },
1182 { CTC_STATE_TX, CTC_EVENT_TIMER, ctcm_chx_txretry },
1183 { CTC_STATE_TX, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1184 { CTC_STATE_TX, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1185
1186 { CTC_STATE_RXERR, CTC_EVENT_STOP, ctcm_chx_haltio },
1187 { CTC_STATE_TXERR, CTC_EVENT_STOP, ctcm_chx_haltio },
1188 { CTC_STATE_TXERR, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1189 { CTC_STATE_RXERR, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1190};
1191
1192int ch_fsm_len = ARRAY_SIZE(ch_fsm);
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216static void ctcmpc_chx_txdone(fsm_instance *fi, int event, void *arg)
1217{
1218 struct channel *ch = arg;
1219 struct net_device *dev = ch->netdev;
1220 struct ctcm_priv *priv = dev->ml_priv;
1221 struct mpc_group *grp = priv->mpcg;
1222 struct sk_buff *skb;
1223 int first = 1;
1224 int i;
1225 __u32 data_space;
1226 unsigned long duration;
1227 struct sk_buff *peekskb;
1228 int rc;
1229 struct th_header *header;
1230 struct pdu *p_header;
1231 unsigned long done_stamp = jiffies;
1232
1233 CTCM_PR_DEBUG("Enter %s: %s cp:%i\n",
1234 __func__, dev->name, smp_processor_id());
1235
1236 duration = done_stamp - ch->prof.send_stamp;
1237 if (duration > ch->prof.tx_time)
1238 ch->prof.tx_time = duration;
1239
1240 if (ch->irb->scsw.cmd.count != 0)
1241 CTCM_DBF_TEXT_(MPC_TRACE, CTC_DBF_DEBUG,
1242 "%s(%s): TX not complete, remaining %d bytes",
1243 CTCM_FUNTAIL, dev->name, ch->irb->scsw.cmd.count);
1244 fsm_deltimer(&ch->timer);
1245 while ((skb = skb_dequeue(&ch->io_queue))) {
1246 priv->stats.tx_packets++;
1247 priv->stats.tx_bytes += skb->len - TH_HEADER_LENGTH;
1248 if (first) {
1249 priv->stats.tx_bytes += 2;
1250 first = 0;
1251 }
1252 refcount_dec(&skb->users);
1253 dev_kfree_skb_irq(skb);
1254 }
1255 spin_lock(&ch->collect_lock);
1256 clear_normalized_cda(&ch->ccw[4]);
1257 if ((ch->collect_len <= 0) || (grp->in_sweep != 0)) {
1258 spin_unlock(&ch->collect_lock);
1259 fsm_newstate(fi, CTC_STATE_TXIDLE);
1260 goto done;
1261 }
1262
1263 if (ctcm_checkalloc_buffer(ch)) {
1264 spin_unlock(&ch->collect_lock);
1265 goto done;
1266 }
1267 ch->trans_skb->data = ch->trans_skb_data;
1268 skb_reset_tail_pointer(ch->trans_skb);
1269 ch->trans_skb->len = 0;
1270 if (ch->prof.maxmulti < (ch->collect_len + TH_HEADER_LENGTH))
1271 ch->prof.maxmulti = ch->collect_len + TH_HEADER_LENGTH;
1272 if (ch->prof.maxcqueue < skb_queue_len(&ch->collect_queue))
1273 ch->prof.maxcqueue = skb_queue_len(&ch->collect_queue);
1274 i = 0;
1275 p_header = NULL;
1276 data_space = grp->group_max_buflen - TH_HEADER_LENGTH;
1277
1278 CTCM_PR_DBGDATA("%s: building trans_skb from collect_q"
1279 " data_space:%04x\n",
1280 __func__, data_space);
1281
1282 while ((skb = skb_dequeue(&ch->collect_queue))) {
1283 skb_put_data(ch->trans_skb, skb->data, skb->len);
1284 p_header = (struct pdu *)
1285 (skb_tail_pointer(ch->trans_skb) - skb->len);
1286 p_header->pdu_flag = 0x00;
1287 if (be16_to_cpu(skb->protocol) == ETH_P_SNAP)
1288 p_header->pdu_flag |= 0x60;
1289 else
1290 p_header->pdu_flag |= 0x20;
1291
1292 CTCM_PR_DBGDATA("%s: trans_skb len:%04x \n",
1293 __func__, ch->trans_skb->len);
1294 CTCM_PR_DBGDATA("%s: pdu header and data for up"
1295 " to 32 bytes sent to vtam\n", __func__);
1296 CTCM_D3_DUMP((char *)p_header, min_t(int, skb->len, 32));
1297
1298 ch->collect_len -= skb->len;
1299 data_space -= skb->len;
1300 priv->stats.tx_packets++;
1301 priv->stats.tx_bytes += skb->len;
1302 refcount_dec(&skb->users);
1303 dev_kfree_skb_any(skb);
1304 peekskb = skb_peek(&ch->collect_queue);
1305 if (peekskb->len > data_space)
1306 break;
1307 i++;
1308 }
1309
1310 if (p_header)
1311 p_header->pdu_flag |= PDU_LAST;
1312 header = kzalloc(TH_HEADER_LENGTH, gfp_type());
1313 if (!header) {
1314 spin_unlock(&ch->collect_lock);
1315 fsm_event(priv->mpcg->fsm, MPCG_EVENT_INOP, dev);
1316 goto done;
1317 }
1318 header->th_ch_flag = TH_HAS_PDU;
1319 ch->th_seq_num++;
1320 header->th_seq_num = ch->th_seq_num;
1321
1322 CTCM_PR_DBGDATA("%s: ToVTAM_th_seq= %08x\n" ,
1323 __func__, ch->th_seq_num);
1324
1325 memcpy(skb_push(ch->trans_skb, TH_HEADER_LENGTH), header,
1326 TH_HEADER_LENGTH);
1327
1328 kfree(header);
1329
1330 CTCM_PR_DBGDATA("%s: trans_skb len:%04x \n",
1331 __func__, ch->trans_skb->len);
1332 CTCM_PR_DBGDATA("%s: up-to-50 bytes of trans_skb "
1333 "data to vtam from collect_q\n", __func__);
1334 CTCM_D3_DUMP((char *)ch->trans_skb->data,
1335 min_t(int, ch->trans_skb->len, 50));
1336
1337 spin_unlock(&ch->collect_lock);
1338 clear_normalized_cda(&ch->ccw[1]);
1339
1340 CTCM_PR_DBGDATA("ccwcda=0x%p data=0x%p\n",
1341 (void *)(unsigned long)ch->ccw[1].cda,
1342 ch->trans_skb->data);
1343 ch->ccw[1].count = ch->max_bufsize;
1344
1345 if (set_normalized_cda(&ch->ccw[1], ch->trans_skb->data)) {
1346 dev_kfree_skb_any(ch->trans_skb);
1347 ch->trans_skb = NULL;
1348 CTCM_DBF_TEXT_(MPC_TRACE, CTC_DBF_ERROR,
1349 "%s: %s: IDAL alloc failed",
1350 CTCM_FUNTAIL, ch->id);
1351 fsm_event(priv->mpcg->fsm, MPCG_EVENT_INOP, dev);
1352 return;
1353 }
1354
1355 CTCM_PR_DBGDATA("ccwcda=0x%p data=0x%p\n",
1356 (void *)(unsigned long)ch->ccw[1].cda,
1357 ch->trans_skb->data);
1358
1359 ch->ccw[1].count = ch->trans_skb->len;
1360 fsm_addtimer(&ch->timer, CTCM_TIME_5_SEC, CTC_EVENT_TIMER, ch);
1361 ch->prof.send_stamp = jiffies;
1362 if (do_debug_ccw)
1363 ctcmpc_dumpit((char *)&ch->ccw[0], sizeof(struct ccw1) * 3);
1364 rc = ccw_device_start(ch->cdev, &ch->ccw[0],
1365 (unsigned long)ch, 0xff, 0);
1366 ch->prof.doios_multi++;
1367 if (rc != 0) {
1368 priv->stats.tx_dropped += i;
1369 priv->stats.tx_errors += i;
1370 fsm_deltimer(&ch->timer);
1371 ctcm_ccw_check_rc(ch, rc, "chained TX");
1372 }
1373done:
1374 ctcm_clear_busy(dev);
1375 return;
1376}
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386static void ctcmpc_chx_rx(fsm_instance *fi, int event, void *arg)
1387{
1388 struct channel *ch = arg;
1389 struct net_device *dev = ch->netdev;
1390 struct ctcm_priv *priv = dev->ml_priv;
1391 struct mpc_group *grp = priv->mpcg;
1392 struct sk_buff *skb = ch->trans_skb;
1393 struct sk_buff *new_skb;
1394 unsigned long saveflags = 0;
1395 int len = ch->max_bufsize - ch->irb->scsw.cmd.count;
1396
1397 CTCM_PR_DEBUG("%s: %s: cp:%i %s maxbuf : %04x, len: %04x\n",
1398 CTCM_FUNTAIL, dev->name, smp_processor_id(),
1399 ch->id, ch->max_bufsize, len);
1400 fsm_deltimer(&ch->timer);
1401
1402 if (skb == NULL) {
1403 CTCM_DBF_TEXT_(MPC_ERROR, CTC_DBF_ERROR,
1404 "%s(%s): TRANS_SKB = NULL",
1405 CTCM_FUNTAIL, dev->name);
1406 goto again;
1407 }
1408
1409 if (len < TH_HEADER_LENGTH) {
1410 CTCM_DBF_TEXT_(MPC_ERROR, CTC_DBF_ERROR,
1411 "%s(%s): packet length %d to short",
1412 CTCM_FUNTAIL, dev->name, len);
1413 priv->stats.rx_dropped++;
1414 priv->stats.rx_length_errors++;
1415 } else {
1416
1417 __u32 block_len = len;
1418 len = TH_HEADER_LENGTH + XID2_LENGTH + 4;
1419 new_skb = __dev_alloc_skb(ch->max_bufsize, GFP_ATOMIC);
1420
1421 if (new_skb == NULL) {
1422 CTCM_DBF_TEXT_(MPC_ERROR, CTC_DBF_ERROR,
1423 "%s(%d): skb allocation failed",
1424 CTCM_FUNTAIL, dev->name);
1425 fsm_event(priv->mpcg->fsm, MPCG_EVENT_INOP, dev);
1426 goto again;
1427 }
1428 switch (fsm_getstate(grp->fsm)) {
1429 case MPCG_STATE_RESET:
1430 case MPCG_STATE_INOP:
1431 dev_kfree_skb_any(new_skb);
1432 break;
1433 case MPCG_STATE_FLOWC:
1434 case MPCG_STATE_READY:
1435 skb_put_data(new_skb, skb->data, block_len);
1436 skb_queue_tail(&ch->io_queue, new_skb);
1437 tasklet_schedule(&ch->ch_tasklet);
1438 break;
1439 default:
1440 skb_put_data(new_skb, skb->data, len);
1441 skb_queue_tail(&ch->io_queue, new_skb);
1442 tasklet_hi_schedule(&ch->ch_tasklet);
1443 break;
1444 }
1445 }
1446
1447again:
1448 switch (fsm_getstate(grp->fsm)) {
1449 int rc, dolock;
1450 case MPCG_STATE_FLOWC:
1451 case MPCG_STATE_READY:
1452 if (ctcm_checkalloc_buffer(ch))
1453 break;
1454 ch->trans_skb->data = ch->trans_skb_data;
1455 skb_reset_tail_pointer(ch->trans_skb);
1456 ch->trans_skb->len = 0;
1457 ch->ccw[1].count = ch->max_bufsize;
1458 if (do_debug_ccw)
1459 ctcmpc_dumpit((char *)&ch->ccw[0],
1460 sizeof(struct ccw1) * 3);
1461 dolock = !in_irq();
1462 if (dolock)
1463 spin_lock_irqsave(
1464 get_ccwdev_lock(ch->cdev), saveflags);
1465 rc = ccw_device_start(ch->cdev, &ch->ccw[0],
1466 (unsigned long)ch, 0xff, 0);
1467 if (dolock)
1468 spin_unlock_irqrestore(
1469 get_ccwdev_lock(ch->cdev), saveflags);
1470 if (rc != 0)
1471 ctcm_ccw_check_rc(ch, rc, "normal RX");
1472 default:
1473 break;
1474 }
1475
1476 CTCM_PR_DEBUG("Exit %s: %s, ch=0x%p, id=%s\n",
1477 __func__, dev->name, ch, ch->id);
1478
1479}
1480
1481
1482
1483
1484
1485
1486
1487
1488static void ctcmpc_chx_firstio(fsm_instance *fi, int event, void *arg)
1489{
1490 struct channel *ch = arg;
1491 struct net_device *dev = ch->netdev;
1492 struct ctcm_priv *priv = dev->ml_priv;
1493 struct mpc_group *gptr = priv->mpcg;
1494
1495 CTCM_PR_DEBUG("Enter %s: id=%s, ch=0x%p\n",
1496 __func__, ch->id, ch);
1497
1498 CTCM_DBF_TEXT_(MPC_TRACE, CTC_DBF_INFO,
1499 "%s: %s: chstate:%i, grpstate:%i, prot:%i\n",
1500 CTCM_FUNTAIL, ch->id, fsm_getstate(fi),
1501 fsm_getstate(gptr->fsm), ch->protocol);
1502
1503 if (fsm_getstate(fi) == CTC_STATE_TXIDLE)
1504 MPC_DBF_DEV_NAME(TRACE, dev, "remote side issued READ? ");
1505
1506 fsm_deltimer(&ch->timer);
1507 if (ctcm_checkalloc_buffer(ch))
1508 goto done;
1509
1510 switch (fsm_getstate(fi)) {
1511 case CTC_STATE_STARTRETRY:
1512 case CTC_STATE_SETUPWAIT:
1513 if (CHANNEL_DIRECTION(ch->flags) == CTCM_READ) {
1514 ctcmpc_chx_rxidle(fi, event, arg);
1515 } else {
1516 fsm_newstate(fi, CTC_STATE_TXIDLE);
1517 fsm_event(priv->fsm, DEV_EVENT_TXUP, dev);
1518 }
1519 goto done;
1520 default:
1521 break;
1522 }
1523
1524 fsm_newstate(fi, (CHANNEL_DIRECTION(ch->flags) == CTCM_READ)
1525 ? CTC_STATE_RXINIT : CTC_STATE_TXINIT);
1526
1527done:
1528 CTCM_PR_DEBUG("Exit %s: id=%s, ch=0x%p\n",
1529 __func__, ch->id, ch);
1530 return;
1531}
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542void ctcmpc_chx_rxidle(fsm_instance *fi, int event, void *arg)
1543{
1544 struct channel *ch = arg;
1545 struct net_device *dev = ch->netdev;
1546 struct ctcm_priv *priv = dev->ml_priv;
1547 struct mpc_group *grp = priv->mpcg;
1548 int rc;
1549 unsigned long saveflags = 0;
1550
1551 fsm_deltimer(&ch->timer);
1552 CTCM_PR_DEBUG("%s: %s: %s: cp:%i, chstate:%i grpstate:%i\n",
1553 __func__, ch->id, dev->name, smp_processor_id(),
1554 fsm_getstate(fi), fsm_getstate(grp->fsm));
1555
1556 fsm_newstate(fi, CTC_STATE_RXIDLE);
1557
1558
1559 switch (fsm_getstate(grp->fsm)) {
1560 case MPCG_STATE_FLOWC:
1561 case MPCG_STATE_READY:
1562 if (ctcm_checkalloc_buffer(ch))
1563 goto done;
1564 ch->trans_skb->data = ch->trans_skb_data;
1565 skb_reset_tail_pointer(ch->trans_skb);
1566 ch->trans_skb->len = 0;
1567 ch->ccw[1].count = ch->max_bufsize;
1568 CTCM_CCW_DUMP((char *)&ch->ccw[0], sizeof(struct ccw1) * 3);
1569 if (event == CTC_EVENT_START)
1570
1571 spin_lock_irqsave(get_ccwdev_lock(ch->cdev), saveflags);
1572 rc = ccw_device_start(ch->cdev, &ch->ccw[0],
1573 (unsigned long)ch, 0xff, 0);
1574 if (event == CTC_EVENT_START)
1575 spin_unlock_irqrestore(
1576 get_ccwdev_lock(ch->cdev), saveflags);
1577 if (rc != 0) {
1578 fsm_newstate(fi, CTC_STATE_RXINIT);
1579 ctcm_ccw_check_rc(ch, rc, "initial RX");
1580 goto done;
1581 }
1582 break;
1583 default:
1584 break;
1585 }
1586
1587 fsm_event(priv->fsm, DEV_EVENT_RXUP, dev);
1588done:
1589 return;
1590}
1591
1592
1593
1594
1595
1596
1597static void ctcmpc_chx_attn(fsm_instance *fsm, int event, void *arg)
1598{
1599 struct channel *ch = arg;
1600 struct net_device *dev = ch->netdev;
1601 struct ctcm_priv *priv = dev->ml_priv;
1602 struct mpc_group *grp = priv->mpcg;
1603
1604 CTCM_PR_DEBUG("%s(%s): %s(ch=0x%p), cp=%i, ChStat:%s, GrpStat:%s\n",
1605 __func__, dev->name, ch->id, ch, smp_processor_id(),
1606 fsm_getstate_str(ch->fsm), fsm_getstate_str(grp->fsm));
1607
1608 switch (fsm_getstate(grp->fsm)) {
1609 case MPCG_STATE_XID2INITW:
1610
1611 if (!ch->in_mpcgroup)
1612 break;
1613 if (fsm_getstate(ch->fsm) == CH_XID0_PENDING) {
1614 fsm_deltimer(&grp->timer);
1615 fsm_addtimer(&grp->timer,
1616 MPC_XID_TIMEOUT_VALUE,
1617 MPCG_EVENT_TIMER, dev);
1618 fsm_event(grp->fsm, MPCG_EVENT_XID0DO, ch);
1619
1620 } else if (fsm_getstate(ch->fsm) < CH_XID7_PENDING1)
1621
1622 fsm_newstate(ch->fsm, CH_XID7_PENDING1);
1623 break;
1624 case MPCG_STATE_XID2INITX:
1625 case MPCG_STATE_XID0IOWAIT:
1626 case MPCG_STATE_XID0IOWAIX:
1627
1628
1629 if (fsm_getstate(ch->fsm) < CH_XID7_PENDING1)
1630 fsm_newstate(ch->fsm, CH_XID7_PENDING1);
1631 break;
1632 case MPCG_STATE_XID7INITW:
1633 case MPCG_STATE_XID7INITX:
1634 case MPCG_STATE_XID7INITI:
1635 case MPCG_STATE_XID7INITZ:
1636 switch (fsm_getstate(ch->fsm)) {
1637 case CH_XID7_PENDING:
1638 fsm_newstate(ch->fsm, CH_XID7_PENDING1);
1639 break;
1640 case CH_XID7_PENDING2:
1641 fsm_newstate(ch->fsm, CH_XID7_PENDING3);
1642 break;
1643 }
1644 fsm_event(grp->fsm, MPCG_EVENT_XID7DONE, dev);
1645 break;
1646 }
1647
1648 return;
1649}
1650
1651
1652
1653
1654
1655
1656static void ctcmpc_chx_attnbusy(fsm_instance *fsm, int event, void *arg)
1657{
1658 struct channel *ch = arg;
1659 struct net_device *dev = ch->netdev;
1660 struct ctcm_priv *priv = dev->ml_priv;
1661 struct mpc_group *grp = priv->mpcg;
1662
1663 CTCM_PR_DEBUG("%s(%s): %s\n ChState:%s GrpState:%s\n",
1664 __func__, dev->name, ch->id,
1665 fsm_getstate_str(ch->fsm), fsm_getstate_str(grp->fsm));
1666
1667 fsm_deltimer(&ch->timer);
1668
1669 switch (fsm_getstate(grp->fsm)) {
1670 case MPCG_STATE_XID0IOWAIT:
1671
1672
1673
1674 grp->changed_side = 1;
1675 fsm_newstate(grp->fsm, MPCG_STATE_XID2INITW);
1676 break;
1677 case MPCG_STATE_XID2INITW:
1678 if (grp->changed_side == 1) {
1679 grp->changed_side = 2;
1680 break;
1681 }
1682
1683
1684
1685 if (grp->estconnfunc)
1686 goto done;
1687
1688
1689
1690
1691
1692 if (fsm_getstate(ch->fsm) == CH_XID0_INPROGRESS) {
1693 fsm_newstate(ch->fsm, CH_XID0_PENDING) ;
1694 fsm_deltimer(&grp->timer);
1695 goto done;
1696 }
1697 fsm_event(grp->fsm, MPCG_EVENT_INOP, dev);
1698 goto done;
1699 case MPCG_STATE_XID2INITX:
1700
1701
1702
1703 if (grp->changed_side == 1) {
1704 grp->changed_side = 2;
1705 break;
1706 }
1707 case MPCG_STATE_XID0IOWAIX:
1708 case MPCG_STATE_XID7INITW:
1709 case MPCG_STATE_XID7INITX:
1710 case MPCG_STATE_XID7INITI:
1711 case MPCG_STATE_XID7INITZ:
1712 default:
1713
1714
1715
1716 fsm_event(grp->fsm, MPCG_EVENT_INOP, dev);
1717 goto done;
1718 }
1719
1720 if (grp->changed_side == 1) {
1721 fsm_deltimer(&grp->timer);
1722 fsm_addtimer(&grp->timer, MPC_XID_TIMEOUT_VALUE,
1723 MPCG_EVENT_TIMER, dev);
1724 }
1725 if (ch->in_mpcgroup)
1726 fsm_event(grp->fsm, MPCG_EVENT_XID0DO, ch);
1727 else
1728 CTCM_DBF_TEXT_(MPC_ERROR, CTC_DBF_ERROR,
1729 "%s(%s): channel %s not added to group",
1730 CTCM_FUNTAIL, dev->name, ch->id);
1731
1732done:
1733 return;
1734}
1735
1736
1737
1738
1739
1740
1741static void ctcmpc_chx_resend(fsm_instance *fsm, int event, void *arg)
1742{
1743 struct channel *ch = arg;
1744 struct net_device *dev = ch->netdev;
1745 struct ctcm_priv *priv = dev->ml_priv;
1746 struct mpc_group *grp = priv->mpcg;
1747
1748 fsm_event(grp->fsm, MPCG_EVENT_XID0DO, ch);
1749 return;
1750}
1751
1752
1753
1754
1755
1756
1757static void ctcmpc_chx_send_sweep(fsm_instance *fsm, int event, void *arg)
1758{
1759 struct channel *ach = arg;
1760 struct net_device *dev = ach->netdev;
1761 struct ctcm_priv *priv = dev->ml_priv;
1762 struct mpc_group *grp = priv->mpcg;
1763 struct channel *wch = priv->channel[CTCM_WRITE];
1764 struct channel *rch = priv->channel[CTCM_READ];
1765 struct sk_buff *skb;
1766 struct th_sweep *header;
1767 int rc = 0;
1768 unsigned long saveflags = 0;
1769
1770 CTCM_PR_DEBUG("ctcmpc enter: %s(): cp=%i ch=0x%p id=%s\n",
1771 __func__, smp_processor_id(), ach, ach->id);
1772
1773 if (grp->in_sweep == 0)
1774 goto done;
1775
1776 CTCM_PR_DBGDATA("%s: 1: ToVTAM_th_seq= %08x\n" ,
1777 __func__, wch->th_seq_num);
1778 CTCM_PR_DBGDATA("%s: 1: FromVTAM_th_seq= %08x\n" ,
1779 __func__, rch->th_seq_num);
1780
1781 if (fsm_getstate(wch->fsm) != CTC_STATE_TXIDLE) {
1782
1783 fsm_addtimer(&wch->sweep_timer,
1784 200, CTC_EVENT_RSWEEP_TIMER, wch);
1785 goto done;
1786 }
1787
1788 skb = skb_dequeue(&wch->sweep_queue);
1789 if (!skb)
1790 goto done;
1791
1792 if (set_normalized_cda(&wch->ccw[4], skb->data)) {
1793 grp->in_sweep = 0;
1794 ctcm_clear_busy_do(dev);
1795 dev_kfree_skb_any(skb);
1796 fsm_event(grp->fsm, MPCG_EVENT_INOP, dev);
1797 goto done;
1798 } else {
1799 refcount_inc(&skb->users);
1800 skb_queue_tail(&wch->io_queue, skb);
1801 }
1802
1803
1804 wch->ccw[4].count = skb->len;
1805
1806 header = (struct th_sweep *)skb->data;
1807 switch (header->th.th_ch_flag) {
1808 case TH_SWEEP_REQ:
1809 grp->sweep_req_pend_num--;
1810 break;
1811 case TH_SWEEP_RESP:
1812 grp->sweep_rsp_pend_num--;
1813 break;
1814 }
1815
1816 header->sw.th_last_seq = wch->th_seq_num;
1817
1818 CTCM_CCW_DUMP((char *)&wch->ccw[3], sizeof(struct ccw1) * 3);
1819 CTCM_PR_DBGDATA("%s: sweep packet\n", __func__);
1820 CTCM_D3_DUMP((char *)header, TH_SWEEP_LENGTH);
1821
1822 fsm_addtimer(&wch->timer, CTCM_TIME_5_SEC, CTC_EVENT_TIMER, wch);
1823 fsm_newstate(wch->fsm, CTC_STATE_TX);
1824
1825 spin_lock_irqsave(get_ccwdev_lock(wch->cdev), saveflags);
1826 wch->prof.send_stamp = jiffies;
1827 rc = ccw_device_start(wch->cdev, &wch->ccw[3],
1828 (unsigned long) wch, 0xff, 0);
1829 spin_unlock_irqrestore(get_ccwdev_lock(wch->cdev), saveflags);
1830
1831 if ((grp->sweep_req_pend_num == 0) &&
1832 (grp->sweep_rsp_pend_num == 0)) {
1833 grp->in_sweep = 0;
1834 rch->th_seq_num = 0x00;
1835 wch->th_seq_num = 0x00;
1836 ctcm_clear_busy_do(dev);
1837 }
1838
1839 CTCM_PR_DBGDATA("%s: To-/From-VTAM_th_seq = %08x/%08x\n" ,
1840 __func__, wch->th_seq_num, rch->th_seq_num);
1841
1842 if (rc != 0)
1843 ctcm_ccw_check_rc(wch, rc, "send sweep");
1844
1845done:
1846 return;
1847}
1848
1849
1850
1851
1852
1853
1854const fsm_node ctcmpc_ch_fsm[] = {
1855 { CTC_STATE_STOPPED, CTC_EVENT_STOP, ctcm_action_nop },
1856 { CTC_STATE_STOPPED, CTC_EVENT_START, ctcm_chx_start },
1857 { CTC_STATE_STOPPED, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1858 { CTC_STATE_STOPPED, CTC_EVENT_FINSTAT, ctcm_action_nop },
1859 { CTC_STATE_STOPPED, CTC_EVENT_MC_FAIL, ctcm_action_nop },
1860
1861 { CTC_STATE_NOTOP, CTC_EVENT_STOP, ctcm_chx_stop },
1862 { CTC_STATE_NOTOP, CTC_EVENT_START, ctcm_action_nop },
1863 { CTC_STATE_NOTOP, CTC_EVENT_FINSTAT, ctcm_action_nop },
1864 { CTC_STATE_NOTOP, CTC_EVENT_MC_FAIL, ctcm_action_nop },
1865 { CTC_STATE_NOTOP, CTC_EVENT_MC_GOOD, ctcm_chx_start },
1866 { CTC_STATE_NOTOP, CTC_EVENT_UC_RCRESET, ctcm_chx_stop },
1867 { CTC_STATE_NOTOP, CTC_EVENT_UC_RSRESET, ctcm_chx_stop },
1868 { CTC_STATE_NOTOP, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1869
1870 { CTC_STATE_STARTWAIT, CTC_EVENT_STOP, ctcm_chx_haltio },
1871 { CTC_STATE_STARTWAIT, CTC_EVENT_START, ctcm_action_nop },
1872 { CTC_STATE_STARTWAIT, CTC_EVENT_FINSTAT, ctcm_chx_setmode },
1873 { CTC_STATE_STARTWAIT, CTC_EVENT_TIMER, ctcm_chx_setuperr },
1874 { CTC_STATE_STARTWAIT, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1875 { CTC_STATE_STARTWAIT, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1876
1877 { CTC_STATE_STARTRETRY, CTC_EVENT_STOP, ctcm_chx_haltio },
1878 { CTC_STATE_STARTRETRY, CTC_EVENT_TIMER, ctcm_chx_setmode },
1879 { CTC_STATE_STARTRETRY, CTC_EVENT_FINSTAT, ctcm_chx_setmode },
1880 { CTC_STATE_STARTRETRY, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1881 { CTC_STATE_STARTRETRY, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1882
1883 { CTC_STATE_SETUPWAIT, CTC_EVENT_STOP, ctcm_chx_haltio },
1884 { CTC_STATE_SETUPWAIT, CTC_EVENT_START, ctcm_action_nop },
1885 { CTC_STATE_SETUPWAIT, CTC_EVENT_FINSTAT, ctcmpc_chx_firstio },
1886 { CTC_STATE_SETUPWAIT, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1887 { CTC_STATE_SETUPWAIT, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1888 { CTC_STATE_SETUPWAIT, CTC_EVENT_TIMER, ctcm_chx_setmode },
1889 { CTC_STATE_SETUPWAIT, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1890 { CTC_STATE_SETUPWAIT, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1891
1892 { CTC_STATE_RXINIT, CTC_EVENT_STOP, ctcm_chx_haltio },
1893 { CTC_STATE_RXINIT, CTC_EVENT_START, ctcm_action_nop },
1894 { CTC_STATE_RXINIT, CTC_EVENT_FINSTAT, ctcmpc_chx_rxidle },
1895 { CTC_STATE_RXINIT, CTC_EVENT_UC_RCRESET, ctcm_chx_rxiniterr },
1896 { CTC_STATE_RXINIT, CTC_EVENT_UC_RSRESET, ctcm_chx_rxiniterr },
1897 { CTC_STATE_RXINIT, CTC_EVENT_TIMER, ctcm_chx_rxiniterr },
1898 { CTC_STATE_RXINIT, CTC_EVENT_ATTNBUSY, ctcm_chx_rxinitfail },
1899 { CTC_STATE_RXINIT, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1900 { CTC_STATE_RXINIT, CTC_EVENT_UC_ZERO, ctcmpc_chx_firstio },
1901 { CTC_STATE_RXINIT, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1902
1903 { CH_XID0_PENDING, CTC_EVENT_FINSTAT, ctcm_action_nop },
1904 { CH_XID0_PENDING, CTC_EVENT_ATTN, ctcmpc_chx_attn },
1905 { CH_XID0_PENDING, CTC_EVENT_STOP, ctcm_chx_haltio },
1906 { CH_XID0_PENDING, CTC_EVENT_START, ctcm_action_nop },
1907 { CH_XID0_PENDING, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1908 { CH_XID0_PENDING, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1909 { CH_XID0_PENDING, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1910 { CH_XID0_PENDING, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1911 { CH_XID0_PENDING, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1912 { CH_XID0_PENDING, CTC_EVENT_ATTNBUSY, ctcm_chx_iofatal },
1913
1914 { CH_XID0_INPROGRESS, CTC_EVENT_FINSTAT, ctcmpc_chx_rx },
1915 { CH_XID0_INPROGRESS, CTC_EVENT_ATTN, ctcmpc_chx_attn },
1916 { CH_XID0_INPROGRESS, CTC_EVENT_STOP, ctcm_chx_haltio },
1917 { CH_XID0_INPROGRESS, CTC_EVENT_START, ctcm_action_nop },
1918 { CH_XID0_INPROGRESS, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1919 { CH_XID0_INPROGRESS, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1920 { CH_XID0_INPROGRESS, CTC_EVENT_UC_ZERO, ctcmpc_chx_rx },
1921 { CH_XID0_INPROGRESS, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1922 { CH_XID0_INPROGRESS, CTC_EVENT_ATTNBUSY, ctcmpc_chx_attnbusy },
1923 { CH_XID0_INPROGRESS, CTC_EVENT_TIMER, ctcmpc_chx_resend },
1924 { CH_XID0_INPROGRESS, CTC_EVENT_IO_EBUSY, ctcm_chx_fail },
1925
1926 { CH_XID7_PENDING, CTC_EVENT_FINSTAT, ctcmpc_chx_rx },
1927 { CH_XID7_PENDING, CTC_EVENT_ATTN, ctcmpc_chx_attn },
1928 { CH_XID7_PENDING, CTC_EVENT_STOP, ctcm_chx_haltio },
1929 { CH_XID7_PENDING, CTC_EVENT_START, ctcm_action_nop },
1930 { CH_XID7_PENDING, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1931 { CH_XID7_PENDING, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1932 { CH_XID7_PENDING, CTC_EVENT_UC_ZERO, ctcmpc_chx_rx },
1933 { CH_XID7_PENDING, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1934 { CH_XID7_PENDING, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1935 { CH_XID7_PENDING, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1936 { CH_XID7_PENDING, CTC_EVENT_ATTNBUSY, ctcm_chx_iofatal },
1937 { CH_XID7_PENDING, CTC_EVENT_TIMER, ctcmpc_chx_resend },
1938 { CH_XID7_PENDING, CTC_EVENT_IO_EBUSY, ctcm_chx_fail },
1939
1940 { CH_XID7_PENDING1, CTC_EVENT_FINSTAT, ctcmpc_chx_rx },
1941 { CH_XID7_PENDING1, CTC_EVENT_ATTN, ctcmpc_chx_attn },
1942 { CH_XID7_PENDING1, CTC_EVENT_STOP, ctcm_chx_haltio },
1943 { CH_XID7_PENDING1, CTC_EVENT_START, ctcm_action_nop },
1944 { CH_XID7_PENDING1, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1945 { CH_XID7_PENDING1, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1946 { CH_XID7_PENDING1, CTC_EVENT_UC_ZERO, ctcmpc_chx_rx },
1947 { CH_XID7_PENDING1, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1948 { CH_XID7_PENDING1, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1949 { CH_XID7_PENDING1, CTC_EVENT_ATTNBUSY, ctcm_chx_iofatal },
1950 { CH_XID7_PENDING1, CTC_EVENT_TIMER, ctcmpc_chx_resend },
1951 { CH_XID7_PENDING1, CTC_EVENT_IO_EBUSY, ctcm_chx_fail },
1952
1953 { CH_XID7_PENDING2, CTC_EVENT_FINSTAT, ctcmpc_chx_rx },
1954 { CH_XID7_PENDING2, CTC_EVENT_ATTN, ctcmpc_chx_attn },
1955 { CH_XID7_PENDING2, CTC_EVENT_STOP, ctcm_chx_haltio },
1956 { CH_XID7_PENDING2, CTC_EVENT_START, ctcm_action_nop },
1957 { CH_XID7_PENDING2, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1958 { CH_XID7_PENDING2, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1959 { CH_XID7_PENDING2, CTC_EVENT_UC_ZERO, ctcmpc_chx_rx },
1960 { CH_XID7_PENDING2, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1961 { CH_XID7_PENDING2, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1962 { CH_XID7_PENDING2, CTC_EVENT_ATTNBUSY, ctcm_chx_iofatal },
1963 { CH_XID7_PENDING2, CTC_EVENT_TIMER, ctcmpc_chx_resend },
1964 { CH_XID7_PENDING2, CTC_EVENT_IO_EBUSY, ctcm_chx_fail },
1965
1966 { CH_XID7_PENDING3, CTC_EVENT_FINSTAT, ctcmpc_chx_rx },
1967 { CH_XID7_PENDING3, CTC_EVENT_ATTN, ctcmpc_chx_attn },
1968 { CH_XID7_PENDING3, CTC_EVENT_STOP, ctcm_chx_haltio },
1969 { CH_XID7_PENDING3, CTC_EVENT_START, ctcm_action_nop },
1970 { CH_XID7_PENDING3, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1971 { CH_XID7_PENDING3, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1972 { CH_XID7_PENDING3, CTC_EVENT_UC_ZERO, ctcmpc_chx_rx },
1973 { CH_XID7_PENDING3, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1974 { CH_XID7_PENDING3, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1975 { CH_XID7_PENDING3, CTC_EVENT_ATTNBUSY, ctcm_chx_iofatal },
1976 { CH_XID7_PENDING3, CTC_EVENT_TIMER, ctcmpc_chx_resend },
1977 { CH_XID7_PENDING3, CTC_EVENT_IO_EBUSY, ctcm_chx_fail },
1978
1979 { CH_XID7_PENDING4, CTC_EVENT_FINSTAT, ctcmpc_chx_rx },
1980 { CH_XID7_PENDING4, CTC_EVENT_ATTN, ctcmpc_chx_attn },
1981 { CH_XID7_PENDING4, CTC_EVENT_STOP, ctcm_chx_haltio },
1982 { CH_XID7_PENDING4, CTC_EVENT_START, ctcm_action_nop },
1983 { CH_XID7_PENDING4, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1984 { CH_XID7_PENDING4, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1985 { CH_XID7_PENDING4, CTC_EVENT_UC_ZERO, ctcmpc_chx_rx },
1986 { CH_XID7_PENDING4, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1987 { CH_XID7_PENDING4, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1988 { CH_XID7_PENDING4, CTC_EVENT_ATTNBUSY, ctcm_chx_iofatal },
1989 { CH_XID7_PENDING4, CTC_EVENT_TIMER, ctcmpc_chx_resend },
1990 { CH_XID7_PENDING4, CTC_EVENT_IO_EBUSY, ctcm_chx_fail },
1991
1992 { CTC_STATE_RXIDLE, CTC_EVENT_STOP, ctcm_chx_haltio },
1993 { CTC_STATE_RXIDLE, CTC_EVENT_START, ctcm_action_nop },
1994 { CTC_STATE_RXIDLE, CTC_EVENT_FINSTAT, ctcmpc_chx_rx },
1995 { CTC_STATE_RXIDLE, CTC_EVENT_UC_RCRESET, ctcm_chx_rxdisc },
1996 { CTC_STATE_RXIDLE, CTC_EVENT_UC_RSRESET, ctcm_chx_fail },
1997 { CTC_STATE_RXIDLE, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1998 { CTC_STATE_RXIDLE, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1999 { CTC_STATE_RXIDLE, CTC_EVENT_UC_ZERO, ctcmpc_chx_rx },
2000
2001 { CTC_STATE_TXINIT, CTC_EVENT_STOP, ctcm_chx_haltio },
2002 { CTC_STATE_TXINIT, CTC_EVENT_START, ctcm_action_nop },
2003 { CTC_STATE_TXINIT, CTC_EVENT_FINSTAT, ctcm_chx_txidle },
2004 { CTC_STATE_TXINIT, CTC_EVENT_UC_RCRESET, ctcm_chx_txiniterr },
2005 { CTC_STATE_TXINIT, CTC_EVENT_UC_RSRESET, ctcm_chx_txiniterr },
2006 { CTC_STATE_TXINIT, CTC_EVENT_TIMER, ctcm_chx_txiniterr },
2007 { CTC_STATE_TXINIT, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
2008 { CTC_STATE_TXINIT, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
2009 { CTC_STATE_TXINIT, CTC_EVENT_RSWEEP_TIMER, ctcmpc_chx_send_sweep },
2010
2011 { CTC_STATE_TXIDLE, CTC_EVENT_STOP, ctcm_chx_haltio },
2012 { CTC_STATE_TXIDLE, CTC_EVENT_START, ctcm_action_nop },
2013 { CTC_STATE_TXIDLE, CTC_EVENT_FINSTAT, ctcmpc_chx_firstio },
2014 { CTC_STATE_TXIDLE, CTC_EVENT_UC_RCRESET, ctcm_chx_fail },
2015 { CTC_STATE_TXIDLE, CTC_EVENT_UC_RSRESET, ctcm_chx_fail },
2016 { CTC_STATE_TXIDLE, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
2017 { CTC_STATE_TXIDLE, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
2018 { CTC_STATE_TXIDLE, CTC_EVENT_RSWEEP_TIMER, ctcmpc_chx_send_sweep },
2019
2020 { CTC_STATE_TERM, CTC_EVENT_STOP, ctcm_action_nop },
2021 { CTC_STATE_TERM, CTC_EVENT_START, ctcm_chx_restart },
2022 { CTC_STATE_TERM, CTC_EVENT_FINSTAT, ctcm_chx_stopped },
2023 { CTC_STATE_TERM, CTC_EVENT_UC_RCRESET, ctcm_action_nop },
2024 { CTC_STATE_TERM, CTC_EVENT_UC_RSRESET, ctcm_action_nop },
2025 { CTC_STATE_TERM, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
2026 { CTC_STATE_TERM, CTC_EVENT_IO_EBUSY, ctcm_chx_fail },
2027 { CTC_STATE_TERM, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
2028
2029 { CTC_STATE_DTERM, CTC_EVENT_STOP, ctcm_chx_haltio },
2030 { CTC_STATE_DTERM, CTC_EVENT_START, ctcm_chx_restart },
2031 { CTC_STATE_DTERM, CTC_EVENT_FINSTAT, ctcm_chx_setmode },
2032 { CTC_STATE_DTERM, CTC_EVENT_UC_RCRESET, ctcm_action_nop },
2033 { CTC_STATE_DTERM, CTC_EVENT_UC_RSRESET, ctcm_action_nop },
2034 { CTC_STATE_DTERM, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
2035 { CTC_STATE_DTERM, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
2036
2037 { CTC_STATE_TX, CTC_EVENT_STOP, ctcm_chx_haltio },
2038 { CTC_STATE_TX, CTC_EVENT_START, ctcm_action_nop },
2039 { CTC_STATE_TX, CTC_EVENT_FINSTAT, ctcmpc_chx_txdone },
2040 { CTC_STATE_TX, CTC_EVENT_UC_RCRESET, ctcm_chx_fail },
2041 { CTC_STATE_TX, CTC_EVENT_UC_RSRESET, ctcm_chx_fail },
2042 { CTC_STATE_TX, CTC_EVENT_TIMER, ctcm_chx_txretry },
2043 { CTC_STATE_TX, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
2044 { CTC_STATE_TX, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
2045 { CTC_STATE_TX, CTC_EVENT_RSWEEP_TIMER, ctcmpc_chx_send_sweep },
2046 { CTC_STATE_TX, CTC_EVENT_IO_EBUSY, ctcm_chx_fail },
2047
2048 { CTC_STATE_RXERR, CTC_EVENT_STOP, ctcm_chx_haltio },
2049 { CTC_STATE_TXERR, CTC_EVENT_STOP, ctcm_chx_haltio },
2050 { CTC_STATE_TXERR, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
2051 { CTC_STATE_TXERR, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
2052 { CTC_STATE_RXERR, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
2053};
2054
2055int mpc_ch_fsm_len = ARRAY_SIZE(ctcmpc_ch_fsm);
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068static void dev_action_start(fsm_instance *fi, int event, void *arg)
2069{
2070 struct net_device *dev = arg;
2071 struct ctcm_priv *priv = dev->ml_priv;
2072 int direction;
2073
2074 CTCMY_DBF_DEV_NAME(SETUP, dev, "");
2075
2076 fsm_deltimer(&priv->restart_timer);
2077 fsm_newstate(fi, DEV_STATE_STARTWAIT_RXTX);
2078 if (IS_MPC(priv))
2079 priv->mpcg->channels_terminating = 0;
2080 for (direction = CTCM_READ; direction <= CTCM_WRITE; direction++) {
2081 struct channel *ch = priv->channel[direction];
2082 fsm_event(ch->fsm, CTC_EVENT_START, ch);
2083 }
2084}
2085
2086
2087
2088
2089
2090
2091
2092
2093static void dev_action_stop(fsm_instance *fi, int event, void *arg)
2094{
2095 int direction;
2096 struct net_device *dev = arg;
2097 struct ctcm_priv *priv = dev->ml_priv;
2098
2099 CTCMY_DBF_DEV_NAME(SETUP, dev, "");
2100
2101 fsm_newstate(fi, DEV_STATE_STOPWAIT_RXTX);
2102 for (direction = CTCM_READ; direction <= CTCM_WRITE; direction++) {
2103 struct channel *ch = priv->channel[direction];
2104 fsm_event(ch->fsm, CTC_EVENT_STOP, ch);
2105 ch->th_seq_num = 0x00;
2106 CTCM_PR_DEBUG("%s: CH_th_seq= %08x\n",
2107 __func__, ch->th_seq_num);
2108 }
2109 if (IS_MPC(priv))
2110 fsm_newstate(priv->mpcg->fsm, MPCG_STATE_RESET);
2111}
2112
2113static void dev_action_restart(fsm_instance *fi, int event, void *arg)
2114{
2115 int restart_timer;
2116 struct net_device *dev = arg;
2117 struct ctcm_priv *priv = dev->ml_priv;
2118
2119 CTCMY_DBF_DEV_NAME(TRACE, dev, "");
2120
2121 if (IS_MPC(priv)) {
2122 restart_timer = CTCM_TIME_1_SEC;
2123 } else {
2124 restart_timer = CTCM_TIME_5_SEC;
2125 }
2126 dev_info(&dev->dev, "Restarting device\n");
2127
2128 dev_action_stop(fi, event, arg);
2129 fsm_event(priv->fsm, DEV_EVENT_STOP, dev);
2130 if (IS_MPC(priv))
2131 fsm_newstate(priv->mpcg->fsm, MPCG_STATE_RESET);
2132
2133
2134
2135
2136 fsm_addtimer(&priv->restart_timer, restart_timer,
2137 DEV_EVENT_START, dev);
2138}
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148static void dev_action_chup(fsm_instance *fi, int event, void *arg)
2149{
2150 struct net_device *dev = arg;
2151 struct ctcm_priv *priv = dev->ml_priv;
2152 int dev_stat = fsm_getstate(fi);
2153
2154 CTCM_DBF_TEXT_(SETUP, CTC_DBF_NOTICE,
2155 "%s(%s): priv = %p [%d,%d]\n ", CTCM_FUNTAIL,
2156 dev->name, dev->ml_priv, dev_stat, event);
2157
2158 switch (fsm_getstate(fi)) {
2159 case DEV_STATE_STARTWAIT_RXTX:
2160 if (event == DEV_EVENT_RXUP)
2161 fsm_newstate(fi, DEV_STATE_STARTWAIT_TX);
2162 else
2163 fsm_newstate(fi, DEV_STATE_STARTWAIT_RX);
2164 break;
2165 case DEV_STATE_STARTWAIT_RX:
2166 if (event == DEV_EVENT_RXUP) {
2167 fsm_newstate(fi, DEV_STATE_RUNNING);
2168 dev_info(&dev->dev,
2169 "Connected with remote side\n");
2170 ctcm_clear_busy(dev);
2171 }
2172 break;
2173 case DEV_STATE_STARTWAIT_TX:
2174 if (event == DEV_EVENT_TXUP) {
2175 fsm_newstate(fi, DEV_STATE_RUNNING);
2176 dev_info(&dev->dev,
2177 "Connected with remote side\n");
2178 ctcm_clear_busy(dev);
2179 }
2180 break;
2181 case DEV_STATE_STOPWAIT_TX:
2182 if (event == DEV_EVENT_RXUP)
2183 fsm_newstate(fi, DEV_STATE_STOPWAIT_RXTX);
2184 break;
2185 case DEV_STATE_STOPWAIT_RX:
2186 if (event == DEV_EVENT_TXUP)
2187 fsm_newstate(fi, DEV_STATE_STOPWAIT_RXTX);
2188 break;
2189 }
2190
2191 if (IS_MPC(priv)) {
2192 if (event == DEV_EVENT_RXUP)
2193 mpc_channel_action(priv->channel[CTCM_READ],
2194 CTCM_READ, MPC_CHANNEL_ADD);
2195 else
2196 mpc_channel_action(priv->channel[CTCM_WRITE],
2197 CTCM_WRITE, MPC_CHANNEL_ADD);
2198 }
2199}
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209static void dev_action_chdown(fsm_instance *fi, int event, void *arg)
2210{
2211
2212 struct net_device *dev = arg;
2213 struct ctcm_priv *priv = dev->ml_priv;
2214
2215 CTCMY_DBF_DEV_NAME(SETUP, dev, "");
2216
2217 switch (fsm_getstate(fi)) {
2218 case DEV_STATE_RUNNING:
2219 if (event == DEV_EVENT_TXDOWN)
2220 fsm_newstate(fi, DEV_STATE_STARTWAIT_TX);
2221 else
2222 fsm_newstate(fi, DEV_STATE_STARTWAIT_RX);
2223 break;
2224 case DEV_STATE_STARTWAIT_RX:
2225 if (event == DEV_EVENT_TXDOWN)
2226 fsm_newstate(fi, DEV_STATE_STARTWAIT_RXTX);
2227 break;
2228 case DEV_STATE_STARTWAIT_TX:
2229 if (event == DEV_EVENT_RXDOWN)
2230 fsm_newstate(fi, DEV_STATE_STARTWAIT_RXTX);
2231 break;
2232 case DEV_STATE_STOPWAIT_RXTX:
2233 if (event == DEV_EVENT_TXDOWN)
2234 fsm_newstate(fi, DEV_STATE_STOPWAIT_RX);
2235 else
2236 fsm_newstate(fi, DEV_STATE_STOPWAIT_TX);
2237 break;
2238 case DEV_STATE_STOPWAIT_RX:
2239 if (event == DEV_EVENT_RXDOWN)
2240 fsm_newstate(fi, DEV_STATE_STOPPED);
2241 break;
2242 case DEV_STATE_STOPWAIT_TX:
2243 if (event == DEV_EVENT_TXDOWN)
2244 fsm_newstate(fi, DEV_STATE_STOPPED);
2245 break;
2246 }
2247 if (IS_MPC(priv)) {
2248 if (event == DEV_EVENT_RXDOWN)
2249 mpc_channel_action(priv->channel[CTCM_READ],
2250 CTCM_READ, MPC_CHANNEL_REMOVE);
2251 else
2252 mpc_channel_action(priv->channel[CTCM_WRITE],
2253 CTCM_WRITE, MPC_CHANNEL_REMOVE);
2254 }
2255}
2256
2257const fsm_node dev_fsm[] = {
2258 { DEV_STATE_STOPPED, DEV_EVENT_START, dev_action_start },
2259 { DEV_STATE_STOPWAIT_RXTX, DEV_EVENT_START, dev_action_start },
2260 { DEV_STATE_STOPWAIT_RXTX, DEV_EVENT_RXDOWN, dev_action_chdown },
2261 { DEV_STATE_STOPWAIT_RXTX, DEV_EVENT_TXDOWN, dev_action_chdown },
2262 { DEV_STATE_STOPWAIT_RXTX, DEV_EVENT_RESTART, dev_action_restart },
2263 { DEV_STATE_STOPWAIT_RX, DEV_EVENT_START, dev_action_start },
2264 { DEV_STATE_STOPWAIT_RX, DEV_EVENT_RXUP, dev_action_chup },
2265 { DEV_STATE_STOPWAIT_RX, DEV_EVENT_TXUP, dev_action_chup },
2266 { DEV_STATE_STOPWAIT_RX, DEV_EVENT_RXDOWN, dev_action_chdown },
2267 { DEV_STATE_STOPWAIT_RX, DEV_EVENT_RESTART, dev_action_restart },
2268 { DEV_STATE_STOPWAIT_TX, DEV_EVENT_START, dev_action_start },
2269 { DEV_STATE_STOPWAIT_TX, DEV_EVENT_RXUP, dev_action_chup },
2270 { DEV_STATE_STOPWAIT_TX, DEV_EVENT_TXUP, dev_action_chup },
2271 { DEV_STATE_STOPWAIT_TX, DEV_EVENT_TXDOWN, dev_action_chdown },
2272 { DEV_STATE_STOPWAIT_TX, DEV_EVENT_RESTART, dev_action_restart },
2273 { DEV_STATE_STARTWAIT_RXTX, DEV_EVENT_STOP, dev_action_stop },
2274 { DEV_STATE_STARTWAIT_RXTX, DEV_EVENT_RXUP, dev_action_chup },
2275 { DEV_STATE_STARTWAIT_RXTX, DEV_EVENT_TXUP, dev_action_chup },
2276 { DEV_STATE_STARTWAIT_RXTX, DEV_EVENT_RXDOWN, dev_action_chdown },
2277 { DEV_STATE_STARTWAIT_RXTX, DEV_EVENT_TXDOWN, dev_action_chdown },
2278 { DEV_STATE_STARTWAIT_RXTX, DEV_EVENT_RESTART, dev_action_restart },
2279 { DEV_STATE_STARTWAIT_TX, DEV_EVENT_STOP, dev_action_stop },
2280 { DEV_STATE_STARTWAIT_TX, DEV_EVENT_RXUP, dev_action_chup },
2281 { DEV_STATE_STARTWAIT_TX, DEV_EVENT_TXUP, dev_action_chup },
2282 { DEV_STATE_STARTWAIT_TX, DEV_EVENT_RXDOWN, dev_action_chdown },
2283 { DEV_STATE_STARTWAIT_TX, DEV_EVENT_RESTART, dev_action_restart },
2284 { DEV_STATE_STARTWAIT_RX, DEV_EVENT_STOP, dev_action_stop },
2285 { DEV_STATE_STARTWAIT_RX, DEV_EVENT_RXUP, dev_action_chup },
2286 { DEV_STATE_STARTWAIT_RX, DEV_EVENT_TXUP, dev_action_chup },
2287 { DEV_STATE_STARTWAIT_RX, DEV_EVENT_TXDOWN, dev_action_chdown },
2288 { DEV_STATE_STARTWAIT_RX, DEV_EVENT_RESTART, dev_action_restart },
2289 { DEV_STATE_RUNNING, DEV_EVENT_STOP, dev_action_stop },
2290 { DEV_STATE_RUNNING, DEV_EVENT_RXDOWN, dev_action_chdown },
2291 { DEV_STATE_RUNNING, DEV_EVENT_TXDOWN, dev_action_chdown },
2292 { DEV_STATE_RUNNING, DEV_EVENT_TXUP, ctcm_action_nop },
2293 { DEV_STATE_RUNNING, DEV_EVENT_RXUP, ctcm_action_nop },
2294 { DEV_STATE_RUNNING, DEV_EVENT_RESTART, dev_action_restart },
2295};
2296
2297int dev_fsm_len = ARRAY_SIZE(dev_fsm);
2298
2299
2300
2301