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15#ifndef _LINUX_NVME_H
16#define _LINUX_NVME_H
17
18#include <linux/types.h>
19#include <linux/uuid.h>
20
21
22#define NVMF_NQN_FIELD_LEN 256
23
24
25#define NVMF_NQN_SIZE 223
26
27#define NVMF_TRSVCID_SIZE 32
28#define NVMF_TRADDR_SIZE 256
29#define NVMF_TSAS_SIZE 256
30
31#define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
32
33#define NVME_RDMA_IP_PORT 4420
34
35#define NVME_NSID_ALL 0xffffffff
36
37enum nvme_subsys_type {
38 NVME_NQN_DISC = 1,
39 NVME_NQN_NVME = 2,
40};
41
42
43enum {
44 NVMF_ADDR_FAMILY_PCI = 0,
45 NVMF_ADDR_FAMILY_IP4 = 1,
46 NVMF_ADDR_FAMILY_IP6 = 2,
47 NVMF_ADDR_FAMILY_IB = 3,
48 NVMF_ADDR_FAMILY_FC = 4,
49};
50
51
52enum {
53 NVMF_TRTYPE_RDMA = 1,
54 NVMF_TRTYPE_FC = 2,
55 NVMF_TRTYPE_TCP = 3,
56 NVMF_TRTYPE_LOOP = 254,
57 NVMF_TRTYPE_MAX,
58};
59
60
61enum {
62 NVMF_TREQ_NOT_SPECIFIED = 0,
63 NVMF_TREQ_REQUIRED = 1,
64 NVMF_TREQ_NOT_REQUIRED = 2,
65#define NVME_TREQ_SECURE_CHANNEL_MASK \
66 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
67
68 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2),
69};
70
71
72
73
74enum {
75 NVMF_RDMA_QPTYPE_CONNECTED = 1,
76 NVMF_RDMA_QPTYPE_DATAGRAM = 2,
77};
78
79
80
81
82enum {
83 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1,
84 NVMF_RDMA_PRTYPE_IB = 2,
85 NVMF_RDMA_PRTYPE_ROCE = 3,
86 NVMF_RDMA_PRTYPE_ROCEV2 = 4,
87 NVMF_RDMA_PRTYPE_IWARP = 5,
88};
89
90
91
92
93enum {
94 NVMF_RDMA_CMS_RDMA_CM = 1,
95};
96
97#define NVME_AQ_DEPTH 32
98#define NVME_NR_AEN_COMMANDS 1
99#define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
100
101
102
103
104
105#define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
106
107enum {
108 NVME_REG_CAP = 0x0000,
109 NVME_REG_VS = 0x0008,
110 NVME_REG_INTMS = 0x000c,
111 NVME_REG_INTMC = 0x0010,
112 NVME_REG_CC = 0x0014,
113 NVME_REG_CSTS = 0x001c,
114 NVME_REG_NSSR = 0x0020,
115 NVME_REG_AQA = 0x0024,
116 NVME_REG_ASQ = 0x0028,
117 NVME_REG_ACQ = 0x0030,
118 NVME_REG_CMBLOC = 0x0038,
119 NVME_REG_CMBSZ = 0x003c,
120 NVME_REG_DBS = 0x1000,
121};
122
123#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
124#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
125#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
126#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
127#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
128#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
129
130#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
131#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
132
133enum {
134 NVME_CMBSZ_SQS = 1 << 0,
135 NVME_CMBSZ_CQS = 1 << 1,
136 NVME_CMBSZ_LISTS = 1 << 2,
137 NVME_CMBSZ_RDS = 1 << 3,
138 NVME_CMBSZ_WDS = 1 << 4,
139
140 NVME_CMBSZ_SZ_SHIFT = 12,
141 NVME_CMBSZ_SZ_MASK = 0xfffff,
142
143 NVME_CMBSZ_SZU_SHIFT = 8,
144 NVME_CMBSZ_SZU_MASK = 0xf,
145};
146
147
148
149
150
151#define NVME_NVM_IOSQES 6
152#define NVME_NVM_IOCQES 4
153
154enum {
155 NVME_CC_ENABLE = 1 << 0,
156 NVME_CC_CSS_NVM = 0 << 4,
157 NVME_CC_EN_SHIFT = 0,
158 NVME_CC_CSS_SHIFT = 4,
159 NVME_CC_MPS_SHIFT = 7,
160 NVME_CC_AMS_SHIFT = 11,
161 NVME_CC_SHN_SHIFT = 14,
162 NVME_CC_IOSQES_SHIFT = 16,
163 NVME_CC_IOCQES_SHIFT = 20,
164 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
165 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
166 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
167 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
168 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
169 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
170 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
171 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
172 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
173 NVME_CSTS_RDY = 1 << 0,
174 NVME_CSTS_CFS = 1 << 1,
175 NVME_CSTS_NSSRO = 1 << 4,
176 NVME_CSTS_PP = 1 << 5,
177 NVME_CSTS_SHST_NORMAL = 0 << 2,
178 NVME_CSTS_SHST_OCCUR = 1 << 2,
179 NVME_CSTS_SHST_CMPLT = 2 << 2,
180 NVME_CSTS_SHST_MASK = 3 << 2,
181};
182
183struct nvme_id_power_state {
184 __le16 max_power;
185 __u8 rsvd2;
186 __u8 flags;
187 __le32 entry_lat;
188 __le32 exit_lat;
189 __u8 read_tput;
190 __u8 read_lat;
191 __u8 write_tput;
192 __u8 write_lat;
193 __le16 idle_power;
194 __u8 idle_scale;
195 __u8 rsvd19;
196 __le16 active_power;
197 __u8 active_work_scale;
198 __u8 rsvd23[9];
199};
200
201enum {
202 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
203 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
204};
205
206enum nvme_ctrl_attr {
207 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
208 NVME_CTRL_ATTR_TBKAS = (1 << 6),
209};
210
211struct nvme_id_ctrl {
212 __le16 vid;
213 __le16 ssvid;
214 char sn[20];
215 char mn[40];
216 char fr[8];
217 __u8 rab;
218 __u8 ieee[3];
219 __u8 cmic;
220 __u8 mdts;
221 __le16 cntlid;
222 __le32 ver;
223 __le32 rtd3r;
224 __le32 rtd3e;
225 __le32 oaes;
226 __le32 ctratt;
227 __u8 rsvd100[28];
228 __le16 crdt1;
229 __le16 crdt2;
230 __le16 crdt3;
231 __u8 rsvd134[122];
232 __le16 oacs;
233 __u8 acl;
234 __u8 aerl;
235 __u8 frmw;
236 __u8 lpa;
237 __u8 elpe;
238 __u8 npss;
239 __u8 avscc;
240 __u8 apsta;
241 __le16 wctemp;
242 __le16 cctemp;
243 __le16 mtfa;
244 __le32 hmpre;
245 __le32 hmmin;
246 __u8 tnvmcap[16];
247 __u8 unvmcap[16];
248 __le32 rpmbs;
249 __le16 edstt;
250 __u8 dsto;
251 __u8 fwug;
252 __le16 kas;
253 __le16 hctma;
254 __le16 mntmt;
255 __le16 mxtmt;
256 __le32 sanicap;
257 __le32 hmminds;
258 __le16 hmmaxd;
259 __u8 rsvd338[4];
260 __u8 anatt;
261 __u8 anacap;
262 __le32 anagrpmax;
263 __le32 nanagrpid;
264 __u8 rsvd352[160];
265 __u8 sqes;
266 __u8 cqes;
267 __le16 maxcmd;
268 __le32 nn;
269 __le16 oncs;
270 __le16 fuses;
271 __u8 fna;
272 __u8 vwc;
273 __le16 awun;
274 __le16 awupf;
275 __u8 nvscc;
276 __u8 nwpc;
277 __le16 acwu;
278 __u8 rsvd534[2];
279 __le32 sgls;
280 __le32 mnan;
281 __u8 rsvd544[224];
282 char subnqn[256];
283 __u8 rsvd1024[768];
284 __le32 ioccsz;
285 __le32 iorcsz;
286 __le16 icdoff;
287 __u8 ctrattr;
288 __u8 msdbd;
289 __u8 rsvd1804[244];
290 struct nvme_id_power_state psd[32];
291 __u8 vs[1024];
292};
293
294enum {
295 NVME_CTRL_ONCS_COMPARE = 1 << 0,
296 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
297 NVME_CTRL_ONCS_DSM = 1 << 2,
298 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
299 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
300 NVME_CTRL_VWC_PRESENT = 1 << 0,
301 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
302 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
303 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
304 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
305};
306
307struct nvme_lbaf {
308 __le16 ms;
309 __u8 ds;
310 __u8 rp;
311};
312
313struct nvme_id_ns {
314 __le64 nsze;
315 __le64 ncap;
316 __le64 nuse;
317 __u8 nsfeat;
318 __u8 nlbaf;
319 __u8 flbas;
320 __u8 mc;
321 __u8 dpc;
322 __u8 dps;
323 __u8 nmic;
324 __u8 rescap;
325 __u8 fpi;
326 __u8 rsvd33;
327 __le16 nawun;
328 __le16 nawupf;
329 __le16 nacwu;
330 __le16 nabsn;
331 __le16 nabo;
332 __le16 nabspf;
333 __le16 noiob;
334 __u8 nvmcap[16];
335 __u8 rsvd64[28];
336 __le32 anagrpid;
337 __u8 rsvd96[3];
338 __u8 nsattr;
339 __u8 rsvd100[4];
340 __u8 nguid[16];
341 __u8 eui64[8];
342 struct nvme_lbaf lbaf[16];
343 __u8 rsvd192[192];
344 __u8 vs[3712];
345};
346
347enum {
348 NVME_ID_CNS_NS = 0x00,
349 NVME_ID_CNS_CTRL = 0x01,
350 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
351 NVME_ID_CNS_NS_DESC_LIST = 0x03,
352 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
353 NVME_ID_CNS_NS_PRESENT = 0x11,
354 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
355 NVME_ID_CNS_CTRL_LIST = 0x13,
356};
357
358enum {
359 NVME_DIR_IDENTIFY = 0x00,
360 NVME_DIR_STREAMS = 0x01,
361 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
362 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
363 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
364 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
365 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
366 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
367 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
368 NVME_DIR_ENDIR = 0x01,
369};
370
371enum {
372 NVME_NS_FEAT_THIN = 1 << 0,
373 NVME_NS_FLBAS_LBA_MASK = 0xf,
374 NVME_NS_FLBAS_META_EXT = 0x10,
375 NVME_LBAF_RP_BEST = 0,
376 NVME_LBAF_RP_BETTER = 1,
377 NVME_LBAF_RP_GOOD = 2,
378 NVME_LBAF_RP_DEGRADED = 3,
379 NVME_NS_DPC_PI_LAST = 1 << 4,
380 NVME_NS_DPC_PI_FIRST = 1 << 3,
381 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
382 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
383 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
384 NVME_NS_DPS_PI_FIRST = 1 << 3,
385 NVME_NS_DPS_PI_MASK = 0x7,
386 NVME_NS_DPS_PI_TYPE1 = 1,
387 NVME_NS_DPS_PI_TYPE2 = 2,
388 NVME_NS_DPS_PI_TYPE3 = 3,
389};
390
391struct nvme_ns_id_desc {
392 __u8 nidt;
393 __u8 nidl;
394 __le16 reserved;
395};
396
397#define NVME_NIDT_EUI64_LEN 8
398#define NVME_NIDT_NGUID_LEN 16
399#define NVME_NIDT_UUID_LEN 16
400
401enum {
402 NVME_NIDT_EUI64 = 0x01,
403 NVME_NIDT_NGUID = 0x02,
404 NVME_NIDT_UUID = 0x03,
405};
406
407struct nvme_smart_log {
408 __u8 critical_warning;
409 __u8 temperature[2];
410 __u8 avail_spare;
411 __u8 spare_thresh;
412 __u8 percent_used;
413 __u8 rsvd6[26];
414 __u8 data_units_read[16];
415 __u8 data_units_written[16];
416 __u8 host_reads[16];
417 __u8 host_writes[16];
418 __u8 ctrl_busy_time[16];
419 __u8 power_cycles[16];
420 __u8 power_on_hours[16];
421 __u8 unsafe_shutdowns[16];
422 __u8 media_errors[16];
423 __u8 num_err_log_entries[16];
424 __le32 warning_temp_time;
425 __le32 critical_comp_time;
426 __le16 temp_sensor[8];
427 __u8 rsvd216[296];
428};
429
430struct nvme_fw_slot_info_log {
431 __u8 afi;
432 __u8 rsvd1[7];
433 __le64 frs[7];
434 __u8 rsvd64[448];
435};
436
437enum {
438 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
439 NVME_CMD_EFFECTS_LBCC = 1 << 1,
440 NVME_CMD_EFFECTS_NCC = 1 << 2,
441 NVME_CMD_EFFECTS_NIC = 1 << 3,
442 NVME_CMD_EFFECTS_CCC = 1 << 4,
443 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
444};
445
446struct nvme_effects_log {
447 __le32 acs[256];
448 __le32 iocs[256];
449 __u8 resv[2048];
450};
451
452enum nvme_ana_state {
453 NVME_ANA_OPTIMIZED = 0x01,
454 NVME_ANA_NONOPTIMIZED = 0x02,
455 NVME_ANA_INACCESSIBLE = 0x03,
456 NVME_ANA_PERSISTENT_LOSS = 0x04,
457 NVME_ANA_CHANGE = 0x0f,
458};
459
460struct nvme_ana_group_desc {
461 __le32 grpid;
462 __le32 nnsids;
463 __le64 chgcnt;
464 __u8 state;
465 __u8 rsvd17[15];
466 __le32 nsids[];
467};
468
469
470#define NVME_ANA_LOG_RGO (1 << 0)
471
472struct nvme_ana_rsp_hdr {
473 __le64 chgcnt;
474 __le16 ngrps;
475 __le16 rsvd10[3];
476};
477
478enum {
479 NVME_SMART_CRIT_SPARE = 1 << 0,
480 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
481 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
482 NVME_SMART_CRIT_MEDIA = 1 << 3,
483 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
484};
485
486enum {
487 NVME_AER_ERROR = 0,
488 NVME_AER_SMART = 1,
489 NVME_AER_NOTICE = 2,
490 NVME_AER_CSS = 6,
491 NVME_AER_VS = 7,
492};
493
494enum {
495 NVME_AER_NOTICE_NS_CHANGED = 0x00,
496 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
497 NVME_AER_NOTICE_ANA = 0x03,
498 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
499};
500
501enum {
502 NVME_AEN_BIT_NS_ATTR = 8,
503 NVME_AEN_BIT_FW_ACT = 9,
504 NVME_AEN_BIT_ANA_CHANGE = 11,
505 NVME_AEN_BIT_DISC_CHANGE = 31,
506};
507
508enum {
509 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
510 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
511 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
512 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
513};
514
515struct nvme_lba_range_type {
516 __u8 type;
517 __u8 attributes;
518 __u8 rsvd2[14];
519 __u64 slba;
520 __u64 nlb;
521 __u8 guid[16];
522 __u8 rsvd48[16];
523};
524
525enum {
526 NVME_LBART_TYPE_FS = 0x01,
527 NVME_LBART_TYPE_RAID = 0x02,
528 NVME_LBART_TYPE_CACHE = 0x03,
529 NVME_LBART_TYPE_SWAP = 0x04,
530
531 NVME_LBART_ATTRIB_TEMP = 1 << 0,
532 NVME_LBART_ATTRIB_HIDE = 1 << 1,
533};
534
535struct nvme_reservation_status {
536 __le32 gen;
537 __u8 rtype;
538 __u8 regctl[2];
539 __u8 resv5[2];
540 __u8 ptpls;
541 __u8 resv10[13];
542 struct {
543 __le16 cntlid;
544 __u8 rcsts;
545 __u8 resv3[5];
546 __le64 hostid;
547 __le64 rkey;
548 } regctl_ds[];
549};
550
551enum nvme_async_event_type {
552 NVME_AER_TYPE_ERROR = 0,
553 NVME_AER_TYPE_SMART = 1,
554 NVME_AER_TYPE_NOTICE = 2,
555};
556
557
558
559enum nvme_opcode {
560 nvme_cmd_flush = 0x00,
561 nvme_cmd_write = 0x01,
562 nvme_cmd_read = 0x02,
563 nvme_cmd_write_uncor = 0x04,
564 nvme_cmd_compare = 0x05,
565 nvme_cmd_write_zeroes = 0x08,
566 nvme_cmd_dsm = 0x09,
567 nvme_cmd_resv_register = 0x0d,
568 nvme_cmd_resv_report = 0x0e,
569 nvme_cmd_resv_acquire = 0x11,
570 nvme_cmd_resv_release = 0x15,
571};
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581
582enum {
583 NVME_SGL_FMT_ADDRESS = 0x00,
584 NVME_SGL_FMT_OFFSET = 0x01,
585 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
586 NVME_SGL_FMT_INVALIDATE = 0x0f,
587};
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603enum {
604 NVME_SGL_FMT_DATA_DESC = 0x00,
605 NVME_SGL_FMT_SEG_DESC = 0x02,
606 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
607 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
608 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
609};
610
611struct nvme_sgl_desc {
612 __le64 addr;
613 __le32 length;
614 __u8 rsvd[3];
615 __u8 type;
616};
617
618struct nvme_keyed_sgl_desc {
619 __le64 addr;
620 __u8 length[3];
621 __u8 key[4];
622 __u8 type;
623};
624
625union nvme_data_ptr {
626 struct {
627 __le64 prp1;
628 __le64 prp2;
629 };
630 struct nvme_sgl_desc sgl;
631 struct nvme_keyed_sgl_desc ksgl;
632};
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647
648enum {
649 NVME_CMD_FUSE_FIRST = (1 << 0),
650 NVME_CMD_FUSE_SECOND = (1 << 1),
651
652 NVME_CMD_SGL_METABUF = (1 << 6),
653 NVME_CMD_SGL_METASEG = (1 << 7),
654 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
655};
656
657struct nvme_common_command {
658 __u8 opcode;
659 __u8 flags;
660 __u16 command_id;
661 __le32 nsid;
662 __le32 cdw2[2];
663 __le64 metadata;
664 union nvme_data_ptr dptr;
665 __le32 cdw10;
666 __le32 cdw11;
667 __le32 cdw12;
668 __le32 cdw13;
669 __le32 cdw14;
670 __le32 cdw15;
671};
672
673struct nvme_rw_command {
674 __u8 opcode;
675 __u8 flags;
676 __u16 command_id;
677 __le32 nsid;
678 __u64 rsvd2;
679 __le64 metadata;
680 union nvme_data_ptr dptr;
681 __le64 slba;
682 __le16 length;
683 __le16 control;
684 __le32 dsmgmt;
685 __le32 reftag;
686 __le16 apptag;
687 __le16 appmask;
688};
689
690enum {
691 NVME_RW_LR = 1 << 15,
692 NVME_RW_FUA = 1 << 14,
693 NVME_RW_DSM_FREQ_UNSPEC = 0,
694 NVME_RW_DSM_FREQ_TYPICAL = 1,
695 NVME_RW_DSM_FREQ_RARE = 2,
696 NVME_RW_DSM_FREQ_READS = 3,
697 NVME_RW_DSM_FREQ_WRITES = 4,
698 NVME_RW_DSM_FREQ_RW = 5,
699 NVME_RW_DSM_FREQ_ONCE = 6,
700 NVME_RW_DSM_FREQ_PREFETCH = 7,
701 NVME_RW_DSM_FREQ_TEMP = 8,
702 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
703 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
704 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
705 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
706 NVME_RW_DSM_SEQ_REQ = 1 << 6,
707 NVME_RW_DSM_COMPRESSED = 1 << 7,
708 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
709 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
710 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
711 NVME_RW_PRINFO_PRACT = 1 << 13,
712 NVME_RW_DTYPE_STREAMS = 1 << 4,
713};
714
715struct nvme_dsm_cmd {
716 __u8 opcode;
717 __u8 flags;
718 __u16 command_id;
719 __le32 nsid;
720 __u64 rsvd2[2];
721 union nvme_data_ptr dptr;
722 __le32 nr;
723 __le32 attributes;
724 __u32 rsvd12[4];
725};
726
727enum {
728 NVME_DSMGMT_IDR = 1 << 0,
729 NVME_DSMGMT_IDW = 1 << 1,
730 NVME_DSMGMT_AD = 1 << 2,
731};
732
733#define NVME_DSM_MAX_RANGES 256
734
735struct nvme_dsm_range {
736 __le32 cattr;
737 __le32 nlb;
738 __le64 slba;
739};
740
741struct nvme_write_zeroes_cmd {
742 __u8 opcode;
743 __u8 flags;
744 __u16 command_id;
745 __le32 nsid;
746 __u64 rsvd2;
747 __le64 metadata;
748 union nvme_data_ptr dptr;
749 __le64 slba;
750 __le16 length;
751 __le16 control;
752 __le32 dsmgmt;
753 __le32 reftag;
754 __le16 apptag;
755 __le16 appmask;
756};
757
758
759
760struct nvme_feat_auto_pst {
761 __le64 entries[32];
762};
763
764enum {
765 NVME_HOST_MEM_ENABLE = (1 << 0),
766 NVME_HOST_MEM_RETURN = (1 << 1),
767};
768
769struct nvme_feat_host_behavior {
770 __u8 acre;
771 __u8 resv1[511];
772};
773
774enum {
775 NVME_ENABLE_ACRE = 1,
776};
777
778
779
780enum nvme_admin_opcode {
781 nvme_admin_delete_sq = 0x00,
782 nvme_admin_create_sq = 0x01,
783 nvme_admin_get_log_page = 0x02,
784 nvme_admin_delete_cq = 0x04,
785 nvme_admin_create_cq = 0x05,
786 nvme_admin_identify = 0x06,
787 nvme_admin_abort_cmd = 0x08,
788 nvme_admin_set_features = 0x09,
789 nvme_admin_get_features = 0x0a,
790 nvme_admin_async_event = 0x0c,
791 nvme_admin_ns_mgmt = 0x0d,
792 nvme_admin_activate_fw = 0x10,
793 nvme_admin_download_fw = 0x11,
794 nvme_admin_ns_attach = 0x15,
795 nvme_admin_keep_alive = 0x18,
796 nvme_admin_directive_send = 0x19,
797 nvme_admin_directive_recv = 0x1a,
798 nvme_admin_dbbuf = 0x7C,
799 nvme_admin_format_nvm = 0x80,
800 nvme_admin_security_send = 0x81,
801 nvme_admin_security_recv = 0x82,
802 nvme_admin_sanitize_nvm = 0x84,
803};
804
805enum {
806 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
807 NVME_CQ_IRQ_ENABLED = (1 << 1),
808 NVME_SQ_PRIO_URGENT = (0 << 1),
809 NVME_SQ_PRIO_HIGH = (1 << 1),
810 NVME_SQ_PRIO_MEDIUM = (2 << 1),
811 NVME_SQ_PRIO_LOW = (3 << 1),
812 NVME_FEAT_ARBITRATION = 0x01,
813 NVME_FEAT_POWER_MGMT = 0x02,
814 NVME_FEAT_LBA_RANGE = 0x03,
815 NVME_FEAT_TEMP_THRESH = 0x04,
816 NVME_FEAT_ERR_RECOVERY = 0x05,
817 NVME_FEAT_VOLATILE_WC = 0x06,
818 NVME_FEAT_NUM_QUEUES = 0x07,
819 NVME_FEAT_IRQ_COALESCE = 0x08,
820 NVME_FEAT_IRQ_CONFIG = 0x09,
821 NVME_FEAT_WRITE_ATOMIC = 0x0a,
822 NVME_FEAT_ASYNC_EVENT = 0x0b,
823 NVME_FEAT_AUTO_PST = 0x0c,
824 NVME_FEAT_HOST_MEM_BUF = 0x0d,
825 NVME_FEAT_TIMESTAMP = 0x0e,
826 NVME_FEAT_KATO = 0x0f,
827 NVME_FEAT_HOST_BEHAVIOR = 0x16,
828 NVME_FEAT_SW_PROGRESS = 0x80,
829 NVME_FEAT_HOST_ID = 0x81,
830 NVME_FEAT_RESV_MASK = 0x82,
831 NVME_FEAT_RESV_PERSIST = 0x83,
832 NVME_FEAT_WRITE_PROTECT = 0x84,
833 NVME_LOG_ERROR = 0x01,
834 NVME_LOG_SMART = 0x02,
835 NVME_LOG_FW_SLOT = 0x03,
836 NVME_LOG_CHANGED_NS = 0x04,
837 NVME_LOG_CMD_EFFECTS = 0x05,
838 NVME_LOG_ANA = 0x0c,
839 NVME_LOG_DISC = 0x70,
840 NVME_LOG_RESERVATION = 0x80,
841 NVME_FWACT_REPL = (0 << 3),
842 NVME_FWACT_REPL_ACTV = (1 << 3),
843 NVME_FWACT_ACTV = (2 << 3),
844};
845
846
847enum {
848 NVME_NS_NO_WRITE_PROTECT = 0,
849 NVME_NS_WRITE_PROTECT,
850 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
851 NVME_NS_WRITE_PROTECT_PERMANENT,
852};
853
854#define NVME_MAX_CHANGED_NAMESPACES 1024
855
856struct nvme_identify {
857 __u8 opcode;
858 __u8 flags;
859 __u16 command_id;
860 __le32 nsid;
861 __u64 rsvd2[2];
862 union nvme_data_ptr dptr;
863 __u8 cns;
864 __u8 rsvd3;
865 __le16 ctrlid;
866 __u32 rsvd11[5];
867};
868
869#define NVME_IDENTIFY_DATA_SIZE 4096
870
871struct nvme_features {
872 __u8 opcode;
873 __u8 flags;
874 __u16 command_id;
875 __le32 nsid;
876 __u64 rsvd2[2];
877 union nvme_data_ptr dptr;
878 __le32 fid;
879 __le32 dword11;
880 __le32 dword12;
881 __le32 dword13;
882 __le32 dword14;
883 __le32 dword15;
884};
885
886struct nvme_host_mem_buf_desc {
887 __le64 addr;
888 __le32 size;
889 __u32 rsvd;
890};
891
892struct nvme_create_cq {
893 __u8 opcode;
894 __u8 flags;
895 __u16 command_id;
896 __u32 rsvd1[5];
897 __le64 prp1;
898 __u64 rsvd8;
899 __le16 cqid;
900 __le16 qsize;
901 __le16 cq_flags;
902 __le16 irq_vector;
903 __u32 rsvd12[4];
904};
905
906struct nvme_create_sq {
907 __u8 opcode;
908 __u8 flags;
909 __u16 command_id;
910 __u32 rsvd1[5];
911 __le64 prp1;
912 __u64 rsvd8;
913 __le16 sqid;
914 __le16 qsize;
915 __le16 sq_flags;
916 __le16 cqid;
917 __u32 rsvd12[4];
918};
919
920struct nvme_delete_queue {
921 __u8 opcode;
922 __u8 flags;
923 __u16 command_id;
924 __u32 rsvd1[9];
925 __le16 qid;
926 __u16 rsvd10;
927 __u32 rsvd11[5];
928};
929
930struct nvme_abort_cmd {
931 __u8 opcode;
932 __u8 flags;
933 __u16 command_id;
934 __u32 rsvd1[9];
935 __le16 sqid;
936 __u16 cid;
937 __u32 rsvd11[5];
938};
939
940struct nvme_download_firmware {
941 __u8 opcode;
942 __u8 flags;
943 __u16 command_id;
944 __u32 rsvd1[5];
945 union nvme_data_ptr dptr;
946 __le32 numd;
947 __le32 offset;
948 __u32 rsvd12[4];
949};
950
951struct nvme_format_cmd {
952 __u8 opcode;
953 __u8 flags;
954 __u16 command_id;
955 __le32 nsid;
956 __u64 rsvd2[4];
957 __le32 cdw10;
958 __u32 rsvd11[5];
959};
960
961struct nvme_get_log_page_command {
962 __u8 opcode;
963 __u8 flags;
964 __u16 command_id;
965 __le32 nsid;
966 __u64 rsvd2[2];
967 union nvme_data_ptr dptr;
968 __u8 lid;
969 __u8 lsp;
970 __le16 numdl;
971 __le16 numdu;
972 __u16 rsvd11;
973 __le32 lpol;
974 __le32 lpou;
975 __u32 rsvd14[2];
976};
977
978struct nvme_directive_cmd {
979 __u8 opcode;
980 __u8 flags;
981 __u16 command_id;
982 __le32 nsid;
983 __u64 rsvd2[2];
984 union nvme_data_ptr dptr;
985 __le32 numd;
986 __u8 doper;
987 __u8 dtype;
988 __le16 dspec;
989 __u8 endir;
990 __u8 tdtype;
991 __u16 rsvd15;
992
993 __u32 rsvd16[3];
994};
995
996
997
998
999enum nvmf_fabrics_opcode {
1000 nvme_fabrics_command = 0x7f,
1001};
1002
1003enum nvmf_capsule_command {
1004 nvme_fabrics_type_property_set = 0x00,
1005 nvme_fabrics_type_connect = 0x01,
1006 nvme_fabrics_type_property_get = 0x04,
1007};
1008
1009struct nvmf_common_command {
1010 __u8 opcode;
1011 __u8 resv1;
1012 __u16 command_id;
1013 __u8 fctype;
1014 __u8 resv2[35];
1015 __u8 ts[24];
1016};
1017
1018
1019
1020
1021
1022
1023
1024#define NVME_CNTLID_MIN 1
1025#define NVME_CNTLID_MAX 0xffef
1026#define NVME_CNTLID_DYNAMIC 0xffff
1027
1028#define MAX_DISC_LOGS 255
1029
1030
1031struct nvmf_disc_rsp_page_entry {
1032 __u8 trtype;
1033 __u8 adrfam;
1034 __u8 subtype;
1035 __u8 treq;
1036 __le16 portid;
1037 __le16 cntlid;
1038 __le16 asqsz;
1039 __u8 resv8[22];
1040 char trsvcid[NVMF_TRSVCID_SIZE];
1041 __u8 resv64[192];
1042 char subnqn[NVMF_NQN_FIELD_LEN];
1043 char traddr[NVMF_TRADDR_SIZE];
1044 union tsas {
1045 char common[NVMF_TSAS_SIZE];
1046 struct rdma {
1047 __u8 qptype;
1048 __u8 prtype;
1049 __u8 cms;
1050 __u8 resv3[5];
1051 __u16 pkey;
1052 __u8 resv10[246];
1053 } rdma;
1054 } tsas;
1055};
1056
1057
1058struct nvmf_disc_rsp_page_hdr {
1059 __le64 genctr;
1060 __le64 numrec;
1061 __le16 recfmt;
1062 __u8 resv14[1006];
1063 struct nvmf_disc_rsp_page_entry entries[0];
1064};
1065
1066enum {
1067 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1068};
1069
1070struct nvmf_connect_command {
1071 __u8 opcode;
1072 __u8 resv1;
1073 __u16 command_id;
1074 __u8 fctype;
1075 __u8 resv2[19];
1076 union nvme_data_ptr dptr;
1077 __le16 recfmt;
1078 __le16 qid;
1079 __le16 sqsize;
1080 __u8 cattr;
1081 __u8 resv3;
1082 __le32 kato;
1083 __u8 resv4[12];
1084};
1085
1086struct nvmf_connect_data {
1087 uuid_t hostid;
1088 __le16 cntlid;
1089 char resv4[238];
1090 char subsysnqn[NVMF_NQN_FIELD_LEN];
1091 char hostnqn[NVMF_NQN_FIELD_LEN];
1092 char resv5[256];
1093};
1094
1095struct nvmf_property_set_command {
1096 __u8 opcode;
1097 __u8 resv1;
1098 __u16 command_id;
1099 __u8 fctype;
1100 __u8 resv2[35];
1101 __u8 attrib;
1102 __u8 resv3[3];
1103 __le32 offset;
1104 __le64 value;
1105 __u8 resv4[8];
1106};
1107
1108struct nvmf_property_get_command {
1109 __u8 opcode;
1110 __u8 resv1;
1111 __u16 command_id;
1112 __u8 fctype;
1113 __u8 resv2[35];
1114 __u8 attrib;
1115 __u8 resv3[3];
1116 __le32 offset;
1117 __u8 resv4[16];
1118};
1119
1120struct nvme_dbbuf {
1121 __u8 opcode;
1122 __u8 flags;
1123 __u16 command_id;
1124 __u32 rsvd1[5];
1125 __le64 prp1;
1126 __le64 prp2;
1127 __u32 rsvd12[6];
1128};
1129
1130struct streams_directive_params {
1131 __le16 msl;
1132 __le16 nssa;
1133 __le16 nsso;
1134 __u8 rsvd[10];
1135 __le32 sws;
1136 __le16 sgs;
1137 __le16 nsa;
1138 __le16 nso;
1139 __u8 rsvd2[6];
1140};
1141
1142struct nvme_command {
1143 union {
1144 struct nvme_common_command common;
1145 struct nvme_rw_command rw;
1146 struct nvme_identify identify;
1147 struct nvme_features features;
1148 struct nvme_create_cq create_cq;
1149 struct nvme_create_sq create_sq;
1150 struct nvme_delete_queue delete_queue;
1151 struct nvme_download_firmware dlfw;
1152 struct nvme_format_cmd format;
1153 struct nvme_dsm_cmd dsm;
1154 struct nvme_write_zeroes_cmd write_zeroes;
1155 struct nvme_abort_cmd abort;
1156 struct nvme_get_log_page_command get_log_page;
1157 struct nvmf_common_command fabrics;
1158 struct nvmf_connect_command connect;
1159 struct nvmf_property_set_command prop_set;
1160 struct nvmf_property_get_command prop_get;
1161 struct nvme_dbbuf dbbuf;
1162 struct nvme_directive_cmd directive;
1163 };
1164};
1165
1166struct nvme_error_slot {
1167 __le64 error_count;
1168 __le16 sqid;
1169 __le16 cmdid;
1170 __le16 status_field;
1171 __le16 param_error_location;
1172 __le64 lba;
1173 __le32 nsid;
1174 __u8 vs;
1175 __u8 resv[3];
1176 __le64 cs;
1177 __u8 resv2[24];
1178};
1179
1180static inline bool nvme_is_write(struct nvme_command *cmd)
1181{
1182
1183
1184
1185
1186
1187 if (unlikely(cmd->common.opcode == nvme_fabrics_command))
1188 return cmd->fabrics.fctype & 1;
1189 return cmd->common.opcode & 1;
1190}
1191
1192enum {
1193
1194
1195
1196 NVME_SC_SUCCESS = 0x0,
1197 NVME_SC_INVALID_OPCODE = 0x1,
1198 NVME_SC_INVALID_FIELD = 0x2,
1199 NVME_SC_CMDID_CONFLICT = 0x3,
1200 NVME_SC_DATA_XFER_ERROR = 0x4,
1201 NVME_SC_POWER_LOSS = 0x5,
1202 NVME_SC_INTERNAL = 0x6,
1203 NVME_SC_ABORT_REQ = 0x7,
1204 NVME_SC_ABORT_QUEUE = 0x8,
1205 NVME_SC_FUSED_FAIL = 0x9,
1206 NVME_SC_FUSED_MISSING = 0xa,
1207 NVME_SC_INVALID_NS = 0xb,
1208 NVME_SC_CMD_SEQ_ERROR = 0xc,
1209 NVME_SC_SGL_INVALID_LAST = 0xd,
1210 NVME_SC_SGL_INVALID_COUNT = 0xe,
1211 NVME_SC_SGL_INVALID_DATA = 0xf,
1212 NVME_SC_SGL_INVALID_METADATA = 0x10,
1213 NVME_SC_SGL_INVALID_TYPE = 0x11,
1214
1215 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1216 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1217
1218 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1219
1220 NVME_SC_LBA_RANGE = 0x80,
1221 NVME_SC_CAP_EXCEEDED = 0x81,
1222 NVME_SC_NS_NOT_READY = 0x82,
1223 NVME_SC_RESERVATION_CONFLICT = 0x83,
1224
1225
1226
1227
1228 NVME_SC_CQ_INVALID = 0x100,
1229 NVME_SC_QID_INVALID = 0x101,
1230 NVME_SC_QUEUE_SIZE = 0x102,
1231 NVME_SC_ABORT_LIMIT = 0x103,
1232 NVME_SC_ABORT_MISSING = 0x104,
1233 NVME_SC_ASYNC_LIMIT = 0x105,
1234 NVME_SC_FIRMWARE_SLOT = 0x106,
1235 NVME_SC_FIRMWARE_IMAGE = 0x107,
1236 NVME_SC_INVALID_VECTOR = 0x108,
1237 NVME_SC_INVALID_LOG_PAGE = 0x109,
1238 NVME_SC_INVALID_FORMAT = 0x10a,
1239 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1240 NVME_SC_INVALID_QUEUE = 0x10c,
1241 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1242 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1243 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1244 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1245 NVME_SC_FW_NEEDS_RESET = 0x111,
1246 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1247 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
1248 NVME_SC_OVERLAPPING_RANGE = 0x114,
1249 NVME_SC_NS_INSUFFICENT_CAP = 0x115,
1250 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1251 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1252 NVME_SC_NS_IS_PRIVATE = 0x119,
1253 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1254 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1255 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1256
1257
1258
1259
1260 NVME_SC_BAD_ATTRIBUTES = 0x180,
1261 NVME_SC_INVALID_PI = 0x181,
1262 NVME_SC_READ_ONLY = 0x182,
1263 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1264
1265
1266
1267
1268 NVME_SC_CONNECT_FORMAT = 0x180,
1269 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1270 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1271 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1272 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1273
1274 NVME_SC_DISCOVERY_RESTART = 0x190,
1275 NVME_SC_AUTH_REQUIRED = 0x191,
1276
1277
1278
1279
1280 NVME_SC_WRITE_FAULT = 0x280,
1281 NVME_SC_READ_ERROR = 0x281,
1282 NVME_SC_GUARD_CHECK = 0x282,
1283 NVME_SC_APPTAG_CHECK = 0x283,
1284 NVME_SC_REFTAG_CHECK = 0x284,
1285 NVME_SC_COMPARE_FAILED = 0x285,
1286 NVME_SC_ACCESS_DENIED = 0x286,
1287 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1288
1289
1290
1291
1292 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1293 NVME_SC_ANA_INACCESSIBLE = 0x302,
1294 NVME_SC_ANA_TRANSITION = 0x303,
1295 NVME_SC_HOST_PATH_ERROR = 0x370,
1296
1297 NVME_SC_CRD = 0x1800,
1298 NVME_SC_DNR = 0x4000,
1299};
1300
1301struct nvme_completion {
1302
1303
1304
1305 union nvme_result {
1306 __le16 u16;
1307 __le32 u32;
1308 __le64 u64;
1309 } result;
1310 __le16 sq_head;
1311 __le16 sq_id;
1312 __u16 command_id;
1313 __le16 status;
1314};
1315
1316#define NVME_VS(major, minor, tertiary) \
1317 (((major) << 16) | ((minor) << 8) | (tertiary))
1318
1319#define NVME_MAJOR(ver) ((ver) >> 16)
1320#define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1321#define NVME_TERTIARY(ver) ((ver) & 0xff)
1322
1323#endif
1324
