1/* 2 * NAU8810 ALSA SoC audio driver 3 * 4 * Copyright 2016 Nuvoton Technology Corp. 5 * Author: David Lin <ctlin0@nuvoton.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12#ifndef __NAU8810_H__ 13#define __NAU8810_H__ 14 15#define NAU8810_REG_RESET 0x00 16#define NAU8810_REG_POWER1 0x01 17#define NAU8810_REG_POWER2 0x02 18#define NAU8810_REG_POWER3 0x03 19#define NAU8810_REG_IFACE 0x04 20#define NAU8810_REG_COMP 0x05 21#define NAU8810_REG_CLOCK 0x06 22#define NAU8810_REG_SMPLR 0x07 23#define NAU8810_REG_DAC 0x0A 24#define NAU8810_REG_DACGAIN 0x0B 25#define NAU8810_REG_ADC 0x0E 26#define NAU8810_REG_ADCGAIN 0x0F 27#define NAU8810_REG_EQ1 0x12 28#define NAU8810_REG_EQ2 0x13 29#define NAU8810_REG_EQ3 0x14 30#define NAU8810_REG_EQ4 0x15 31#define NAU8810_REG_EQ5 0x16 32#define NAU8810_REG_DACLIM1 0x18 33#define NAU8810_REG_DACLIM2 0x19 34#define NAU8810_REG_NOTCH1 0x1B 35#define NAU8810_REG_NOTCH2 0x1C 36#define NAU8810_REG_NOTCH3 0x1D 37#define NAU8810_REG_NOTCH4 0x1E 38#define NAU8810_REG_ALC1 0x20 39#define NAU8810_REG_ALC2 0x21 40#define NAU8810_REG_ALC3 0x22 41#define NAU8810_REG_NOISEGATE 0x23 42#define NAU8810_REG_PLLN 0x24 43#define NAU8810_REG_PLLK1 0x25 44#define NAU8810_REG_PLLK2 0x26 45#define NAU8810_REG_PLLK3 0x27 46#define NAU8810_REG_ATTEN 0x28 47#define NAU8810_REG_INPUT_SIGNAL 0x2C 48#define NAU8810_REG_PGAGAIN 0x2D 49#define NAU8810_REG_ADCBOOST 0x2F 50#define NAU8810_REG_OUTPUT 0x31 51#define NAU8810_REG_SPKMIX 0x32 52#define NAU8810_REG_SPKGAIN 0x36 53#define NAU8810_REG_MONOMIX 0x38 54#define NAU8810_REG_POWER4 0x3A 55#define NAU8810_REG_TSLOTCTL1 0x3B 56#define NAU8810_REG_TSLOTCTL2 0x3C 57#define NAU8810_REG_DEVICE_REVID 0x3E 58#define NAU8810_REG_I2C_DEVICEID 0x3F 59#define NAU8810_REG_ADDITIONID 0x40 60#define NAU8810_REG_RESERVE 0x41 61#define NAU8810_REG_OUTCTL 0x45 62#define NAU8810_REG_ALC1ENHAN1 0x46 63#define NAU8810_REG_ALC1ENHAN2 0x47 64#define NAU8810_REG_MISCCTL 0x49 65#define NAU8810_REG_OUTTIEOFF 0x4B 66#define NAU8810_REG_AGCP2POUT 0x4C 67#define NAU8810_REG_AGCPOUT 0x4D 68#define NAU8810_REG_AMTCTL 0x4E 69#define NAU8810_REG_OUTTIEOFFMAN 0x4F 70#define NAU8810_REG_MAX NAU8810_REG_OUTTIEOFFMAN 71 72 73/* NAU8810_REG_POWER1 (0x1) */ 74#define NAU8810_DCBUF_EN (0x1 << 8) 75#define NAU8810_PLL_EN_SFT 5 76#define NAU8810_MICBIAS_EN_SFT 4 77#define NAU8810_ABIAS_EN (0x1 << 3) 78#define NAU8810_IOBUF_EN (0x1 << 2) 79#define NAU8810_REFIMP_MASK 0x3 80#define NAU8810_REFIMP_DIS 0x0 81#define NAU8810_REFIMP_80K 0x1 82#define NAU8810_REFIMP_300K 0x2 83#define NAU8810_REFIMP_3K 0x3 84 85/* NAU8810_REG_POWER2 (0x2) */ 86#define NAU8810_BST_EN_SFT 4 87#define NAU8810_PGA_EN_SFT 2 88#define NAU8810_ADC_EN_SFT 0 89 90/* NAU8810_REG_POWER3 (0x3) */ 91#define NAU8810_DAC_EN_SFT 0 92#define NAU8810_SPKMX_EN_SFT 2 93#define NAU8810_MOUTMX_EN_SFT 3 94#define NAU8810_PSPK_EN_SFT 5 95#define NAU8810_NSPK_EN_SFT 6 96#define NAU8810_MOUT_EN_SFT 7 97 98/* NAU8810_REG_IFACE (0x4) */ 99#define NAU8810_AIFMT_SFT 3 100#define NAU8810_AIFMT_MASK (0x3 << NAU8810_AIFMT_SFT) 101#define NAU8810_AIFMT_RIGHT (0x0 << NAU8810_AIFMT_SFT) 102#define NAU8810_AIFMT_LEFT (0x1 << NAU8810_AIFMT_SFT) 103#define NAU8810_AIFMT_I2S (0x2 << NAU8810_AIFMT_SFT) 104#define NAU8810_AIFMT_PCM_A (0x3 << NAU8810_AIFMT_SFT) 105#define NAU8810_WLEN_SFT 5 106#define NAU8810_WLEN_MASK (0x3 << NAU8810_WLEN_SFT) 107#define NAU8810_WLEN_16 (0x0 << NAU8810_WLEN_SFT) 108#define NAU8810_WLEN_20 (0x1 << NAU8810_WLEN_SFT) 109#define NAU8810_WLEN_24 (0x2 << NAU8810_WLEN_SFT) 110#define NAU8810_WLEN_32 (0x3 << NAU8810_WLEN_SFT) 111#define NAU8810_FSP_IF (0x1 << 7) 112#define NAU8810_BCLKP_IB (0x1 << 8) 113 114/* NAU8810_REG_COMP (0x5) */ 115#define NAU8810_ADDAP_SFT 0 116#define NAU8810_ADCCM_SFT 1 117#define NAU8810_DACCM_SFT 3 118 119/* NAU8810_REG_CLOCK (0x6) */ 120#define NAU8810_CLKIO_MASK 0x1 121#define NAU8810_CLKIO_SLAVE 0x0 122#define NAU8810_CLKIO_MASTER 0x1 123#define NAU8810_BCLKSEL_SFT 2 124#define NAU8810_BCLKSEL_MASK (0x7 << NAU8810_BCLKSEL_SFT) 125#define NAU8810_BCLKDIV_1 (0x0 << NAU8810_BCLKSEL_SFT) 126#define NAU8810_BCLKDIV_2 (0x1 << NAU8810_BCLKSEL_SFT) 127#define NAU8810_BCLKDIV_4 (0x2 << NAU8810_BCLKSEL_SFT) 128#define NAU8810_BCLKDIV_8 (0x3 << NAU8810_BCLKSEL_SFT) 129#define NAU8810_BCLKDIV_16 (0x4 << NAU8810_BCLKSEL_SFT) 130#define NAU8810_BCLKDIV_32 (0x5 << NAU8810_BCLKSEL_SFT) 131#define NAU8810_MCLKSEL_SFT 5 132#define NAU8810_MCLKSEL_MASK (0x7 << NAU8810_MCLKSEL_SFT) 133#define NAU8810_CLKM_SFT 8 134#define NAU8810_CLKM_MASK (0x1 << NAU8810_CLKM_SFT) 135#define NAU8810_CLKM_MCLK (0x0 << NAU8810_CLKM_SFT) 136#define NAU8810_CLKM_PLL (0x1 << NAU8810_CLKM_SFT) 137 138/* NAU8810_REG_SMPLR (0x7) */ 139#define NAU8810_SMPLR_SFT 1 140#define NAU8810_SMPLR_MASK (0x7 << NAU8810_SMPLR_SFT) 141#define NAU8810_SMPLR_48K (0x0 << NAU8810_SMPLR_SFT) 142#define NAU8810_SMPLR_32K (0x1 << NAU8810_SMPLR_SFT) 143#define NAU8810_SMPLR_24K (0x2 << NAU8810_SMPLR_SFT) 144#define NAU8810_SMPLR_16K (0x3 << NAU8810_SMPLR_SFT) 145#define NAU8810_SMPLR_12K (0x4 << NAU8810_SMPLR_SFT) 146#define NAU8810_SMPLR_8K (0x5 << NAU8810_SMPLR_SFT) 147 148/* NAU8810_REG_DAC (0xA) */ 149#define NAU8810_DACPL_SFT 0 150#define NAU8810_DACOS_SFT 3 151#define NAU8810_DEEMP_SFT 4 152 153/* NAU8810_REG_DACGAIN (0xB) */ 154#define NAU8810_DACGAIN_SFT 0 155 156/* NAU8810_REG_ADC (0xE) */ 157#define NAU8810_ADCPL_SFT 0 158#define NAU8810_ADCOS_SFT 3 159#define NAU8810_HPF_SFT 4 160#define NAU8810_HPFEN_SFT 8 161 162/* NAU8810_REG_ADCGAIN (0xF) */ 163#define NAU8810_ADCGAIN_SFT 0 164 165/* NAU8810_REG_EQ1 (0x12) */ 166#define NAU8810_EQ1GC_SFT 0 167#define NAU8810_EQ1CF_SFT 5 168#define NAU8810_EQM_SFT 8 169 170/* NAU8810_REG_EQ2 (0x13) */ 171#define NAU8810_EQ2GC_SFT 0 172#define NAU8810_EQ2CF_SFT 5 173#define NAU8810_EQ2BW_SFT 8 174 175/* NAU8810_REG_EQ3 (0x14) */ 176#define NAU8810_EQ3GC_SFT 0 177#define NAU8810_EQ3CF_SFT 5 178#define NAU8810_EQ3BW_SFT 8 179 180/* NAU8810_REG_EQ4 (0x15) */ 181#define NAU8810_EQ4GC_SFT 0 182#define NAU8810_EQ4CF_SFT 5 183#define NAU8810_EQ4BW_SFT 8 184 185/* NAU8810_REG_EQ5 (0x16) */ 186#define NAU8810_EQ5GC_SFT 0 187#define NAU8810_EQ5CF_SFT 5 188 189/* NAU8810_REG_DACLIM1 (0x18) */ 190#define NAU8810_DACLIMATK_SFT 0 191#define NAU8810_DACLIMDCY_SFT 4 192#define NAU8810_DACLIMEN_SFT 8 193 194/* NAU8810_REG_DACLIM2 (0x19) */ 195#define NAU8810_DACLIMBST_SFT 0 196#define NAU8810_DACLIMTHL_SFT 4 197 198/* NAU8810_REG_ALC1 (0x20) */ 199#define NAU8810_ALCMINGAIN_SFT 0 200#define NAU8810_ALCMXGAIN_SFT 3 201#define NAU8810_ALCEN_SFT 8 202 203/* NAU8810_REG_ALC2 (0x21) */ 204#define NAU8810_ALCSL_SFT 0 205#define NAU8810_ALCHT_SFT 4 206#define NAU8810_ALCZC_SFT 8 207 208/* NAU8810_REG_ALC3 (0x22) */ 209#define NAU8810_ALCATK_SFT 0 210#define NAU8810_ALCDCY_SFT 4 211#define NAU8810_ALCM_SFT 8 212 213/* NAU8810_REG_NOISEGATE (0x23) */ 214#define NAU8810_ALCNTH_SFT 0 215#define NAU8810_ALCNEN_SFT 3 216 217/* NAU8810_REG_PLLN (0x24) */ 218#define NAU8810_PLLN_MASK 0xF 219#define NAU8810_PLLMCLK_DIV2 (0x1 << 4) 220 221/* NAU8810_REG_PLLK1 (0x25) */ 222#define NAU8810_PLLK1_SFT 18 223#define NAU8810_PLLK1_MASK 0x3F 224 225/* NAU8810_REG_PLLK2 (0x26) */ 226#define NAU8810_PLLK2_SFT 9 227#define NAU8810_PLLK2_MASK 0x1FF 228 229/* NAU8810_REG_PLLK3 (0x27) */ 230#define NAU8810_PLLK3_MASK 0x1FF 231 232/* NAU8810_REG_INPUT_SIGNAL (0x2C) */ 233#define NAU8810_PMICPGA_SFT 0 234#define NAU8810_NMICPGA_SFT 1 235 236/* NAU8810_REG_PGAGAIN (0x2D) */ 237#define NAU8810_PGAGAIN_SFT 0 238#define NAU8810_PGAMT_SFT 6 239#define NAU8810_PGAZC_SFT 7 240 241/* NAU8810_REG_ADCBOOST (0x2F) */ 242#define NAU8810_PMICBSTGAIN_SFT 4 243#define NAU8810_PGABST_SFT 8 244 245/* NAU8810_REG_SPKMIX (0x32) */ 246#define NAU8810_DACSPK_SFT 0 247#define NAU8810_BYPSPK_SFT 1 248 249/* NAU8810_REG_SPKGAIN (0x36) */ 250#define NAU8810_SPKGAIN_SFT 0 251#define NAU8810_SPKMT_SFT 6 252#define NAU8810_SPKZC_SFT 7 253 254/* NAU8810_REG_MONOMIX (0x38) */ 255#define NAU8810_DACMOUT_SFT 0 256#define NAU8810_BYPMOUT_SFT 1 257#define NAU8810_MOUTMXMT_SFT 6 258 259 260/* System Clock Source */ 261enum { 262 NAU8810_SCLK_MCLK, 263 NAU8810_SCLK_PLL, 264}; 265 266struct nau8810_pll { 267 int pre_factor; 268 int mclk_scaler; 269 int pll_frac; 270 int pll_int; 271}; 272 273struct nau8810 { 274 struct device *dev; 275 struct regmap *regmap; 276 struct nau8810_pll pll; 277 int sysclk; 278 int clk_id; 279}; 280 281#endif 282