LXR linux/sound/soc/codecs/rl6231.c

   1/*
   2 * rl6231.c - RL6231 class device shared support
   3 *
   4 * Copyright 2014 Realtek Semiconductor Corp.
   5 *
   6 * Author: Oder Chiou <oder_chiou@realtek.com>
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License version 2 as
  10 * published by the Free Software Foundation.
  11 */
  12
  13#include <linux/module.h>
  14#include <linux/regmap.h>
  15
  16#include <linux/gcd.h>
  17#include "rl6231.h"
  18
  19/**
  20 * rl6231_get_pre_div - Return the value of pre divider.
  21 *
  22 * @map: map for setting.
  23 * @reg: register.
  24 * @sft: shift.
  25 *
  26 * Return the value of pre divider from given register value.
  27 * Return negative error code for unexpected register value.
  28 */
  29int rl6231_get_pre_div(struct regmap *map, unsigned int reg, int sft)
  30{
  31        int pd, val;
  32
  33        regmap_read(map, reg, &val);
  34
  35        val = (val >> sft) & 0x7;
  36
  37        switch (val) {
  38        case 0:
  39        case 1:
  40        case 2:
  41        case 3:
  42                pd = val + 1;
  43                break;
  44        case 4:
  45                pd = 6;
  46                break;
  47        case 5:
  48                pd = 8;
  49                break;
  50        case 6:
  51                pd = 12;
  52                break;
  53        case 7:
  54                pd = 16;
  55                break;
  56        default:
  57                pd = -EINVAL;
  58                break;
  59        }
  60
  61        return pd;
  62}
  63EXPORT_SYMBOL_GPL(rl6231_get_pre_div);
  64
  65/**
  66 * rl6231_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
  67 *
  68 * @rate: base clock rate.
  69 *
  70 * Choose divider parameter that gives the highest possible DMIC frequency in
  71 * 1MHz - 3MHz range.
  72 */
  73int rl6231_calc_dmic_clk(int rate)
  74{
  75        static const int div[] = {2, 3, 4, 6, 8, 12};
  76        int i;
  77
  78        if (rate < 1000000 * div[0]) {
  79                pr_warn("Base clock rate %d is too low\n", rate);
  80                return -EINVAL;
  81        }
  82
  83        for (i = 0; i < ARRAY_SIZE(div); i++) {
  84                if ((div[i] % 3) == 0)
  85                        continue;
  86                /* find divider that gives DMIC frequency below 3.072MHz */
  87                if (3072000 * div[i] >= rate)
  88                        return i;
  89        }
  90
  91        pr_warn("Base clock rate %d is too high\n", rate);
  92        return -EINVAL;
  93}
  94EXPORT_SYMBOL_GPL(rl6231_calc_dmic_clk);
  95
  96struct pll_calc_map {
  97        unsigned int pll_in;
  98        unsigned int pll_out;
  99        int k;
 100        int n;
 101        int m;
 102        bool m_bp;
 103};
 104
 105static const struct pll_calc_map pll_preset_table[] = {
 106        {19200000,  4096000,  23, 14, 1, false},
 107        {19200000,  24576000,  3, 30, 3, false},
 108};
 109
 110static unsigned int find_best_div(unsigned int in,
 111        unsigned int max, unsigned int div)
 112{
 113        unsigned int d;
 114
 115        if (in <= max)
 116                return 1;
 117
 118        d = in / max;
 119        if (in % max)
 120                d++;
 121
 122        while (div % d != 0)
 123                d++;
 124
 125
 126        return d;
 127}
 128
 129/**
 130 * rl6231_pll_calc - Calcualte PLL M/N/K code.
 131 * @freq_in: external clock provided to codec.
 132 * @freq_out: target clock which codec works on.
 133 * @pll_code: Pointer to structure with M, N, K and bypass flag.
 134 *
 135 * Calcualte M/N/K code to configure PLL for codec.
 136 *
 137 * Returns 0 for success or negative error code.
 138 */
 139int rl6231_pll_calc(const unsigned int freq_in,
 140        const unsigned int freq_out, struct rl6231_pll_code *pll_code)
 141{
 142        int max_n = RL6231_PLL_N_MAX, max_m = RL6231_PLL_M_MAX;
 143        int i, k, n_t;
 144        int k_t, min_k, max_k, n = 0, m = 0, m_t = 0;
 145        unsigned int red, pll_out, in_t, out_t, div, div_t;
 146        unsigned int red_t = abs(freq_out - freq_in);
 147        unsigned int f_in, f_out, f_max;
 148        bool bypass = false;
 149
 150        if (RL6231_PLL_INP_MAX < freq_in || RL6231_PLL_INP_MIN > freq_in)
 151                return -EINVAL;
 152
 153        for (i = 0; i < ARRAY_SIZE(pll_preset_table); i++) {
 154                if (freq_in == pll_preset_table[i].pll_in &&
 155                        freq_out == pll_preset_table[i].pll_out) {
 156                        k = pll_preset_table[i].k;
 157                        m = pll_preset_table[i].m;
 158                        n = pll_preset_table[i].n;
 159                        bypass = pll_preset_table[i].m_bp;
 160                        pr_debug("Use preset PLL parameter table\n");
 161                        goto code_find;
 162                }
 163        }
 164
 165        min_k = 80000000 / freq_out - 2;
 166        max_k = 150000000 / freq_out - 2;
 167        if (max_k > RL6231_PLL_K_MAX)
 168                max_k = RL6231_PLL_K_MAX;
 169        if (min_k > RL6231_PLL_K_MAX)
 170                min_k = max_k = RL6231_PLL_K_MAX;
 171        div_t = gcd(freq_in, freq_out);
 172        f_max = 0xffffffff / RL6231_PLL_N_MAX;
 173        div = find_best_div(freq_in, f_max, div_t);
 174        f_in = freq_in / div;
 175        f_out = freq_out / div;
 176        k = min_k;
 177        for (k_t = min_k; k_t <= max_k; k_t++) {
 178                for (n_t = 0; n_t <= max_n; n_t++) {
 179                        in_t = f_in * (n_t + 2);
 180                        pll_out = f_out * (k_t + 2);
 181                        if (in_t == pll_out) {
 182                                bypass = true;
 183                                n = n_t;
 184                                k = k_t;
 185                                goto code_find;
 186                        }
 187                        out_t = in_t / (k_t + 2);
 188                        red = abs(f_out - out_t);
 189                        if (red < red_t) {
 190                                bypass = true;
 191                                n = n_t;
 192                                m = 0;
 193                                k = k_t;
 194                                if (red == 0)
 195                                        goto code_find;
 196                                red_t = red;
 197                        }
 198                        for (m_t = 0; m_t <= max_m; m_t++) {
 199                                out_t = in_t / ((m_t + 2) * (k_t + 2));
 200                                red = abs(f_out - out_t);
 201                                if (red < red_t) {
 202                                        bypass = false;
 203                                        n = n_t;
 204                                        m = m_t;
 205                                        k = k_t;
 206                                        if (red == 0)
 207                                                goto code_find;
 208                                        red_t = red;
 209                                }
 210                        }
 211                }
 212        }
 213        pr_debug("Only get approximation about PLL\n");
 214
 215code_find:
 216
 217        pll_code->m_bp = bypass;
 218        pll_code->m_code = m;
 219        pll_code->n_code = n;
 220        pll_code->k_code = k;
 221        return 0;
 222}
 223EXPORT_SYMBOL_GPL(rl6231_pll_calc);
 224
 225int rl6231_get_clk_info(int sclk, int rate)
 226{
 227        int i;
 228        static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
 229
 230        if (sclk <= 0 || rate <= 0)
 231                return -EINVAL;
 232
 233        rate = rate << 8;
 234        for (i = 0; i < ARRAY_SIZE(pd); i++)
 235                if (sclk == rate * pd[i])
 236                        return i;
 237
 238        return -EINVAL;
 239}
 240EXPORT_SYMBOL_GPL(rl6231_get_clk_info);
 241
 242MODULE_DESCRIPTION("RL6231 class device shared support");
 243MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
 244MODULE_LICENSE("GPL v2");
 245