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15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/interrupt.h>
18#include <linux/irqreturn.h>
19#include <linux/init.h>
20#include <linux/spi/spi.h>
21#include <linux/firmware.h>
22#include <linux/delay.h>
23#include <linux/fs.h>
24#include <linux/gpio.h>
25#include <linux/regulator/consumer.h>
26#include <linux/mutex.h>
27#include <linux/workqueue.h>
28
29#include <sound/soc.h>
30#include <sound/wm0010.h>
31
32#define DEVICE_ID_WM0010 10
33
34
35#define INFO_VERSION 1
36
37enum dfw_cmd {
38 DFW_CMD_FUSE = 0x01,
39 DFW_CMD_CODE_HDR,
40 DFW_CMD_CODE_DATA,
41 DFW_CMD_PLL,
42 DFW_CMD_INFO = 0xff
43};
44
45struct dfw_binrec {
46 u8 command;
47 u32 length:24;
48 u32 address;
49 uint8_t data[0];
50} __packed;
51
52struct dfw_inforec {
53 u8 info_version;
54 u8 tool_major_version;
55 u8 tool_minor_version;
56 u8 dsp_target;
57};
58
59struct dfw_pllrec {
60 u8 command;
61 u32 length:24;
62 u32 address;
63 u32 clkctrl1;
64 u32 clkctrl2;
65 u32 clkctrl3;
66 u32 ldetctrl;
67 u32 uart_div;
68 u32 spi_div;
69} __packed;
70
71static struct pll_clock_map {
72 int max_sysclk;
73 int max_pll_spi_speed;
74 u32 pll_clkctrl1;
75} pll_clock_map[] = {
76 { 22000000, 26000000, 0x00201f11 },
77 { 18000000, 26000000, 0x00203f21 },
78 { 14000000, 26000000, 0x00202620 },
79 { 10000000, 22000000, 0x00203120 },
80 { 6500000, 22000000, 0x00204520 },
81 { 5500000, 22000000, 0x00103f10 },
82};
83
84enum wm0010_state {
85 WM0010_POWER_OFF,
86 WM0010_OUT_OF_RESET,
87 WM0010_BOOTROM,
88 WM0010_STAGE2,
89 WM0010_FIRMWARE,
90};
91
92struct wm0010_priv {
93 struct snd_soc_component *component;
94
95 struct mutex lock;
96 struct device *dev;
97
98 struct wm0010_pdata pdata;
99
100 int gpio_reset;
101 int gpio_reset_value;
102
103 struct regulator_bulk_data core_supplies[2];
104 struct regulator *dbvdd;
105
106 int sysclk;
107
108 enum wm0010_state state;
109 bool boot_failed;
110 bool ready;
111 bool pll_running;
112 int max_spi_freq;
113 int board_max_spi_speed;
114 u32 pll_clkctrl1;
115
116 spinlock_t irq_lock;
117 int irq;
118
119 struct completion boot_completion;
120};
121
122struct wm0010_spi_msg {
123 struct spi_message m;
124 struct spi_transfer t;
125 u8 *tx_buf;
126 u8 *rx_buf;
127 size_t len;
128};
129
130static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = {
131SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0),
132};
133
134static const struct snd_soc_dapm_route wm0010_dapm_routes[] = {
135 { "SDI2 Capture", NULL, "SDI1 Playback" },
136 { "SDI1 Capture", NULL, "SDI2 Playback" },
137
138 { "SDI1 Capture", NULL, "CLKIN" },
139 { "SDI2 Capture", NULL, "CLKIN" },
140 { "SDI1 Playback", NULL, "CLKIN" },
141 { "SDI2 Playback", NULL, "CLKIN" },
142};
143
144static const char *wm0010_state_to_str(enum wm0010_state state)
145{
146 static const char * const state_to_str[] = {
147 "Power off",
148 "Out of reset",
149 "Boot ROM",
150 "Stage2",
151 "Firmware"
152 };
153
154 if (state < 0 || state >= ARRAY_SIZE(state_to_str))
155 return "null";
156 return state_to_str[state];
157}
158
159
160static void wm0010_halt(struct snd_soc_component *component)
161{
162 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
163 unsigned long flags;
164 enum wm0010_state state;
165
166
167 spin_lock_irqsave(&wm0010->irq_lock, flags);
168 state = wm0010->state;
169 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
170
171 switch (state) {
172 case WM0010_POWER_OFF:
173
174 return;
175 case WM0010_OUT_OF_RESET:
176 case WM0010_BOOTROM:
177 case WM0010_STAGE2:
178 case WM0010_FIRMWARE:
179
180 gpio_set_value_cansleep(wm0010->gpio_reset,
181 wm0010->gpio_reset_value);
182
183 regulator_disable(wm0010->dbvdd);
184 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
185 wm0010->core_supplies);
186 break;
187 }
188
189 spin_lock_irqsave(&wm0010->irq_lock, flags);
190 wm0010->state = WM0010_POWER_OFF;
191 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
192}
193
194struct wm0010_boot_xfer {
195 struct list_head list;
196 struct snd_soc_component *component;
197 struct completion *done;
198 struct spi_message m;
199 struct spi_transfer t;
200};
201
202
203static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010)
204{
205 enum wm0010_state state;
206 unsigned long flags;
207
208 spin_lock_irqsave(&wm0010->irq_lock, flags);
209 state = wm0010->state;
210 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
211
212 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n",
213 wm0010_state_to_str(state), wm0010_state_to_str(state + 1));
214
215 wm0010->boot_failed = true;
216}
217
218static void wm0010_boot_xfer_complete(void *data)
219{
220 struct wm0010_boot_xfer *xfer = data;
221 struct snd_soc_component *component = xfer->component;
222 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
223 u32 *out32 = xfer->t.rx_buf;
224 int i;
225
226 if (xfer->m.status != 0) {
227 dev_err(component->dev, "SPI transfer failed: %d\n",
228 xfer->m.status);
229 wm0010_mark_boot_failure(wm0010);
230 if (xfer->done)
231 complete(xfer->done);
232 return;
233 }
234
235 for (i = 0; i < xfer->t.len / 4; i++) {
236 dev_dbg(component->dev, "%d: %04x\n", i, out32[i]);
237
238 switch (be32_to_cpu(out32[i])) {
239 case 0xe0e0e0e0:
240 dev_err(component->dev,
241 "%d: ROM error reported in stage 2\n", i);
242 wm0010_mark_boot_failure(wm0010);
243 break;
244
245 case 0x55555555:
246 if (wm0010->state < WM0010_STAGE2)
247 break;
248 dev_err(component->dev,
249 "%d: ROM bootloader running in stage 2\n", i);
250 wm0010_mark_boot_failure(wm0010);
251 break;
252
253 case 0x0fed0000:
254 dev_dbg(component->dev, "Stage2 loader running\n");
255 break;
256
257 case 0x0fed0007:
258 dev_dbg(component->dev, "CODE_HDR packet received\n");
259 break;
260
261 case 0x0fed0008:
262 dev_dbg(component->dev, "CODE_DATA packet received\n");
263 break;
264
265 case 0x0fed0009:
266 dev_dbg(component->dev, "Download complete\n");
267 break;
268
269 case 0x0fed000c:
270 dev_dbg(component->dev, "Application start\n");
271 break;
272
273 case 0x0fed000e:
274 dev_dbg(component->dev, "PLL packet received\n");
275 wm0010->pll_running = true;
276 break;
277
278 case 0x0fed0025:
279 dev_err(component->dev, "Device reports image too long\n");
280 wm0010_mark_boot_failure(wm0010);
281 break;
282
283 case 0x0fed002c:
284 dev_err(component->dev, "Device reports bad SPI packet\n");
285 wm0010_mark_boot_failure(wm0010);
286 break;
287
288 case 0x0fed0031:
289 dev_err(component->dev, "Device reports SPI read overflow\n");
290 wm0010_mark_boot_failure(wm0010);
291 break;
292
293 case 0x0fed0032:
294 dev_err(component->dev, "Device reports SPI underclock\n");
295 wm0010_mark_boot_failure(wm0010);
296 break;
297
298 case 0x0fed0033:
299 dev_err(component->dev, "Device reports bad header packet\n");
300 wm0010_mark_boot_failure(wm0010);
301 break;
302
303 case 0x0fed0034:
304 dev_err(component->dev, "Device reports invalid packet type\n");
305 wm0010_mark_boot_failure(wm0010);
306 break;
307
308 case 0x0fed0035:
309 dev_err(component->dev, "Device reports data before header error\n");
310 wm0010_mark_boot_failure(wm0010);
311 break;
312
313 case 0x0fed0038:
314 dev_err(component->dev, "Device reports invalid PLL packet\n");
315 break;
316
317 case 0x0fed003a:
318 dev_err(component->dev, "Device reports packet alignment error\n");
319 wm0010_mark_boot_failure(wm0010);
320 break;
321
322 default:
323 dev_err(component->dev, "Unrecognised return 0x%x\n",
324 be32_to_cpu(out32[i]));
325 wm0010_mark_boot_failure(wm0010);
326 break;
327 }
328
329 if (wm0010->boot_failed)
330 break;
331 }
332
333 if (xfer->done)
334 complete(xfer->done);
335}
336
337static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len)
338{
339 int i;
340
341 for (i = 0; i < len / 8; i++)
342 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i]));
343}
344
345static int wm0010_firmware_load(const char *name, struct snd_soc_component *component)
346{
347 struct spi_device *spi = to_spi_device(component->dev);
348 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
349 struct list_head xfer_list;
350 struct wm0010_boot_xfer *xfer;
351 int ret;
352 struct completion done;
353 const struct firmware *fw;
354 const struct dfw_binrec *rec;
355 const struct dfw_inforec *inforec;
356 u64 *img;
357 u8 *out, dsp;
358 u32 len, offset;
359
360 INIT_LIST_HEAD(&xfer_list);
361
362 ret = request_firmware(&fw, name, component->dev);
363 if (ret != 0) {
364 dev_err(component->dev, "Failed to request application(%s): %d\n",
365 name, ret);
366 return ret;
367 }
368
369 rec = (const struct dfw_binrec *)fw->data;
370 inforec = (const struct dfw_inforec *)rec->data;
371 offset = 0;
372 dsp = inforec->dsp_target;
373 wm0010->boot_failed = false;
374 if (WARN_ON(!list_empty(&xfer_list)))
375 return -EINVAL;
376 init_completion(&done);
377
378
379 if (rec->command != DFW_CMD_INFO) {
380 dev_err(component->dev, "First record not INFO\r\n");
381 ret = -EINVAL;
382 goto abort;
383 }
384
385 if (inforec->info_version != INFO_VERSION) {
386 dev_err(component->dev,
387 "Unsupported version (%02d) of INFO record\r\n",
388 inforec->info_version);
389 ret = -EINVAL;
390 goto abort;
391 }
392
393 dev_dbg(component->dev, "Version v%02d INFO record found\r\n",
394 inforec->info_version);
395
396
397 if (dsp != DEVICE_ID_WM0010) {
398 dev_err(component->dev, "Not a WM0010 firmware file.\r\n");
399 ret = -EINVAL;
400 goto abort;
401 }
402
403
404 offset += ((rec->length) + 8);
405 rec = (void *)&rec->data[rec->length];
406
407 while (offset < fw->size) {
408 dev_dbg(component->dev,
409 "Packet: command %d, data length = 0x%x\r\n",
410 rec->command, rec->length);
411 len = rec->length + 8;
412
413 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
414 if (!xfer) {
415 ret = -ENOMEM;
416 goto abort;
417 }
418
419 xfer->component = component;
420 list_add_tail(&xfer->list, &xfer_list);
421
422 out = kzalloc(len, GFP_KERNEL | GFP_DMA);
423 if (!out) {
424 ret = -ENOMEM;
425 goto abort1;
426 }
427 xfer->t.rx_buf = out;
428
429 img = kzalloc(len, GFP_KERNEL | GFP_DMA);
430 if (!img) {
431 ret = -ENOMEM;
432 goto abort1;
433 }
434 xfer->t.tx_buf = img;
435
436 byte_swap_64((u64 *)&rec->command, img, len);
437
438 spi_message_init(&xfer->m);
439 xfer->m.complete = wm0010_boot_xfer_complete;
440 xfer->m.context = xfer;
441 xfer->t.len = len;
442 xfer->t.bits_per_word = 8;
443
444 if (!wm0010->pll_running) {
445 xfer->t.speed_hz = wm0010->sysclk / 6;
446 } else {
447 xfer->t.speed_hz = wm0010->max_spi_freq;
448
449 if (wm0010->board_max_spi_speed &&
450 (wm0010->board_max_spi_speed < wm0010->max_spi_freq))
451 xfer->t.speed_hz = wm0010->board_max_spi_speed;
452 }
453
454
455 wm0010->max_spi_freq = xfer->t.speed_hz;
456
457 spi_message_add_tail(&xfer->t, &xfer->m);
458
459 offset += ((rec->length) + 8);
460 rec = (void *)&rec->data[rec->length];
461
462 if (offset >= fw->size) {
463 dev_dbg(component->dev, "All transfers scheduled\n");
464 xfer->done = &done;
465 }
466
467 ret = spi_async(spi, &xfer->m);
468 if (ret != 0) {
469 dev_err(component->dev, "Write failed: %d\n", ret);
470 goto abort1;
471 }
472
473 if (wm0010->boot_failed) {
474 dev_dbg(component->dev, "Boot fail!\n");
475 ret = -EINVAL;
476 goto abort1;
477 }
478 }
479
480 wait_for_completion(&done);
481
482 ret = 0;
483
484abort1:
485 while (!list_empty(&xfer_list)) {
486 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer,
487 list);
488 kfree(xfer->t.rx_buf);
489 kfree(xfer->t.tx_buf);
490 list_del(&xfer->list);
491 kfree(xfer);
492 }
493
494abort:
495 release_firmware(fw);
496 return ret;
497}
498
499static int wm0010_stage2_load(struct snd_soc_component *component)
500{
501 struct spi_device *spi = to_spi_device(component->dev);
502 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
503 const struct firmware *fw;
504 struct spi_message m;
505 struct spi_transfer t;
506 u32 *img;
507 u8 *out;
508 int i;
509 int ret = 0;
510
511 ret = request_firmware(&fw, "wm0010_stage2.bin", component->dev);
512 if (ret != 0) {
513 dev_err(component->dev, "Failed to request stage2 loader: %d\n",
514 ret);
515 return ret;
516 }
517
518 dev_dbg(component->dev, "Downloading %zu byte stage 2 loader\n", fw->size);
519
520
521 img = kzalloc(fw->size, GFP_KERNEL | GFP_DMA);
522 if (!img) {
523 ret = -ENOMEM;
524 goto abort2;
525 }
526
527 out = kzalloc(fw->size, GFP_KERNEL | GFP_DMA);
528 if (!out) {
529 ret = -ENOMEM;
530 goto abort1;
531 }
532
533 memcpy(img, &fw->data[0], fw->size);
534
535 spi_message_init(&m);
536 memset(&t, 0, sizeof(t));
537 t.rx_buf = out;
538 t.tx_buf = img;
539 t.len = fw->size;
540 t.bits_per_word = 8;
541 t.speed_hz = wm0010->sysclk / 10;
542 spi_message_add_tail(&t, &m);
543
544 dev_dbg(component->dev, "Starting initial download at %dHz\n",
545 t.speed_hz);
546
547 ret = spi_sync(spi, &m);
548 if (ret != 0) {
549 dev_err(component->dev, "Initial download failed: %d\n", ret);
550 goto abort;
551 }
552
553
554 for (i = 0; i < fw->size; i++) {
555 if (out[i] != 0x55) {
556 dev_err(component->dev, "Boot ROM error: %x in %d\n",
557 out[i], i);
558 wm0010_mark_boot_failure(wm0010);
559 ret = -EBUSY;
560 goto abort;
561 }
562 }
563abort:
564 kfree(out);
565abort1:
566 kfree(img);
567abort2:
568 release_firmware(fw);
569
570 return ret;
571}
572
573static int wm0010_boot(struct snd_soc_component *component)
574{
575 struct spi_device *spi = to_spi_device(component->dev);
576 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
577 unsigned long flags;
578 int ret;
579 struct spi_message m;
580 struct spi_transfer t;
581 struct dfw_pllrec pll_rec;
582 u32 *p, len;
583 u64 *img_swap;
584 u8 *out;
585 int i;
586
587 spin_lock_irqsave(&wm0010->irq_lock, flags);
588 if (wm0010->state != WM0010_POWER_OFF)
589 dev_warn(wm0010->dev, "DSP already powered up!\n");
590 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
591
592 if (wm0010->sysclk > 26000000) {
593 dev_err(component->dev, "Max DSP clock frequency is 26MHz\n");
594 ret = -ECANCELED;
595 goto err;
596 }
597
598 mutex_lock(&wm0010->lock);
599 wm0010->pll_running = false;
600
601 dev_dbg(component->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
602
603 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
604 wm0010->core_supplies);
605 if (ret != 0) {
606 dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
607 ret);
608 mutex_unlock(&wm0010->lock);
609 goto err;
610 }
611
612 ret = regulator_enable(wm0010->dbvdd);
613 if (ret != 0) {
614 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
615 goto err_core;
616 }
617
618
619 gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value);
620 spin_lock_irqsave(&wm0010->irq_lock, flags);
621 wm0010->state = WM0010_OUT_OF_RESET;
622 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
623
624 if (!wait_for_completion_timeout(&wm0010->boot_completion,
625 msecs_to_jiffies(20)))
626 dev_err(component->dev, "Failed to get interrupt from DSP\n");
627
628 spin_lock_irqsave(&wm0010->irq_lock, flags);
629 wm0010->state = WM0010_BOOTROM;
630 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
631
632 ret = wm0010_stage2_load(component);
633 if (ret)
634 goto abort;
635
636 if (!wait_for_completion_timeout(&wm0010->boot_completion,
637 msecs_to_jiffies(20)))
638 dev_err(component->dev, "Failed to get interrupt from DSP loader.\n");
639
640 spin_lock_irqsave(&wm0010->irq_lock, flags);
641 wm0010->state = WM0010_STAGE2;
642 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
643
644
645 if (wm0010->max_spi_freq) {
646
647
648 memset(&pll_rec, 0, sizeof(pll_rec));
649 pll_rec.command = DFW_CMD_PLL;
650 pll_rec.length = (sizeof(pll_rec) - 8);
651
652
653 pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
654
655 ret = -ENOMEM;
656 len = pll_rec.length + 8;
657 out = kzalloc(len, GFP_KERNEL | GFP_DMA);
658 if (!out)
659 goto abort;
660
661 img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA);
662 if (!img_swap)
663 goto abort_out;
664
665
666 byte_swap_64((u64 *)&pll_rec, img_swap, len);
667
668 spi_message_init(&m);
669 memset(&t, 0, sizeof(t));
670 t.rx_buf = out;
671 t.tx_buf = img_swap;
672 t.len = len;
673 t.bits_per_word = 8;
674 t.speed_hz = wm0010->sysclk / 6;
675 spi_message_add_tail(&t, &m);
676
677 ret = spi_sync(spi, &m);
678 if (ret) {
679 dev_err(component->dev, "First PLL write failed: %d\n", ret);
680 goto abort_swap;
681 }
682
683
684 ret = spi_sync(spi, &m);
685 if (ret) {
686 dev_err(component->dev, "Second PLL write failed: %d\n", ret);
687 goto abort_swap;
688 }
689
690 p = (u32 *)out;
691
692
693 for (i = 0; i < len / 4; i++) {
694 if (*p == 0x0e00ed0f) {
695 dev_dbg(component->dev, "PLL packet received\n");
696 wm0010->pll_running = true;
697 break;
698 }
699 p++;
700 }
701
702 kfree(img_swap);
703 kfree(out);
704 } else
705 dev_dbg(component->dev, "Not enabling DSP PLL.");
706
707 ret = wm0010_firmware_load("wm0010.dfw", component);
708
709 if (ret != 0)
710 goto abort;
711
712 spin_lock_irqsave(&wm0010->irq_lock, flags);
713 wm0010->state = WM0010_FIRMWARE;
714 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
715
716 mutex_unlock(&wm0010->lock);
717
718 return 0;
719
720abort_swap:
721 kfree(img_swap);
722abort_out:
723 kfree(out);
724abort:
725
726 wm0010_halt(component);
727 mutex_unlock(&wm0010->lock);
728 return ret;
729
730err_core:
731 mutex_unlock(&wm0010->lock);
732 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
733 wm0010->core_supplies);
734err:
735 return ret;
736}
737
738static int wm0010_set_bias_level(struct snd_soc_component *component,
739 enum snd_soc_bias_level level)
740{
741 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
742
743 switch (level) {
744 case SND_SOC_BIAS_ON:
745 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE)
746 wm0010_boot(component);
747 break;
748 case SND_SOC_BIAS_PREPARE:
749 break;
750 case SND_SOC_BIAS_STANDBY:
751 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) {
752 mutex_lock(&wm0010->lock);
753 wm0010_halt(component);
754 mutex_unlock(&wm0010->lock);
755 }
756 break;
757 case SND_SOC_BIAS_OFF:
758 break;
759 }
760
761 return 0;
762}
763
764static int wm0010_set_sysclk(struct snd_soc_component *component, int source,
765 int clk_id, unsigned int freq, int dir)
766{
767 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
768 unsigned int i;
769
770 wm0010->sysclk = freq;
771
772 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) {
773 wm0010->max_spi_freq = 0;
774 } else {
775 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++)
776 if (freq >= pll_clock_map[i].max_sysclk) {
777 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed;
778 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1;
779 break;
780 }
781 }
782
783 return 0;
784}
785
786static int wm0010_probe(struct snd_soc_component *component);
787
788static const struct snd_soc_component_driver soc_component_dev_wm0010 = {
789 .probe = wm0010_probe,
790 .set_bias_level = wm0010_set_bias_level,
791 .set_sysclk = wm0010_set_sysclk,
792 .dapm_widgets = wm0010_dapm_widgets,
793 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets),
794 .dapm_routes = wm0010_dapm_routes,
795 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes),
796 .use_pmdown_time = 1,
797 .endianness = 1,
798 .non_legacy_dai_naming = 1,
799};
800
801#define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
802#define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
803 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
804 SNDRV_PCM_FMTBIT_S32_LE)
805
806static struct snd_soc_dai_driver wm0010_dai[] = {
807 {
808 .name = "wm0010-sdi1",
809 .playback = {
810 .stream_name = "SDI1 Playback",
811 .channels_min = 1,
812 .channels_max = 2,
813 .rates = WM0010_RATES,
814 .formats = WM0010_FORMATS,
815 },
816 .capture = {
817 .stream_name = "SDI1 Capture",
818 .channels_min = 1,
819 .channels_max = 2,
820 .rates = WM0010_RATES,
821 .formats = WM0010_FORMATS,
822 },
823 },
824 {
825 .name = "wm0010-sdi2",
826 .playback = {
827 .stream_name = "SDI2 Playback",
828 .channels_min = 1,
829 .channels_max = 2,
830 .rates = WM0010_RATES,
831 .formats = WM0010_FORMATS,
832 },
833 .capture = {
834 .stream_name = "SDI2 Capture",
835 .channels_min = 1,
836 .channels_max = 2,
837 .rates = WM0010_RATES,
838 .formats = WM0010_FORMATS,
839 },
840 },
841};
842
843static irqreturn_t wm0010_irq(int irq, void *data)
844{
845 struct wm0010_priv *wm0010 = data;
846
847 switch (wm0010->state) {
848 case WM0010_OUT_OF_RESET:
849 case WM0010_BOOTROM:
850 case WM0010_STAGE2:
851 spin_lock(&wm0010->irq_lock);
852 complete(&wm0010->boot_completion);
853 spin_unlock(&wm0010->irq_lock);
854 return IRQ_HANDLED;
855 default:
856 return IRQ_NONE;
857 }
858
859 return IRQ_NONE;
860}
861
862static int wm0010_probe(struct snd_soc_component *component)
863{
864 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
865
866 wm0010->component = component;
867
868 return 0;
869}
870
871static int wm0010_spi_probe(struct spi_device *spi)
872{
873 unsigned long gpio_flags;
874 int ret;
875 int trigger;
876 int irq;
877 struct wm0010_priv *wm0010;
878
879 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010),
880 GFP_KERNEL);
881 if (!wm0010)
882 return -ENOMEM;
883
884 mutex_init(&wm0010->lock);
885 spin_lock_init(&wm0010->irq_lock);
886
887 spi_set_drvdata(spi, wm0010);
888 wm0010->dev = &spi->dev;
889
890 if (dev_get_platdata(&spi->dev))
891 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev),
892 sizeof(wm0010->pdata));
893
894 init_completion(&wm0010->boot_completion);
895
896 wm0010->core_supplies[0].supply = "AVDD";
897 wm0010->core_supplies[1].supply = "DCVDD";
898 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies),
899 wm0010->core_supplies);
900 if (ret != 0) {
901 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n",
902 ret);
903 return ret;
904 }
905
906 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD");
907 if (IS_ERR(wm0010->dbvdd)) {
908 ret = PTR_ERR(wm0010->dbvdd);
909 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret);
910 return ret;
911 }
912
913 if (wm0010->pdata.gpio_reset) {
914 wm0010->gpio_reset = wm0010->pdata.gpio_reset;
915
916 if (wm0010->pdata.reset_active_high)
917 wm0010->gpio_reset_value = 1;
918 else
919 wm0010->gpio_reset_value = 0;
920
921 if (wm0010->gpio_reset_value)
922 gpio_flags = GPIOF_OUT_INIT_HIGH;
923 else
924 gpio_flags = GPIOF_OUT_INIT_LOW;
925
926 ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset,
927 gpio_flags, "wm0010 reset");
928 if (ret < 0) {
929 dev_err(wm0010->dev,
930 "Failed to request GPIO for DSP reset: %d\n",
931 ret);
932 return ret;
933 }
934 } else {
935 dev_err(wm0010->dev, "No reset GPIO configured\n");
936 return -EINVAL;
937 }
938
939 wm0010->state = WM0010_POWER_OFF;
940
941 irq = spi->irq;
942 if (wm0010->pdata.irq_flags)
943 trigger = wm0010->pdata.irq_flags;
944 else
945 trigger = IRQF_TRIGGER_FALLING;
946 trigger |= IRQF_ONESHOT;
947
948 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger,
949 "wm0010", wm0010);
950 if (ret) {
951 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n",
952 irq, ret);
953 return ret;
954 }
955 wm0010->irq = irq;
956
957 ret = irq_set_irq_wake(irq, 1);
958 if (ret) {
959 dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n",
960 irq, ret);
961 return ret;
962 }
963
964 if (spi->max_speed_hz)
965 wm0010->board_max_spi_speed = spi->max_speed_hz;
966 else
967 wm0010->board_max_spi_speed = 0;
968
969 ret = devm_snd_soc_register_component(&spi->dev,
970 &soc_component_dev_wm0010, wm0010_dai,
971 ARRAY_SIZE(wm0010_dai));
972 if (ret < 0)
973 return ret;
974
975 return 0;
976}
977
978static int wm0010_spi_remove(struct spi_device *spi)
979{
980 struct wm0010_priv *wm0010 = spi_get_drvdata(spi);
981
982 gpio_set_value_cansleep(wm0010->gpio_reset,
983 wm0010->gpio_reset_value);
984
985 irq_set_irq_wake(wm0010->irq, 0);
986
987 if (wm0010->irq)
988 free_irq(wm0010->irq, wm0010);
989
990 return 0;
991}
992
993static struct spi_driver wm0010_spi_driver = {
994 .driver = {
995 .name = "wm0010",
996 },
997 .probe = wm0010_spi_probe,
998 .remove = wm0010_spi_remove,
999};
1000
1001module_spi_driver(wm0010_spi_driver);
1002
1003MODULE_DESCRIPTION("ASoC WM0010 driver");
1004MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1005MODULE_LICENSE("GPL");
1006
