1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2005 Silicon Graphics, Inc. 4 */ 5#ifndef IA64_SN_IOC3_H 6#define IA64_SN_IOC3_H 7 8/* serial port register map */ 9struct ioc3_serialregs { 10 uint32_t sscr; 11 uint32_t stpir; 12 uint32_t stcir; 13 uint32_t srpir; 14 uint32_t srcir; 15 uint32_t srtr; 16 uint32_t shadow; 17}; 18 19/* SUPERIO uart register map */ 20struct ioc3_uartregs { 21 char iu_lcr; 22 union { 23 char iir; /* read only */ 24 char fcr; /* write only */ 25 } u3; 26 union { 27 char ier; /* DLAB == 0 */ 28 char dlm; /* DLAB == 1 */ 29 } u2; 30 union { 31 char rbr; /* read only, DLAB == 0 */ 32 char thr; /* write only, DLAB == 0 */ 33 char dll; /* DLAB == 1 */ 34 } u1; 35 char iu_scr; 36 char iu_msr; 37 char iu_lsr; 38 char iu_mcr; 39}; 40 41#define iu_rbr u1.rbr 42#define iu_thr u1.thr 43#define iu_dll u1.dll 44#define iu_ier u2.ier 45#define iu_dlm u2.dlm 46#define iu_iir u3.iir 47#define iu_fcr u3.fcr 48 49struct ioc3_sioregs { 50 char fill[0x170]; 51 struct ioc3_uartregs uartb; 52 struct ioc3_uartregs uarta; 53}; 54 55/* PCI IO/mem space register map */ 56struct ioc3 { 57 uint32_t pci_id; 58 uint32_t pci_scr; 59 uint32_t pci_rev; 60 uint32_t pci_lat; 61 uint32_t pci_addr; 62 uint32_t pci_err_addr_l; 63 uint32_t pci_err_addr_h; 64 65 uint32_t sio_ir; 66 /* these registers are read-only for general kernel code. To 67 * modify them use the functions in ioc3.c 68 */ 69 uint32_t sio_ies; 70 uint32_t sio_iec; 71 uint32_t sio_cr; 72 uint32_t int_out; 73 uint32_t mcr; 74 uint32_t gpcr_s; 75 uint32_t gpcr_c; 76 uint32_t gpdr; 77 uint32_t gppr[9]; 78 char fill[0x4c]; 79 80 /* serial port registers */ 81 uint32_t sbbr_h; 82 uint32_t sbbr_l; 83 84 struct ioc3_serialregs port_a; 85 struct ioc3_serialregs port_b; 86 char fill1[0x1ff10]; 87 /* superio registers */ 88 struct ioc3_sioregs sregs; 89}; 90 91/* These don't exist on the ioc3 serial card... */ 92#define eier fill1[8] 93#define eisr fill1[4] 94 95#define PCI_LAT 0xc /* Latency Timer */ 96#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */ 97#define UARTA_BASE 0x178 98#define UARTB_BASE 0x170 99 100 101/* bitmasks for serial RX status byte */ 102#define RXSB_OVERRUN 0x01 /* char(s) lost */ 103#define RXSB_PAR_ERR 0x02 /* parity error */ 104#define RXSB_FRAME_ERR 0x04 /* framing error */ 105#define RXSB_BREAK 0x08 /* break character */ 106#define RXSB_CTS 0x10 /* state of CTS */ 107#define RXSB_DCD 0x20 /* state of DCD */ 108#define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */ 109#define RXSB_DATA_VALID 0x80 /* FRAME_ERR PAR_ERR & BREAK valid */ 110 111/* bitmasks for serial TX control byte */ 112#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */ 113#define TXCB_INVALID 0x00 /* byte is invalid */ 114#define TXCB_VALID 0x40 /* byte is valid */ 115#define TXCB_MCR 0x80 /* data<7:0> to modem cntrl register */ 116#define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */ 117 118/* bitmasks for SBBR_L */ 119#define SBBR_L_SIZE 0x00000001 /* 0 1KB rings, 1 4KB rings */ 120 121/* bitmasks for SSCR_<A:B> */ 122#define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */ 123#define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */ 124#define SSCR_HFC_EN 0x00020000 /* h/w flow cntrl enabled */ 125#define SSCR_RX_RING_DCD 0x00040000 /* postRX record on delta-DCD */ 126#define SSCR_RX_RING_CTS 0x00080000 /* postRX record on delta-CTS */ 127#define SSCR_HIGH_SPD 0x00100000 /* 4X speed */ 128#define SSCR_DIAG 0x00200000 /* bypass clock divider */ 129#define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */ 130#define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */ 131#define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */ 132#define SSCR_PAUSE_STATE 0x40000000 /* set when PAUSE takes effect*/ 133#define SSCR_RESET 0x80000000 /* reset DMA channels */ 134 135/* all producer/consumer pointers are the same bitfield */ 136#define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */ 137#define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */ 138#define PROD_CONS_PTR_OFF 3 139 140/* bitmasks for SRCIR_<A:B> */ 141#define SRCIR_ARM 0x80000000 /* arm RX timer */ 142 143/* bitmasks for SHADOW_<A:B> */ 144#define SHADOW_DR 0x00000001 /* data ready */ 145#define SHADOW_OE 0x00000002 /* overrun error */ 146#define SHADOW_PE 0x00000004 /* parity error */ 147#define SHADOW_FE 0x00000008 /* framing error */ 148#define SHADOW_BI 0x00000010 /* break interrupt */ 149#define SHADOW_THRE 0x00000020 /* transmit holding reg empty */ 150#define SHADOW_TEMT 0x00000040 /* transmit shift reg empty */ 151#define SHADOW_RFCE 0x00000080 /* char in RX fifo has error */ 152#define SHADOW_DCTS 0x00010000 /* delta clear to send */ 153#define SHADOW_DDCD 0x00080000 /* delta data carrier detect */ 154#define SHADOW_CTS 0x00100000 /* clear to send */ 155#define SHADOW_DCD 0x00800000 /* data carrier detect */ 156#define SHADOW_DTR 0x01000000 /* data terminal ready */ 157#define SHADOW_RTS 0x02000000 /* request to send */ 158#define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */ 159#define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */ 160#define SHADOW_LOOP 0x10000000 /* loopback enabled */ 161 162/* bitmasks for SRTR_<A:B> */ 163#define SRTR_CNT 0x00000fff /* reload value for RX timer */ 164#define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */ 165#define SRTR_CNT_VAL_SHIFT 16 166#define SRTR_HZ 16000 /* SRTR clock frequency */ 167 168/* bitmasks for SIO_IR, SIO_IEC and SIO_IES */ 169#define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */ 170#define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */ 171#define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */ 172#define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */ 173#define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */ 174#define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */ 175#define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */ 176#define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */ 177#define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */ 178#define SIO_IR_SB_TX_MT 0x00000200 179#define SIO_IR_SB_RX_FULL 0x00000400 180#define SIO_IR_SB_RX_HIGH 0x00000800 181#define SIO_IR_SB_RX_TIMER 0x00001000 182#define SIO_IR_SB_DELTA_DCD 0x00002000 183#define SIO_IR_SB_DELTA_CTS 0x00004000 184#define SIO_IR_SB_INT 0x00008000 185#define SIO_IR_SB_TX_EXPLICIT 0x00010000 186#define SIO_IR_SB_MEMERR 0x00020000 187#define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */ 188#define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */ 189#define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */ 190#define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */ 191#define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */ 192#define SIO_IR_RT_INT 0x08000000 /* RT output pulse */ 193#define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */ 194#define SIO_IR_GEN_INT_SHIFT 28 195 196/* per device interrupt masks */ 197#define SIO_IR_SA (SIO_IR_SA_TX_MT | \ 198 SIO_IR_SA_RX_FULL | \ 199 SIO_IR_SA_RX_HIGH | \ 200 SIO_IR_SA_RX_TIMER | \ 201 SIO_IR_SA_DELTA_DCD | \ 202 SIO_IR_SA_DELTA_CTS | \ 203 SIO_IR_SA_INT | \ 204 SIO_IR_SA_TX_EXPLICIT | \ 205 SIO_IR_SA_MEMERR) 206 207#define SIO_IR_SB (SIO_IR_SB_TX_MT | \ 208 SIO_IR_SB_RX_FULL | \ 209 SIO_IR_SB_RX_HIGH | \ 210 SIO_IR_SB_RX_TIMER | \ 211 SIO_IR_SB_DELTA_DCD | \ 212 SIO_IR_SB_DELTA_CTS | \ 213 SIO_IR_SB_INT | \ 214 SIO_IR_SB_TX_EXPLICIT | \ 215 SIO_IR_SB_MEMERR) 216 217#define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \ 218 SIO_IR_PP_INTB | SIO_IR_PP_MEMERR) 219#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1) 220 221/* bitmasks for SIO_CR */ 222#define SIO_CR_CMD_PULSE_SHIFT 15 223#define SIO_CR_SER_A_BASE_SHIFT 1 224#define SIO_CR_SER_B_BASE_SHIFT 8 225#define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */ 226#define SIO_CR_ARB_DIAG_TXA 0x00000000 227#define SIO_CR_ARB_DIAG_RXA 0x00080000 228#define SIO_CR_ARB_DIAG_TXB 0x00100000 229#define SIO_CR_ARB_DIAG_RXB 0x00180000 230#define SIO_CR_ARB_DIAG_PP 0x00200000 231#define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */ 232 233/* defs for some of the generic I/O pins */ 234#define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */ 235#define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */ 236#define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */ 237 238#define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */ 239#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin cntrling uartb modeselect */ 240#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin cntrling uarta modeselect */ 241 242#endif /* IA64_SN_IOC3_H */ 243