LXR linux/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 2004 Cavium Networks
   7 */
   8#ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
   9#define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
  10
  11#include <linux/types.h>
  12#include <asm/mipsregs.h>
  13
  14/*
  15 * Cavium Octeons are MIPS64v2 processors
  16 */
  17#define cpu_dcache_line_size()  128
  18#define cpu_icache_line_size()  128
  19
  20
  21#define cpu_has_4kex            1
  22#define cpu_has_3k_cache        0
  23#define cpu_has_4k_cache        0
  24#define cpu_has_tx39_cache      0
  25#define cpu_has_counter         1
  26#define cpu_has_watch           1
  27#define cpu_has_divec           1
  28#define cpu_has_vce             0
  29#define cpu_has_cache_cdex_p    0
  30#define cpu_has_cache_cdex_s    0
  31#define cpu_has_prefetch        1
  32
  33#define cpu_has_llsc            1
  34/*
  35 * We Disable LL/SC on non SMP systems as it is faster to disable
  36 * interrupts for atomic access than a LL/SC.
  37 */
  38#ifdef CONFIG_SMP
  39# define kernel_uses_llsc       1
  40#else
  41# define kernel_uses_llsc       0
  42#endif
  43#define cpu_has_vtag_icache     1
  44#define cpu_has_dc_aliases      0
  45#define cpu_has_ic_fills_f_dc   0
  46#define cpu_has_64bits          1
  47#define cpu_has_octeon_cache    1
  48#define cpu_has_saa             octeon_has_saa()
  49#define cpu_has_mips32r1        1
  50#define cpu_has_mips32r2        1
  51#define cpu_has_mips64r1        1
  52#define cpu_has_mips64r2        1
  53#define cpu_has_dsp             0
  54#define cpu_has_dsp2            0
  55#define cpu_has_mipsmt          0
  56#define cpu_has_vint            0
  57#define cpu_has_veic            0
  58#define cpu_hwrena_impl_bits    (MIPS_HWRENA_IMPL1 | MIPS_HWRENA_IMPL2)
  59#define cpu_has_wsbh            1
  60
  61#define cpu_has_rixi            (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
  62
  63#define ARCH_HAS_IRQ_PER_CPU    1
  64#define ARCH_HAS_SPINLOCK_PREFETCH 1
  65#define spin_lock_prefetch(x) prefetch(x)
  66#define PREFETCH_STRIDE 128
  67
  68#ifdef __OCTEON__
  69/*
  70 * All gcc versions that have OCTEON support define __OCTEON__ and have the
  71 *  __builtin_popcount support.
  72 */
  73#define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1
  74#endif
  75
  76static inline int octeon_has_saa(void)
  77{
  78        int id;
  79        asm volatile ("mfc0 %0, $15,0" : "=r" (id));
  80        return id >= 0x000d0300;
  81}
  82
  83/*
  84 * The last 256MB are reserved for device to device mappings and the
  85 * BAR1 hole.
  86 */
  87#define MAX_DMA32_PFN (((1ULL << 32) - (1ULL << 28)) >> PAGE_SHIFT)
  88
  89#endif
  90