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20#define pr_fmt(fmt) "ACPI: " fmt
21
22#include <linux/kernel.h>
23#include <linux/pci.h>
24#include <linux/pci-acpi.h>
25#include <linux/pci-ecam.h>
26
27
28struct mcfg_entry {
29 struct list_head list;
30 phys_addr_t addr;
31 u16 segment;
32 u8 bus_start;
33 u8 bus_end;
34};
35
36#ifdef CONFIG_PCI_QUIRKS
37struct mcfg_fixup {
38 char oem_id[ACPI_OEM_ID_SIZE + 1];
39 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
40 u32 oem_revision;
41 u16 segment;
42 struct resource bus_range;
43 struct pci_ecam_ops *ops;
44 struct resource cfgres;
45};
46
47#define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start), \
48 ((end) - (start) + 1), \
49 NULL, IORESOURCE_BUS)
50#define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff)
51
52static struct mcfg_fixup mcfg_quirks[] = {
53
54
55#define AL_ECAM(table_id, rev, seg, ops) \
56 { "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
57
58 AL_ECAM("GRAVITON", 0, 0, &al_pcie_ops),
59 AL_ECAM("GRAVITON", 0, 1, &al_pcie_ops),
60 AL_ECAM("GRAVITON", 0, 2, &al_pcie_ops),
61 AL_ECAM("GRAVITON", 0, 3, &al_pcie_ops),
62 AL_ECAM("GRAVITON", 0, 4, &al_pcie_ops),
63 AL_ECAM("GRAVITON", 0, 5, &al_pcie_ops),
64 AL_ECAM("GRAVITON", 0, 6, &al_pcie_ops),
65 AL_ECAM("GRAVITON", 0, 7, &al_pcie_ops),
66
67#define QCOM_ECAM32(seg) \
68 { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
69
70 QCOM_ECAM32(0),
71 QCOM_ECAM32(1),
72 QCOM_ECAM32(2),
73 QCOM_ECAM32(3),
74 QCOM_ECAM32(4),
75 QCOM_ECAM32(5),
76 QCOM_ECAM32(6),
77 QCOM_ECAM32(7),
78
79#define HISI_QUAD_DOM(table_id, seg, ops) \
80 { "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
81 { "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
82 { "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
83 { "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
84
85 HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops),
86 HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops),
87 HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops),
88 HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops),
89 HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops),
90 HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops),
91
92#define THUNDER_PEM_RES(addr, node) \
93 DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
94
95#define THUNDER_PEM_QUIRK(rev, node) \
96 { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
97 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \
98 { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \
99 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) }, \
100 { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \
101 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) }, \
102 { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \
103 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) }, \
104 { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \
105 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \
106 { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
107 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
108
109#define THUNDER_ECAM_QUIRK(rev, seg) \
110 { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
111 &pci_thunder_ecam_ops }
112
113
114 THUNDER_PEM_QUIRK(1, 0),
115 THUNDER_PEM_QUIRK(1, 1),
116 THUNDER_ECAM_QUIRK(1, 10),
117
118
119 THUNDER_PEM_QUIRK(2, 0),
120 THUNDER_PEM_QUIRK(2, 1),
121 THUNDER_ECAM_QUIRK(2, 0),
122 THUNDER_ECAM_QUIRK(2, 1),
123 THUNDER_ECAM_QUIRK(2, 2),
124 THUNDER_ECAM_QUIRK(2, 3),
125 THUNDER_ECAM_QUIRK(2, 10),
126 THUNDER_ECAM_QUIRK(2, 11),
127 THUNDER_ECAM_QUIRK(2, 12),
128 THUNDER_ECAM_QUIRK(2, 13),
129
130#define XGENE_V1_ECAM_MCFG(rev, seg) \
131 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
132 &xgene_v1_pcie_ecam_ops }
133
134#define XGENE_V2_ECAM_MCFG(rev, seg) \
135 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
136 &xgene_v2_pcie_ecam_ops }
137
138
139 XGENE_V1_ECAM_MCFG(1, 0),
140 XGENE_V1_ECAM_MCFG(1, 1),
141 XGENE_V1_ECAM_MCFG(1, 2),
142 XGENE_V1_ECAM_MCFG(1, 3),
143 XGENE_V1_ECAM_MCFG(1, 4),
144 XGENE_V1_ECAM_MCFG(2, 0),
145 XGENE_V1_ECAM_MCFG(2, 1),
146 XGENE_V1_ECAM_MCFG(2, 2),
147 XGENE_V1_ECAM_MCFG(2, 3),
148 XGENE_V1_ECAM_MCFG(2, 4),
149
150 XGENE_V2_ECAM_MCFG(3, 0),
151 XGENE_V2_ECAM_MCFG(3, 1),
152
153 XGENE_V2_ECAM_MCFG(4, 0),
154 XGENE_V2_ECAM_MCFG(4, 1),
155 XGENE_V2_ECAM_MCFG(4, 2),
156
157#define BCM_ECAM_MCFG(rev, seg) \
158 {"BRCM ", "BRCM-SRX", rev, seg, MCFG_BUS_ANY, \
159 &iproc_pcie_paxcv2_ecam_ops }
160 BCM_ECAM_MCFG(1, 8),
161};
162
163static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
164static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
165static u32 mcfg_oem_revision;
166
167static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
168 struct resource *bus_range)
169{
170 if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
171 !memcmp(f->oem_table_id, mcfg_oem_table_id,
172 ACPI_OEM_TABLE_ID_SIZE) &&
173 f->oem_revision == mcfg_oem_revision &&
174 f->segment == segment &&
175 resource_contains(&f->bus_range, bus_range))
176 return 1;
177
178 return 0;
179}
180#endif
181
182static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
183 struct resource *cfgres,
184 struct pci_ecam_ops **ecam_ops)
185{
186#ifdef CONFIG_PCI_QUIRKS
187 u16 segment = root->segment;
188 struct resource *bus_range = &root->secondary;
189 struct mcfg_fixup *f;
190 int i;
191
192 for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
193 if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
194 if (f->cfgres.start)
195 *cfgres = f->cfgres;
196 if (f->ops)
197 *ecam_ops = f->ops;
198 dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",
199 cfgres, bus_range, *ecam_ops);
200 return;
201 }
202 }
203#endif
204}
205
206
207static LIST_HEAD(pci_mcfg_list);
208
209int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
210 struct pci_ecam_ops **ecam_ops)
211{
212 struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
213 struct resource *bus_res = &root->secondary;
214 u16 seg = root->segment;
215 struct mcfg_entry *e;
216 struct resource res;
217
218
219 if (root->mcfg_addr)
220 goto skip_lookup;
221
222
223
224
225 list_for_each_entry(e, &pci_mcfg_list, list) {
226 if (e->segment == seg && e->bus_start <= bus_res->start &&
227 e->bus_end >= bus_res->end) {
228 root->mcfg_addr = e->addr;
229 }
230
231 }
232
233skip_lookup:
234 memset(&res, 0, sizeof(res));
235 if (root->mcfg_addr) {
236 res.start = root->mcfg_addr + (bus_res->start << 20);
237 res.end = res.start + (resource_size(bus_res) << 20) - 1;
238 res.flags = IORESOURCE_MEM;
239 }
240
241
242
243
244
245
246
247 pci_mcfg_apply_quirks(root, &res, &ops);
248 if (!res.start)
249 return -ENXIO;
250
251 *cfgres = res;
252 *ecam_ops = ops;
253 return 0;
254}
255
256static __init int pci_mcfg_parse(struct acpi_table_header *header)
257{
258 struct acpi_table_mcfg *mcfg;
259 struct acpi_mcfg_allocation *mptr;
260 struct mcfg_entry *e, *arr;
261 int i, n;
262
263 if (header->length < sizeof(struct acpi_table_mcfg))
264 return -EINVAL;
265
266 n = (header->length - sizeof(struct acpi_table_mcfg)) /
267 sizeof(struct acpi_mcfg_allocation);
268 mcfg = (struct acpi_table_mcfg *)header;
269 mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
270
271 arr = kcalloc(n, sizeof(*arr), GFP_KERNEL);
272 if (!arr)
273 return -ENOMEM;
274
275 for (i = 0, e = arr; i < n; i++, mptr++, e++) {
276 e->segment = mptr->pci_segment;
277 e->addr = mptr->address;
278 e->bus_start = mptr->start_bus_number;
279 e->bus_end = mptr->end_bus_number;
280 list_add(&e->list, &pci_mcfg_list);
281 }
282
283#ifdef CONFIG_PCI_QUIRKS
284
285 memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
286 memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
287 mcfg_oem_revision = header->oem_revision;
288#endif
289
290 pr_info("MCFG table detected, %d entries\n", n);
291 return 0;
292}
293
294
295void __init pci_mmcfg_late_init(void)
296{
297 int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
298 if (err)
299 pr_err("Failed to parse MCFG (%d)\n", err);
300}
301
