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11#include <linux/clk-provider.h>
12#include <linux/clk/renesas.h>
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/spinlock.h>
19
20struct r8a73a4_cpg {
21 struct clk_onecell_data data;
22 spinlock_t lock;
23 void __iomem *reg;
24};
25
26#define CPG_CKSCR 0xc0
27#define CPG_FRQCRA 0x00
28#define CPG_FRQCRB 0x04
29#define CPG_FRQCRC 0xe0
30#define CPG_PLL0CR 0xd8
31#define CPG_PLL1CR 0x28
32#define CPG_PLL2CR 0x2c
33#define CPG_PLL2HCR 0xe4
34#define CPG_PLL2SCR 0xf4
35
36#define CLK_ENABLE_ON_INIT BIT(0)
37
38struct div4_clk {
39 const char *name;
40 unsigned int reg;
41 unsigned int shift;
42};
43
44static struct div4_clk div4_clks[] = {
45 { "i", CPG_FRQCRA, 20 },
46 { "m3", CPG_FRQCRA, 12 },
47 { "b", CPG_FRQCRA, 8 },
48 { "m1", CPG_FRQCRA, 4 },
49 { "m2", CPG_FRQCRA, 0 },
50 { "zx", CPG_FRQCRB, 12 },
51 { "zs", CPG_FRQCRB, 8 },
52 { "hp", CPG_FRQCRB, 4 },
53 { NULL, 0, 0 },
54};
55
56static const struct clk_div_table div4_div_table[] = {
57 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
58 { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
59 { 12, 10 }, { 0, 0 }
60};
61
62static struct clk * __init
63r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
64 const char *name)
65{
66 const struct clk_div_table *table = NULL;
67 const char *parent_name;
68 unsigned int shift, reg;
69 unsigned int mult = 1;
70 unsigned int div = 1;
71
72
73 if (!strcmp(name, "main")) {
74 u32 ckscr = readl(cpg->reg + CPG_CKSCR);
75
76 switch ((ckscr >> 28) & 3) {
77 case 0:
78 parent_name = of_clk_get_parent_name(np, 0);
79 break;
80 case 1:
81 parent_name = of_clk_get_parent_name(np, 0);
82 div = 2;
83 break;
84 case 2:
85 parent_name = of_clk_get_parent_name(np, 1);
86 break;
87 case 3:
88 parent_name = of_clk_get_parent_name(np, 1);
89 div = 2;
90 break;
91 }
92 } else if (!strcmp(name, "pll0")) {
93
94
95
96
97
98 u32 value = readl(cpg->reg + CPG_PLL0CR);
99
100 parent_name = "main";
101 mult = ((value >> 24) & 0x7f) + 1;
102 if (value & BIT(20))
103 div = 2;
104 } else if (!strcmp(name, "pll1")) {
105 u32 value = readl(cpg->reg + CPG_PLL1CR);
106
107 parent_name = "main";
108
109 mult = ((value >> 24) & 0x7f) + 1;
110 if (value & BIT(7))
111 div = 2;
112 } else if (!strncmp(name, "pll2", 4)) {
113 u32 value, cr;
114
115 switch (name[4]) {
116 case 0:
117 cr = CPG_PLL2CR;
118 break;
119 case 's':
120 cr = CPG_PLL2SCR;
121 break;
122 case 'h':
123 cr = CPG_PLL2HCR;
124 break;
125 default:
126 return ERR_PTR(-EINVAL);
127 }
128 value = readl(cpg->reg + cr);
129 switch ((value >> 5) & 7) {
130 case 0:
131 parent_name = "main";
132 div = 2;
133 break;
134 case 1:
135 parent_name = "extal2";
136 div = 2;
137 break;
138 case 3:
139 parent_name = "extal2";
140 div = 4;
141 break;
142 case 4:
143 parent_name = "main";
144 break;
145 case 5:
146 parent_name = "extal2";
147 break;
148 default:
149 pr_warn("%s: unexpected parent of %s\n", __func__,
150 name);
151 return ERR_PTR(-EINVAL);
152 }
153
154 mult = ((value >> 24) & 0x7f) + 1;
155 } else if (!strcmp(name, "z") || !strcmp(name, "z2")) {
156 u32 shift = 8;
157
158 parent_name = "pll0";
159 if (name[1] == '2') {
160 div = 2;
161 shift = 0;
162 }
163 div *= 32;
164 mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f);
165 } else {
166 struct div4_clk *c;
167
168 for (c = div4_clks; c->name; c++) {
169 if (!strcmp(name, c->name))
170 break;
171 }
172 if (!c->name)
173 return ERR_PTR(-EINVAL);
174
175 parent_name = "pll1";
176 table = div4_div_table;
177 reg = c->reg;
178 shift = c->shift;
179 }
180
181 if (!table) {
182 return clk_register_fixed_factor(NULL, name, parent_name, 0,
183 mult, div);
184 } else {
185 return clk_register_divider_table(NULL, name, parent_name, 0,
186 cpg->reg + reg, shift, 4, 0,
187 table, &cpg->lock);
188 }
189}
190
191static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
192{
193 struct r8a73a4_cpg *cpg;
194 struct clk **clks;
195 unsigned int i;
196 int num_clks;
197
198 num_clks = of_property_count_strings(np, "clock-output-names");
199 if (num_clks < 0) {
200 pr_err("%s: failed to count clocks\n", __func__);
201 return;
202 }
203
204 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
205 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
206 if (cpg == NULL || clks == NULL) {
207
208
209
210 return;
211 }
212
213 spin_lock_init(&cpg->lock);
214
215 cpg->data.clks = clks;
216 cpg->data.clk_num = num_clks;
217
218 cpg->reg = of_iomap(np, 0);
219 if (WARN_ON(cpg->reg == NULL))
220 return;
221
222 for (i = 0; i < num_clks; ++i) {
223 const char *name;
224 struct clk *clk;
225
226 of_property_read_string_index(np, "clock-output-names", i,
227 &name);
228
229 clk = r8a73a4_cpg_register_clock(np, cpg, name);
230 if (IS_ERR(clk))
231 pr_err("%s: failed to register %s %s clock (%ld)\n",
232 __func__, np->name, name, PTR_ERR(clk));
233 else
234 cpg->data.clks[i] = clk;
235 }
236
237 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
238}
239CLK_OF_DECLARE(r8a73a4_cpg_clks, "renesas,r8a73a4-cpg-clocks",
240 r8a73a4_cpg_clocks_init);
241
