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9#include <linux/clk.h>
10#include <linux/host1x.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/of_device.h>
14#include <linux/of_graph.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/reset.h>
18
19#include <drm/drmP.h>
20#include <drm/drm_atomic.h>
21#include <drm/drm_atomic_helper.h>
22#include <drm/drm_crtc_helper.h>
23
24#include "drm.h"
25#include "dc.h"
26#include "plane.h"
27
28static const u32 tegra_shared_plane_formats[] = {
29 DRM_FORMAT_ARGB1555,
30 DRM_FORMAT_RGB565,
31 DRM_FORMAT_RGBA5551,
32 DRM_FORMAT_ARGB8888,
33 DRM_FORMAT_ABGR8888,
34
35 DRM_FORMAT_ABGR4444,
36 DRM_FORMAT_ABGR1555,
37 DRM_FORMAT_BGRA5551,
38 DRM_FORMAT_XRGB1555,
39 DRM_FORMAT_RGBX5551,
40 DRM_FORMAT_XBGR1555,
41 DRM_FORMAT_BGRX5551,
42 DRM_FORMAT_BGR565,
43 DRM_FORMAT_XRGB8888,
44 DRM_FORMAT_XBGR8888,
45
46 DRM_FORMAT_UYVY,
47 DRM_FORMAT_YUYV,
48 DRM_FORMAT_YUV420,
49 DRM_FORMAT_YUV422,
50};
51
52static const u64 tegra_shared_plane_modifiers[] = {
53 DRM_FORMAT_MOD_LINEAR,
54 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
55 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
56 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
57 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
58 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
59 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
60 DRM_FORMAT_MOD_INVALID
61};
62
63static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
64 unsigned int offset)
65{
66 if (offset >= 0x500 && offset <= 0x581) {
67 offset = 0x000 + (offset - 0x500);
68 return plane->offset + offset;
69 }
70
71 if (offset >= 0x700 && offset <= 0x73c) {
72 offset = 0x180 + (offset - 0x700);
73 return plane->offset + offset;
74 }
75
76 if (offset >= 0x800 && offset <= 0x83e) {
77 offset = 0x1c0 + (offset - 0x800);
78 return plane->offset + offset;
79 }
80
81 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
82
83 return plane->offset + offset;
84}
85
86static inline u32 tegra_plane_readl(struct tegra_plane *plane,
87 unsigned int offset)
88{
89 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
90}
91
92static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
93 unsigned int offset)
94{
95 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
96}
97
98static int tegra_windowgroup_enable(struct tegra_windowgroup *wgrp)
99{
100 mutex_lock(&wgrp->lock);
101
102 if (wgrp->usecount == 0) {
103 pm_runtime_get_sync(wgrp->parent);
104 reset_control_deassert(wgrp->rst);
105 }
106
107 wgrp->usecount++;
108 mutex_unlock(&wgrp->lock);
109
110 return 0;
111}
112
113static void tegra_windowgroup_disable(struct tegra_windowgroup *wgrp)
114{
115 int err;
116
117 mutex_lock(&wgrp->lock);
118
119 if (wgrp->usecount == 1) {
120 err = reset_control_assert(wgrp->rst);
121 if (err < 0) {
122 pr_err("failed to assert reset for window group %u\n",
123 wgrp->index);
124 }
125
126 pm_runtime_put(wgrp->parent);
127 }
128
129 wgrp->usecount--;
130 mutex_unlock(&wgrp->lock);
131}
132
133int tegra_display_hub_prepare(struct tegra_display_hub *hub)
134{
135 unsigned int i;
136
137
138
139
140
141
142
143 for (i = 0; i < hub->soc->num_wgrps; i++) {
144 struct tegra_windowgroup *wgrp = &hub->wgrps[i];
145
146 tegra_windowgroup_enable(wgrp);
147 }
148
149 return 0;
150}
151
152void tegra_display_hub_cleanup(struct tegra_display_hub *hub)
153{
154 unsigned int i;
155
156
157
158
159
160 for (i = 0; i < hub->soc->num_wgrps; i++) {
161 struct tegra_windowgroup *wgrp = &hub->wgrps[i];
162
163 tegra_windowgroup_disable(wgrp);
164 }
165}
166
167static void tegra_shared_plane_update(struct tegra_plane *plane)
168{
169 struct tegra_dc *dc = plane->dc;
170 unsigned long timeout;
171 u32 mask, value;
172
173 mask = COMMON_UPDATE | WIN_A_UPDATE << plane->base.index;
174 tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
175
176 timeout = jiffies + msecs_to_jiffies(1000);
177
178 while (time_before(jiffies, timeout)) {
179 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
180 if ((value & mask) == 0)
181 break;
182
183 usleep_range(100, 400);
184 }
185}
186
187static void tegra_shared_plane_activate(struct tegra_plane *plane)
188{
189 struct tegra_dc *dc = plane->dc;
190 unsigned long timeout;
191 u32 mask, value;
192
193 mask = COMMON_ACTREQ | WIN_A_ACT_REQ << plane->base.index;
194 tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
195
196 timeout = jiffies + msecs_to_jiffies(1000);
197
198 while (time_before(jiffies, timeout)) {
199 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
200 if ((value & mask) == 0)
201 break;
202
203 usleep_range(100, 400);
204 }
205}
206
207static unsigned int
208tegra_shared_plane_get_owner(struct tegra_plane *plane, struct tegra_dc *dc)
209{
210 unsigned int offset =
211 tegra_plane_offset(plane, DC_WIN_CORE_WINDOWGROUP_SET_CONTROL);
212
213 return tegra_dc_readl(dc, offset) & OWNER_MASK;
214}
215
216static bool tegra_dc_owns_shared_plane(struct tegra_dc *dc,
217 struct tegra_plane *plane)
218{
219 struct device *dev = dc->dev;
220
221 if (tegra_shared_plane_get_owner(plane, dc) == dc->pipe) {
222 if (plane->dc == dc)
223 return true;
224
225 dev_WARN(dev, "head %u owns window %u but is not attached\n",
226 dc->pipe, plane->index);
227 }
228
229 return false;
230}
231
232static int tegra_shared_plane_set_owner(struct tegra_plane *plane,
233 struct tegra_dc *new)
234{
235 unsigned int offset =
236 tegra_plane_offset(plane, DC_WIN_CORE_WINDOWGROUP_SET_CONTROL);
237 struct tegra_dc *old = plane->dc, *dc = new ? new : old;
238 struct device *dev = new ? new->dev : old->dev;
239 unsigned int owner, index = plane->index;
240 u32 value;
241
242 value = tegra_dc_readl(dc, offset);
243 owner = value & OWNER_MASK;
244
245 if (new && (owner != OWNER_MASK && owner != new->pipe)) {
246 dev_WARN(dev, "window %u owned by head %u\n", index, owner);
247 return -EBUSY;
248 }
249
250
251
252
253
254
255 if (old && owner == OWNER_MASK)
256 dev_dbg(dev, "window %u not owned by head %u but %u\n", index,
257 old->pipe, owner);
258
259 value &= ~OWNER_MASK;
260
261 if (new)
262 value |= OWNER(new->pipe);
263 else
264 value |= OWNER_MASK;
265
266 tegra_dc_writel(dc, value, offset);
267
268 plane->dc = new;
269
270 return 0;
271}
272
273static void tegra_dc_assign_shared_plane(struct tegra_dc *dc,
274 struct tegra_plane *plane)
275{
276 u32 value;
277 int err;
278
279 if (!tegra_dc_owns_shared_plane(dc, plane)) {
280 err = tegra_shared_plane_set_owner(plane, dc);
281 if (err < 0)
282 return;
283 }
284
285 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_LINEBUF_CONFIG);
286 value |= MODE_FOUR_LINES;
287 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_LINEBUF_CONFIG);
288
289 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_FETCH_METER);
290 value = SLOTS(1);
291 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_FETCH_METER);
292
293
294 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA);
295 value &= ~LATENCY_CTL_MODE_ENABLE;
296 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA);
297
298 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB);
299 value |= WATERMARK_MASK;
300 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB);
301
302
303 value = tegra_plane_readl(plane, DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER);
304 value = PIPE_METER_INT(0) | PIPE_METER_FRAC(0);
305 tegra_plane_writel(plane, value, DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER);
306
307
308 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG);
309 value = MEMPOOL_ENTRIES(0x331);
310 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG);
311
312 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_THREAD_GROUP);
313 value &= ~THREAD_NUM_MASK;
314 value |= THREAD_NUM(plane->base.index);
315 value |= THREAD_GROUP_ENABLE;
316 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_THREAD_GROUP);
317
318 tegra_shared_plane_update(plane);
319 tegra_shared_plane_activate(plane);
320}
321
322static void tegra_dc_remove_shared_plane(struct tegra_dc *dc,
323 struct tegra_plane *plane)
324{
325 tegra_shared_plane_set_owner(plane, NULL);
326}
327
328static int tegra_shared_plane_atomic_check(struct drm_plane *plane,
329 struct drm_plane_state *state)
330{
331 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
332 struct tegra_shared_plane *tegra = to_tegra_shared_plane(plane);
333 struct tegra_bo_tiling *tiling = &plane_state->tiling;
334 struct tegra_dc *dc = to_tegra_dc(state->crtc);
335 int err;
336
337
338 if (!state->crtc || !state->fb)
339 return 0;
340
341 err = tegra_plane_format(state->fb->format->format,
342 &plane_state->format,
343 &plane_state->swap);
344 if (err < 0)
345 return err;
346
347 err = tegra_fb_get_tiling(state->fb, tiling);
348 if (err < 0)
349 return err;
350
351 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
352 !dc->soc->supports_block_linear) {
353 DRM_ERROR("hardware doesn't support block linear mode\n");
354 return -EINVAL;
355 }
356
357
358
359
360
361
362 if (state->fb->format->num_planes > 2) {
363 if (state->fb->pitches[2] != state->fb->pitches[1]) {
364 DRM_ERROR("unsupported UV-plane configuration\n");
365 return -EINVAL;
366 }
367 }
368
369
370
371 err = tegra_plane_state_add(&tegra->base, state);
372 if (err < 0)
373 return err;
374
375 return 0;
376}
377
378static void tegra_shared_plane_atomic_disable(struct drm_plane *plane,
379 struct drm_plane_state *old_state)
380{
381 struct tegra_dc *dc = to_tegra_dc(old_state->crtc);
382 struct tegra_plane *p = to_tegra_plane(plane);
383 u32 value;
384
385
386 if (!old_state || !old_state->crtc)
387 return;
388
389
390
391
392
393
394 if (WARN_ON(p->dc == NULL))
395 p->dc = dc;
396
397 pm_runtime_get_sync(dc->dev);
398
399 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
400 value &= ~WIN_ENABLE;
401 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
402
403 tegra_dc_remove_shared_plane(dc, p);
404
405 pm_runtime_put(dc->dev);
406}
407
408static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
409 struct drm_plane_state *old_state)
410{
411 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
412 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
413 unsigned int zpos = plane->state->normalized_zpos;
414 struct drm_framebuffer *fb = plane->state->fb;
415 struct tegra_plane *p = to_tegra_plane(plane);
416 struct tegra_bo *bo;
417 dma_addr_t base;
418 u32 value;
419
420
421 if (!plane->state->crtc || !plane->state->fb)
422 return;
423
424 if (!plane->state->visible) {
425 tegra_shared_plane_atomic_disable(plane, old_state);
426 return;
427 }
428
429 pm_runtime_get_sync(dc->dev);
430
431 tegra_dc_assign_shared_plane(dc, p);
432
433 tegra_plane_writel(p, VCOUNTER, DC_WIN_CORE_ACT_CONTROL);
434
435
436 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
437 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
438 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
439 tegra_plane_writel(p, value, DC_WIN_BLEND_MATCH_SELECT);
440
441 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
442 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
443 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
444 tegra_plane_writel(p, value, DC_WIN_BLEND_NOMATCH_SELECT);
445
446 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - zpos);
447 tegra_plane_writel(p, value, DC_WIN_BLEND_LAYER_CONTROL);
448
449
450 value = HORIZONTAL_TAPS_5 | VERTICAL_TAPS_5;
451 tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER);
452
453 value = INPUT_SCALER_VBYPASS | INPUT_SCALER_HBYPASS;
454 tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE);
455
456
457 tegra_plane_writel(p, 0, DC_WINBUF_CDE_CONTROL);
458
459 bo = tegra_fb_get_plane(fb, 0);
460 base = bo->paddr;
461
462 tegra_plane_writel(p, state->format, DC_WIN_COLOR_DEPTH);
463 tegra_plane_writel(p, 0, DC_WIN_PRECOMP_WGRP_PARAMS);
464
465 value = V_POSITION(plane->state->crtc_y) |
466 H_POSITION(plane->state->crtc_x);
467 tegra_plane_writel(p, value, DC_WIN_POSITION);
468
469 value = V_SIZE(plane->state->crtc_h) | H_SIZE(plane->state->crtc_w);
470 tegra_plane_writel(p, value, DC_WIN_SIZE);
471
472 value = WIN_ENABLE | COLOR_EXPAND;
473 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
474
475 value = V_SIZE(plane->state->crtc_h) | H_SIZE(plane->state->crtc_w);
476 tegra_plane_writel(p, value, DC_WIN_CROPPED_SIZE);
477
478 tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI);
479 tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR);
480
481 value = PITCH(fb->pitches[0]);
482 tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE);
483
484 value = CLAMP_BEFORE_BLEND | DEGAMMA_SRGB | INPUT_RANGE_FULL;
485 tegra_plane_writel(p, value, DC_WIN_SET_PARAMS);
486
487 value = OFFSET_X(plane->state->src_y >> 16) |
488 OFFSET_Y(plane->state->src_x >> 16);
489 tegra_plane_writel(p, value, DC_WINBUF_CROPPED_POINT);
490
491 if (dc->soc->supports_block_linear) {
492 unsigned long height = state->tiling.value;
493
494
495 switch (state->tiling.mode) {
496 case TEGRA_BO_TILING_MODE_PITCH:
497 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(0) |
498 DC_WINBUF_SURFACE_KIND_PITCH;
499 break;
500
501
502 case TEGRA_BO_TILING_MODE_TILED:
503 value = DC_WINBUF_SURFACE_KIND_TILED;
504 break;
505
506 case TEGRA_BO_TILING_MODE_BLOCK:
507 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
508 DC_WINBUF_SURFACE_KIND_BLOCK;
509 break;
510 }
511
512 tegra_plane_writel(p, value, DC_WINBUF_SURFACE_KIND);
513 }
514
515
516 value = tegra_plane_readl(p, DC_WIN_WINDOW_SET_CONTROL);
517 value &= ~CONTROL_CSC_ENABLE;
518 tegra_plane_writel(p, value, DC_WIN_WINDOW_SET_CONTROL);
519
520 pm_runtime_put(dc->dev);
521}
522
523static const struct drm_plane_helper_funcs tegra_shared_plane_helper_funcs = {
524 .atomic_check = tegra_shared_plane_atomic_check,
525 .atomic_update = tegra_shared_plane_atomic_update,
526 .atomic_disable = tegra_shared_plane_atomic_disable,
527};
528
529struct drm_plane *tegra_shared_plane_create(struct drm_device *drm,
530 struct tegra_dc *dc,
531 unsigned int wgrp,
532 unsigned int index)
533{
534 enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
535 struct tegra_drm *tegra = drm->dev_private;
536 struct tegra_display_hub *hub = tegra->hub;
537
538 unsigned int possible_crtcs = 0x7;
539 struct tegra_shared_plane *plane;
540 unsigned int num_formats;
541 const u64 *modifiers;
542 struct drm_plane *p;
543 const u32 *formats;
544 int err;
545
546 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
547 if (!plane)
548 return ERR_PTR(-ENOMEM);
549
550 plane->base.offset = 0x0a00 + 0x0300 * index;
551 plane->base.index = index;
552
553 plane->wgrp = &hub->wgrps[wgrp];
554 plane->wgrp->parent = dc->dev;
555
556 p = &plane->base.base;
557
558 num_formats = ARRAY_SIZE(tegra_shared_plane_formats);
559 formats = tegra_shared_plane_formats;
560 modifiers = tegra_shared_plane_modifiers;
561
562 err = drm_universal_plane_init(drm, p, possible_crtcs,
563 &tegra_plane_funcs, formats,
564 num_formats, modifiers, type, NULL);
565 if (err < 0) {
566 kfree(plane);
567 return ERR_PTR(err);
568 }
569
570 drm_plane_helper_add(p, &tegra_shared_plane_helper_funcs);
571 drm_plane_create_zpos_property(p, 0, 0, 255);
572
573 return p;
574}
575
576static struct drm_private_state *
577tegra_display_hub_duplicate_state(struct drm_private_obj *obj)
578{
579 struct tegra_display_hub_state *state;
580
581 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
582 if (!state)
583 return NULL;
584
585 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
586
587 return &state->base;
588}
589
590static void tegra_display_hub_destroy_state(struct drm_private_obj *obj,
591 struct drm_private_state *state)
592{
593 struct tegra_display_hub_state *hub_state =
594 to_tegra_display_hub_state(state);
595
596 kfree(hub_state);
597}
598
599static const struct drm_private_state_funcs tegra_display_hub_state_funcs = {
600 .atomic_duplicate_state = tegra_display_hub_duplicate_state,
601 .atomic_destroy_state = tegra_display_hub_destroy_state,
602};
603
604static struct tegra_display_hub_state *
605tegra_display_hub_get_state(struct tegra_display_hub *hub,
606 struct drm_atomic_state *state)
607{
608 struct drm_device *drm = dev_get_drvdata(hub->client.parent);
609 struct drm_private_state *priv;
610
611 WARN_ON(!drm_modeset_is_locked(&drm->mode_config.connection_mutex));
612
613 priv = drm_atomic_get_private_obj_state(state, &hub->base);
614 if (IS_ERR(priv))
615 return ERR_CAST(priv);
616
617 return to_tegra_display_hub_state(priv);
618}
619
620int tegra_display_hub_atomic_check(struct drm_device *drm,
621 struct drm_atomic_state *state)
622{
623 struct tegra_drm *tegra = drm->dev_private;
624 struct tegra_display_hub_state *hub_state;
625 struct drm_crtc_state *old, *new;
626 struct drm_crtc *crtc;
627 unsigned int i;
628
629 if (!tegra->hub)
630 return 0;
631
632 hub_state = tegra_display_hub_get_state(tegra->hub, state);
633 if (IS_ERR(hub_state))
634 return PTR_ERR(hub_state);
635
636
637
638
639
640
641
642
643
644 for_each_oldnew_crtc_in_state(state, crtc, old, new, i) {
645 struct tegra_dc_state *dc = to_dc_state(new);
646
647 if (new->active) {
648 if (!hub_state->clk || dc->pclk > hub_state->rate) {
649 hub_state->dc = to_tegra_dc(dc->base.crtc);
650 hub_state->clk = hub_state->dc->clk;
651 hub_state->rate = dc->pclk;
652 }
653 }
654 }
655
656 return 0;
657}
658
659static void tegra_display_hub_update(struct tegra_dc *dc)
660{
661 u32 value;
662
663 pm_runtime_get_sync(dc->dev);
664
665 value = tegra_dc_readl(dc, DC_CMD_IHUB_COMMON_MISC_CTL);
666 value &= ~LATENCY_EVENT;
667 tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL);
668
669 value = tegra_dc_readl(dc, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);
670 value = CURS_SLOTS(1) | WGRP_SLOTS(1);
671 tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);
672
673 tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL);
674 tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
675 tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL);
676 tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
677
678 pm_runtime_put(dc->dev);
679}
680
681void tegra_display_hub_atomic_commit(struct drm_device *drm,
682 struct drm_atomic_state *state)
683{
684 struct tegra_drm *tegra = drm->dev_private;
685 struct tegra_display_hub *hub = tegra->hub;
686 struct tegra_display_hub_state *hub_state;
687 struct device *dev = hub->client.dev;
688 int err;
689
690 hub_state = to_tegra_display_hub_state(hub->base.state);
691
692 if (hub_state->clk) {
693 err = clk_set_rate(hub_state->clk, hub_state->rate);
694 if (err < 0)
695 dev_err(dev, "failed to set rate of %pC to %lu Hz\n",
696 hub_state->clk, hub_state->rate);
697
698 err = clk_set_parent(hub->clk_disp, hub_state->clk);
699 if (err < 0)
700 dev_err(dev, "failed to set parent of %pC to %pC: %d\n",
701 hub->clk_disp, hub_state->clk, err);
702 }
703
704 if (hub_state->dc)
705 tegra_display_hub_update(hub_state->dc);
706}
707
708static int tegra_display_hub_init(struct host1x_client *client)
709{
710 struct tegra_display_hub *hub = to_tegra_display_hub(client);
711 struct drm_device *drm = dev_get_drvdata(client->parent);
712 struct tegra_drm *tegra = drm->dev_private;
713 struct tegra_display_hub_state *state;
714
715 state = kzalloc(sizeof(*state), GFP_KERNEL);
716 if (!state)
717 return -ENOMEM;
718
719 drm_atomic_private_obj_init(&hub->base, &state->base,
720 &tegra_display_hub_state_funcs);
721
722 tegra->hub = hub;
723
724 return 0;
725}
726
727static int tegra_display_hub_exit(struct host1x_client *client)
728{
729 struct drm_device *drm = dev_get_drvdata(client->parent);
730 struct tegra_drm *tegra = drm->dev_private;
731
732 drm_atomic_private_obj_fini(&tegra->hub->base);
733 tegra->hub = NULL;
734
735 return 0;
736}
737
738static const struct host1x_client_ops tegra_display_hub_ops = {
739 .init = tegra_display_hub_init,
740 .exit = tegra_display_hub_exit,
741};
742
743static int tegra_display_hub_probe(struct platform_device *pdev)
744{
745 struct tegra_display_hub *hub;
746 unsigned int i;
747 int err;
748
749 hub = devm_kzalloc(&pdev->dev, sizeof(*hub), GFP_KERNEL);
750 if (!hub)
751 return -ENOMEM;
752
753 hub->soc = of_device_get_match_data(&pdev->dev);
754
755 hub->clk_disp = devm_clk_get(&pdev->dev, "disp");
756 if (IS_ERR(hub->clk_disp)) {
757 err = PTR_ERR(hub->clk_disp);
758 return err;
759 }
760
761 hub->clk_dsc = devm_clk_get(&pdev->dev, "dsc");
762 if (IS_ERR(hub->clk_dsc)) {
763 err = PTR_ERR(hub->clk_dsc);
764 return err;
765 }
766
767 hub->clk_hub = devm_clk_get(&pdev->dev, "hub");
768 if (IS_ERR(hub->clk_hub)) {
769 err = PTR_ERR(hub->clk_hub);
770 return err;
771 }
772
773 hub->rst = devm_reset_control_get(&pdev->dev, "misc");
774 if (IS_ERR(hub->rst)) {
775 err = PTR_ERR(hub->rst);
776 return err;
777 }
778
779 hub->wgrps = devm_kcalloc(&pdev->dev, hub->soc->num_wgrps,
780 sizeof(*hub->wgrps), GFP_KERNEL);
781 if (!hub->wgrps)
782 return -ENOMEM;
783
784 for (i = 0; i < hub->soc->num_wgrps; i++) {
785 struct tegra_windowgroup *wgrp = &hub->wgrps[i];
786 char id[8];
787
788 snprintf(id, sizeof(id), "wgrp%u", i);
789 mutex_init(&wgrp->lock);
790 wgrp->usecount = 0;
791 wgrp->index = i;
792
793 wgrp->rst = devm_reset_control_get(&pdev->dev, id);
794 if (IS_ERR(wgrp->rst))
795 return PTR_ERR(wgrp->rst);
796
797 err = reset_control_assert(wgrp->rst);
798 if (err < 0)
799 return err;
800 }
801
802
803 err = reset_control_assert(hub->rst);
804 if (err < 0)
805 return err;
806
807 platform_set_drvdata(pdev, hub);
808 pm_runtime_enable(&pdev->dev);
809
810 INIT_LIST_HEAD(&hub->client.list);
811 hub->client.ops = &tegra_display_hub_ops;
812 hub->client.dev = &pdev->dev;
813
814 err = host1x_client_register(&hub->client);
815 if (err < 0)
816 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
817 err);
818
819 return err;
820}
821
822static int tegra_display_hub_remove(struct platform_device *pdev)
823{
824 struct tegra_display_hub *hub = platform_get_drvdata(pdev);
825 int err;
826
827 err = host1x_client_unregister(&hub->client);
828 if (err < 0) {
829 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
830 err);
831 }
832
833 pm_runtime_disable(&pdev->dev);
834
835 return err;
836}
837
838static int __maybe_unused tegra_display_hub_suspend(struct device *dev)
839{
840 struct tegra_display_hub *hub = dev_get_drvdata(dev);
841 int err;
842
843 err = reset_control_assert(hub->rst);
844 if (err < 0)
845 return err;
846
847 clk_disable_unprepare(hub->clk_hub);
848 clk_disable_unprepare(hub->clk_dsc);
849 clk_disable_unprepare(hub->clk_disp);
850
851 return 0;
852}
853
854static int __maybe_unused tegra_display_hub_resume(struct device *dev)
855{
856 struct tegra_display_hub *hub = dev_get_drvdata(dev);
857 int err;
858
859 err = clk_prepare_enable(hub->clk_disp);
860 if (err < 0)
861 return err;
862
863 err = clk_prepare_enable(hub->clk_dsc);
864 if (err < 0)
865 goto disable_disp;
866
867 err = clk_prepare_enable(hub->clk_hub);
868 if (err < 0)
869 goto disable_dsc;
870
871 err = reset_control_deassert(hub->rst);
872 if (err < 0)
873 goto disable_hub;
874
875 return 0;
876
877disable_hub:
878 clk_disable_unprepare(hub->clk_hub);
879disable_dsc:
880 clk_disable_unprepare(hub->clk_dsc);
881disable_disp:
882 clk_disable_unprepare(hub->clk_disp);
883 return err;
884}
885
886static const struct dev_pm_ops tegra_display_hub_pm_ops = {
887 SET_RUNTIME_PM_OPS(tegra_display_hub_suspend,
888 tegra_display_hub_resume, NULL)
889};
890
891static const struct tegra_display_hub_soc tegra186_display_hub = {
892 .num_wgrps = 6,
893};
894
895static const struct of_device_id tegra_display_hub_of_match[] = {
896 {
897 .compatible = "nvidia,tegra186-display",
898 .data = &tegra186_display_hub
899 }, {
900
901 }
902};
903MODULE_DEVICE_TABLE(of, tegra_display_hub_of_match);
904
905struct platform_driver tegra_display_hub_driver = {
906 .driver = {
907 .name = "tegra-display-hub",
908 .of_match_table = tegra_display_hub_of_match,
909 .pm = &tegra_display_hub_pm_ops,
910 },
911 .probe = tegra_display_hub_probe,
912 .remove = tegra_display_hub_remove,
913};
914
