LXR linux/drivers/hwmon/jc42.c

   1/*
   2 * jc42.c - driver for Jedec JC42.4 compliant temperature sensors
   3 *
   4 * Copyright (c) 2010  Ericsson AB.
   5 *
   6 * Derived from lm77.c by Andras BALI <drewie@freemail.hu>.
   7 *
   8 * JC42.4 compliant temperature sensors are typically used on memory modules.
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License as published by
  12 * the Free Software Foundation; either version 2 of the License, or
  13 * (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23 */
  24
  25#include <linux/bitops.h>
  26#include <linux/module.h>
  27#include <linux/init.h>
  28#include <linux/slab.h>
  29#include <linux/jiffies.h>
  30#include <linux/i2c.h>
  31#include <linux/hwmon.h>
  32#include <linux/err.h>
  33#include <linux/mutex.h>
  34#include <linux/of.h>
  35
  36/* Addresses to scan */
  37static const unsigned short normal_i2c[] = {
  38        0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
  39
  40/* JC42 registers. All registers are 16 bit. */
  41#define JC42_REG_CAP            0x00
  42#define JC42_REG_CONFIG         0x01
  43#define JC42_REG_TEMP_UPPER     0x02
  44#define JC42_REG_TEMP_LOWER     0x03
  45#define JC42_REG_TEMP_CRITICAL  0x04
  46#define JC42_REG_TEMP           0x05
  47#define JC42_REG_MANID          0x06
  48#define JC42_REG_DEVICEID       0x07
  49#define JC42_REG_SMBUS          0x22 /* NXP and Atmel, possibly others? */
  50
  51/* Status bits in temperature register */
  52#define JC42_ALARM_CRIT_BIT     15
  53#define JC42_ALARM_MAX_BIT      14
  54#define JC42_ALARM_MIN_BIT      13
  55
  56/* Configuration register defines */
  57#define JC42_CFG_CRIT_ONLY      (1 << 2)
  58#define JC42_CFG_TCRIT_LOCK     (1 << 6)
  59#define JC42_CFG_EVENT_LOCK     (1 << 7)
  60#define JC42_CFG_SHUTDOWN       (1 << 8)
  61#define JC42_CFG_HYST_SHIFT     9
  62#define JC42_CFG_HYST_MASK      (0x03 << 9)
  63
  64/* Capabilities */
  65#define JC42_CAP_RANGE          (1 << 2)
  66
  67/* Manufacturer IDs */
  68#define ADT_MANID               0x11d4  /* Analog Devices */
  69#define ATMEL_MANID             0x001f  /* Atmel */
  70#define ATMEL_MANID2            0x1114  /* Atmel */
  71#define MAX_MANID               0x004d  /* Maxim */
  72#define IDT_MANID               0x00b3  /* IDT */
  73#define MCP_MANID               0x0054  /* Microchip */
  74#define NXP_MANID               0x1131  /* NXP Semiconductors */
  75#define ONS_MANID               0x1b09  /* ON Semiconductor */
  76#define STM_MANID               0x104a  /* ST Microelectronics */
  77#define GT_MANID                0x1c68  /* Giantec */
  78#define GT_MANID2               0x132d  /* Giantec, 2nd mfg ID */
  79
  80/* SMBUS register */
  81#define SMBUS_STMOUT            BIT(7)  /* SMBus time-out, active low */
  82
  83/* Supported chips */
  84
  85/* Analog Devices */
  86#define ADT7408_DEVID           0x0801
  87#define ADT7408_DEVID_MASK      0xffff
  88
  89/* Atmel */
  90#define AT30TS00_DEVID          0x8201
  91#define AT30TS00_DEVID_MASK     0xffff
  92
  93#define AT30TSE004_DEVID        0x2200
  94#define AT30TSE004_DEVID_MASK   0xffff
  95
  96/* Giantec */
  97#define GT30TS00_DEVID          0x2200
  98#define GT30TS00_DEVID_MASK     0xff00
  99
 100#define GT34TS02_DEVID          0x3300
 101#define GT34TS02_DEVID_MASK     0xff00
 102
 103/* IDT */
 104#define TSE2004_DEVID           0x2200
 105#define TSE2004_DEVID_MASK      0xff00
 106
 107#define TS3000_DEVID            0x2900  /* Also matches TSE2002 */
 108#define TS3000_DEVID_MASK       0xff00
 109
 110#define TS3001_DEVID            0x3000
 111#define TS3001_DEVID_MASK       0xff00
 112
 113/* Maxim */
 114#define MAX6604_DEVID           0x3e00
 115#define MAX6604_DEVID_MASK      0xffff
 116
 117/* Microchip */
 118#define MCP9804_DEVID           0x0200
 119#define MCP9804_DEVID_MASK      0xfffc
 120
 121#define MCP9808_DEVID           0x0400
 122#define MCP9808_DEVID_MASK      0xfffc
 123
 124#define MCP98242_DEVID          0x2000
 125#define MCP98242_DEVID_MASK     0xfffc
 126
 127#define MCP98243_DEVID          0x2100
 128#define MCP98243_DEVID_MASK     0xfffc
 129
 130#define MCP98244_DEVID          0x2200
 131#define MCP98244_DEVID_MASK     0xfffc
 132
 133#define MCP9843_DEVID           0x0000  /* Also matches mcp9805 */
 134#define MCP9843_DEVID_MASK      0xfffe
 135
 136/* NXP */
 137#define SE97_DEVID              0xa200
 138#define SE97_DEVID_MASK         0xfffc
 139
 140#define SE98_DEVID              0xa100
 141#define SE98_DEVID_MASK         0xfffc
 142
 143/* ON Semiconductor */
 144#define CAT6095_DEVID           0x0800  /* Also matches CAT34TS02 */
 145#define CAT6095_DEVID_MASK      0xffe0
 146
 147#define CAT34TS02C_DEVID        0x0a00
 148#define CAT34TS02C_DEVID_MASK   0xfff0
 149
 150#define CAT34TS04_DEVID         0x2200
 151#define CAT34TS04_DEVID_MASK    0xfff0
 152
 153/* ST Microelectronics */
 154#define STTS424_DEVID           0x0101
 155#define STTS424_DEVID_MASK      0xffff
 156
 157#define STTS424E_DEVID          0x0000
 158#define STTS424E_DEVID_MASK     0xfffe
 159
 160#define STTS2002_DEVID          0x0300
 161#define STTS2002_DEVID_MASK     0xffff
 162
 163#define STTS2004_DEVID          0x2201
 164#define STTS2004_DEVID_MASK     0xffff
 165
 166#define STTS3000_DEVID          0x0200
 167#define STTS3000_DEVID_MASK     0xffff
 168
 169static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
 170
 171struct jc42_chips {
 172        u16 manid;
 173        u16 devid;
 174        u16 devid_mask;
 175};
 176
 177static struct jc42_chips jc42_chips[] = {
 178        { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
 179        { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
 180        { ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK },
 181        { GT_MANID, GT30TS00_DEVID, GT30TS00_DEVID_MASK },
 182        { GT_MANID2, GT34TS02_DEVID, GT34TS02_DEVID_MASK },
 183        { IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
 184        { IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK },
 185        { IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK },
 186        { MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
 187        { MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
 188        { MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK },
 189        { MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
 190        { MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
 191        { MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
 192        { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
 193        { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
 194        { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
 195        { ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK },
 196        { ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK },
 197        { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
 198        { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
 199        { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
 200        { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
 201        { STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
 202        { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
 203};
 204
 205enum temp_index {
 206        t_input = 0,
 207        t_crit,
 208        t_min,
 209        t_max,
 210        t_num_temp
 211};
 212
 213static const u8 temp_regs[t_num_temp] = {
 214        [t_input] = JC42_REG_TEMP,
 215        [t_crit] = JC42_REG_TEMP_CRITICAL,
 216        [t_min] = JC42_REG_TEMP_LOWER,
 217        [t_max] = JC42_REG_TEMP_UPPER,
 218};
 219
 220/* Each client has this additional data */
 221struct jc42_data {
 222        struct i2c_client *client;
 223        struct mutex    update_lock;    /* protect register access */
 224        bool            extended;       /* true if extended range supported */
 225        bool            valid;
 226        unsigned long   last_updated;   /* In jiffies */
 227        u16             orig_config;    /* original configuration */
 228        u16             config;         /* current configuration */
 229        u16             temp[t_num_temp];/* Temperatures */
 230};
 231
 232#define JC42_TEMP_MIN_EXTENDED  (-40000)
 233#define JC42_TEMP_MIN           0
 234#define JC42_TEMP_MAX           125000
 235
 236static u16 jc42_temp_to_reg(long temp, bool extended)
 237{
 238        int ntemp = clamp_val(temp,
 239                              extended ? JC42_TEMP_MIN_EXTENDED :
 240                              JC42_TEMP_MIN, JC42_TEMP_MAX);
 241
 242        /* convert from 0.001 to 0.0625 resolution */
 243        return (ntemp * 2 / 125) & 0x1fff;
 244}
 245
 246static int jc42_temp_from_reg(s16 reg)
 247{
 248        reg = sign_extend32(reg, 12);
 249
 250        /* convert from 0.0625 to 0.001 resolution */
 251        return reg * 125 / 2;
 252}
 253
 254static struct jc42_data *jc42_update_device(struct device *dev)
 255{
 256        struct jc42_data *data = dev_get_drvdata(dev);
 257        struct i2c_client *client = data->client;
 258        struct jc42_data *ret = data;
 259        int i, val;
 260
 261        mutex_lock(&data->update_lock);
 262
 263        if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
 264                for (i = 0; i < t_num_temp; i++) {
 265                        val = i2c_smbus_read_word_swapped(client, temp_regs[i]);
 266                        if (val < 0) {
 267                                ret = ERR_PTR(val);
 268                                goto abort;
 269                        }
 270                        data->temp[i] = val;
 271                }
 272                data->last_updated = jiffies;
 273                data->valid = true;
 274        }
 275abort:
 276        mutex_unlock(&data->update_lock);
 277        return ret;
 278}
 279
 280static int jc42_read(struct device *dev, enum hwmon_sensor_types type,
 281                     u32 attr, int channel, long *val)
 282{
 283        struct jc42_data *data = jc42_update_device(dev);
 284        int temp, hyst;
 285
 286        if (IS_ERR(data))
 287                return PTR_ERR(data);
 288
 289        switch (attr) {
 290        case hwmon_temp_input:
 291                *val = jc42_temp_from_reg(data->temp[t_input]);
 292                return 0;
 293        case hwmon_temp_min:
 294                *val = jc42_temp_from_reg(data->temp[t_min]);
 295                return 0;
 296        case hwmon_temp_max:
 297                *val = jc42_temp_from_reg(data->temp[t_max]);
 298                return 0;
 299        case hwmon_temp_crit:
 300                *val = jc42_temp_from_reg(data->temp[t_crit]);
 301                return 0;
 302        case hwmon_temp_max_hyst:
 303                temp = jc42_temp_from_reg(data->temp[t_max]);
 304                hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
 305                                                >> JC42_CFG_HYST_SHIFT];
 306                *val = temp - hyst;
 307                return 0;
 308        case hwmon_temp_crit_hyst:
 309                temp = jc42_temp_from_reg(data->temp[t_crit]);
 310                hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
 311                                                >> JC42_CFG_HYST_SHIFT];
 312                *val = temp - hyst;
 313                return 0;
 314        case hwmon_temp_min_alarm:
 315                *val = (data->temp[t_input] >> JC42_ALARM_MIN_BIT) & 1;
 316                return 0;
 317        case hwmon_temp_max_alarm:
 318                *val = (data->temp[t_input] >> JC42_ALARM_MAX_BIT) & 1;
 319                return 0;
 320        case hwmon_temp_crit_alarm:
 321                *val = (data->temp[t_input] >> JC42_ALARM_CRIT_BIT) & 1;
 322                return 0;
 323        default:
 324                return -EOPNOTSUPP;
 325        }
 326}
 327
 328static int jc42_write(struct device *dev, enum hwmon_sensor_types type,
 329                      u32 attr, int channel, long val)
 330{
 331        struct jc42_data *data = dev_get_drvdata(dev);
 332        struct i2c_client *client = data->client;
 333        int diff, hyst;
 334        int ret;
 335
 336        mutex_lock(&data->update_lock);
 337
 338        switch (attr) {
 339        case hwmon_temp_min:
 340                data->temp[t_min] = jc42_temp_to_reg(val, data->extended);
 341                ret = i2c_smbus_write_word_swapped(client, temp_regs[t_min],
 342                                                   data->temp[t_min]);
 343                break;
 344        case hwmon_temp_max:
 345                data->temp[t_max] = jc42_temp_to_reg(val, data->extended);
 346                ret = i2c_smbus_write_word_swapped(client, temp_regs[t_max],
 347                                                   data->temp[t_max]);
 348                break;
 349        case hwmon_temp_crit:
 350                data->temp[t_crit] = jc42_temp_to_reg(val, data->extended);
 351                ret = i2c_smbus_write_word_swapped(client, temp_regs[t_crit],
 352                                                   data->temp[t_crit]);
 353                break;
 354        case hwmon_temp_crit_hyst:
 355                /*
 356                 * JC42.4 compliant chips only support four hysteresis values.
 357                 * Pick best choice and go from there.
 358                 */
 359                val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED
 360                                                     : JC42_TEMP_MIN) - 6000,
 361                                JC42_TEMP_MAX);
 362                diff = jc42_temp_from_reg(data->temp[t_crit]) - val;
 363                hyst = 0;
 364                if (diff > 0) {
 365                        if (diff < 2250)
 366                                hyst = 1;       /* 1.5 degrees C */
 367                        else if (diff < 4500)
 368                                hyst = 2;       /* 3.0 degrees C */
 369                        else
 370                                hyst = 3;       /* 6.0 degrees C */
 371                }
 372                data->config = (data->config & ~JC42_CFG_HYST_MASK) |
 373                                (hyst << JC42_CFG_HYST_SHIFT);
 374                ret = i2c_smbus_write_word_swapped(data->client,
 375                                                   JC42_REG_CONFIG,
 376                                                   data->config);
 377                break;
 378        default:
 379                ret = -EOPNOTSUPP;
 380                break;
 381        }
 382
 383        mutex_unlock(&data->update_lock);
 384
 385        return ret;
 386}
 387
 388static umode_t jc42_is_visible(const void *_data, enum hwmon_sensor_types type,
 389                               u32 attr, int channel)
 390{
 391        const struct jc42_data *data = _data;
 392        unsigned int config = data->config;
 393        umode_t mode = S_IRUGO;
 394
 395        switch (attr) {
 396        case hwmon_temp_min:
 397        case hwmon_temp_max:
 398                if (!(config & JC42_CFG_EVENT_LOCK))
 399                        mode |= S_IWUSR;
 400                break;
 401        case hwmon_temp_crit:
 402                if (!(config & JC42_CFG_TCRIT_LOCK))
 403                        mode |= S_IWUSR;
 404                break;
 405        case hwmon_temp_crit_hyst:
 406                if (!(config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK)))
 407                        mode |= S_IWUSR;
 408                break;
 409        case hwmon_temp_input:
 410        case hwmon_temp_max_hyst:
 411        case hwmon_temp_min_alarm:
 412        case hwmon_temp_max_alarm:
 413        case hwmon_temp_crit_alarm:
 414                break;
 415        default:
 416                mode = 0;
 417                break;
 418        }
 419        return mode;
 420}
 421
 422/* Return 0 if detection is successful, -ENODEV otherwise */
 423static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info)
 424{
 425        struct i2c_adapter *adapter = client->adapter;
 426        int i, config, cap, manid, devid;
 427
 428        if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
 429                                     I2C_FUNC_SMBUS_WORD_DATA))
 430                return -ENODEV;
 431
 432        cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
 433        config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
 434        manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID);
 435        devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID);
 436
 437        if (cap < 0 || config < 0 || manid < 0 || devid < 0)
 438                return -ENODEV;
 439
 440        if ((cap & 0xff00) || (config & 0xf800))
 441                return -ENODEV;
 442
 443        for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {
 444                struct jc42_chips *chip = &jc42_chips[i];
 445                if (manid == chip->manid &&
 446                    (devid & chip->devid_mask) == chip->devid) {
 447                        strlcpy(info->type, "jc42", I2C_NAME_SIZE);
 448                        return 0;
 449                }
 450        }
 451        return -ENODEV;
 452}
 453
 454static const u32 jc42_temp_config[] = {
 455        HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | HWMON_T_CRIT |
 456        HWMON_T_MAX_HYST | HWMON_T_CRIT_HYST |
 457        HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM,
 458        0
 459};
 460
 461static const struct hwmon_channel_info jc42_temp = {
 462        .type = hwmon_temp,
 463        .config = jc42_temp_config,
 464};
 465
 466static const struct hwmon_channel_info *jc42_info[] = {
 467        &jc42_temp,
 468        NULL
 469};
 470
 471static const struct hwmon_ops jc42_hwmon_ops = {
 472        .is_visible = jc42_is_visible,
 473        .read = jc42_read,
 474        .write = jc42_write,
 475};
 476
 477static const struct hwmon_chip_info jc42_chip_info = {
 478        .ops = &jc42_hwmon_ops,
 479        .info = jc42_info,
 480};
 481
 482static int jc42_probe(struct i2c_client *client, const struct i2c_device_id *id)
 483{
 484        struct device *dev = &client->dev;
 485        struct device *hwmon_dev;
 486        struct jc42_data *data;
 487        int config, cap;
 488
 489        data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL);
 490        if (!data)
 491                return -ENOMEM;
 492
 493        data->client = client;
 494        i2c_set_clientdata(client, data);
 495        mutex_init(&data->update_lock);
 496
 497        cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
 498        if (cap < 0)
 499                return cap;
 500
 501        data->extended = !!(cap & JC42_CAP_RANGE);
 502
 503        if (device_property_read_bool(dev, "smbus-timeout-disable")) {
 504                int smbus;
 505
 506                /*
 507                 * Not all chips support this register, but from a
 508                 * quick read of various datasheets no chip appears
 509                 * incompatible with the below attempt to disable
 510                 * the timeout. And the whole thing is opt-in...
 511                 */
 512                smbus = i2c_smbus_read_word_swapped(client, JC42_REG_SMBUS);
 513                if (smbus < 0)
 514                        return smbus;
 515                i2c_smbus_write_word_swapped(client, JC42_REG_SMBUS,
 516                                             smbus | SMBUS_STMOUT);
 517        }
 518
 519        config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
 520        if (config < 0)
 521                return config;
 522
 523        data->orig_config = config;
 524        if (config & JC42_CFG_SHUTDOWN) {
 525                config &= ~JC42_CFG_SHUTDOWN;
 526                i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
 527        }
 528        data->config = config;
 529
 530        hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
 531                                                         data, &jc42_chip_info,
 532                                                         NULL);
 533        return PTR_ERR_OR_ZERO(hwmon_dev);
 534}
 535
 536static int jc42_remove(struct i2c_client *client)
 537{
 538        struct jc42_data *data = i2c_get_clientdata(client);
 539
 540        /* Restore original configuration except hysteresis */
 541        if ((data->config & ~JC42_CFG_HYST_MASK) !=
 542            (data->orig_config & ~JC42_CFG_HYST_MASK)) {
 543                int config;
 544
 545                config = (data->orig_config & ~JC42_CFG_HYST_MASK)
 546                  | (data->config & JC42_CFG_HYST_MASK);
 547                i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
 548        }
 549        return 0;
 550}
 551
 552#ifdef CONFIG_PM
 553
 554static int jc42_suspend(struct device *dev)
 555{
 556        struct jc42_data *data = dev_get_drvdata(dev);
 557
 558        data->config |= JC42_CFG_SHUTDOWN;
 559        i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
 560                                     data->config);
 561        return 0;
 562}
 563
 564static int jc42_resume(struct device *dev)
 565{
 566        struct jc42_data *data = dev_get_drvdata(dev);
 567
 568        data->config &= ~JC42_CFG_SHUTDOWN;
 569        i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
 570                                     data->config);
 571        return 0;
 572}
 573
 574static const struct dev_pm_ops jc42_dev_pm_ops = {
 575        .suspend = jc42_suspend,
 576        .resume = jc42_resume,
 577};
 578
 579#define JC42_DEV_PM_OPS (&jc42_dev_pm_ops)
 580#else
 581#define JC42_DEV_PM_OPS NULL
 582#endif /* CONFIG_PM */
 583
 584static const struct i2c_device_id jc42_id[] = {
 585        { "jc42", 0 },
 586        { }
 587};
 588MODULE_DEVICE_TABLE(i2c, jc42_id);
 589
 590#ifdef CONFIG_OF
 591static const struct of_device_id jc42_of_ids[] = {
 592        { .compatible = "jedec,jc-42.4-temp", },
 593        { }
 594};
 595MODULE_DEVICE_TABLE(of, jc42_of_ids);
 596#endif
 597
 598static struct i2c_driver jc42_driver = {
 599        .class          = I2C_CLASS_SPD | I2C_CLASS_HWMON,
 600        .driver = {
 601                .name   = "jc42",
 602                .pm = JC42_DEV_PM_OPS,
 603                .of_match_table = of_match_ptr(jc42_of_ids),
 604        },
 605        .probe          = jc42_probe,
 606        .remove         = jc42_remove,
 607        .id_table       = jc42_id,
 608        .detect         = jc42_detect,
 609        .address_list   = normal_i2c,
 610};
 611
 612module_i2c_driver(jc42_driver);
 613
 614MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
 615MODULE_DESCRIPTION("JC42 driver");
 616MODULE_LICENSE("GPL");
 617