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11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/types.h>
14#include <linux/platform_device.h>
15#include <linux/mfd/dln2.h>
16
17#include <linux/iio/iio.h>
18#include <linux/iio/sysfs.h>
19#include <linux/iio/trigger.h>
20#include <linux/iio/trigger_consumer.h>
21#include <linux/iio/triggered_buffer.h>
22#include <linux/iio/buffer.h>
23#include <linux/iio/kfifo_buf.h>
24
25#define DLN2_ADC_MOD_NAME "dln2-adc"
26
27#define DLN2_ADC_ID 0x06
28
29#define DLN2_ADC_GET_CHANNEL_COUNT DLN2_CMD(0x01, DLN2_ADC_ID)
30#define DLN2_ADC_ENABLE DLN2_CMD(0x02, DLN2_ADC_ID)
31#define DLN2_ADC_DISABLE DLN2_CMD(0x03, DLN2_ADC_ID)
32#define DLN2_ADC_CHANNEL_ENABLE DLN2_CMD(0x05, DLN2_ADC_ID)
33#define DLN2_ADC_CHANNEL_DISABLE DLN2_CMD(0x06, DLN2_ADC_ID)
34#define DLN2_ADC_SET_RESOLUTION DLN2_CMD(0x08, DLN2_ADC_ID)
35#define DLN2_ADC_CHANNEL_GET_VAL DLN2_CMD(0x0A, DLN2_ADC_ID)
36#define DLN2_ADC_CHANNEL_GET_ALL_VAL DLN2_CMD(0x0B, DLN2_ADC_ID)
37#define DLN2_ADC_CHANNEL_SET_CFG DLN2_CMD(0x0C, DLN2_ADC_ID)
38#define DLN2_ADC_CHANNEL_GET_CFG DLN2_CMD(0x0D, DLN2_ADC_ID)
39#define DLN2_ADC_CONDITION_MET_EV DLN2_CMD(0x10, DLN2_ADC_ID)
40
41#define DLN2_ADC_EVENT_NONE 0
42#define DLN2_ADC_EVENT_BELOW 1
43#define DLN2_ADC_EVENT_LEVEL_ABOVE 2
44#define DLN2_ADC_EVENT_OUTSIDE 3
45#define DLN2_ADC_EVENT_INSIDE 4
46#define DLN2_ADC_EVENT_ALWAYS 5
47
48#define DLN2_ADC_MAX_CHANNELS 8
49#define DLN2_ADC_DATA_BITS 10
50
51
52
53
54
55struct dln2_adc_demux_table {
56 unsigned int from;
57 unsigned int to;
58 unsigned int length;
59};
60
61struct dln2_adc {
62 struct platform_device *pdev;
63 struct iio_chan_spec iio_channels[DLN2_ADC_MAX_CHANNELS + 1];
64 int port, trigger_chan;
65 struct iio_trigger *trig;
66 struct mutex mutex;
67
68 unsigned int sample_period;
69
70 unsigned int demux_count;
71 struct dln2_adc_demux_table demux[DLN2_ADC_MAX_CHANNELS];
72
73 unsigned int ts_pad_offset, ts_pad_length;
74};
75
76struct dln2_adc_port_chan {
77 u8 port;
78 u8 chan;
79};
80
81struct dln2_adc_get_all_vals {
82 __le16 channel_mask;
83 __le16 values[DLN2_ADC_MAX_CHANNELS];
84};
85
86static void dln2_adc_add_demux(struct dln2_adc *dln2,
87 unsigned int in_loc, unsigned int out_loc,
88 unsigned int length)
89{
90 struct dln2_adc_demux_table *p = dln2->demux_count ?
91 &dln2->demux[dln2->demux_count - 1] : NULL;
92
93 if (p && p->from + p->length == in_loc &&
94 p->to + p->length == out_loc) {
95 p->length += length;
96 } else if (dln2->demux_count < DLN2_ADC_MAX_CHANNELS) {
97 p = &dln2->demux[dln2->demux_count++];
98 p->from = in_loc;
99 p->to = out_loc;
100 p->length = length;
101 }
102}
103
104static void dln2_adc_update_demux(struct dln2_adc *dln2)
105{
106 int in_ind = -1, out_ind;
107 unsigned int in_loc = 0, out_loc = 0;
108 struct iio_dev *indio_dev = platform_get_drvdata(dln2->pdev);
109
110
111 dln2->demux_count = 0;
112
113
114 if (indio_dev->masklength &&
115 (*indio_dev->active_scan_mask & 0xff) == 0xff) {
116 dln2_adc_add_demux(dln2, 0, 0, 16);
117 dln2->ts_pad_offset = 0;
118 dln2->ts_pad_length = 0;
119 return;
120 }
121
122
123 for_each_set_bit(out_ind,
124 indio_dev->active_scan_mask,
125 indio_dev->masklength) {
126
127 if (out_ind == DLN2_ADC_MAX_CHANNELS)
128 break;
129 for (++in_ind; in_ind != out_ind; ++in_ind)
130 in_loc += 2;
131 dln2_adc_add_demux(dln2, in_loc, out_loc, 2);
132 out_loc += 2;
133 in_loc += 2;
134 }
135
136 if (indio_dev->scan_timestamp) {
137 size_t ts_offset = indio_dev->scan_bytes / sizeof(int64_t) - 1;
138
139 dln2->ts_pad_offset = out_loc;
140 dln2->ts_pad_length = ts_offset * sizeof(int64_t) - out_loc;
141 } else {
142 dln2->ts_pad_offset = 0;
143 dln2->ts_pad_length = 0;
144 }
145}
146
147static int dln2_adc_get_chan_count(struct dln2_adc *dln2)
148{
149 int ret;
150 u8 port = dln2->port;
151 u8 count;
152 int olen = sizeof(count);
153
154 ret = dln2_transfer(dln2->pdev, DLN2_ADC_GET_CHANNEL_COUNT,
155 &port, sizeof(port), &count, &olen);
156 if (ret < 0) {
157 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
158 return ret;
159 }
160 if (olen < sizeof(count))
161 return -EPROTO;
162
163 return count;
164}
165
166static int dln2_adc_set_port_resolution(struct dln2_adc *dln2)
167{
168 int ret;
169 struct dln2_adc_port_chan port_chan = {
170 .port = dln2->port,
171 .chan = DLN2_ADC_DATA_BITS,
172 };
173
174 ret = dln2_transfer_tx(dln2->pdev, DLN2_ADC_SET_RESOLUTION,
175 &port_chan, sizeof(port_chan));
176 if (ret < 0)
177 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
178
179 return ret;
180}
181
182static int dln2_adc_set_chan_enabled(struct dln2_adc *dln2,
183 int channel, bool enable)
184{
185 int ret;
186 struct dln2_adc_port_chan port_chan = {
187 .port = dln2->port,
188 .chan = channel,
189 };
190 u16 cmd = enable ? DLN2_ADC_CHANNEL_ENABLE : DLN2_ADC_CHANNEL_DISABLE;
191
192 ret = dln2_transfer_tx(dln2->pdev, cmd, &port_chan, sizeof(port_chan));
193 if (ret < 0)
194 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
195
196 return ret;
197}
198
199static int dln2_adc_set_port_enabled(struct dln2_adc *dln2, bool enable,
200 u16 *conflict_out)
201{
202 int ret;
203 u8 port = dln2->port;
204 __le16 conflict;
205 int olen = sizeof(conflict);
206 u16 cmd = enable ? DLN2_ADC_ENABLE : DLN2_ADC_DISABLE;
207
208 if (conflict_out)
209 *conflict_out = 0;
210
211 ret = dln2_transfer(dln2->pdev, cmd, &port, sizeof(port),
212 &conflict, &olen);
213 if (ret < 0) {
214 dev_dbg(&dln2->pdev->dev, "Problem in %s(%d)\n",
215 __func__, (int)enable);
216 if (conflict_out && enable && olen >= sizeof(conflict))
217 *conflict_out = le16_to_cpu(conflict);
218 return ret;
219 }
220 if (enable && olen < sizeof(conflict))
221 return -EPROTO;
222
223 return ret;
224}
225
226static int dln2_adc_set_chan_period(struct dln2_adc *dln2,
227 unsigned int channel, unsigned int period)
228{
229 int ret;
230 struct {
231 struct dln2_adc_port_chan port_chan;
232 __u8 type;
233 __le16 period;
234 __le16 low;
235 __le16 high;
236 } __packed set_cfg = {
237 .port_chan.port = dln2->port,
238 .port_chan.chan = channel,
239 .type = period ? DLN2_ADC_EVENT_ALWAYS : DLN2_ADC_EVENT_NONE,
240 .period = cpu_to_le16(period)
241 };
242
243 ret = dln2_transfer_tx(dln2->pdev, DLN2_ADC_CHANNEL_SET_CFG,
244 &set_cfg, sizeof(set_cfg));
245 if (ret < 0)
246 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
247
248 return ret;
249}
250
251static int dln2_adc_read(struct dln2_adc *dln2, unsigned int channel)
252{
253 int ret, i;
254 struct iio_dev *indio_dev = platform_get_drvdata(dln2->pdev);
255 u16 conflict;
256 __le16 value;
257 int olen = sizeof(value);
258 struct dln2_adc_port_chan port_chan = {
259 .port = dln2->port,
260 .chan = channel,
261 };
262
263 ret = iio_device_claim_direct_mode(indio_dev);
264 if (ret < 0)
265 return ret;
266
267 ret = dln2_adc_set_chan_enabled(dln2, channel, true);
268 if (ret < 0)
269 goto release_direct;
270
271 ret = dln2_adc_set_port_enabled(dln2, true, &conflict);
272 if (ret < 0) {
273 if (conflict) {
274 dev_err(&dln2->pdev->dev,
275 "ADC pins conflict with mask %04X\n",
276 (int)conflict);
277 ret = -EBUSY;
278 }
279 goto disable_chan;
280 }
281
282
283
284
285
286 for (i = 0; i < 2; ++i) {
287 ret = dln2_transfer(dln2->pdev, DLN2_ADC_CHANNEL_GET_VAL,
288 &port_chan, sizeof(port_chan),
289 &value, &olen);
290 if (ret < 0) {
291 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
292 goto disable_port;
293 }
294 if (olen < sizeof(value)) {
295 ret = -EPROTO;
296 goto disable_port;
297 }
298 }
299
300 ret = le16_to_cpu(value);
301
302disable_port:
303 dln2_adc_set_port_enabled(dln2, false, NULL);
304disable_chan:
305 dln2_adc_set_chan_enabled(dln2, channel, false);
306release_direct:
307 iio_device_release_direct_mode(indio_dev);
308
309 return ret;
310}
311
312static int dln2_adc_read_all(struct dln2_adc *dln2,
313 struct dln2_adc_get_all_vals *get_all_vals)
314{
315 int ret;
316 __u8 port = dln2->port;
317 int olen = sizeof(*get_all_vals);
318
319 ret = dln2_transfer(dln2->pdev, DLN2_ADC_CHANNEL_GET_ALL_VAL,
320 &port, sizeof(port), get_all_vals, &olen);
321 if (ret < 0) {
322 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
323 return ret;
324 }
325 if (olen < sizeof(*get_all_vals))
326 return -EPROTO;
327
328 return ret;
329}
330
331static int dln2_adc_read_raw(struct iio_dev *indio_dev,
332 struct iio_chan_spec const *chan,
333 int *val,
334 int *val2,
335 long mask)
336{
337 int ret;
338 unsigned int microhertz;
339 struct dln2_adc *dln2 = iio_priv(indio_dev);
340
341 switch (mask) {
342 case IIO_CHAN_INFO_RAW:
343 mutex_lock(&dln2->mutex);
344 ret = dln2_adc_read(dln2, chan->channel);
345 mutex_unlock(&dln2->mutex);
346
347 if (ret < 0)
348 return ret;
349
350 *val = ret;
351 return IIO_VAL_INT;
352
353 case IIO_CHAN_INFO_SCALE:
354
355
356
357
358 *val = 0;
359 *val2 = 3222656;
360 return IIO_VAL_INT_PLUS_NANO;
361
362 case IIO_CHAN_INFO_SAMP_FREQ:
363 if (dln2->sample_period) {
364 microhertz = 1000000000 / dln2->sample_period;
365 *val = microhertz / 1000000;
366 *val2 = microhertz % 1000000;
367 } else {
368 *val = 0;
369 *val2 = 0;
370 }
371
372 return IIO_VAL_INT_PLUS_MICRO;
373
374 default:
375 return -EINVAL;
376 }
377}
378
379static int dln2_adc_write_raw(struct iio_dev *indio_dev,
380 struct iio_chan_spec const *chan,
381 int val,
382 int val2,
383 long mask)
384{
385 int ret;
386 unsigned int microhertz;
387 struct dln2_adc *dln2 = iio_priv(indio_dev);
388
389 switch (mask) {
390 case IIO_CHAN_INFO_SAMP_FREQ:
391 microhertz = 1000000 * val + val2;
392
393 mutex_lock(&dln2->mutex);
394
395 dln2->sample_period =
396 microhertz ? 1000000000 / microhertz : UINT_MAX;
397 if (dln2->sample_period > 65535) {
398 dln2->sample_period = 65535;
399 dev_warn(&dln2->pdev->dev,
400 "clamping period to 65535ms\n");
401 }
402
403
404
405
406
407
408
409
410 if (dln2->trigger_chan != -1)
411 ret = dln2_adc_set_chan_period(dln2,
412 dln2->trigger_chan, dln2->sample_period);
413 else
414 ret = 0;
415
416 mutex_unlock(&dln2->mutex);
417
418 return ret;
419
420 default:
421 return -EINVAL;
422 }
423}
424
425static int dln2_update_scan_mode(struct iio_dev *indio_dev,
426 const unsigned long *scan_mask)
427{
428 struct dln2_adc *dln2 = iio_priv(indio_dev);
429 int chan_count = indio_dev->num_channels - 1;
430 int ret, i, j;
431
432 mutex_lock(&dln2->mutex);
433
434 for (i = 0; i < chan_count; ++i) {
435 ret = dln2_adc_set_chan_enabled(dln2, i,
436 test_bit(i, scan_mask));
437 if (ret < 0) {
438 for (j = 0; j < i; ++j)
439 dln2_adc_set_chan_enabled(dln2, j, false);
440 mutex_unlock(&dln2->mutex);
441 dev_err(&dln2->pdev->dev,
442 "Unable to enable ADC channel %d\n", i);
443 return -EBUSY;
444 }
445 }
446
447 dln2_adc_update_demux(dln2);
448
449 mutex_unlock(&dln2->mutex);
450
451 return 0;
452}
453
454#define DLN2_ADC_CHAN(lval, idx) { \
455 lval.type = IIO_VOLTAGE; \
456 lval.channel = idx; \
457 lval.indexed = 1; \
458 lval.info_mask_separate = BIT(IIO_CHAN_INFO_RAW); \
459 lval.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | \
460 BIT(IIO_CHAN_INFO_SAMP_FREQ); \
461 lval.scan_index = idx; \
462 lval.scan_type.sign = 'u'; \
463 lval.scan_type.realbits = DLN2_ADC_DATA_BITS; \
464 lval.scan_type.storagebits = 16; \
465 lval.scan_type.endianness = IIO_LE; \
466}
467
468
469#define IIO_CHAN_SOFT_TIMESTAMP_ASSIGN(lval, _si) { \
470 lval.type = IIO_TIMESTAMP; \
471 lval.channel = -1; \
472 lval.scan_index = _si; \
473 lval.scan_type.sign = 's'; \
474 lval.scan_type.realbits = 64; \
475 lval.scan_type.storagebits = 64; \
476}
477
478static const struct iio_info dln2_adc_info = {
479 .read_raw = dln2_adc_read_raw,
480 .write_raw = dln2_adc_write_raw,
481 .update_scan_mode = dln2_update_scan_mode,
482};
483
484static irqreturn_t dln2_adc_trigger_h(int irq, void *p)
485{
486 struct iio_poll_func *pf = p;
487 struct iio_dev *indio_dev = pf->indio_dev;
488 struct {
489 __le16 values[DLN2_ADC_MAX_CHANNELS];
490 int64_t timestamp_space;
491 } data;
492 struct dln2_adc_get_all_vals dev_data;
493 struct dln2_adc *dln2 = iio_priv(indio_dev);
494 const struct dln2_adc_demux_table *t;
495 int ret, i;
496
497 mutex_lock(&dln2->mutex);
498 ret = dln2_adc_read_all(dln2, &dev_data);
499 mutex_unlock(&dln2->mutex);
500 if (ret < 0)
501 goto done;
502
503
504 for (i = 0; i < dln2->demux_count; ++i) {
505 t = &dln2->demux[i];
506 memcpy((void *)data.values + t->to,
507 (void *)dev_data.values + t->from, t->length);
508 }
509
510
511 if (dln2->ts_pad_length)
512 memset((void *)data.values + dln2->ts_pad_offset,
513 0, dln2->ts_pad_length);
514
515 iio_push_to_buffers_with_timestamp(indio_dev, &data,
516 iio_get_time_ns(indio_dev));
517
518done:
519 iio_trigger_notify_done(indio_dev->trig);
520 return IRQ_HANDLED;
521}
522
523static int dln2_adc_triggered_buffer_postenable(struct iio_dev *indio_dev)
524{
525 int ret;
526 struct dln2_adc *dln2 = iio_priv(indio_dev);
527 u16 conflict;
528 unsigned int trigger_chan;
529
530 mutex_lock(&dln2->mutex);
531
532
533 ret = dln2_adc_set_port_enabled(dln2, true, &conflict);
534 if (ret < 0) {
535 mutex_unlock(&dln2->mutex);
536 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
537 if (conflict) {
538 dev_err(&dln2->pdev->dev,
539 "ADC pins conflict with mask %04X\n",
540 (int)conflict);
541 ret = -EBUSY;
542 }
543 return ret;
544 }
545
546
547 trigger_chan = find_first_bit(indio_dev->active_scan_mask,
548 indio_dev->masklength);
549 if (trigger_chan < DLN2_ADC_MAX_CHANNELS) {
550 dln2->trigger_chan = trigger_chan;
551 ret = dln2_adc_set_chan_period(dln2, dln2->trigger_chan,
552 dln2->sample_period);
553 mutex_unlock(&dln2->mutex);
554 if (ret < 0) {
555 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
556 return ret;
557 }
558 } else {
559 dln2->trigger_chan = -1;
560 mutex_unlock(&dln2->mutex);
561 }
562
563 return iio_triggered_buffer_postenable(indio_dev);
564}
565
566static int dln2_adc_triggered_buffer_predisable(struct iio_dev *indio_dev)
567{
568 int ret;
569 struct dln2_adc *dln2 = iio_priv(indio_dev);
570
571 mutex_lock(&dln2->mutex);
572
573
574 if (dln2->trigger_chan != -1) {
575 dln2_adc_set_chan_period(dln2, dln2->trigger_chan, 0);
576 dln2->trigger_chan = -1;
577 }
578
579
580 ret = dln2_adc_set_port_enabled(dln2, false, NULL);
581
582 mutex_unlock(&dln2->mutex);
583 if (ret < 0) {
584 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
585 return ret;
586 }
587
588 return iio_triggered_buffer_predisable(indio_dev);
589}
590
591static const struct iio_buffer_setup_ops dln2_adc_buffer_setup_ops = {
592 .postenable = dln2_adc_triggered_buffer_postenable,
593 .predisable = dln2_adc_triggered_buffer_predisable,
594};
595
596static void dln2_adc_event(struct platform_device *pdev, u16 echo,
597 const void *data, int len)
598{
599 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
600 struct dln2_adc *dln2 = iio_priv(indio_dev);
601
602
603 iio_trigger_poll(dln2->trig);
604}
605
606static int dln2_adc_probe(struct platform_device *pdev)
607{
608 struct device *dev = &pdev->dev;
609 struct dln2_adc *dln2;
610 struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev);
611 struct iio_dev *indio_dev;
612 int i, ret, chans;
613
614 indio_dev = devm_iio_device_alloc(dev, sizeof(*dln2));
615 if (!indio_dev) {
616 dev_err(dev, "failed allocating iio device\n");
617 return -ENOMEM;
618 }
619
620 dln2 = iio_priv(indio_dev);
621 dln2->pdev = pdev;
622 dln2->port = pdata->port;
623 dln2->trigger_chan = -1;
624 mutex_init(&dln2->mutex);
625
626 platform_set_drvdata(pdev, indio_dev);
627
628 ret = dln2_adc_set_port_resolution(dln2);
629 if (ret < 0) {
630 dev_err(dev, "failed to set ADC resolution to 10 bits\n");
631 return ret;
632 }
633
634 chans = dln2_adc_get_chan_count(dln2);
635 if (chans < 0) {
636 dev_err(dev, "failed to get channel count: %d\n", chans);
637 return chans;
638 }
639 if (chans > DLN2_ADC_MAX_CHANNELS) {
640 chans = DLN2_ADC_MAX_CHANNELS;
641 dev_warn(dev, "clamping channels to %d\n",
642 DLN2_ADC_MAX_CHANNELS);
643 }
644
645 for (i = 0; i < chans; ++i)
646 DLN2_ADC_CHAN(dln2->iio_channels[i], i)
647 IIO_CHAN_SOFT_TIMESTAMP_ASSIGN(dln2->iio_channels[i], i);
648
649 indio_dev->name = DLN2_ADC_MOD_NAME;
650 indio_dev->dev.parent = dev;
651 indio_dev->info = &dln2_adc_info;
652 indio_dev->modes = INDIO_DIRECT_MODE;
653 indio_dev->channels = dln2->iio_channels;
654 indio_dev->num_channels = chans + 1;
655 indio_dev->setup_ops = &dln2_adc_buffer_setup_ops;
656
657 dln2->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
658 indio_dev->name, indio_dev->id);
659 if (!dln2->trig) {
660 dev_err(dev, "failed to allocate trigger\n");
661 return -ENOMEM;
662 }
663 iio_trigger_set_drvdata(dln2->trig, dln2);
664 devm_iio_trigger_register(dev, dln2->trig);
665 iio_trigger_set_immutable(indio_dev, dln2->trig);
666
667 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
668 dln2_adc_trigger_h,
669 &dln2_adc_buffer_setup_ops);
670 if (ret) {
671 dev_err(dev, "failed to allocate triggered buffer: %d\n", ret);
672 return ret;
673 }
674
675 ret = dln2_register_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV,
676 dln2_adc_event);
677 if (ret) {
678 dev_err(dev, "failed to setup DLN2 periodic event: %d\n", ret);
679 return ret;
680 }
681
682 ret = iio_device_register(indio_dev);
683 if (ret) {
684 dev_err(dev, "failed to register iio device: %d\n", ret);
685 goto unregister_event;
686 }
687
688 return ret;
689
690unregister_event:
691 dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV);
692
693 return ret;
694}
695
696static int dln2_adc_remove(struct platform_device *pdev)
697{
698 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
699
700 iio_device_unregister(indio_dev);
701 dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV);
702 return 0;
703}
704
705static struct platform_driver dln2_adc_driver = {
706 .driver.name = DLN2_ADC_MOD_NAME,
707 .probe = dln2_adc_probe,
708 .remove = dln2_adc_remove,
709};
710
711module_platform_driver(dln2_adc_driver);
712
713MODULE_AUTHOR("Jack Andersen <jackoalan@gmail.com");
714MODULE_DESCRIPTION("Driver for the Diolan DLN2 ADC interface");
715MODULE_LICENSE("GPL v2");
716MODULE_ALIAS("platform:dln2-adc");
717
