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8#include <linux/platform_device.h>
9#include <linux/input.h>
10#include <linux/interrupt.h>
11#include <linux/module.h>
12#include <linux/clk.h>
13#include <linux/io.h>
14#include <linux/slab.h>
15#include <linux/of.h>
16
17
18
19
20#define LPC32XX_TSC_STAT 0x00
21#define LPC32XX_TSC_SEL 0x04
22#define LPC32XX_TSC_CON 0x08
23#define LPC32XX_TSC_FIFO 0x0C
24#define LPC32XX_TSC_DTR 0x10
25#define LPC32XX_TSC_RTR 0x14
26#define LPC32XX_TSC_UTR 0x18
27#define LPC32XX_TSC_TTR 0x1C
28#define LPC32XX_TSC_DXP 0x20
29#define LPC32XX_TSC_MIN_X 0x24
30#define LPC32XX_TSC_MAX_X 0x28
31#define LPC32XX_TSC_MIN_Y 0x2C
32#define LPC32XX_TSC_MAX_Y 0x30
33#define LPC32XX_TSC_AUX_UTR 0x34
34#define LPC32XX_TSC_AUX_MIN 0x38
35#define LPC32XX_TSC_AUX_MAX 0x3C
36
37#define LPC32XX_TSC_STAT_FIFO_OVRRN (1 << 8)
38#define LPC32XX_TSC_STAT_FIFO_EMPTY (1 << 7)
39
40#define LPC32XX_TSC_SEL_DEFVAL 0x0284
41
42#define LPC32XX_TSC_ADCCON_IRQ_TO_FIFO_4 (0x1 << 11)
43#define LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(s) ((10 - (s)) << 7)
44#define LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(s) ((10 - (s)) << 4)
45#define LPC32XX_TSC_ADCCON_POWER_UP (1 << 2)
46#define LPC32XX_TSC_ADCCON_AUTO_EN (1 << 0)
47
48#define LPC32XX_TSC_FIFO_TS_P_LEVEL (1 << 31)
49#define LPC32XX_TSC_FIFO_NORMALIZE_X_VAL(x) (((x) & 0x03FF0000) >> 16)
50#define LPC32XX_TSC_FIFO_NORMALIZE_Y_VAL(y) ((y) & 0x000003FF)
51
52#define LPC32XX_TSC_ADCDAT_VALUE_MASK 0x000003FF
53
54#define LPC32XX_TSC_MIN_XY_VAL 0x0
55#define LPC32XX_TSC_MAX_XY_VAL 0x3FF
56
57#define MOD_NAME "ts-lpc32xx"
58
59#define tsc_readl(dev, reg) \
60 __raw_readl((dev)->tsc_base + (reg))
61#define tsc_writel(dev, reg, val) \
62 __raw_writel((val), (dev)->tsc_base + (reg))
63
64struct lpc32xx_tsc {
65 struct input_dev *dev;
66 void __iomem *tsc_base;
67 int irq;
68 struct clk *clk;
69};
70
71static void lpc32xx_fifo_clear(struct lpc32xx_tsc *tsc)
72{
73 while (!(tsc_readl(tsc, LPC32XX_TSC_STAT) &
74 LPC32XX_TSC_STAT_FIFO_EMPTY))
75 tsc_readl(tsc, LPC32XX_TSC_FIFO);
76}
77
78static irqreturn_t lpc32xx_ts_interrupt(int irq, void *dev_id)
79{
80 u32 tmp, rv[4], xs[4], ys[4];
81 int idx;
82 struct lpc32xx_tsc *tsc = dev_id;
83 struct input_dev *input = tsc->dev;
84
85 tmp = tsc_readl(tsc, LPC32XX_TSC_STAT);
86
87 if (tmp & LPC32XX_TSC_STAT_FIFO_OVRRN) {
88
89 lpc32xx_fifo_clear(tsc);
90 return IRQ_HANDLED;
91 }
92
93
94
95
96
97
98 idx = 0;
99 while (idx < 4 &&
100 !(tsc_readl(tsc, LPC32XX_TSC_STAT) &
101 LPC32XX_TSC_STAT_FIFO_EMPTY)) {
102 tmp = tsc_readl(tsc, LPC32XX_TSC_FIFO);
103 xs[idx] = LPC32XX_TSC_ADCDAT_VALUE_MASK -
104 LPC32XX_TSC_FIFO_NORMALIZE_X_VAL(tmp);
105 ys[idx] = LPC32XX_TSC_ADCDAT_VALUE_MASK -
106 LPC32XX_TSC_FIFO_NORMALIZE_Y_VAL(tmp);
107 rv[idx] = tmp;
108 idx++;
109 }
110
111
112 if (!(rv[3] & LPC32XX_TSC_FIFO_TS_P_LEVEL) && idx == 4) {
113
114 input_report_abs(input, ABS_X, (xs[1] + xs[2]) / 2);
115 input_report_abs(input, ABS_Y, (ys[1] + ys[2]) / 2);
116 input_report_key(input, BTN_TOUCH, 1);
117 } else {
118 input_report_key(input, BTN_TOUCH, 0);
119 }
120
121 input_sync(input);
122
123 return IRQ_HANDLED;
124}
125
126static void lpc32xx_stop_tsc(struct lpc32xx_tsc *tsc)
127{
128
129 tsc_writel(tsc, LPC32XX_TSC_CON,
130 tsc_readl(tsc, LPC32XX_TSC_CON) &
131 ~LPC32XX_TSC_ADCCON_AUTO_EN);
132
133 clk_disable_unprepare(tsc->clk);
134}
135
136static int lpc32xx_setup_tsc(struct lpc32xx_tsc *tsc)
137{
138 u32 tmp;
139 int err;
140
141 err = clk_prepare_enable(tsc->clk);
142 if (err)
143 return err;
144
145 tmp = tsc_readl(tsc, LPC32XX_TSC_CON) & ~LPC32XX_TSC_ADCCON_POWER_UP;
146
147
148 tmp = LPC32XX_TSC_ADCCON_IRQ_TO_FIFO_4 |
149 LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(10) |
150 LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(10);
151 tsc_writel(tsc, LPC32XX_TSC_CON, tmp);
152
153
154 tsc_writel(tsc, LPC32XX_TSC_SEL, LPC32XX_TSC_SEL_DEFVAL);
155 tsc_writel(tsc, LPC32XX_TSC_MIN_X, LPC32XX_TSC_MIN_XY_VAL);
156 tsc_writel(tsc, LPC32XX_TSC_MAX_X, LPC32XX_TSC_MAX_XY_VAL);
157 tsc_writel(tsc, LPC32XX_TSC_MIN_Y, LPC32XX_TSC_MIN_XY_VAL);
158 tsc_writel(tsc, LPC32XX_TSC_MAX_Y, LPC32XX_TSC_MAX_XY_VAL);
159
160
161 tsc_writel(tsc, LPC32XX_TSC_AUX_UTR, 0);
162 tsc_writel(tsc, LPC32XX_TSC_AUX_MIN, 0);
163 tsc_writel(tsc, LPC32XX_TSC_AUX_MAX, 0);
164
165
166
167
168
169
170
171 tsc_writel(tsc, LPC32XX_TSC_RTR, 0x2);
172 tsc_writel(tsc, LPC32XX_TSC_DTR, 0x2);
173 tsc_writel(tsc, LPC32XX_TSC_TTR, 0x10);
174 tsc_writel(tsc, LPC32XX_TSC_DXP, 0x4);
175 tsc_writel(tsc, LPC32XX_TSC_UTR, 88);
176
177 lpc32xx_fifo_clear(tsc);
178
179
180 tsc_writel(tsc, LPC32XX_TSC_CON, tmp | LPC32XX_TSC_ADCCON_AUTO_EN);
181
182 return 0;
183}
184
185static int lpc32xx_ts_open(struct input_dev *dev)
186{
187 struct lpc32xx_tsc *tsc = input_get_drvdata(dev);
188
189 return lpc32xx_setup_tsc(tsc);
190}
191
192static void lpc32xx_ts_close(struct input_dev *dev)
193{
194 struct lpc32xx_tsc *tsc = input_get_drvdata(dev);
195
196 lpc32xx_stop_tsc(tsc);
197}
198
199static int lpc32xx_ts_probe(struct platform_device *pdev)
200{
201 struct lpc32xx_tsc *tsc;
202 struct input_dev *input;
203 struct resource *res;
204 resource_size_t size;
205 int irq;
206 int error;
207
208 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
209 if (!res) {
210 dev_err(&pdev->dev, "Can't get memory resource\n");
211 return -ENOENT;
212 }
213
214 irq = platform_get_irq(pdev, 0);
215 if (irq < 0) {
216 dev_err(&pdev->dev, "Can't get interrupt resource\n");
217 return irq;
218 }
219
220 tsc = kzalloc(sizeof(*tsc), GFP_KERNEL);
221 input = input_allocate_device();
222 if (!tsc || !input) {
223 dev_err(&pdev->dev, "failed allocating memory\n");
224 error = -ENOMEM;
225 goto err_free_mem;
226 }
227
228 tsc->dev = input;
229 tsc->irq = irq;
230
231 size = resource_size(res);
232
233 if (!request_mem_region(res->start, size, pdev->name)) {
234 dev_err(&pdev->dev, "TSC registers are not free\n");
235 error = -EBUSY;
236 goto err_free_mem;
237 }
238
239 tsc->tsc_base = ioremap(res->start, size);
240 if (!tsc->tsc_base) {
241 dev_err(&pdev->dev, "Can't map memory\n");
242 error = -ENOMEM;
243 goto err_release_mem;
244 }
245
246 tsc->clk = clk_get(&pdev->dev, NULL);
247 if (IS_ERR(tsc->clk)) {
248 dev_err(&pdev->dev, "failed getting clock\n");
249 error = PTR_ERR(tsc->clk);
250 goto err_unmap;
251 }
252
253 input->name = MOD_NAME;
254 input->phys = "lpc32xx/input0";
255 input->id.bustype = BUS_HOST;
256 input->id.vendor = 0x0001;
257 input->id.product = 0x0002;
258 input->id.version = 0x0100;
259 input->dev.parent = &pdev->dev;
260 input->open = lpc32xx_ts_open;
261 input->close = lpc32xx_ts_close;
262
263 input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
264 input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
265 input_set_abs_params(input, ABS_X, LPC32XX_TSC_MIN_XY_VAL,
266 LPC32XX_TSC_MAX_XY_VAL, 0, 0);
267 input_set_abs_params(input, ABS_Y, LPC32XX_TSC_MIN_XY_VAL,
268 LPC32XX_TSC_MAX_XY_VAL, 0, 0);
269
270 input_set_drvdata(input, tsc);
271
272 error = request_irq(tsc->irq, lpc32xx_ts_interrupt,
273 0, pdev->name, tsc);
274 if (error) {
275 dev_err(&pdev->dev, "failed requesting interrupt\n");
276 goto err_put_clock;
277 }
278
279 error = input_register_device(input);
280 if (error) {
281 dev_err(&pdev->dev, "failed registering input device\n");
282 goto err_free_irq;
283 }
284
285 platform_set_drvdata(pdev, tsc);
286 device_init_wakeup(&pdev->dev, 1);
287
288 return 0;
289
290err_free_irq:
291 free_irq(tsc->irq, tsc);
292err_put_clock:
293 clk_put(tsc->clk);
294err_unmap:
295 iounmap(tsc->tsc_base);
296err_release_mem:
297 release_mem_region(res->start, size);
298err_free_mem:
299 input_free_device(input);
300 kfree(tsc);
301
302 return error;
303}
304
305static int lpc32xx_ts_remove(struct platform_device *pdev)
306{
307 struct lpc32xx_tsc *tsc = platform_get_drvdata(pdev);
308 struct resource *res;
309
310 free_irq(tsc->irq, tsc);
311
312 input_unregister_device(tsc->dev);
313
314 clk_put(tsc->clk);
315
316 iounmap(tsc->tsc_base);
317 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
318 release_mem_region(res->start, resource_size(res));
319
320 kfree(tsc);
321
322 return 0;
323}
324
325#ifdef CONFIG_PM
326static int lpc32xx_ts_suspend(struct device *dev)
327{
328 struct lpc32xx_tsc *tsc = dev_get_drvdata(dev);
329 struct input_dev *input = tsc->dev;
330
331
332
333
334
335
336
337 mutex_lock(&input->mutex);
338
339 if (input->users) {
340 if (device_may_wakeup(dev))
341 enable_irq_wake(tsc->irq);
342 else
343 lpc32xx_stop_tsc(tsc);
344 }
345
346 mutex_unlock(&input->mutex);
347
348 return 0;
349}
350
351static int lpc32xx_ts_resume(struct device *dev)
352{
353 struct lpc32xx_tsc *tsc = dev_get_drvdata(dev);
354 struct input_dev *input = tsc->dev;
355
356 mutex_lock(&input->mutex);
357
358 if (input->users) {
359 if (device_may_wakeup(dev))
360 disable_irq_wake(tsc->irq);
361 else
362 lpc32xx_setup_tsc(tsc);
363 }
364
365 mutex_unlock(&input->mutex);
366
367 return 0;
368}
369
370static const struct dev_pm_ops lpc32xx_ts_pm_ops = {
371 .suspend = lpc32xx_ts_suspend,
372 .resume = lpc32xx_ts_resume,
373};
374#define LPC32XX_TS_PM_OPS (&lpc32xx_ts_pm_ops)
375#else
376#define LPC32XX_TS_PM_OPS NULL
377#endif
378
379#ifdef CONFIG_OF
380static const struct of_device_id lpc32xx_tsc_of_match[] = {
381 { .compatible = "nxp,lpc3220-tsc", },
382 { },
383};
384MODULE_DEVICE_TABLE(of, lpc32xx_tsc_of_match);
385#endif
386
387static struct platform_driver lpc32xx_ts_driver = {
388 .probe = lpc32xx_ts_probe,
389 .remove = lpc32xx_ts_remove,
390 .driver = {
391 .name = MOD_NAME,
392 .pm = LPC32XX_TS_PM_OPS,
393 .of_match_table = of_match_ptr(lpc32xx_tsc_of_match),
394 },
395};
396module_platform_driver(lpc32xx_ts_driver);
397
398MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com");
399MODULE_DESCRIPTION("LPC32XX TSC Driver");
400MODULE_LICENSE("GPL");
401MODULE_ALIAS("platform:lpc32xx_ts");
402
