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16#define pr_fmt(fmt) "GICv2m: " fmt
17
18#include <linux/acpi.h>
19#include <linux/dma-iommu.h>
20#include <linux/irq.h>
21#include <linux/irqdomain.h>
22#include <linux/kernel.h>
23#include <linux/msi.h>
24#include <linux/of_address.h>
25#include <linux/of_pci.h>
26#include <linux/slab.h>
27#include <linux/spinlock.h>
28#include <linux/irqchip/arm-gic.h>
29
30
31
32
33
34
35
36
37#define V2M_MSI_TYPER 0x008
38#define V2M_MSI_TYPER_BASE_SHIFT 16
39#define V2M_MSI_TYPER_BASE_MASK 0x3FF
40#define V2M_MSI_TYPER_NUM_MASK 0x3FF
41#define V2M_MSI_SETSPI_NS 0x040
42#define V2M_MIN_SPI 32
43#define V2M_MAX_SPI 1019
44#define V2M_MSI_IIDR 0xFCC
45
46#define V2M_MSI_TYPER_BASE_SPI(x) \
47 (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
48
49#define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK)
50
51
52#define XGENE_GICV2M_MSI_IIDR 0x06000170
53
54
55#define BCM_NS2_GICV2M_MSI_IIDR 0x0000013f
56
57
58#define GICV2M_NEEDS_SPI_OFFSET 0x00000001
59#define GICV2M_GRAVITON_ADDRESS_ONLY 0x00000002
60
61static LIST_HEAD(v2m_nodes);
62static DEFINE_SPINLOCK(v2m_lock);
63
64struct v2m_data {
65 struct list_head entry;
66 struct fwnode_handle *fwnode;
67 struct resource res;
68 void __iomem *base;
69 u32 spi_start;
70 u32 nr_spis;
71 u32 spi_offset;
72 unsigned long *bm;
73 u32 flags;
74};
75
76static void gicv2m_mask_msi_irq(struct irq_data *d)
77{
78 pci_msi_mask_irq(d);
79 irq_chip_mask_parent(d);
80}
81
82static void gicv2m_unmask_msi_irq(struct irq_data *d)
83{
84 pci_msi_unmask_irq(d);
85 irq_chip_unmask_parent(d);
86}
87
88static struct irq_chip gicv2m_msi_irq_chip = {
89 .name = "MSI",
90 .irq_mask = gicv2m_mask_msi_irq,
91 .irq_unmask = gicv2m_unmask_msi_irq,
92 .irq_eoi = irq_chip_eoi_parent,
93 .irq_write_msi_msg = pci_msi_domain_write_msg,
94};
95
96static struct msi_domain_info gicv2m_msi_domain_info = {
97 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
98 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
99 .chip = &gicv2m_msi_irq_chip,
100};
101
102static phys_addr_t gicv2m_get_msi_addr(struct v2m_data *v2m, int hwirq)
103{
104 if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)
105 return v2m->res.start | ((hwirq - 32) << 3);
106 else
107 return v2m->res.start + V2M_MSI_SETSPI_NS;
108}
109
110static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
111{
112 struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
113 phys_addr_t addr = gicv2m_get_msi_addr(v2m, data->hwirq);
114
115 msg->address_hi = upper_32_bits(addr);
116 msg->address_lo = lower_32_bits(addr);
117
118 if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)
119 msg->data = 0;
120 else
121 msg->data = data->hwirq;
122 if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
123 msg->data -= v2m->spi_offset;
124
125 iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg);
126}
127
128static struct irq_chip gicv2m_irq_chip = {
129 .name = "GICv2m",
130 .irq_mask = irq_chip_mask_parent,
131 .irq_unmask = irq_chip_unmask_parent,
132 .irq_eoi = irq_chip_eoi_parent,
133 .irq_set_affinity = irq_chip_set_affinity_parent,
134 .irq_compose_msi_msg = gicv2m_compose_msi_msg,
135};
136
137static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
138 unsigned int virq,
139 irq_hw_number_t hwirq)
140{
141 struct irq_fwspec fwspec;
142 struct irq_data *d;
143 int err;
144
145 if (is_of_node(domain->parent->fwnode)) {
146 fwspec.fwnode = domain->parent->fwnode;
147 fwspec.param_count = 3;
148 fwspec.param[0] = 0;
149 fwspec.param[1] = hwirq - 32;
150 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
151 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
152 fwspec.fwnode = domain->parent->fwnode;
153 fwspec.param_count = 2;
154 fwspec.param[0] = hwirq;
155 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
156 } else {
157 return -EINVAL;
158 }
159
160 err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
161 if (err)
162 return err;
163
164
165 d = irq_domain_get_irq_data(domain->parent, virq);
166 d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
167 return 0;
168}
169
170static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq,
171 int nr_irqs)
172{
173 spin_lock(&v2m_lock);
174 bitmap_release_region(v2m->bm, hwirq - v2m->spi_start,
175 get_count_order(nr_irqs));
176 spin_unlock(&v2m_lock);
177}
178
179static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
180 unsigned int nr_irqs, void *args)
181{
182 msi_alloc_info_t *info = args;
183 struct v2m_data *v2m = NULL, *tmp;
184 int hwirq, offset, i, err = 0;
185
186 spin_lock(&v2m_lock);
187 list_for_each_entry(tmp, &v2m_nodes, entry) {
188 offset = bitmap_find_free_region(tmp->bm, tmp->nr_spis,
189 get_count_order(nr_irqs));
190 if (offset >= 0) {
191 v2m = tmp;
192 break;
193 }
194 }
195 spin_unlock(&v2m_lock);
196
197 if (!v2m)
198 return -ENOSPC;
199
200 hwirq = v2m->spi_start + offset;
201
202 err = iommu_dma_prepare_msi(info->desc,
203 gicv2m_get_msi_addr(v2m, hwirq));
204 if (err)
205 return err;
206
207 for (i = 0; i < nr_irqs; i++) {
208 err = gicv2m_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
209 if (err)
210 goto fail;
211
212 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
213 &gicv2m_irq_chip, v2m);
214 }
215
216 return 0;
217
218fail:
219 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
220 gicv2m_unalloc_msi(v2m, hwirq, nr_irqs);
221 return err;
222}
223
224static void gicv2m_irq_domain_free(struct irq_domain *domain,
225 unsigned int virq, unsigned int nr_irqs)
226{
227 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
228 struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
229
230 gicv2m_unalloc_msi(v2m, d->hwirq, nr_irqs);
231 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
232}
233
234static const struct irq_domain_ops gicv2m_domain_ops = {
235 .alloc = gicv2m_irq_domain_alloc,
236 .free = gicv2m_irq_domain_free,
237};
238
239static bool is_msi_spi_valid(u32 base, u32 num)
240{
241 if (base < V2M_MIN_SPI) {
242 pr_err("Invalid MSI base SPI (base:%u)\n", base);
243 return false;
244 }
245
246 if ((num == 0) || (base + num > V2M_MAX_SPI)) {
247 pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
248 num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
249 return false;
250 }
251
252 return true;
253}
254
255static struct irq_chip gicv2m_pmsi_irq_chip = {
256 .name = "pMSI",
257};
258
259static struct msi_domain_ops gicv2m_pmsi_ops = {
260};
261
262static struct msi_domain_info gicv2m_pmsi_domain_info = {
263 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
264 .ops = &gicv2m_pmsi_ops,
265 .chip = &gicv2m_pmsi_irq_chip,
266};
267
268static void gicv2m_teardown(void)
269{
270 struct v2m_data *v2m, *tmp;
271
272 list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
273 list_del(&v2m->entry);
274 kfree(v2m->bm);
275 iounmap(v2m->base);
276 of_node_put(to_of_node(v2m->fwnode));
277 if (is_fwnode_irqchip(v2m->fwnode))
278 irq_domain_free_fwnode(v2m->fwnode);
279 kfree(v2m);
280 }
281}
282
283static int gicv2m_allocate_domains(struct irq_domain *parent)
284{
285 struct irq_domain *inner_domain, *pci_domain, *plat_domain;
286 struct v2m_data *v2m;
287
288 v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
289 if (!v2m)
290 return 0;
291
292 inner_domain = irq_domain_create_tree(v2m->fwnode,
293 &gicv2m_domain_ops, v2m);
294 if (!inner_domain) {
295 pr_err("Failed to create GICv2m domain\n");
296 return -ENOMEM;
297 }
298
299 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
300 inner_domain->parent = parent;
301 pci_domain = pci_msi_create_irq_domain(v2m->fwnode,
302 &gicv2m_msi_domain_info,
303 inner_domain);
304 plat_domain = platform_msi_create_irq_domain(v2m->fwnode,
305 &gicv2m_pmsi_domain_info,
306 inner_domain);
307 if (!pci_domain || !plat_domain) {
308 pr_err("Failed to create MSI domains\n");
309 if (plat_domain)
310 irq_domain_remove(plat_domain);
311 if (pci_domain)
312 irq_domain_remove(pci_domain);
313 irq_domain_remove(inner_domain);
314 return -ENOMEM;
315 }
316
317 return 0;
318}
319
320static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
321 u32 spi_start, u32 nr_spis,
322 struct resource *res, u32 flags)
323{
324 int ret;
325 struct v2m_data *v2m;
326
327 v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
328 if (!v2m) {
329 pr_err("Failed to allocate struct v2m_data.\n");
330 return -ENOMEM;
331 }
332
333 INIT_LIST_HEAD(&v2m->entry);
334 v2m->fwnode = fwnode;
335 v2m->flags = flags;
336
337 memcpy(&v2m->res, res, sizeof(struct resource));
338
339 v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
340 if (!v2m->base) {
341 pr_err("Failed to map GICv2m resource\n");
342 ret = -ENOMEM;
343 goto err_free_v2m;
344 }
345
346 if (spi_start && nr_spis) {
347 v2m->spi_start = spi_start;
348 v2m->nr_spis = nr_spis;
349 } else {
350 u32 typer;
351
352
353 if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) {
354 ret = -EINVAL;
355 goto err_iounmap;
356 }
357 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
358
359 v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
360 v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
361 }
362
363 if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
364 ret = -EINVAL;
365 goto err_iounmap;
366 }
367
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379
380
381 if (!(v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)) {
382 switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) {
383 case XGENE_GICV2M_MSI_IIDR:
384 v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
385 v2m->spi_offset = v2m->spi_start;
386 break;
387 case BCM_NS2_GICV2M_MSI_IIDR:
388 v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
389 v2m->spi_offset = 32;
390 break;
391 }
392 }
393 v2m->bm = kcalloc(BITS_TO_LONGS(v2m->nr_spis), sizeof(long),
394 GFP_KERNEL);
395 if (!v2m->bm) {
396 ret = -ENOMEM;
397 goto err_iounmap;
398 }
399
400 list_add_tail(&v2m->entry, &v2m_nodes);
401
402 pr_info("range%pR, SPI[%d:%d]\n", res,
403 v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1));
404 return 0;
405
406err_iounmap:
407 iounmap(v2m->base);
408err_free_v2m:
409 kfree(v2m);
410 return ret;
411}
412
413static struct of_device_id gicv2m_device_id[] = {
414 { .compatible = "arm,gic-v2m-frame", },
415 {},
416};
417
418static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
419 struct irq_domain *parent)
420{
421 int ret = 0;
422 struct device_node *node = to_of_node(parent_handle);
423 struct device_node *child;
424
425 for (child = of_find_matching_node(node, gicv2m_device_id); child;
426 child = of_find_matching_node(child, gicv2m_device_id)) {
427 u32 spi_start = 0, nr_spis = 0;
428 struct resource res;
429
430 if (!of_find_property(child, "msi-controller", NULL))
431 continue;
432
433 ret = of_address_to_resource(child, 0, &res);
434 if (ret) {
435 pr_err("Failed to allocate v2m resource.\n");
436 break;
437 }
438
439 if (!of_property_read_u32(child, "arm,msi-base-spi",
440 &spi_start) &&
441 !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
442 pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
443 spi_start, nr_spis);
444
445 ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis,
446 &res, 0);
447 if (ret) {
448 of_node_put(child);
449 break;
450 }
451 }
452
453 if (!ret)
454 ret = gicv2m_allocate_domains(parent);
455 if (ret)
456 gicv2m_teardown();
457 return ret;
458}
459
460#ifdef CONFIG_ACPI
461static int acpi_num_msi;
462
463static struct fwnode_handle *gicv2m_get_fwnode(struct device *dev)
464{
465 struct v2m_data *data;
466
467 if (WARN_ON(acpi_num_msi <= 0))
468 return NULL;
469
470
471 data = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
472 if (!data)
473 return NULL;
474
475 return data->fwnode;
476}
477
478static bool acpi_check_amazon_graviton_quirks(void)
479{
480 static struct acpi_table_madt *madt;
481 acpi_status status;
482 bool rc = false;
483
484#define ACPI_AMZN_OEM_ID "AMAZON"
485
486 status = acpi_get_table(ACPI_SIG_MADT, 0,
487 (struct acpi_table_header **)&madt);
488
489 if (ACPI_FAILURE(status) || !madt)
490 return rc;
491 rc = !memcmp(madt->header.oem_id, ACPI_AMZN_OEM_ID, ACPI_OEM_ID_SIZE);
492 acpi_put_table((struct acpi_table_header *)madt);
493
494 return rc;
495}
496
497static int __init
498acpi_parse_madt_msi(union acpi_subtable_headers *header,
499 const unsigned long end)
500{
501 int ret;
502 struct resource res;
503 u32 spi_start = 0, nr_spis = 0;
504 struct acpi_madt_generic_msi_frame *m;
505 struct fwnode_handle *fwnode;
506 u32 flags = 0;
507
508 m = (struct acpi_madt_generic_msi_frame *)header;
509 if (BAD_MADT_ENTRY(m, end))
510 return -EINVAL;
511
512 res.start = m->base_address;
513 res.end = m->base_address + SZ_4K - 1;
514 res.flags = IORESOURCE_MEM;
515
516 if (acpi_check_amazon_graviton_quirks()) {
517 pr_info("applying Amazon Graviton quirk\n");
518 res.end = res.start + SZ_8K - 1;
519 flags |= GICV2M_GRAVITON_ADDRESS_ONLY;
520 gicv2m_msi_domain_info.flags &= ~MSI_FLAG_MULTI_PCI_MSI;
521 }
522
523 if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
524 spi_start = m->spi_base;
525 nr_spis = m->spi_count;
526
527 pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n",
528 spi_start, nr_spis);
529 }
530
531 fwnode = irq_domain_alloc_fwnode((void *)m->base_address);
532 if (!fwnode) {
533 pr_err("Unable to allocate GICv2m domain token\n");
534 return -EINVAL;
535 }
536
537 ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res, flags);
538 if (ret)
539 irq_domain_free_fwnode(fwnode);
540
541 return ret;
542}
543
544static int __init gicv2m_acpi_init(struct irq_domain *parent)
545{
546 int ret;
547
548 if (acpi_num_msi > 0)
549 return 0;
550
551 acpi_num_msi = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_MSI_FRAME,
552 acpi_parse_madt_msi, 0);
553
554 if (acpi_num_msi <= 0)
555 goto err_out;
556
557 ret = gicv2m_allocate_domains(parent);
558 if (ret)
559 goto err_out;
560
561 pci_msi_register_fwnode_provider(&gicv2m_get_fwnode);
562
563 return 0;
564
565err_out:
566 gicv2m_teardown();
567 return -EINVAL;
568}
569#else
570static int __init gicv2m_acpi_init(struct irq_domain *parent)
571{
572 return -EINVAL;
573}
574#endif
575
576int __init gicv2m_init(struct fwnode_handle *parent_handle,
577 struct irq_domain *parent)
578{
579 if (is_of_node(parent_handle))
580 return gicv2m_of_init(parent_handle, parent);
581
582 return gicv2m_acpi_init(parent);
583}
584