1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24#include "cx88.h"
25
26#include <linux/init.h>
27#include <linux/list.h>
28#include <linux/module.h>
29#include <linux/kmod.h>
30#include <linux/kernel.h>
31#include <linux/slab.h>
32#include <linux/interrupt.h>
33#include <linux/dma-mapping.h>
34#include <linux/delay.h>
35#include <linux/kthread.h>
36#include <asm/div64.h>
37
38#include <media/v4l2-common.h>
39#include <media/v4l2-ioctl.h>
40#include <media/v4l2-event.h>
41#include <media/i2c/wm8775.h>
42
43MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards");
44MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
45MODULE_LICENSE("GPL");
46MODULE_VERSION(CX88_VERSION);
47
48
49
50static unsigned int video_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
51static unsigned int vbi_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
52static unsigned int radio_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
53
54module_param_array(video_nr, int, NULL, 0444);
55module_param_array(vbi_nr, int, NULL, 0444);
56module_param_array(radio_nr, int, NULL, 0444);
57
58MODULE_PARM_DESC(video_nr, "video device numbers");
59MODULE_PARM_DESC(vbi_nr, "vbi device numbers");
60MODULE_PARM_DESC(radio_nr, "radio device numbers");
61
62static unsigned int video_debug;
63module_param(video_debug, int, 0644);
64MODULE_PARM_DESC(video_debug, "enable debug messages [video]");
65
66static unsigned int irq_debug;
67module_param(irq_debug, int, 0644);
68MODULE_PARM_DESC(irq_debug, "enable debug messages [IRQ handler]");
69
70#define dprintk(level, fmt, arg...) do { \
71 if (video_debug >= level) \
72 printk(KERN_DEBUG pr_fmt("%s: video:" fmt), \
73 __func__, ##arg); \
74} while (0)
75
76
77
78
79static const struct cx8800_fmt formats[] = {
80 {
81 .name = "8 bpp, gray",
82 .fourcc = V4L2_PIX_FMT_GREY,
83 .cxformat = ColorFormatY8,
84 .depth = 8,
85 .flags = FORMAT_FLAGS_PACKED,
86 }, {
87 .name = "15 bpp RGB, le",
88 .fourcc = V4L2_PIX_FMT_RGB555,
89 .cxformat = ColorFormatRGB15,
90 .depth = 16,
91 .flags = FORMAT_FLAGS_PACKED,
92 }, {
93 .name = "15 bpp RGB, be",
94 .fourcc = V4L2_PIX_FMT_RGB555X,
95 .cxformat = ColorFormatRGB15 | ColorFormatBSWAP,
96 .depth = 16,
97 .flags = FORMAT_FLAGS_PACKED,
98 }, {
99 .name = "16 bpp RGB, le",
100 .fourcc = V4L2_PIX_FMT_RGB565,
101 .cxformat = ColorFormatRGB16,
102 .depth = 16,
103 .flags = FORMAT_FLAGS_PACKED,
104 }, {
105 .name = "16 bpp RGB, be",
106 .fourcc = V4L2_PIX_FMT_RGB565X,
107 .cxformat = ColorFormatRGB16 | ColorFormatBSWAP,
108 .depth = 16,
109 .flags = FORMAT_FLAGS_PACKED,
110 }, {
111 .name = "24 bpp RGB, le",
112 .fourcc = V4L2_PIX_FMT_BGR24,
113 .cxformat = ColorFormatRGB24,
114 .depth = 24,
115 .flags = FORMAT_FLAGS_PACKED,
116 }, {
117 .name = "32 bpp RGB, le",
118 .fourcc = V4L2_PIX_FMT_BGR32,
119 .cxformat = ColorFormatRGB32,
120 .depth = 32,
121 .flags = FORMAT_FLAGS_PACKED,
122 }, {
123 .name = "32 bpp RGB, be",
124 .fourcc = V4L2_PIX_FMT_RGB32,
125 .cxformat = ColorFormatRGB32 | ColorFormatBSWAP |
126 ColorFormatWSWAP,
127 .depth = 32,
128 .flags = FORMAT_FLAGS_PACKED,
129 }, {
130 .name = "4:2:2, packed, YUYV",
131 .fourcc = V4L2_PIX_FMT_YUYV,
132 .cxformat = ColorFormatYUY2,
133 .depth = 16,
134 .flags = FORMAT_FLAGS_PACKED,
135 }, {
136 .name = "4:2:2, packed, UYVY",
137 .fourcc = V4L2_PIX_FMT_UYVY,
138 .cxformat = ColorFormatYUY2 | ColorFormatBSWAP,
139 .depth = 16,
140 .flags = FORMAT_FLAGS_PACKED,
141 },
142};
143
144static const struct cx8800_fmt *format_by_fourcc(unsigned int fourcc)
145{
146 unsigned int i;
147
148 for (i = 0; i < ARRAY_SIZE(formats); i++)
149 if (formats[i].fourcc == fourcc)
150 return formats + i;
151 return NULL;
152}
153
154
155
156struct cx88_ctrl {
157
158 u32 id;
159 s32 minimum;
160 s32 maximum;
161 u32 step;
162 s32 default_value;
163
164
165 u32 off;
166 u32 reg;
167 u32 sreg;
168 u32 mask;
169 u32 shift;
170};
171
172static const struct cx88_ctrl cx8800_vid_ctls[] = {
173
174 {
175 .id = V4L2_CID_BRIGHTNESS,
176 .minimum = 0x00,
177 .maximum = 0xff,
178 .step = 1,
179 .default_value = 0x7f,
180 .off = 128,
181 .reg = MO_CONTR_BRIGHT,
182 .mask = 0x00ff,
183 .shift = 0,
184 }, {
185 .id = V4L2_CID_CONTRAST,
186 .minimum = 0,
187 .maximum = 0xff,
188 .step = 1,
189 .default_value = 0x3f,
190 .off = 0,
191 .reg = MO_CONTR_BRIGHT,
192 .mask = 0xff00,
193 .shift = 8,
194 }, {
195 .id = V4L2_CID_HUE,
196 .minimum = 0,
197 .maximum = 0xff,
198 .step = 1,
199 .default_value = 0x7f,
200 .off = 128,
201 .reg = MO_HUE,
202 .mask = 0x00ff,
203 .shift = 0,
204 }, {
205
206
207
208 .id = V4L2_CID_SATURATION,
209 .minimum = 0,
210 .maximum = 0xff,
211 .step = 1,
212 .default_value = 0x7f,
213 .off = 0,
214 .reg = MO_UV_SATURATION,
215 .mask = 0x00ff,
216 .shift = 0,
217 }, {
218 .id = V4L2_CID_SHARPNESS,
219 .minimum = 0,
220 .maximum = 4,
221 .step = 1,
222 .default_value = 0x0,
223 .off = 0,
224
225
226
227
228 .reg = MO_FILTER_ODD,
229 .mask = 7 << 7,
230 .shift = 7,
231 }, {
232 .id = V4L2_CID_CHROMA_AGC,
233 .minimum = 0,
234 .maximum = 1,
235 .default_value = 0x1,
236 .reg = MO_INPUT_FORMAT,
237 .mask = 1 << 10,
238 .shift = 10,
239 }, {
240 .id = V4L2_CID_COLOR_KILLER,
241 .minimum = 0,
242 .maximum = 1,
243 .default_value = 0x1,
244 .reg = MO_INPUT_FORMAT,
245 .mask = 1 << 9,
246 .shift = 9,
247 }, {
248 .id = V4L2_CID_BAND_STOP_FILTER,
249 .minimum = 0,
250 .maximum = 1,
251 .step = 1,
252 .default_value = 0x0,
253 .off = 0,
254 .reg = MO_HTOTAL,
255 .mask = 3 << 11,
256 .shift = 11,
257 }
258};
259
260static const struct cx88_ctrl cx8800_aud_ctls[] = {
261 {
262
263 .id = V4L2_CID_AUDIO_MUTE,
264 .minimum = 0,
265 .maximum = 1,
266 .default_value = 1,
267 .reg = AUD_VOL_CTL,
268 .sreg = SHADOW_AUD_VOL_CTL,
269 .mask = (1 << 6),
270 .shift = 6,
271 }, {
272 .id = V4L2_CID_AUDIO_VOLUME,
273 .minimum = 0,
274 .maximum = 0x3f,
275 .step = 1,
276 .default_value = 0x3f,
277 .reg = AUD_VOL_CTL,
278 .sreg = SHADOW_AUD_VOL_CTL,
279 .mask = 0x3f,
280 .shift = 0,
281 }, {
282 .id = V4L2_CID_AUDIO_BALANCE,
283 .minimum = 0,
284 .maximum = 0x7f,
285 .step = 1,
286 .default_value = 0x40,
287 .reg = AUD_BAL_CTL,
288 .sreg = SHADOW_AUD_BAL_CTL,
289 .mask = 0x7f,
290 .shift = 0,
291 }
292};
293
294enum {
295 CX8800_VID_CTLS = ARRAY_SIZE(cx8800_vid_ctls),
296 CX8800_AUD_CTLS = ARRAY_SIZE(cx8800_aud_ctls),
297};
298
299
300
301int cx88_video_mux(struct cx88_core *core, unsigned int input)
302{
303
304
305 dprintk(1, "video_mux: %d [vmux=%d,gpio=0x%x,0x%x,0x%x,0x%x]\n",
306 input, INPUT(input).vmux,
307 INPUT(input).gpio0, INPUT(input).gpio1,
308 INPUT(input).gpio2, INPUT(input).gpio3);
309 core->input = input;
310 cx_andor(MO_INPUT_FORMAT, 0x03 << 14, INPUT(input).vmux << 14);
311 cx_write(MO_GP3_IO, INPUT(input).gpio3);
312 cx_write(MO_GP0_IO, INPUT(input).gpio0);
313 cx_write(MO_GP1_IO, INPUT(input).gpio1);
314 cx_write(MO_GP2_IO, INPUT(input).gpio2);
315
316 switch (INPUT(input).type) {
317 case CX88_VMUX_SVIDEO:
318 cx_set(MO_AFECFG_IO, 0x00000001);
319 cx_set(MO_INPUT_FORMAT, 0x00010010);
320 cx_set(MO_FILTER_EVEN, 0x00002020);
321 cx_set(MO_FILTER_ODD, 0x00002020);
322 break;
323 default:
324 cx_clear(MO_AFECFG_IO, 0x00000001);
325 cx_clear(MO_INPUT_FORMAT, 0x00010010);
326 cx_clear(MO_FILTER_EVEN, 0x00002020);
327 cx_clear(MO_FILTER_ODD, 0x00002020);
328 break;
329 }
330
331
332
333
334
335 if (INPUT(input).audioroute) {
336
337
338
339
340
341 if (core->sd_wm8775) {
342 call_all(core, audio, s_routing,
343 INPUT(input).audioroute, 0, 0);
344 }
345
346
347
348
349
350 if (INPUT(input).type != CX88_VMUX_TELEVISION &&
351 INPUT(input).type != CX88_VMUX_CABLE) {
352
353 core->tvaudio = WW_I2SADC;
354 cx88_set_tvaudio(core);
355 } else {
356
357 cx_write(AUD_I2SCNTL, 0x0);
358 cx_clear(AUD_CTL, EN_I2SIN_ENABLE);
359 }
360 }
361
362 return 0;
363}
364EXPORT_SYMBOL(cx88_video_mux);
365
366
367
368static int start_video_dma(struct cx8800_dev *dev,
369 struct cx88_dmaqueue *q,
370 struct cx88_buffer *buf)
371{
372 struct cx88_core *core = dev->core;
373
374
375 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21],
376 buf->bpl, buf->risc.dma);
377 cx88_set_scale(core, core->width, core->height, core->field);
378 cx_write(MO_COLOR_CTRL, dev->fmt->cxformat | ColorFormatGamma);
379
380
381 cx_write(MO_VIDY_GPCNTRL, GP_COUNT_CONTROL_RESET);
382 q->count = 0;
383
384
385 cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT);
386
387
388
389
390
391
392
393
394
395 cx_set(MO_VID_INTMSK, 0x0f0011);
396
397
398 cx_set(VID_CAPTURE_CONTROL, 0x06);
399
400
401 cx_set(MO_DEV_CNTRL2, (1 << 5));
402 cx_set(MO_VID_DMACNTRL, 0x11);
403
404 return 0;
405}
406
407#ifdef CONFIG_PM
408static int stop_video_dma(struct cx8800_dev *dev)
409{
410 struct cx88_core *core = dev->core;
411
412
413 cx_clear(MO_VID_DMACNTRL, 0x11);
414
415
416 cx_clear(VID_CAPTURE_CONTROL, 0x06);
417
418
419 cx_clear(MO_PCI_INTMSK, PCI_INT_VIDINT);
420 cx_clear(MO_VID_INTMSK, 0x0f0011);
421 return 0;
422}
423
424static int restart_video_queue(struct cx8800_dev *dev,
425 struct cx88_dmaqueue *q)
426{
427 struct cx88_buffer *buf;
428
429 if (!list_empty(&q->active)) {
430 buf = list_entry(q->active.next, struct cx88_buffer, list);
431 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
432 buf, buf->vb.vb2_buf.index);
433 start_video_dma(dev, q, buf);
434 }
435 return 0;
436}
437#endif
438
439
440
441static int queue_setup(struct vb2_queue *q,
442 unsigned int *num_buffers, unsigned int *num_planes,
443 unsigned int sizes[], struct device *alloc_devs[])
444{
445 struct cx8800_dev *dev = q->drv_priv;
446 struct cx88_core *core = dev->core;
447
448 *num_planes = 1;
449 sizes[0] = (dev->fmt->depth * core->width * core->height) >> 3;
450 return 0;
451}
452
453static int buffer_prepare(struct vb2_buffer *vb)
454{
455 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
456 struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
457 struct cx88_core *core = dev->core;
458 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
459 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
460
461 buf->bpl = core->width * dev->fmt->depth >> 3;
462
463 if (vb2_plane_size(vb, 0) < core->height * buf->bpl)
464 return -EINVAL;
465 vb2_set_plane_payload(vb, 0, core->height * buf->bpl);
466
467 switch (core->field) {
468 case V4L2_FIELD_TOP:
469 cx88_risc_buffer(dev->pci, &buf->risc,
470 sgt->sgl, 0, UNSET,
471 buf->bpl, 0, core->height);
472 break;
473 case V4L2_FIELD_BOTTOM:
474 cx88_risc_buffer(dev->pci, &buf->risc,
475 sgt->sgl, UNSET, 0,
476 buf->bpl, 0, core->height);
477 break;
478 case V4L2_FIELD_SEQ_TB:
479 cx88_risc_buffer(dev->pci, &buf->risc,
480 sgt->sgl,
481 0, buf->bpl * (core->height >> 1),
482 buf->bpl, 0,
483 core->height >> 1);
484 break;
485 case V4L2_FIELD_SEQ_BT:
486 cx88_risc_buffer(dev->pci, &buf->risc,
487 sgt->sgl,
488 buf->bpl * (core->height >> 1), 0,
489 buf->bpl, 0,
490 core->height >> 1);
491 break;
492 case V4L2_FIELD_INTERLACED:
493 default:
494 cx88_risc_buffer(dev->pci, &buf->risc,
495 sgt->sgl, 0, buf->bpl,
496 buf->bpl, buf->bpl,
497 core->height >> 1);
498 break;
499 }
500 dprintk(2,
501 "[%p/%d] buffer_prepare - %dx%d %dbpp \"%s\" - dma=0x%08lx\n",
502 buf, buf->vb.vb2_buf.index,
503 core->width, core->height, dev->fmt->depth, dev->fmt->name,
504 (unsigned long)buf->risc.dma);
505 return 0;
506}
507
508static void buffer_finish(struct vb2_buffer *vb)
509{
510 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
511 struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
512 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
513 struct cx88_riscmem *risc = &buf->risc;
514
515 if (risc->cpu)
516 pci_free_consistent(dev->pci, risc->size, risc->cpu, risc->dma);
517 memset(risc, 0, sizeof(*risc));
518}
519
520static void buffer_queue(struct vb2_buffer *vb)
521{
522 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
523 struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
524 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
525 struct cx88_buffer *prev;
526 struct cx88_dmaqueue *q = &dev->vidq;
527
528
529 buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 8);
530 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);
531 buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 8);
532
533 if (list_empty(&q->active)) {
534 list_add_tail(&buf->list, &q->active);
535 dprintk(2, "[%p/%d] buffer_queue - first active\n",
536 buf, buf->vb.vb2_buf.index);
537
538 } else {
539 buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);
540 prev = list_entry(q->active.prev, struct cx88_buffer, list);
541 list_add_tail(&buf->list, &q->active);
542 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
543 dprintk(2, "[%p/%d] buffer_queue - append to active\n",
544 buf, buf->vb.vb2_buf.index);
545 }
546}
547
548static int start_streaming(struct vb2_queue *q, unsigned int count)
549{
550 struct cx8800_dev *dev = q->drv_priv;
551 struct cx88_dmaqueue *dmaq = &dev->vidq;
552 struct cx88_buffer *buf = list_entry(dmaq->active.next,
553 struct cx88_buffer, list);
554
555 start_video_dma(dev, dmaq, buf);
556 return 0;
557}
558
559static void stop_streaming(struct vb2_queue *q)
560{
561 struct cx8800_dev *dev = q->drv_priv;
562 struct cx88_core *core = dev->core;
563 struct cx88_dmaqueue *dmaq = &dev->vidq;
564 unsigned long flags;
565
566 cx_clear(MO_VID_DMACNTRL, 0x11);
567 cx_clear(VID_CAPTURE_CONTROL, 0x06);
568 spin_lock_irqsave(&dev->slock, flags);
569 while (!list_empty(&dmaq->active)) {
570 struct cx88_buffer *buf = list_entry(dmaq->active.next,
571 struct cx88_buffer, list);
572
573 list_del(&buf->list);
574 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
575 }
576 spin_unlock_irqrestore(&dev->slock, flags);
577}
578
579static const struct vb2_ops cx8800_video_qops = {
580 .queue_setup = queue_setup,
581 .buf_prepare = buffer_prepare,
582 .buf_finish = buffer_finish,
583 .buf_queue = buffer_queue,
584 .wait_prepare = vb2_ops_wait_prepare,
585 .wait_finish = vb2_ops_wait_finish,
586 .start_streaming = start_streaming,
587 .stop_streaming = stop_streaming,
588};
589
590
591
592static int radio_open(struct file *file)
593{
594 struct cx8800_dev *dev = video_drvdata(file);
595 struct cx88_core *core = dev->core;
596 int ret = v4l2_fh_open(file);
597
598 if (ret)
599 return ret;
600
601 cx_write(MO_GP3_IO, core->board.radio.gpio3);
602 cx_write(MO_GP0_IO, core->board.radio.gpio0);
603 cx_write(MO_GP1_IO, core->board.radio.gpio1);
604 cx_write(MO_GP2_IO, core->board.radio.gpio2);
605 if (core->board.radio.audioroute) {
606 if (core->sd_wm8775) {
607 call_all(core, audio, s_routing,
608 core->board.radio.audioroute, 0, 0);
609 }
610
611 core->tvaudio = WW_I2SADC;
612 cx88_set_tvaudio(core);
613 } else {
614
615 core->tvaudio = WW_FM;
616 cx88_set_tvaudio(core);
617 cx88_set_stereo(core, V4L2_TUNER_MODE_STEREO, 1);
618 }
619 call_all(core, tuner, s_radio);
620 return 0;
621}
622
623
624
625
626static int cx8800_s_vid_ctrl(struct v4l2_ctrl *ctrl)
627{
628 struct cx88_core *core =
629 container_of(ctrl->handler, struct cx88_core, video_hdl);
630 const struct cx88_ctrl *cc = ctrl->priv;
631 u32 value, mask;
632
633 mask = cc->mask;
634 switch (ctrl->id) {
635 case V4L2_CID_SATURATION:
636
637
638 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
639
640 if (core->tvnorm & V4L2_STD_SECAM) {
641
642 value = value << 8 | value;
643 } else {
644
645 value = (value * 0x5a) / 0x7f << 8 | value;
646 }
647 mask = 0xffff;
648 break;
649 case V4L2_CID_SHARPNESS:
650
651 value = (ctrl->val < 1 ? 0 : ((ctrl->val + 3) << 7));
652
653 cx_andor(MO_FILTER_EVEN, mask, value);
654 break;
655 case V4L2_CID_CHROMA_AGC:
656 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
657 break;
658 default:
659 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
660 break;
661 }
662 dprintk(1,
663 "set_control id=0x%X(%s) ctrl=0x%02x, reg=0x%02x val=0x%02x (mask 0x%02x)%s\n",
664 ctrl->id, ctrl->name, ctrl->val, cc->reg, value,
665 mask, cc->sreg ? " [shadowed]" : "");
666 if (cc->sreg)
667 cx_sandor(cc->sreg, cc->reg, mask, value);
668 else
669 cx_andor(cc->reg, mask, value);
670 return 0;
671}
672
673static int cx8800_s_aud_ctrl(struct v4l2_ctrl *ctrl)
674{
675 struct cx88_core *core =
676 container_of(ctrl->handler, struct cx88_core, audio_hdl);
677 const struct cx88_ctrl *cc = ctrl->priv;
678 u32 value, mask;
679
680
681 if (core->sd_wm8775) {
682 switch (ctrl->id) {
683 case V4L2_CID_AUDIO_MUTE:
684 wm8775_s_ctrl(core, ctrl->id, ctrl->val);
685 break;
686 case V4L2_CID_AUDIO_VOLUME:
687 wm8775_s_ctrl(core, ctrl->id, (ctrl->val) ?
688 (0x90 + ctrl->val) << 8 : 0);
689 break;
690 case V4L2_CID_AUDIO_BALANCE:
691 wm8775_s_ctrl(core, ctrl->id, ctrl->val << 9);
692 break;
693 default:
694 break;
695 }
696 }
697
698 mask = cc->mask;
699 switch (ctrl->id) {
700 case V4L2_CID_AUDIO_BALANCE:
701 value = (ctrl->val < 0x40) ?
702 (0x7f - ctrl->val) : (ctrl->val - 0x40);
703 break;
704 case V4L2_CID_AUDIO_VOLUME:
705 value = 0x3f - (ctrl->val & 0x3f);
706 break;
707 default:
708 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
709 break;
710 }
711 dprintk(1,
712 "set_control id=0x%X(%s) ctrl=0x%02x, reg=0x%02x val=0x%02x (mask 0x%02x)%s\n",
713 ctrl->id, ctrl->name, ctrl->val, cc->reg, value,
714 mask, cc->sreg ? " [shadowed]" : "");
715 if (cc->sreg)
716 cx_sandor(cc->sreg, cc->reg, mask, value);
717 else
718 cx_andor(cc->reg, mask, value);
719 return 0;
720}
721
722
723
724
725static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
726 struct v4l2_format *f)
727{
728 struct cx8800_dev *dev = video_drvdata(file);
729 struct cx88_core *core = dev->core;
730
731 f->fmt.pix.width = core->width;
732 f->fmt.pix.height = core->height;
733 f->fmt.pix.field = core->field;
734 f->fmt.pix.pixelformat = dev->fmt->fourcc;
735 f->fmt.pix.bytesperline =
736 (f->fmt.pix.width * dev->fmt->depth) >> 3;
737 f->fmt.pix.sizeimage =
738 f->fmt.pix.height * f->fmt.pix.bytesperline;
739 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
740 return 0;
741}
742
743static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
744 struct v4l2_format *f)
745{
746 struct cx8800_dev *dev = video_drvdata(file);
747 struct cx88_core *core = dev->core;
748 const struct cx8800_fmt *fmt;
749 enum v4l2_field field;
750 unsigned int maxw, maxh;
751
752 fmt = format_by_fourcc(f->fmt.pix.pixelformat);
753 if (!fmt)
754 return -EINVAL;
755
756 maxw = norm_maxw(core->tvnorm);
757 maxh = norm_maxh(core->tvnorm);
758
759 field = f->fmt.pix.field;
760
761 switch (field) {
762 case V4L2_FIELD_TOP:
763 case V4L2_FIELD_BOTTOM:
764 case V4L2_FIELD_INTERLACED:
765 case V4L2_FIELD_SEQ_BT:
766 case V4L2_FIELD_SEQ_TB:
767 break;
768 default:
769 field = (f->fmt.pix.height > maxh / 2)
770 ? V4L2_FIELD_INTERLACED
771 : V4L2_FIELD_BOTTOM;
772 break;
773 }
774 if (V4L2_FIELD_HAS_T_OR_B(field))
775 maxh /= 2;
776
777 v4l_bound_align_image(&f->fmt.pix.width, 48, maxw, 2,
778 &f->fmt.pix.height, 32, maxh, 0, 0);
779 f->fmt.pix.field = field;
780 f->fmt.pix.bytesperline =
781 (f->fmt.pix.width * fmt->depth) >> 3;
782 f->fmt.pix.sizeimage =
783 f->fmt.pix.height * f->fmt.pix.bytesperline;
784 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
785
786 return 0;
787}
788
789static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
790 struct v4l2_format *f)
791{
792 struct cx8800_dev *dev = video_drvdata(file);
793 struct cx88_core *core = dev->core;
794 int err = vidioc_try_fmt_vid_cap(file, priv, f);
795
796 if (err != 0)
797 return err;
798 if (vb2_is_busy(&dev->vb2_vidq) || vb2_is_busy(&dev->vb2_vbiq))
799 return -EBUSY;
800 if (core->dvbdev && vb2_is_busy(&core->dvbdev->vb2_mpegq))
801 return -EBUSY;
802 dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
803 core->width = f->fmt.pix.width;
804 core->height = f->fmt.pix.height;
805 core->field = f->fmt.pix.field;
806 return 0;
807}
808
809int cx88_querycap(struct file *file, struct cx88_core *core,
810 struct v4l2_capability *cap)
811{
812 struct video_device *vdev = video_devdata(file);
813
814 strlcpy(cap->card, core->board.name, sizeof(cap->card));
815 cap->device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
816 if (core->board.tuner_type != UNSET)
817 cap->device_caps |= V4L2_CAP_TUNER;
818 switch (vdev->vfl_type) {
819 case VFL_TYPE_RADIO:
820 cap->device_caps = V4L2_CAP_RADIO | V4L2_CAP_TUNER;
821 break;
822 case VFL_TYPE_GRABBER:
823 cap->device_caps |= V4L2_CAP_VIDEO_CAPTURE;
824 break;
825 case VFL_TYPE_VBI:
826 cap->device_caps |= V4L2_CAP_VBI_CAPTURE;
827 break;
828 default:
829 return -EINVAL;
830 }
831 cap->capabilities = cap->device_caps | V4L2_CAP_VIDEO_CAPTURE |
832 V4L2_CAP_VBI_CAPTURE | V4L2_CAP_DEVICE_CAPS;
833 if (core->board.radio.type == CX88_RADIO)
834 cap->capabilities |= V4L2_CAP_RADIO;
835 return 0;
836}
837EXPORT_SYMBOL(cx88_querycap);
838
839static int vidioc_querycap(struct file *file, void *priv,
840 struct v4l2_capability *cap)
841{
842 struct cx8800_dev *dev = video_drvdata(file);
843 struct cx88_core *core = dev->core;
844
845 strcpy(cap->driver, "cx8800");
846 sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci));
847 return cx88_querycap(file, core, cap);
848}
849
850static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
851 struct v4l2_fmtdesc *f)
852{
853 if (unlikely(f->index >= ARRAY_SIZE(formats)))
854 return -EINVAL;
855
856 strlcpy(f->description, formats[f->index].name, sizeof(f->description));
857 f->pixelformat = formats[f->index].fourcc;
858
859 return 0;
860}
861
862static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *tvnorm)
863{
864 struct cx8800_dev *dev = video_drvdata(file);
865 struct cx88_core *core = dev->core;
866
867 *tvnorm = core->tvnorm;
868 return 0;
869}
870
871static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id tvnorms)
872{
873 struct cx8800_dev *dev = video_drvdata(file);
874 struct cx88_core *core = dev->core;
875
876 return cx88_set_tvnorm(core, tvnorms);
877}
878
879
880int cx88_enum_input(struct cx88_core *core, struct v4l2_input *i)
881{
882 static const char * const iname[] = {
883 [CX88_VMUX_COMPOSITE1] = "Composite1",
884 [CX88_VMUX_COMPOSITE2] = "Composite2",
885 [CX88_VMUX_COMPOSITE3] = "Composite3",
886 [CX88_VMUX_COMPOSITE4] = "Composite4",
887 [CX88_VMUX_SVIDEO] = "S-Video",
888 [CX88_VMUX_TELEVISION] = "Television",
889 [CX88_VMUX_CABLE] = "Cable TV",
890 [CX88_VMUX_DVB] = "DVB",
891 [CX88_VMUX_DEBUG] = "for debug only",
892 };
893 unsigned int n = i->index;
894
895 if (n >= 4)
896 return -EINVAL;
897 if (!INPUT(n).type)
898 return -EINVAL;
899 i->type = V4L2_INPUT_TYPE_CAMERA;
900 strcpy(i->name, iname[INPUT(n).type]);
901 if ((INPUT(n).type == CX88_VMUX_TELEVISION) ||
902 (INPUT(n).type == CX88_VMUX_CABLE))
903 i->type = V4L2_INPUT_TYPE_TUNER;
904
905 i->std = CX88_NORMS;
906 return 0;
907}
908EXPORT_SYMBOL(cx88_enum_input);
909
910static int vidioc_enum_input(struct file *file, void *priv,
911 struct v4l2_input *i)
912{
913 struct cx8800_dev *dev = video_drvdata(file);
914 struct cx88_core *core = dev->core;
915
916 return cx88_enum_input(core, i);
917}
918
919static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
920{
921 struct cx8800_dev *dev = video_drvdata(file);
922 struct cx88_core *core = dev->core;
923
924 *i = core->input;
925 return 0;
926}
927
928static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
929{
930 struct cx8800_dev *dev = video_drvdata(file);
931 struct cx88_core *core = dev->core;
932
933 if (i >= 4)
934 return -EINVAL;
935 if (!INPUT(i).type)
936 return -EINVAL;
937
938 cx88_newstation(core);
939 cx88_video_mux(core, i);
940 return 0;
941}
942
943static int vidioc_g_tuner(struct file *file, void *priv,
944 struct v4l2_tuner *t)
945{
946 struct cx8800_dev *dev = video_drvdata(file);
947 struct cx88_core *core = dev->core;
948 u32 reg;
949
950 if (unlikely(core->board.tuner_type == UNSET))
951 return -EINVAL;
952 if (t->index != 0)
953 return -EINVAL;
954
955 strcpy(t->name, "Television");
956 t->capability = V4L2_TUNER_CAP_NORM;
957 t->rangehigh = 0xffffffffUL;
958 call_all(core, tuner, g_tuner, t);
959
960 cx88_get_stereo(core, t);
961 reg = cx_read(MO_DEVICE_STATUS);
962 t->signal = (reg & (1 << 5)) ? 0xffff : 0x0000;
963 return 0;
964}
965
966static int vidioc_s_tuner(struct file *file, void *priv,
967 const struct v4l2_tuner *t)
968{
969 struct cx8800_dev *dev = video_drvdata(file);
970 struct cx88_core *core = dev->core;
971
972 if (core->board.tuner_type == UNSET)
973 return -EINVAL;
974 if (t->index != 0)
975 return -EINVAL;
976
977 cx88_set_stereo(core, t->audmode, 1);
978 return 0;
979}
980
981static int vidioc_g_frequency(struct file *file, void *priv,
982 struct v4l2_frequency *f)
983{
984 struct cx8800_dev *dev = video_drvdata(file);
985 struct cx88_core *core = dev->core;
986
987 if (unlikely(core->board.tuner_type == UNSET))
988 return -EINVAL;
989 if (f->tuner)
990 return -EINVAL;
991
992 f->frequency = core->freq;
993
994 call_all(core, tuner, g_frequency, f);
995
996 return 0;
997}
998
999int cx88_set_freq(struct cx88_core *core,
1000 const struct v4l2_frequency *f)
1001{
1002 struct v4l2_frequency new_freq = *f;
1003
1004 if (unlikely(core->board.tuner_type == UNSET))
1005 return -EINVAL;
1006 if (unlikely(f->tuner != 0))
1007 return -EINVAL;
1008
1009 cx88_newstation(core);
1010 call_all(core, tuner, s_frequency, f);
1011 call_all(core, tuner, g_frequency, &new_freq);
1012 core->freq = new_freq.frequency;
1013
1014
1015 usleep_range(10000, 20000);
1016 cx88_set_tvaudio(core);
1017
1018 return 0;
1019}
1020EXPORT_SYMBOL(cx88_set_freq);
1021
1022static int vidioc_s_frequency(struct file *file, void *priv,
1023 const struct v4l2_frequency *f)
1024{
1025 struct cx8800_dev *dev = video_drvdata(file);
1026 struct cx88_core *core = dev->core;
1027
1028 return cx88_set_freq(core, f);
1029}
1030
1031#ifdef CONFIG_VIDEO_ADV_DEBUG
1032static int vidioc_g_register(struct file *file, void *fh,
1033 struct v4l2_dbg_register *reg)
1034{
1035 struct cx8800_dev *dev = video_drvdata(file);
1036 struct cx88_core *core = dev->core;
1037
1038
1039 reg->val = cx_read(reg->reg & 0xfffffc);
1040 reg->size = 4;
1041 return 0;
1042}
1043
1044static int vidioc_s_register(struct file *file, void *fh,
1045 const struct v4l2_dbg_register *reg)
1046{
1047 struct cx8800_dev *dev = video_drvdata(file);
1048 struct cx88_core *core = dev->core;
1049
1050 cx_write(reg->reg & 0xfffffc, reg->val);
1051 return 0;
1052}
1053#endif
1054
1055
1056
1057
1058
1059static int radio_g_tuner(struct file *file, void *priv,
1060 struct v4l2_tuner *t)
1061{
1062 struct cx8800_dev *dev = video_drvdata(file);
1063 struct cx88_core *core = dev->core;
1064
1065 if (unlikely(t->index > 0))
1066 return -EINVAL;
1067
1068 strcpy(t->name, "Radio");
1069
1070 call_all(core, tuner, g_tuner, t);
1071 return 0;
1072}
1073
1074static int radio_s_tuner(struct file *file, void *priv,
1075 const struct v4l2_tuner *t)
1076{
1077 struct cx8800_dev *dev = video_drvdata(file);
1078 struct cx88_core *core = dev->core;
1079
1080 if (t->index != 0)
1081 return -EINVAL;
1082
1083 call_all(core, tuner, s_tuner, t);
1084 return 0;
1085}
1086
1087
1088
1089static const char *cx88_vid_irqs[32] = {
1090 "y_risci1", "u_risci1", "v_risci1", "vbi_risc1",
1091 "y_risci2", "u_risci2", "v_risci2", "vbi_risc2",
1092 "y_oflow", "u_oflow", "v_oflow", "vbi_oflow",
1093 "y_sync", "u_sync", "v_sync", "vbi_sync",
1094 "opc_err", "par_err", "rip_err", "pci_abort",
1095};
1096
1097static void cx8800_vid_irq(struct cx8800_dev *dev)
1098{
1099 struct cx88_core *core = dev->core;
1100 u32 status, mask, count;
1101
1102 status = cx_read(MO_VID_INTSTAT);
1103 mask = cx_read(MO_VID_INTMSK);
1104 if (0 == (status & mask))
1105 return;
1106 cx_write(MO_VID_INTSTAT, status);
1107 if (irq_debug || (status & mask & ~0xff))
1108 cx88_print_irqbits("irq vid",
1109 cx88_vid_irqs, ARRAY_SIZE(cx88_vid_irqs),
1110 status, mask);
1111
1112
1113 if (status & (1 << 16)) {
1114 pr_warn("video risc op code error\n");
1115 cx_clear(MO_VID_DMACNTRL, 0x11);
1116 cx_clear(VID_CAPTURE_CONTROL, 0x06);
1117 cx88_sram_channel_dump(core, &cx88_sram_channels[SRAM_CH21]);
1118 }
1119
1120
1121 if (status & 0x01) {
1122 spin_lock(&dev->slock);
1123 count = cx_read(MO_VIDY_GPCNT);
1124 cx88_wakeup(core, &dev->vidq, count);
1125 spin_unlock(&dev->slock);
1126 }
1127
1128
1129 if (status & 0x08) {
1130 spin_lock(&dev->slock);
1131 count = cx_read(MO_VBI_GPCNT);
1132 cx88_wakeup(core, &dev->vbiq, count);
1133 spin_unlock(&dev->slock);
1134 }
1135}
1136
1137static irqreturn_t cx8800_irq(int irq, void *dev_id)
1138{
1139 struct cx8800_dev *dev = dev_id;
1140 struct cx88_core *core = dev->core;
1141 u32 status;
1142 int loop, handled = 0;
1143
1144 for (loop = 0; loop < 10; loop++) {
1145 status = cx_read(MO_PCI_INTSTAT) &
1146 (core->pci_irqmask | PCI_INT_VIDINT);
1147 if (status == 0)
1148 goto out;
1149 cx_write(MO_PCI_INTSTAT, status);
1150 handled = 1;
1151
1152 if (status & core->pci_irqmask)
1153 cx88_core_irq(core, status);
1154 if (status & PCI_INT_VIDINT)
1155 cx8800_vid_irq(dev);
1156 }
1157 if (loop == 10) {
1158 pr_warn("irq loop -- clearing mask\n");
1159 cx_write(MO_PCI_INTMSK, 0);
1160 }
1161
1162 out:
1163 return IRQ_RETVAL(handled);
1164}
1165
1166
1167
1168
1169static const struct v4l2_file_operations video_fops = {
1170 .owner = THIS_MODULE,
1171 .open = v4l2_fh_open,
1172 .release = vb2_fop_release,
1173 .read = vb2_fop_read,
1174 .poll = vb2_fop_poll,
1175 .mmap = vb2_fop_mmap,
1176 .unlocked_ioctl = video_ioctl2,
1177};
1178
1179static const struct v4l2_ioctl_ops video_ioctl_ops = {
1180 .vidioc_querycap = vidioc_querycap,
1181 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
1182 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
1183 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
1184 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
1185 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1186 .vidioc_querybuf = vb2_ioctl_querybuf,
1187 .vidioc_qbuf = vb2_ioctl_qbuf,
1188 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1189 .vidioc_g_std = vidioc_g_std,
1190 .vidioc_s_std = vidioc_s_std,
1191 .vidioc_enum_input = vidioc_enum_input,
1192 .vidioc_g_input = vidioc_g_input,
1193 .vidioc_s_input = vidioc_s_input,
1194 .vidioc_streamon = vb2_ioctl_streamon,
1195 .vidioc_streamoff = vb2_ioctl_streamoff,
1196 .vidioc_g_tuner = vidioc_g_tuner,
1197 .vidioc_s_tuner = vidioc_s_tuner,
1198 .vidioc_g_frequency = vidioc_g_frequency,
1199 .vidioc_s_frequency = vidioc_s_frequency,
1200 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1201 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1202#ifdef CONFIG_VIDEO_ADV_DEBUG
1203 .vidioc_g_register = vidioc_g_register,
1204 .vidioc_s_register = vidioc_s_register,
1205#endif
1206};
1207
1208static const struct video_device cx8800_video_template = {
1209 .name = "cx8800-video",
1210 .fops = &video_fops,
1211 .ioctl_ops = &video_ioctl_ops,
1212 .tvnorms = CX88_NORMS,
1213};
1214
1215static const struct v4l2_ioctl_ops vbi_ioctl_ops = {
1216 .vidioc_querycap = vidioc_querycap,
1217 .vidioc_g_fmt_vbi_cap = cx8800_vbi_fmt,
1218 .vidioc_try_fmt_vbi_cap = cx8800_vbi_fmt,
1219 .vidioc_s_fmt_vbi_cap = cx8800_vbi_fmt,
1220 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1221 .vidioc_querybuf = vb2_ioctl_querybuf,
1222 .vidioc_qbuf = vb2_ioctl_qbuf,
1223 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1224 .vidioc_g_std = vidioc_g_std,
1225 .vidioc_s_std = vidioc_s_std,
1226 .vidioc_enum_input = vidioc_enum_input,
1227 .vidioc_g_input = vidioc_g_input,
1228 .vidioc_s_input = vidioc_s_input,
1229 .vidioc_streamon = vb2_ioctl_streamon,
1230 .vidioc_streamoff = vb2_ioctl_streamoff,
1231 .vidioc_g_tuner = vidioc_g_tuner,
1232 .vidioc_s_tuner = vidioc_s_tuner,
1233 .vidioc_g_frequency = vidioc_g_frequency,
1234 .vidioc_s_frequency = vidioc_s_frequency,
1235#ifdef CONFIG_VIDEO_ADV_DEBUG
1236 .vidioc_g_register = vidioc_g_register,
1237 .vidioc_s_register = vidioc_s_register,
1238#endif
1239};
1240
1241static const struct video_device cx8800_vbi_template = {
1242 .name = "cx8800-vbi",
1243 .fops = &video_fops,
1244 .ioctl_ops = &vbi_ioctl_ops,
1245 .tvnorms = CX88_NORMS,
1246};
1247
1248static const struct v4l2_file_operations radio_fops = {
1249 .owner = THIS_MODULE,
1250 .open = radio_open,
1251 .poll = v4l2_ctrl_poll,
1252 .release = v4l2_fh_release,
1253 .unlocked_ioctl = video_ioctl2,
1254};
1255
1256static const struct v4l2_ioctl_ops radio_ioctl_ops = {
1257 .vidioc_querycap = vidioc_querycap,
1258 .vidioc_g_tuner = radio_g_tuner,
1259 .vidioc_s_tuner = radio_s_tuner,
1260 .vidioc_g_frequency = vidioc_g_frequency,
1261 .vidioc_s_frequency = vidioc_s_frequency,
1262 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1263 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1264#ifdef CONFIG_VIDEO_ADV_DEBUG
1265 .vidioc_g_register = vidioc_g_register,
1266 .vidioc_s_register = vidioc_s_register,
1267#endif
1268};
1269
1270static const struct video_device cx8800_radio_template = {
1271 .name = "cx8800-radio",
1272 .fops = &radio_fops,
1273 .ioctl_ops = &radio_ioctl_ops,
1274};
1275
1276static const struct v4l2_ctrl_ops cx8800_ctrl_vid_ops = {
1277 .s_ctrl = cx8800_s_vid_ctrl,
1278};
1279
1280static const struct v4l2_ctrl_ops cx8800_ctrl_aud_ops = {
1281 .s_ctrl = cx8800_s_aud_ctrl,
1282};
1283
1284
1285
1286static void cx8800_unregister_video(struct cx8800_dev *dev)
1287{
1288 video_unregister_device(&dev->radio_dev);
1289 video_unregister_device(&dev->vbi_dev);
1290 video_unregister_device(&dev->video_dev);
1291}
1292
1293static int cx8800_initdev(struct pci_dev *pci_dev,
1294 const struct pci_device_id *pci_id)
1295{
1296 struct cx8800_dev *dev;
1297 struct cx88_core *core;
1298 struct vb2_queue *q;
1299 int err;
1300 int i;
1301
1302 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1303 if (!dev)
1304 return -ENOMEM;
1305
1306
1307 dev->pci = pci_dev;
1308 if (pci_enable_device(pci_dev)) {
1309 err = -EIO;
1310 goto fail_free;
1311 }
1312 core = cx88_core_get(dev->pci);
1313 if (!core) {
1314 err = -EINVAL;
1315 goto fail_free;
1316 }
1317 dev->core = core;
1318
1319
1320 dev->pci_rev = pci_dev->revision;
1321 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1322 pr_info("found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
1323 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1324 dev->pci_lat,
1325 (unsigned long long)pci_resource_start(pci_dev, 0));
1326
1327 pci_set_master(pci_dev);
1328 err = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
1329 if (err) {
1330 pr_err("Oops: no 32bit PCI DMA ???\n");
1331 goto fail_core;
1332 }
1333
1334
1335 spin_lock_init(&dev->slock);
1336
1337
1338 INIT_LIST_HEAD(&dev->vidq.active);
1339
1340
1341 INIT_LIST_HEAD(&dev->vbiq.active);
1342
1343
1344 err = request_irq(pci_dev->irq, cx8800_irq,
1345 IRQF_SHARED, core->name, dev);
1346 if (err < 0) {
1347 pr_err("can't get IRQ %d\n", pci_dev->irq);
1348 goto fail_core;
1349 }
1350 cx_set(MO_PCI_INTMSK, core->pci_irqmask);
1351
1352 for (i = 0; i < CX8800_AUD_CTLS; i++) {
1353 const struct cx88_ctrl *cc = &cx8800_aud_ctls[i];
1354 struct v4l2_ctrl *vc;
1355
1356 vc = v4l2_ctrl_new_std(&core->audio_hdl, &cx8800_ctrl_aud_ops,
1357 cc->id, cc->minimum, cc->maximum,
1358 cc->step, cc->default_value);
1359 if (!vc) {
1360 err = core->audio_hdl.error;
1361 goto fail_core;
1362 }
1363 vc->priv = (void *)cc;
1364 }
1365
1366 for (i = 0; i < CX8800_VID_CTLS; i++) {
1367 const struct cx88_ctrl *cc = &cx8800_vid_ctls[i];
1368 struct v4l2_ctrl *vc;
1369
1370 vc = v4l2_ctrl_new_std(&core->video_hdl, &cx8800_ctrl_vid_ops,
1371 cc->id, cc->minimum, cc->maximum,
1372 cc->step, cc->default_value);
1373 if (!vc) {
1374 err = core->video_hdl.error;
1375 goto fail_core;
1376 }
1377 vc->priv = (void *)cc;
1378 if (vc->id == V4L2_CID_CHROMA_AGC)
1379 core->chroma_agc = vc;
1380 }
1381 v4l2_ctrl_add_handler(&core->video_hdl, &core->audio_hdl, NULL);
1382
1383
1384
1385 if (core->board.audio_chip == CX88_AUDIO_WM8775) {
1386 struct i2c_board_info wm8775_info = {
1387 .type = "wm8775",
1388 .addr = 0x36 >> 1,
1389 .platform_data = &core->wm8775_data,
1390 };
1391 struct v4l2_subdev *sd;
1392
1393 if (core->boardnr == CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1)
1394 core->wm8775_data.is_nova_s = true;
1395 else
1396 core->wm8775_data.is_nova_s = false;
1397
1398 sd = v4l2_i2c_new_subdev_board(&core->v4l2_dev, &core->i2c_adap,
1399 &wm8775_info, NULL);
1400 if (sd) {
1401 core->sd_wm8775 = sd;
1402 sd->grp_id = WM8775_GID;
1403 }
1404 }
1405
1406 if (core->board.audio_chip == CX88_AUDIO_TVAUDIO) {
1407
1408
1409
1410
1411 v4l2_i2c_new_subdev(&core->v4l2_dev, &core->i2c_adap,
1412 "tvaudio", 0, I2C_ADDRS(0xb0 >> 1));
1413 }
1414
1415 switch (core->boardnr) {
1416 case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
1417 case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD: {
1418 static const struct i2c_board_info rtc_info = {
1419 I2C_BOARD_INFO("isl1208", 0x6f)
1420 };
1421
1422 request_module("rtc-isl1208");
1423 core->i2c_rtc = i2c_new_device(&core->i2c_adap, &rtc_info);
1424 }
1425
1426 case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
1427 request_module("ir-kbd-i2c");
1428 }
1429
1430
1431 pci_set_drvdata(pci_dev, dev);
1432
1433 dev->fmt = format_by_fourcc(V4L2_PIX_FMT_BGR24);
1434
1435
1436 core->v4ldev = dev;
1437
1438
1439 mutex_lock(&core->lock);
1440 cx88_set_tvnorm(core, V4L2_STD_NTSC_M);
1441 v4l2_ctrl_handler_setup(&core->video_hdl);
1442 v4l2_ctrl_handler_setup(&core->audio_hdl);
1443 cx88_video_mux(core, 0);
1444
1445 q = &dev->vb2_vidq;
1446 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1447 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
1448 q->gfp_flags = GFP_DMA32;
1449 q->min_buffers_needed = 2;
1450 q->drv_priv = dev;
1451 q->buf_struct_size = sizeof(struct cx88_buffer);
1452 q->ops = &cx8800_video_qops;
1453 q->mem_ops = &vb2_dma_sg_memops;
1454 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1455 q->lock = &core->lock;
1456 q->dev = &dev->pci->dev;
1457
1458 err = vb2_queue_init(q);
1459 if (err < 0)
1460 goto fail_unreg;
1461
1462 q = &dev->vb2_vbiq;
1463 q->type = V4L2_BUF_TYPE_VBI_CAPTURE;
1464 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
1465 q->gfp_flags = GFP_DMA32;
1466 q->min_buffers_needed = 2;
1467 q->drv_priv = dev;
1468 q->buf_struct_size = sizeof(struct cx88_buffer);
1469 q->ops = &cx8800_vbi_qops;
1470 q->mem_ops = &vb2_dma_sg_memops;
1471 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1472 q->lock = &core->lock;
1473 q->dev = &dev->pci->dev;
1474
1475 err = vb2_queue_init(q);
1476 if (err < 0)
1477 goto fail_unreg;
1478
1479
1480 cx88_vdev_init(core, dev->pci, &dev->video_dev,
1481 &cx8800_video_template, "video");
1482 video_set_drvdata(&dev->video_dev, dev);
1483 dev->video_dev.ctrl_handler = &core->video_hdl;
1484 dev->video_dev.queue = &dev->vb2_vidq;
1485 err = video_register_device(&dev->video_dev, VFL_TYPE_GRABBER,
1486 video_nr[core->nr]);
1487 if (err < 0) {
1488 pr_err("can't register video device\n");
1489 goto fail_unreg;
1490 }
1491 pr_info("registered device %s [v4l2]\n",
1492 video_device_node_name(&dev->video_dev));
1493
1494 cx88_vdev_init(core, dev->pci, &dev->vbi_dev,
1495 &cx8800_vbi_template, "vbi");
1496 video_set_drvdata(&dev->vbi_dev, dev);
1497 dev->vbi_dev.queue = &dev->vb2_vbiq;
1498 err = video_register_device(&dev->vbi_dev, VFL_TYPE_VBI,
1499 vbi_nr[core->nr]);
1500 if (err < 0) {
1501 pr_err("can't register vbi device\n");
1502 goto fail_unreg;
1503 }
1504 pr_info("registered device %s\n",
1505 video_device_node_name(&dev->vbi_dev));
1506
1507 if (core->board.radio.type == CX88_RADIO) {
1508 cx88_vdev_init(core, dev->pci, &dev->radio_dev,
1509 &cx8800_radio_template, "radio");
1510 video_set_drvdata(&dev->radio_dev, dev);
1511 dev->radio_dev.ctrl_handler = &core->audio_hdl;
1512 err = video_register_device(&dev->radio_dev, VFL_TYPE_RADIO,
1513 radio_nr[core->nr]);
1514 if (err < 0) {
1515 pr_err("can't register radio device\n");
1516 goto fail_unreg;
1517 }
1518 pr_info("registered device %s\n",
1519 video_device_node_name(&dev->radio_dev));
1520 }
1521
1522
1523 if (core->board.tuner_type != UNSET) {
1524 core->kthread = kthread_run(cx88_audio_thread,
1525 core, "cx88 tvaudio");
1526 if (IS_ERR(core->kthread)) {
1527 err = PTR_ERR(core->kthread);
1528 pr_err("failed to create cx88 audio thread, err=%d\n",
1529 err);
1530 }
1531 }
1532 mutex_unlock(&core->lock);
1533
1534 return 0;
1535
1536fail_unreg:
1537 cx8800_unregister_video(dev);
1538 free_irq(pci_dev->irq, dev);
1539 mutex_unlock(&core->lock);
1540fail_core:
1541 core->v4ldev = NULL;
1542 cx88_core_put(core, dev->pci);
1543fail_free:
1544 kfree(dev);
1545 return err;
1546}
1547
1548static void cx8800_finidev(struct pci_dev *pci_dev)
1549{
1550 struct cx8800_dev *dev = pci_get_drvdata(pci_dev);
1551 struct cx88_core *core = dev->core;
1552
1553
1554 if (core->kthread) {
1555 kthread_stop(core->kthread);
1556 core->kthread = NULL;
1557 }
1558
1559 if (core->ir)
1560 cx88_ir_stop(core);
1561
1562 cx88_shutdown(core);
1563
1564
1565
1566 free_irq(pci_dev->irq, dev);
1567 cx8800_unregister_video(dev);
1568 pci_disable_device(pci_dev);
1569
1570 core->v4ldev = NULL;
1571
1572
1573 cx88_core_put(core, dev->pci);
1574 kfree(dev);
1575}
1576
1577#ifdef CONFIG_PM
1578static int cx8800_suspend(struct pci_dev *pci_dev, pm_message_t state)
1579{
1580 struct cx8800_dev *dev = pci_get_drvdata(pci_dev);
1581 struct cx88_core *core = dev->core;
1582 unsigned long flags;
1583
1584
1585 spin_lock_irqsave(&dev->slock, flags);
1586 if (!list_empty(&dev->vidq.active)) {
1587 pr_info("suspend video\n");
1588 stop_video_dma(dev);
1589 }
1590 if (!list_empty(&dev->vbiq.active)) {
1591 pr_info("suspend vbi\n");
1592 cx8800_stop_vbi_dma(dev);
1593 }
1594 spin_unlock_irqrestore(&dev->slock, flags);
1595
1596 if (core->ir)
1597 cx88_ir_stop(core);
1598
1599 cx88_shutdown(core);
1600
1601 pci_save_state(pci_dev);
1602 if (pci_set_power_state(pci_dev,
1603 pci_choose_state(pci_dev, state)) != 0) {
1604 pci_disable_device(pci_dev);
1605 dev->state.disabled = 1;
1606 }
1607 return 0;
1608}
1609
1610static int cx8800_resume(struct pci_dev *pci_dev)
1611{
1612 struct cx8800_dev *dev = pci_get_drvdata(pci_dev);
1613 struct cx88_core *core = dev->core;
1614 unsigned long flags;
1615 int err;
1616
1617 if (dev->state.disabled) {
1618 err = pci_enable_device(pci_dev);
1619 if (err) {
1620 pr_err("can't enable device\n");
1621 return err;
1622 }
1623
1624 dev->state.disabled = 0;
1625 }
1626 err = pci_set_power_state(pci_dev, PCI_D0);
1627 if (err) {
1628 pr_err("can't set power state\n");
1629 pci_disable_device(pci_dev);
1630 dev->state.disabled = 1;
1631
1632 return err;
1633 }
1634 pci_restore_state(pci_dev);
1635
1636
1637 cx88_reset(core);
1638 if (core->ir)
1639 cx88_ir_start(core);
1640
1641 cx_set(MO_PCI_INTMSK, core->pci_irqmask);
1642
1643
1644 spin_lock_irqsave(&dev->slock, flags);
1645 if (!list_empty(&dev->vidq.active)) {
1646 pr_info("resume video\n");
1647 restart_video_queue(dev, &dev->vidq);
1648 }
1649 if (!list_empty(&dev->vbiq.active)) {
1650 pr_info("resume vbi\n");
1651 cx8800_restart_vbi_queue(dev, &dev->vbiq);
1652 }
1653 spin_unlock_irqrestore(&dev->slock, flags);
1654
1655 return 0;
1656}
1657#endif
1658
1659
1660
1661static const struct pci_device_id cx8800_pci_tbl[] = {
1662 {
1663 .vendor = 0x14f1,
1664 .device = 0x8800,
1665 .subvendor = PCI_ANY_ID,
1666 .subdevice = PCI_ANY_ID,
1667 }, {
1668
1669 }
1670};
1671MODULE_DEVICE_TABLE(pci, cx8800_pci_tbl);
1672
1673static struct pci_driver cx8800_pci_driver = {
1674 .name = "cx8800",
1675 .id_table = cx8800_pci_tbl,
1676 .probe = cx8800_initdev,
1677 .remove = cx8800_finidev,
1678#ifdef CONFIG_PM
1679 .suspend = cx8800_suspend,
1680 .resume = cx8800_resume,
1681#endif
1682};
1683
1684module_pci_driver(cx8800_pci_driver);
1685
