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18#include <linux/pci.h>
19#include <linux/netdevice.h>
20#include <linux/vmalloc.h>
21#include "liquidio_common.h"
22#include "octeon_droq.h"
23#include "octeon_iq.h"
24#include "response_manager.h"
25#include "octeon_device.h"
26#include "octeon_main.h"
27#include "octeon_network.h"
28#include "cn66xx_regs.h"
29#include "cn66xx_device.h"
30#include "cn23xx_pf_device.h"
31#include "cn23xx_vf_device.h"
32
33
34
35
36static struct octeon_config default_cn66xx_conf = {
37 .card_type = LIO_210SV,
38 .card_name = LIO_210SV_NAME,
39
40
41 .iq = {
42 .max_iqs = CN6XXX_CFG_IO_QUEUES,
43 .pending_list_size =
44 (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
45 .instr_type = OCTEON_64BYTE_INSTR,
46 .db_min = CN6XXX_DB_MIN,
47 .db_timeout = CN6XXX_DB_TIMEOUT,
48 }
49 ,
50
51
52 .oq = {
53 .max_oqs = CN6XXX_CFG_IO_QUEUES,
54 .refill_threshold = CN6XXX_OQ_REFIL_THRESHOLD,
55 .oq_intr_pkt = CN6XXX_OQ_INTR_PKT,
56 .oq_intr_time = CN6XXX_OQ_INTR_TIME,
57 .pkts_per_intr = CN6XXX_OQ_PKTSPER_INTR,
58 }
59 ,
60
61 .num_nic_ports = DEFAULT_NUM_NIC_PORTS_66XX,
62 .num_def_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
63 .num_def_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
64 .def_rx_buf_size = CN6XXX_OQ_BUF_SIZE,
65
66
67 .nic_if_cfg[0] = {
68
69 .max_txqs = MAX_TXQS_PER_INTF,
70
71
72 .num_txqs = DEF_TXQS_PER_INTF,
73
74
75 .max_rxqs = MAX_RXQS_PER_INTF,
76
77
78 .num_rxqs = DEF_RXQS_PER_INTF,
79
80
81 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
82
83
84 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
85
86
87
88
89 .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
90
91 .base_queue = BASE_QUEUE_NOT_REQUESTED,
92
93 .gmx_port_id = 0,
94 },
95
96 .nic_if_cfg[1] = {
97
98 .max_txqs = MAX_TXQS_PER_INTF,
99
100
101 .num_txqs = DEF_TXQS_PER_INTF,
102
103
104 .max_rxqs = MAX_RXQS_PER_INTF,
105
106
107 .num_rxqs = DEF_RXQS_PER_INTF,
108
109
110 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
111
112
113 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
114
115
116
117
118 .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
119
120 .base_queue = BASE_QUEUE_NOT_REQUESTED,
121
122 .gmx_port_id = 1,
123 },
124
125
126 .misc = {
127
128 .oct_link_query_interval = 100,
129
130
131 .host_link_query_interval = 500,
132
133 .enable_sli_oq_bp = 0,
134
135
136 .ctrlq_grp = 1,
137 }
138 ,
139};
140
141
142
143
144
145static struct octeon_config default_cn68xx_conf = {
146 .card_type = LIO_410NV,
147 .card_name = LIO_410NV_NAME,
148
149
150 .iq = {
151 .max_iqs = CN6XXX_CFG_IO_QUEUES,
152 .pending_list_size =
153 (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
154 .instr_type = OCTEON_64BYTE_INSTR,
155 .db_min = CN6XXX_DB_MIN,
156 .db_timeout = CN6XXX_DB_TIMEOUT,
157 }
158 ,
159
160
161 .oq = {
162 .max_oqs = CN6XXX_CFG_IO_QUEUES,
163 .refill_threshold = CN6XXX_OQ_REFIL_THRESHOLD,
164 .oq_intr_pkt = CN6XXX_OQ_INTR_PKT,
165 .oq_intr_time = CN6XXX_OQ_INTR_TIME,
166 .pkts_per_intr = CN6XXX_OQ_PKTSPER_INTR,
167 }
168 ,
169
170 .num_nic_ports = DEFAULT_NUM_NIC_PORTS_68XX,
171 .num_def_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
172 .num_def_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
173 .def_rx_buf_size = CN6XXX_OQ_BUF_SIZE,
174
175 .nic_if_cfg[0] = {
176
177 .max_txqs = MAX_TXQS_PER_INTF,
178
179
180 .num_txqs = DEF_TXQS_PER_INTF,
181
182
183 .max_rxqs = MAX_RXQS_PER_INTF,
184
185
186 .num_rxqs = DEF_RXQS_PER_INTF,
187
188
189 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
190
191
192 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
193
194
195
196
197 .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
198
199 .base_queue = BASE_QUEUE_NOT_REQUESTED,
200
201 .gmx_port_id = 0,
202 },
203
204 .nic_if_cfg[1] = {
205
206 .max_txqs = MAX_TXQS_PER_INTF,
207
208
209 .num_txqs = DEF_TXQS_PER_INTF,
210
211
212 .max_rxqs = MAX_RXQS_PER_INTF,
213
214
215 .num_rxqs = DEF_RXQS_PER_INTF,
216
217
218 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
219
220
221 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
222
223
224
225
226 .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
227
228 .base_queue = BASE_QUEUE_NOT_REQUESTED,
229
230 .gmx_port_id = 1,
231 },
232
233 .nic_if_cfg[2] = {
234
235 .max_txqs = MAX_TXQS_PER_INTF,
236
237
238 .num_txqs = DEF_TXQS_PER_INTF,
239
240
241 .max_rxqs = MAX_RXQS_PER_INTF,
242
243
244 .num_rxqs = DEF_RXQS_PER_INTF,
245
246
247 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
248
249
250 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
251
252
253
254
255 .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
256
257 .base_queue = BASE_QUEUE_NOT_REQUESTED,
258
259 .gmx_port_id = 2,
260 },
261
262 .nic_if_cfg[3] = {
263
264 .max_txqs = MAX_TXQS_PER_INTF,
265
266
267 .num_txqs = DEF_TXQS_PER_INTF,
268
269
270 .max_rxqs = MAX_RXQS_PER_INTF,
271
272
273 .num_rxqs = DEF_RXQS_PER_INTF,
274
275
276 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
277
278
279 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
280
281
282
283
284 .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
285
286 .base_queue = BASE_QUEUE_NOT_REQUESTED,
287
288 .gmx_port_id = 3,
289 },
290
291
292 .misc = {
293
294 .oct_link_query_interval = 100,
295
296
297 .host_link_query_interval = 500,
298
299 .enable_sli_oq_bp = 0,
300
301
302 .ctrlq_grp = 1,
303 }
304 ,
305};
306
307
308
309
310static struct octeon_config default_cn68xx_210nv_conf = {
311 .card_type = LIO_210NV,
312 .card_name = LIO_210NV_NAME,
313
314
315
316 .iq = {
317 .max_iqs = CN6XXX_CFG_IO_QUEUES,
318 .pending_list_size =
319 (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
320 .instr_type = OCTEON_64BYTE_INSTR,
321 .db_min = CN6XXX_DB_MIN,
322 .db_timeout = CN6XXX_DB_TIMEOUT,
323 }
324 ,
325
326
327 .oq = {
328 .max_oqs = CN6XXX_CFG_IO_QUEUES,
329 .refill_threshold = CN6XXX_OQ_REFIL_THRESHOLD,
330 .oq_intr_pkt = CN6XXX_OQ_INTR_PKT,
331 .oq_intr_time = CN6XXX_OQ_INTR_TIME,
332 .pkts_per_intr = CN6XXX_OQ_PKTSPER_INTR,
333 }
334 ,
335
336 .num_nic_ports = DEFAULT_NUM_NIC_PORTS_68XX_210NV,
337 .num_def_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
338 .num_def_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
339 .def_rx_buf_size = CN6XXX_OQ_BUF_SIZE,
340
341 .nic_if_cfg[0] = {
342
343 .max_txqs = MAX_TXQS_PER_INTF,
344
345
346 .num_txqs = DEF_TXQS_PER_INTF,
347
348
349 .max_rxqs = MAX_RXQS_PER_INTF,
350
351
352 .num_rxqs = DEF_RXQS_PER_INTF,
353
354
355 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
356
357
358 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
359
360
361
362
363 .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
364
365 .base_queue = BASE_QUEUE_NOT_REQUESTED,
366
367 .gmx_port_id = 0,
368 },
369
370 .nic_if_cfg[1] = {
371
372 .max_txqs = MAX_TXQS_PER_INTF,
373
374
375 .num_txqs = DEF_TXQS_PER_INTF,
376
377
378 .max_rxqs = MAX_RXQS_PER_INTF,
379
380
381 .num_rxqs = DEF_RXQS_PER_INTF,
382
383
384 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
385
386
387 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
388
389
390
391
392 .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
393
394 .base_queue = BASE_QUEUE_NOT_REQUESTED,
395
396 .gmx_port_id = 1,
397 },
398
399
400 .misc = {
401
402 .oct_link_query_interval = 100,
403
404
405 .host_link_query_interval = 500,
406
407 .enable_sli_oq_bp = 0,
408
409
410 .ctrlq_grp = 1,
411 }
412 ,
413};
414
415static struct octeon_config default_cn23xx_conf = {
416 .card_type = LIO_23XX,
417 .card_name = LIO_23XX_NAME,
418
419 .iq = {
420 .max_iqs = CN23XX_CFG_IO_QUEUES,
421 .pending_list_size = (CN23XX_DEFAULT_IQ_DESCRIPTORS *
422 CN23XX_CFG_IO_QUEUES),
423 .instr_type = OCTEON_64BYTE_INSTR,
424 .db_min = CN23XX_DB_MIN,
425 .db_timeout = CN23XX_DB_TIMEOUT,
426 .iq_intr_pkt = CN23XX_DEF_IQ_INTR_THRESHOLD,
427 },
428
429
430 .oq = {
431 .max_oqs = CN23XX_CFG_IO_QUEUES,
432 .pkts_per_intr = CN23XX_OQ_PKTSPER_INTR,
433 .refill_threshold = CN23XX_OQ_REFIL_THRESHOLD,
434 .oq_intr_pkt = CN23XX_OQ_INTR_PKT,
435 .oq_intr_time = CN23XX_OQ_INTR_TIME,
436 },
437
438 .num_nic_ports = DEFAULT_NUM_NIC_PORTS_23XX,
439 .num_def_rx_descs = CN23XX_DEFAULT_OQ_DESCRIPTORS,
440 .num_def_tx_descs = CN23XX_DEFAULT_IQ_DESCRIPTORS,
441 .def_rx_buf_size = CN23XX_OQ_BUF_SIZE,
442
443
444 .nic_if_cfg[0] = {
445
446 .max_txqs = MAX_TXQS_PER_INTF,
447
448
449 .num_txqs = DEF_TXQS_PER_INTF,
450
451
452 .max_rxqs = MAX_RXQS_PER_INTF,
453
454
455 .num_rxqs = DEF_RXQS_PER_INTF,
456
457
458 .num_rx_descs = CN23XX_DEFAULT_OQ_DESCRIPTORS,
459
460
461 .num_tx_descs = CN23XX_DEFAULT_IQ_DESCRIPTORS,
462
463
464
465
466 .rx_buf_size = CN23XX_OQ_BUF_SIZE,
467
468 .base_queue = BASE_QUEUE_NOT_REQUESTED,
469
470 .gmx_port_id = 0,
471 },
472
473 .nic_if_cfg[1] = {
474
475 .max_txqs = MAX_TXQS_PER_INTF,
476
477
478 .num_txqs = DEF_TXQS_PER_INTF,
479
480
481 .max_rxqs = MAX_RXQS_PER_INTF,
482
483
484 .num_rxqs = DEF_RXQS_PER_INTF,
485
486
487 .num_rx_descs = CN23XX_DEFAULT_OQ_DESCRIPTORS,
488
489
490 .num_tx_descs = CN23XX_DEFAULT_IQ_DESCRIPTORS,
491
492
493
494
495 .rx_buf_size = CN23XX_OQ_BUF_SIZE,
496
497 .base_queue = BASE_QUEUE_NOT_REQUESTED,
498
499 .gmx_port_id = 1,
500 },
501
502 .misc = {
503
504 .oct_link_query_interval = 100,
505
506
507 .host_link_query_interval = 500,
508
509 .enable_sli_oq_bp = 0,
510
511
512 .ctrlq_grp = 1,
513 }
514};
515
516static struct octeon_config_ptr {
517 u32 conf_type;
518} oct_conf_info[MAX_OCTEON_DEVICES] = {
519 {
520 OCTEON_CONFIG_TYPE_DEFAULT,
521 }, {
522 OCTEON_CONFIG_TYPE_DEFAULT,
523 }, {
524 OCTEON_CONFIG_TYPE_DEFAULT,
525 }, {
526 OCTEON_CONFIG_TYPE_DEFAULT,
527 },
528};
529
530static char oct_dev_state_str[OCT_DEV_STATES + 1][32] = {
531 "BEGIN", "PCI-ENABLE-DONE", "PCI-MAP-DONE", "DISPATCH-INIT-DONE",
532 "IQ-INIT-DONE", "SCBUFF-POOL-INIT-DONE", "RESPLIST-INIT-DONE",
533 "DROQ-INIT-DONE", "MBOX-SETUP-DONE", "MSIX-ALLOC-VECTOR-DONE",
534 "INTR-SET-DONE", "IO-QUEUES-INIT-DONE", "CONSOLE-INIT-DONE",
535 "HOST-READY", "CORE-READY", "RUNNING", "IN-RESET",
536 "INVALID"
537};
538
539static char oct_dev_app_str[CVM_DRV_APP_COUNT + 1][32] = {
540 "BASE", "NIC", "UNKNOWN"};
541
542static struct octeon_device *octeon_device[MAX_OCTEON_DEVICES];
543static atomic_t adapter_refcounts[MAX_OCTEON_DEVICES];
544static atomic_t adapter_fw_states[MAX_OCTEON_DEVICES];
545
546static u32 octeon_device_count;
547
548static spinlock_t octeon_devices_lock;
549
550static struct octeon_core_setup core_setup[MAX_OCTEON_DEVICES];
551
552static void oct_set_config_info(int oct_id, int conf_type)
553{
554 if (conf_type < 0 || conf_type > (NUM_OCTEON_CONFS - 1))
555 conf_type = OCTEON_CONFIG_TYPE_DEFAULT;
556 oct_conf_info[oct_id].conf_type = conf_type;
557}
558
559void octeon_init_device_list(int conf_type)
560{
561 int i;
562
563 memset(octeon_device, 0, (sizeof(void *) * MAX_OCTEON_DEVICES));
564 for (i = 0; i < MAX_OCTEON_DEVICES; i++)
565 oct_set_config_info(i, conf_type);
566 spin_lock_init(&octeon_devices_lock);
567}
568
569static void *__retrieve_octeon_config_info(struct octeon_device *oct,
570 u16 card_type)
571{
572 u32 oct_id = oct->octeon_id;
573 void *ret = NULL;
574
575 switch (oct_conf_info[oct_id].conf_type) {
576 case OCTEON_CONFIG_TYPE_DEFAULT:
577 if (oct->chip_id == OCTEON_CN66XX) {
578 ret = &default_cn66xx_conf;
579 } else if ((oct->chip_id == OCTEON_CN68XX) &&
580 (card_type == LIO_210NV)) {
581 ret = &default_cn68xx_210nv_conf;
582 } else if ((oct->chip_id == OCTEON_CN68XX) &&
583 (card_type == LIO_410NV)) {
584 ret = &default_cn68xx_conf;
585 } else if (oct->chip_id == OCTEON_CN23XX_PF_VID) {
586 ret = &default_cn23xx_conf;
587 } else if (oct->chip_id == OCTEON_CN23XX_VF_VID) {
588 ret = &default_cn23xx_conf;
589 }
590 break;
591 default:
592 break;
593 }
594 return ret;
595}
596
597static int __verify_octeon_config_info(struct octeon_device *oct, void *conf)
598{
599 switch (oct->chip_id) {
600 case OCTEON_CN66XX:
601 case OCTEON_CN68XX:
602 return lio_validate_cn6xxx_config_info(oct, conf);
603 case OCTEON_CN23XX_PF_VID:
604 case OCTEON_CN23XX_VF_VID:
605 return 0;
606 default:
607 break;
608 }
609
610 return 1;
611}
612
613void *oct_get_config_info(struct octeon_device *oct, u16 card_type)
614{
615 void *conf = NULL;
616
617 conf = __retrieve_octeon_config_info(oct, card_type);
618 if (!conf)
619 return NULL;
620
621 if (__verify_octeon_config_info(oct, conf)) {
622 dev_err(&oct->pci_dev->dev, "Configuration verification failed\n");
623 return NULL;
624 }
625
626 return conf;
627}
628
629char *lio_get_state_string(atomic_t *state_ptr)
630{
631 s32 istate = (s32)atomic_read(state_ptr);
632
633 if (istate > OCT_DEV_STATES || istate < 0)
634 return oct_dev_state_str[OCT_DEV_STATE_INVALID];
635 return oct_dev_state_str[istate];
636}
637
638static char *get_oct_app_string(u32 app_mode)
639{
640 if (app_mode <= CVM_DRV_APP_END)
641 return oct_dev_app_str[app_mode - CVM_DRV_APP_START];
642 return oct_dev_app_str[CVM_DRV_INVALID_APP - CVM_DRV_APP_START];
643}
644
645void octeon_free_device_mem(struct octeon_device *oct)
646{
647 int i;
648
649 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
650 if (oct->io_qmask.oq & BIT_ULL(i))
651 vfree(oct->droq[i]);
652 }
653
654 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
655 if (oct->io_qmask.iq & BIT_ULL(i))
656 vfree(oct->instr_queue[i]);
657 }
658
659 i = oct->octeon_id;
660 vfree(oct);
661
662 octeon_device[i] = NULL;
663 octeon_device_count--;
664}
665
666static struct octeon_device *octeon_allocate_device_mem(u32 pci_id,
667 u32 priv_size)
668{
669 struct octeon_device *oct;
670 u8 *buf = NULL;
671 u32 octdevsize = 0, configsize = 0, size;
672
673 switch (pci_id) {
674 case OCTEON_CN68XX:
675 case OCTEON_CN66XX:
676 configsize = sizeof(struct octeon_cn6xxx);
677 break;
678
679 case OCTEON_CN23XX_PF_VID:
680 configsize = sizeof(struct octeon_cn23xx_pf);
681 break;
682 case OCTEON_CN23XX_VF_VID:
683 configsize = sizeof(struct octeon_cn23xx_vf);
684 break;
685 default:
686 pr_err("%s: Unknown PCI Device: 0x%x\n",
687 __func__,
688 pci_id);
689 return NULL;
690 }
691
692 if (configsize & 0x7)
693 configsize += (8 - (configsize & 0x7));
694
695 octdevsize = sizeof(struct octeon_device);
696 if (octdevsize & 0x7)
697 octdevsize += (8 - (octdevsize & 0x7));
698
699 if (priv_size & 0x7)
700 priv_size += (8 - (priv_size & 0x7));
701
702 size = octdevsize + priv_size + configsize +
703 (sizeof(struct octeon_dispatch) * DISPATCH_LIST_SIZE);
704
705 buf = vzalloc(size);
706 if (!buf)
707 return NULL;
708
709 oct = (struct octeon_device *)buf;
710 oct->priv = (void *)(buf + octdevsize);
711 oct->chip = (void *)(buf + octdevsize + priv_size);
712 oct->dispatch.dlist = (struct octeon_dispatch *)
713 (buf + octdevsize + priv_size + configsize);
714
715 return oct;
716}
717
718struct octeon_device *octeon_allocate_device(u32 pci_id,
719 u32 priv_size)
720{
721 u32 oct_idx = 0;
722 struct octeon_device *oct = NULL;
723
724 spin_lock(&octeon_devices_lock);
725
726 for (oct_idx = 0; oct_idx < MAX_OCTEON_DEVICES; oct_idx++)
727 if (!octeon_device[oct_idx])
728 break;
729
730 if (oct_idx < MAX_OCTEON_DEVICES) {
731 oct = octeon_allocate_device_mem(pci_id, priv_size);
732 if (oct) {
733 octeon_device_count++;
734 octeon_device[oct_idx] = oct;
735 }
736 }
737
738 spin_unlock(&octeon_devices_lock);
739 if (!oct)
740 return NULL;
741
742 spin_lock_init(&oct->pci_win_lock);
743 spin_lock_init(&oct->mem_access_lock);
744
745 oct->octeon_id = oct_idx;
746 snprintf(oct->device_name, sizeof(oct->device_name),
747 "LiquidIO%d", (oct->octeon_id));
748
749 return oct;
750}
751
752
753
754
755
756
757
758
759
760int octeon_register_device(struct octeon_device *oct,
761 int bus, int dev, int func, int is_pf)
762{
763 int idx, refcount;
764
765 oct->loc.bus = bus;
766 oct->loc.dev = dev;
767 oct->loc.func = func;
768
769 oct->adapter_refcount = &adapter_refcounts[oct->octeon_id];
770 atomic_set(oct->adapter_refcount, 0);
771
772
773 oct->adapter_fw_state = &adapter_fw_states[oct->octeon_id];
774 atomic_set(oct->adapter_fw_state, FW_NEEDS_TO_BE_LOADED);
775
776 spin_lock(&octeon_devices_lock);
777 for (idx = (int)oct->octeon_id - 1; idx >= 0; idx--) {
778 if (!octeon_device[idx]) {
779 dev_err(&oct->pci_dev->dev,
780 "%s: Internal driver error, missing dev",
781 __func__);
782 spin_unlock(&octeon_devices_lock);
783 atomic_inc(oct->adapter_refcount);
784 return 1;
785 }
786
787
788
789 if ((octeon_device[idx]->loc.bus == bus) &&
790 (octeon_device[idx]->loc.dev == dev)) {
791 oct->adapter_refcount =
792 octeon_device[idx]->adapter_refcount;
793 oct->adapter_fw_state =
794 octeon_device[idx]->adapter_fw_state;
795 break;
796 }
797 }
798 spin_unlock(&octeon_devices_lock);
799
800 atomic_inc(oct->adapter_refcount);
801 refcount = atomic_read(oct->adapter_refcount);
802
803 dev_dbg(&oct->pci_dev->dev, "%s: %02x:%02x:%d refcount %u", __func__,
804 oct->loc.bus, oct->loc.dev, oct->loc.func, refcount);
805
806 return refcount;
807}
808
809
810
811
812
813int octeon_deregister_device(struct octeon_device *oct)
814{
815 int refcount;
816
817 atomic_dec(oct->adapter_refcount);
818 refcount = atomic_read(oct->adapter_refcount);
819
820 dev_dbg(&oct->pci_dev->dev, "%s: %04d:%02d:%d refcount %u", __func__,
821 oct->loc.bus, oct->loc.dev, oct->loc.func, refcount);
822
823 return refcount;
824}
825
826int
827octeon_allocate_ioq_vector(struct octeon_device *oct, u32 num_ioqs)
828{
829 struct octeon_ioq_vector *ioq_vector;
830 int cpu_num;
831 int size;
832 int i;
833
834 size = sizeof(struct octeon_ioq_vector) * num_ioqs;
835
836 oct->ioq_vector = vzalloc(size);
837 if (!oct->ioq_vector)
838 return -1;
839 for (i = 0; i < num_ioqs; i++) {
840 ioq_vector = &oct->ioq_vector[i];
841 ioq_vector->oct_dev = oct;
842 ioq_vector->iq_index = i;
843 ioq_vector->droq_index = i;
844 ioq_vector->mbox = oct->mbox[i];
845
846 cpu_num = i % num_online_cpus();
847 cpumask_set_cpu(cpu_num, &ioq_vector->affinity_mask);
848
849 if (oct->chip_id == OCTEON_CN23XX_PF_VID)
850 ioq_vector->ioq_num = i + oct->sriov_info.pf_srn;
851 else
852 ioq_vector->ioq_num = i;
853 }
854
855 return 0;
856}
857
858void
859octeon_free_ioq_vector(struct octeon_device *oct)
860{
861 vfree(oct->ioq_vector);
862}
863
864
865int octeon_setup_instr_queues(struct octeon_device *oct)
866{
867 u32 num_descs = 0;
868 u32 iq_no = 0;
869 union oct_txpciq txpciq;
870 int numa_node = dev_to_node(&oct->pci_dev->dev);
871
872 if (OCTEON_CN6XXX(oct))
873 num_descs =
874 CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn6xxx));
875 else if (OCTEON_CN23XX_PF(oct))
876 num_descs = CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn23xx_pf));
877 else if (OCTEON_CN23XX_VF(oct))
878 num_descs = CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn23xx_vf));
879
880 oct->num_iqs = 0;
881
882 oct->instr_queue[0] = vzalloc_node(sizeof(*oct->instr_queue[0]),
883 numa_node);
884 if (!oct->instr_queue[0])
885 oct->instr_queue[0] =
886 vzalloc(sizeof(struct octeon_instr_queue));
887 if (!oct->instr_queue[0])
888 return 1;
889 memset(oct->instr_queue[0], 0, sizeof(struct octeon_instr_queue));
890 oct->instr_queue[0]->q_index = 0;
891 oct->instr_queue[0]->app_ctx = (void *)(size_t)0;
892 oct->instr_queue[0]->ifidx = 0;
893 txpciq.u64 = 0;
894 txpciq.s.q_no = iq_no;
895 txpciq.s.pkind = oct->pfvf_hsword.pkind;
896 txpciq.s.use_qpg = 0;
897 txpciq.s.qpg = 0;
898 if (octeon_init_instr_queue(oct, txpciq, num_descs)) {
899
900 vfree(oct->instr_queue[0]);
901 oct->instr_queue[0] = NULL;
902 return 1;
903 }
904
905 oct->num_iqs++;
906 return 0;
907}
908
909int octeon_setup_output_queues(struct octeon_device *oct)
910{
911 u32 num_descs = 0;
912 u32 desc_size = 0;
913 u32 oq_no = 0;
914 int numa_node = dev_to_node(&oct->pci_dev->dev);
915
916 if (OCTEON_CN6XXX(oct)) {
917 num_descs =
918 CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn6xxx));
919 desc_size =
920 CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn6xxx));
921 } else if (OCTEON_CN23XX_PF(oct)) {
922 num_descs = CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn23xx_pf));
923 desc_size = CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn23xx_pf));
924 } else if (OCTEON_CN23XX_VF(oct)) {
925 num_descs = CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn23xx_vf));
926 desc_size = CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn23xx_vf));
927 }
928 oct->num_oqs = 0;
929 oct->droq[0] = vzalloc_node(sizeof(*oct->droq[0]), numa_node);
930 if (!oct->droq[0])
931 oct->droq[0] = vzalloc(sizeof(*oct->droq[0]));
932 if (!oct->droq[0])
933 return 1;
934
935 if (octeon_init_droq(oct, oq_no, num_descs, desc_size, NULL)) {
936 vfree(oct->droq[oq_no]);
937 oct->droq[oq_no] = NULL;
938 return 1;
939 }
940 oct->num_oqs++;
941
942 return 0;
943}
944
945int octeon_set_io_queues_off(struct octeon_device *oct)
946{
947 int loop = BUSY_READING_REG_VF_LOOP_COUNT;
948
949 if (OCTEON_CN6XXX(oct)) {
950 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0);
951 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0);
952 } else if (oct->chip_id == OCTEON_CN23XX_VF_VID) {
953 u32 q_no;
954
955
956
957
958
959 for (q_no = 0; q_no < oct->sriov_info.rings_per_vf; q_no++) {
960 u64 reg_val = octeon_read_csr64(
961 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no));
962
963 while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) &&
964 !(reg_val & CN23XX_PKT_INPUT_CTL_QUIET) &&
965 loop) {
966 reg_val = octeon_read_csr64(
967 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
968 loop--;
969 }
970 if (!loop) {
971 dev_err(&oct->pci_dev->dev,
972 "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n",
973 q_no);
974 return -1;
975 }
976
977 reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
978 octeon_write_csr64(oct,
979 CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
980 reg_val);
981
982 reg_val = octeon_read_csr64(
983 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
984 if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
985 dev_err(&oct->pci_dev->dev,
986 "unable to reset qno %u\n", q_no);
987 return -1;
988 }
989 }
990 }
991 return 0;
992}
993
994void octeon_set_droq_pkt_op(struct octeon_device *oct,
995 u32 q_no,
996 u32 enable)
997{
998 u32 reg_val = 0;
999
1000
1001 if (OCTEON_CN6XXX(oct)) {
1002 reg_val = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB);
1003
1004 if (enable)
1005 reg_val = reg_val | (1 << q_no);
1006 else
1007 reg_val = reg_val & (~(1 << q_no));
1008
1009 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, reg_val);
1010 }
1011}
1012
1013int octeon_init_dispatch_list(struct octeon_device *oct)
1014{
1015 u32 i;
1016
1017 oct->dispatch.count = 0;
1018
1019 for (i = 0; i < DISPATCH_LIST_SIZE; i++) {
1020 oct->dispatch.dlist[i].opcode = 0;
1021 INIT_LIST_HEAD(&oct->dispatch.dlist[i].list);
1022 }
1023
1024 for (i = 0; i <= REQTYPE_LAST; i++)
1025 octeon_register_reqtype_free_fn(oct, i, NULL);
1026
1027 spin_lock_init(&oct->dispatch.lock);
1028
1029 return 0;
1030}
1031
1032void octeon_delete_dispatch_list(struct octeon_device *oct)
1033{
1034 u32 i;
1035 struct list_head freelist, *temp, *tmp2;
1036
1037 INIT_LIST_HEAD(&freelist);
1038
1039 spin_lock_bh(&oct->dispatch.lock);
1040
1041 for (i = 0; i < DISPATCH_LIST_SIZE; i++) {
1042 struct list_head *dispatch;
1043
1044 dispatch = &oct->dispatch.dlist[i].list;
1045 while (dispatch->next != dispatch) {
1046 temp = dispatch->next;
1047 list_del(temp);
1048 list_add_tail(temp, &freelist);
1049 }
1050
1051 oct->dispatch.dlist[i].opcode = 0;
1052 }
1053
1054 oct->dispatch.count = 0;
1055
1056 spin_unlock_bh(&oct->dispatch.lock);
1057
1058 list_for_each_safe(temp, tmp2, &freelist) {
1059 list_del(temp);
1060 vfree(temp);
1061 }
1062}
1063
1064octeon_dispatch_fn_t
1065octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode,
1066 u16 subcode)
1067{
1068 u32 idx;
1069 struct list_head *dispatch;
1070 octeon_dispatch_fn_t fn = NULL;
1071 u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode);
1072
1073 idx = combined_opcode & OCTEON_OPCODE_MASK;
1074
1075 spin_lock_bh(&octeon_dev->dispatch.lock);
1076
1077 if (octeon_dev->dispatch.count == 0) {
1078 spin_unlock_bh(&octeon_dev->dispatch.lock);
1079 return NULL;
1080 }
1081
1082 if (!(octeon_dev->dispatch.dlist[idx].opcode)) {
1083 spin_unlock_bh(&octeon_dev->dispatch.lock);
1084 return NULL;
1085 }
1086
1087 if (octeon_dev->dispatch.dlist[idx].opcode == combined_opcode) {
1088 fn = octeon_dev->dispatch.dlist[idx].dispatch_fn;
1089 } else {
1090 list_for_each(dispatch,
1091 &octeon_dev->dispatch.dlist[idx].list) {
1092 if (((struct octeon_dispatch *)dispatch)->opcode ==
1093 combined_opcode) {
1094 fn = ((struct octeon_dispatch *)
1095 dispatch)->dispatch_fn;
1096 break;
1097 }
1098 }
1099 }
1100
1101 spin_unlock_bh(&octeon_dev->dispatch.lock);
1102 return fn;
1103}
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122int
1123octeon_register_dispatch_fn(struct octeon_device *oct,
1124 u16 opcode,
1125 u16 subcode,
1126 octeon_dispatch_fn_t fn, void *fn_arg)
1127{
1128 u32 idx;
1129 octeon_dispatch_fn_t pfn;
1130 u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode);
1131
1132 idx = combined_opcode & OCTEON_OPCODE_MASK;
1133
1134 spin_lock_bh(&oct->dispatch.lock);
1135
1136 if (oct->dispatch.dlist[idx].opcode == 0) {
1137 oct->dispatch.dlist[idx].opcode = combined_opcode;
1138 oct->dispatch.dlist[idx].dispatch_fn = fn;
1139 oct->dispatch.dlist[idx].arg = fn_arg;
1140 oct->dispatch.count++;
1141 spin_unlock_bh(&oct->dispatch.lock);
1142 return 0;
1143 }
1144
1145 spin_unlock_bh(&oct->dispatch.lock);
1146
1147
1148
1149
1150 pfn = octeon_get_dispatch(oct, opcode, subcode);
1151 if (!pfn) {
1152 struct octeon_dispatch *dispatch;
1153
1154 dev_dbg(&oct->pci_dev->dev,
1155 "Adding opcode to dispatch list linked list\n");
1156 dispatch = (struct octeon_dispatch *)
1157 vmalloc(sizeof(struct octeon_dispatch));
1158 if (!dispatch) {
1159 dev_err(&oct->pci_dev->dev,
1160 "No memory to add dispatch function\n");
1161 return 1;
1162 }
1163 dispatch->opcode = combined_opcode;
1164 dispatch->dispatch_fn = fn;
1165 dispatch->arg = fn_arg;
1166
1167
1168
1169
1170 spin_lock_bh(&oct->dispatch.lock);
1171 list_add(&dispatch->list, &oct->dispatch.dlist[idx].list);
1172 oct->dispatch.count++;
1173 spin_unlock_bh(&oct->dispatch.lock);
1174
1175 } else {
1176 if (pfn == fn &&
1177 octeon_get_dispatch_arg(oct, opcode, subcode) == fn_arg)
1178 return 0;
1179
1180 dev_err(&oct->pci_dev->dev,
1181 "Found previously registered dispatch fn for opcode/subcode: %x/%x\n",
1182 opcode, subcode);
1183 return 1;
1184 }
1185
1186 return 0;
1187}
1188
1189int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf)
1190{
1191 u32 i;
1192 char app_name[16];
1193 struct octeon_device *oct = (struct octeon_device *)buf;
1194 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
1195 struct octeon_core_setup *cs = NULL;
1196 u32 num_nic_ports = 0;
1197
1198 if (OCTEON_CN6XXX(oct))
1199 num_nic_ports =
1200 CFG_GET_NUM_NIC_PORTS(CHIP_CONF(oct, cn6xxx));
1201 else if (OCTEON_CN23XX_PF(oct))
1202 num_nic_ports =
1203 CFG_GET_NUM_NIC_PORTS(CHIP_CONF(oct, cn23xx_pf));
1204
1205 if (atomic_read(&oct->status) >= OCT_DEV_RUNNING) {
1206 dev_err(&oct->pci_dev->dev, "Received CORE OK when device state is 0x%x\n",
1207 atomic_read(&oct->status));
1208 goto core_drv_init_err;
1209 }
1210
1211 strncpy(app_name,
1212 get_oct_app_string(
1213 (u32)recv_pkt->rh.r_core_drv_init.app_mode),
1214 sizeof(app_name) - 1);
1215 oct->app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
1216 if (recv_pkt->rh.r_core_drv_init.app_mode == CVM_DRV_NIC_APP) {
1217 oct->fw_info.max_nic_ports =
1218 (u32)recv_pkt->rh.r_core_drv_init.max_nic_ports;
1219 oct->fw_info.num_gmx_ports =
1220 (u32)recv_pkt->rh.r_core_drv_init.num_gmx_ports;
1221 }
1222
1223 if (oct->fw_info.max_nic_ports < num_nic_ports) {
1224 dev_err(&oct->pci_dev->dev,
1225 "Config has more ports than firmware allows (%d > %d).\n",
1226 num_nic_ports, oct->fw_info.max_nic_ports);
1227 goto core_drv_init_err;
1228 }
1229 oct->fw_info.app_cap_flags = recv_pkt->rh.r_core_drv_init.app_cap_flags;
1230 oct->fw_info.app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
1231 oct->pfvf_hsword.app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
1232
1233 oct->pfvf_hsword.pkind = recv_pkt->rh.r_core_drv_init.pkind;
1234
1235 for (i = 0; i < oct->num_iqs; i++)
1236 oct->instr_queue[i]->txpciq.s.pkind = oct->pfvf_hsword.pkind;
1237
1238 atomic_set(&oct->status, OCT_DEV_CORE_OK);
1239
1240 cs = &core_setup[oct->octeon_id];
1241
1242 if (recv_pkt->buffer_size[0] != (sizeof(*cs) + OCT_DROQ_INFO_SIZE)) {
1243 dev_dbg(&oct->pci_dev->dev, "Core setup bytes expected %u found %d\n",
1244 (u32)sizeof(*cs),
1245 recv_pkt->buffer_size[0]);
1246 }
1247
1248 memcpy(cs, get_rbd(
1249 recv_pkt->buffer_ptr[0]) + OCT_DROQ_INFO_SIZE, sizeof(*cs));
1250
1251 strncpy(oct->boardinfo.name, cs->boardname, OCT_BOARD_NAME);
1252 strncpy(oct->boardinfo.serial_number, cs->board_serial_number,
1253 OCT_SERIAL_LEN);
1254
1255 octeon_swap_8B_data((u64 *)cs, (sizeof(*cs) >> 3));
1256
1257 oct->boardinfo.major = cs->board_rev_major;
1258 oct->boardinfo.minor = cs->board_rev_minor;
1259
1260 dev_info(&oct->pci_dev->dev,
1261 "Running %s (%llu Hz)\n",
1262 app_name, CVM_CAST64(cs->corefreq));
1263
1264core_drv_init_err:
1265 for (i = 0; i < recv_pkt->buffer_count; i++)
1266 recv_buffer_free(recv_pkt->buffer_ptr[i]);
1267 octeon_free_recv_info(recv_info);
1268 return 0;
1269}
1270
1271int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no)
1272
1273{
1274 if (oct && (q_no < MAX_OCTEON_INSTR_QUEUES(oct)) &&
1275 (oct->io_qmask.iq & BIT_ULL(q_no)))
1276 return oct->instr_queue[q_no]->max_count;
1277
1278 return -1;
1279}
1280
1281int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no)
1282{
1283 if (oct && (q_no < MAX_OCTEON_OUTPUT_QUEUES(oct)) &&
1284 (oct->io_qmask.oq & BIT_ULL(q_no)))
1285 return oct->droq[q_no]->max_count;
1286 return -1;
1287}
1288
1289
1290struct octeon_config *octeon_get_conf(struct octeon_device *oct)
1291{
1292 struct octeon_config *default_oct_conf = NULL;
1293
1294
1295
1296
1297
1298 if (OCTEON_CN6XXX(oct)) {
1299 default_oct_conf =
1300 (struct octeon_config *)(CHIP_CONF(oct, cn6xxx));
1301 } else if (OCTEON_CN23XX_PF(oct)) {
1302 default_oct_conf = (struct octeon_config *)
1303 (CHIP_CONF(oct, cn23xx_pf));
1304 } else if (OCTEON_CN23XX_VF(oct)) {
1305 default_oct_conf = (struct octeon_config *)
1306 (CHIP_CONF(oct, cn23xx_vf));
1307 }
1308 return default_oct_conf;
1309}
1310
1311
1312#define CNXX_SLI_SCRATCH1 0x3C0
1313
1314
1315
1316
1317
1318
1319struct octeon_device *lio_get_device(u32 octeon_id)
1320{
1321 if (octeon_id >= MAX_OCTEON_DEVICES)
1322 return NULL;
1323 else
1324 return octeon_device[octeon_id];
1325}
1326
1327u64 lio_pci_readq(struct octeon_device *oct, u64 addr)
1328{
1329 u64 val64;
1330 unsigned long flags;
1331 u32 val32, addrhi;
1332
1333 spin_lock_irqsave(&oct->pci_win_lock, flags);
1334
1335
1336
1337
1338 addrhi = (addr >> 32);
1339 if ((oct->chip_id == OCTEON_CN66XX) ||
1340 (oct->chip_id == OCTEON_CN68XX) ||
1341 (oct->chip_id == OCTEON_CN23XX_PF_VID))
1342 addrhi |= 0x00060000;
1343 writel(addrhi, oct->reg_list.pci_win_rd_addr_hi);
1344
1345
1346 val32 = readl(oct->reg_list.pci_win_rd_addr_hi);
1347
1348 writel(addr & 0xffffffff, oct->reg_list.pci_win_rd_addr_lo);
1349 val32 = readl(oct->reg_list.pci_win_rd_addr_lo);
1350
1351 val64 = readq(oct->reg_list.pci_win_rd_data);
1352
1353 spin_unlock_irqrestore(&oct->pci_win_lock, flags);
1354
1355 return val64;
1356}
1357
1358void lio_pci_writeq(struct octeon_device *oct,
1359 u64 val,
1360 u64 addr)
1361{
1362 u32 val32;
1363 unsigned long flags;
1364
1365 spin_lock_irqsave(&oct->pci_win_lock, flags);
1366
1367 writeq(addr, oct->reg_list.pci_win_wr_addr);
1368
1369
1370 writel(val >> 32, oct->reg_list.pci_win_wr_data_hi);
1371
1372 val32 = readl(oct->reg_list.pci_win_wr_data_hi);
1373
1374 writel(val & 0xffffffff, oct->reg_list.pci_win_wr_data_lo);
1375
1376 spin_unlock_irqrestore(&oct->pci_win_lock, flags);
1377}
1378
1379int octeon_mem_access_ok(struct octeon_device *oct)
1380{
1381 u64 access_okay = 0;
1382 u64 lmc0_reset_ctl;
1383
1384
1385 if (OCTEON_CN23XX_PF(oct)) {
1386 lmc0_reset_ctl = lio_pci_readq(oct, CN23XX_LMC0_RESET_CTL);
1387 access_okay =
1388 (lmc0_reset_ctl & CN23XX_LMC0_RESET_CTL_DDR3RST_MASK);
1389 } else {
1390 lmc0_reset_ctl = lio_pci_readq(oct, CN6XXX_LMC0_RESET_CTL);
1391 access_okay =
1392 (lmc0_reset_ctl & CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK);
1393 }
1394
1395 return access_okay ? 0 : 1;
1396}
1397
1398int octeon_wait_for_ddr_init(struct octeon_device *oct, u32 *timeout)
1399{
1400 int ret = 1;
1401 u32 ms;
1402
1403 if (!timeout)
1404 return ret;
1405
1406 for (ms = 0; (ret != 0) && ((*timeout == 0) || (ms <= *timeout));
1407 ms += HZ / 10) {
1408 ret = octeon_mem_access_ok(oct);
1409
1410
1411 if (ret)
1412 schedule_timeout_uninterruptible(HZ / 10);
1413 }
1414
1415 return ret;
1416}
1417
1418
1419
1420
1421
1422
1423int lio_get_device_id(void *dev)
1424{
1425 struct octeon_device *octeon_dev = (struct octeon_device *)dev;
1426 u32 i;
1427
1428 for (i = 0; i < MAX_OCTEON_DEVICES; i++)
1429 if (octeon_device[i] == octeon_dev)
1430 return octeon_dev->octeon_id;
1431 return -1;
1432}
1433
1434void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq)
1435{
1436 u64 instr_cnt;
1437 u32 pkts_pend;
1438 struct octeon_device *oct = NULL;
1439
1440
1441 if (droq) {
1442 pkts_pend = (u32)atomic_read(&droq->pkts_pending);
1443 spin_lock_bh(&droq->lock);
1444 writel(droq->pkt_count - pkts_pend, droq->pkts_sent_reg);
1445 droq->pkt_count = pkts_pend;
1446
1447 spin_unlock_bh(&droq->lock);
1448 oct = droq->oct_dev;
1449 }
1450 if (iq) {
1451 spin_lock_bh(&iq->lock);
1452 writel(iq->pkt_in_done, iq->inst_cnt_reg);
1453 iq->pkt_in_done = 0;
1454
1455 spin_unlock_bh(&iq->lock);
1456 oct = iq->oct_dev;
1457 }
1458
1459
1460
1461 if (oct && (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct))) {
1462 if (droq)
1463 writeq(CN23XX_INTR_RESEND, droq->pkts_sent_reg);
1464
1465 else if (iq) {
1466 instr_cnt = readq(iq->inst_cnt_reg);
1467 writeq(((instr_cnt & 0xFFFFFFFF00000000ULL) |
1468 CN23XX_INTR_RESEND),
1469 iq->inst_cnt_reg);
1470 }
1471 }
1472}
1473