LXR linux/drivers/net/ethernet/stmicro/stmmac/dwmac4

   1/*
   2 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3 * DWC Ether MAC version 4.xx  has been used for  developing this code.
   4 *
   5 * This contains the functions to handle the dma.
   6 *
   7 * Copyright (C) 2015  STMicroelectronics Ltd
   8 *
   9 * This program is free software; you can redistribute it and/or modify it
  10 * under the terms and conditions of the GNU General Public License,
  11 * version 2, as published by the Free Software Foundation.
  12 *
  13 * Author: Alexandre Torgue <alexandre.torgue@st.com>
  14 */
  15
  16#include <linux/io.h>
  17#include "dwmac4.h"
  18#include "dwmac4_dma.h"
  19
  20static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
  21{
  22        u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
  23        int i;
  24
  25        pr_info("dwmac4: Master AXI performs %s burst length\n",
  26                (value & DMA_SYS_BUS_FB) ? "fixed" : "any");
  27
  28        if (axi->axi_lpi_en)
  29                value |= DMA_AXI_EN_LPI;
  30        if (axi->axi_xit_frm)
  31                value |= DMA_AXI_LPI_XIT_FRM;
  32
  33        value &= ~DMA_AXI_WR_OSR_LMT;
  34        value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<
  35                 DMA_AXI_WR_OSR_LMT_SHIFT;
  36
  37        value &= ~DMA_AXI_RD_OSR_LMT;
  38        value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<
  39                 DMA_AXI_RD_OSR_LMT_SHIFT;
  40
  41        /* Depending on the UNDEF bit the Master AXI will perform any burst
  42         * length according to the BLEN programmed (by default all BLEN are
  43         * set).
  44         */
  45        for (i = 0; i < AXI_BLEN; i++) {
  46                switch (axi->axi_blen[i]) {
  47                case 256:
  48                        value |= DMA_AXI_BLEN256;
  49                        break;
  50                case 128:
  51                        value |= DMA_AXI_BLEN128;
  52                        break;
  53                case 64:
  54                        value |= DMA_AXI_BLEN64;
  55                        break;
  56                case 32:
  57                        value |= DMA_AXI_BLEN32;
  58                        break;
  59                case 16:
  60                        value |= DMA_AXI_BLEN16;
  61                        break;
  62                case 8:
  63                        value |= DMA_AXI_BLEN8;
  64                        break;
  65                case 4:
  66                        value |= DMA_AXI_BLEN4;
  67                        break;
  68                }
  69        }
  70
  71        writel(value, ioaddr + DMA_SYS_BUS_MODE);
  72}
  73
  74static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
  75                                    struct stmmac_dma_cfg *dma_cfg,
  76                                    u32 dma_rx_phy, u32 chan)
  77{
  78        u32 value;
  79        u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
  80
  81        value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
  82        value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
  83        writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
  84
  85        writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
  86}
  87
  88static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
  89                                    struct stmmac_dma_cfg *dma_cfg,
  90                                    u32 dma_tx_phy, u32 chan)
  91{
  92        u32 value;
  93        u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
  94
  95        value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
  96        value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT);
  97
  98        /* Enable OSP to get best performance */
  99        value |= DMA_CONTROL_OSP;
 100
 101        writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
 102
 103        writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
 104}
 105
 106static void dwmac4_dma_init_channel(void __iomem *ioaddr,
 107                                    struct stmmac_dma_cfg *dma_cfg, u32 chan)
 108{
 109        u32 value;
 110
 111        /* common channel control register config */
 112        value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
 113        if (dma_cfg->pblx8)
 114                value = value | DMA_BUS_MODE_PBL;
 115        writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
 116
 117        /* Mask interrupts by writing to CSR7 */
 118        writel(DMA_CHAN_INTR_DEFAULT_MASK,
 119               ioaddr + DMA_CHAN_INTR_ENA(chan));
 120}
 121
 122static void dwmac4_dma_init(void __iomem *ioaddr,
 123                            struct stmmac_dma_cfg *dma_cfg, int atds)
 124{
 125        u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
 126
 127        /* Set the Fixed burst mode */
 128        if (dma_cfg->fixed_burst)
 129                value |= DMA_SYS_BUS_FB;
 130
 131        /* Mixed Burst has no effect when fb is set */
 132        if (dma_cfg->mixed_burst)
 133                value |= DMA_SYS_BUS_MB;
 134
 135        if (dma_cfg->aal)
 136                value |= DMA_SYS_BUS_AAL;
 137
 138        writel(value, ioaddr + DMA_SYS_BUS_MODE);
 139}
 140
 141static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,
 142                                  u32 *reg_space)
 143{
 144        reg_space[DMA_CHAN_CONTROL(channel) / 4] =
 145                readl(ioaddr + DMA_CHAN_CONTROL(channel));
 146        reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] =
 147                readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
 148        reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] =
 149                readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));
 150        reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] =
 151                readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));
 152        reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] =
 153                readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
 154        reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] =
 155                readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel));
 156        reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] =
 157                readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel));
 158        reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] =
 159                readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel));
 160        reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] =
 161                readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel));
 162        reg_space[DMA_CHAN_INTR_ENA(channel) / 4] =
 163                readl(ioaddr + DMA_CHAN_INTR_ENA(channel));
 164        reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] =
 165                readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel));
 166        reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] =
 167                readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel));
 168        reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] =
 169                readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel));
 170        reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] =
 171                readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel));
 172        reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] =
 173                readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel));
 174        reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] =
 175                readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel));
 176        reg_space[DMA_CHAN_STATUS(channel) / 4] =
 177                readl(ioaddr + DMA_CHAN_STATUS(channel));
 178}
 179
 180static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
 181{
 182        int i;
 183
 184        for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
 185                _dwmac4_dump_dma_regs(ioaddr, i, reg_space);
 186}
 187
 188static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan)
 189{
 190        u32 chan;
 191
 192        for (chan = 0; chan < number_chan; chan++)
 193                writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(chan));
 194}
 195
 196static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode,
 197                                       u32 channel, int fifosz, u8 qmode)
 198{
 199        unsigned int rqs = fifosz / 256 - 1;
 200        u32 mtl_rx_op, mtl_rx_int;
 201
 202        mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));
 203
 204        if (mode == SF_DMA_MODE) {
 205                pr_debug("GMAC: enable RX store and forward mode\n");
 206                mtl_rx_op |= MTL_OP_MODE_RSF;
 207        } else {
 208                pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);
 209                mtl_rx_op &= ~MTL_OP_MODE_RSF;
 210                mtl_rx_op &= MTL_OP_MODE_RTC_MASK;
 211                if (mode <= 32)
 212                        mtl_rx_op |= MTL_OP_MODE_RTC_32;
 213                else if (mode <= 64)
 214                        mtl_rx_op |= MTL_OP_MODE_RTC_64;
 215                else if (mode <= 96)
 216                        mtl_rx_op |= MTL_OP_MODE_RTC_96;
 217                else
 218                        mtl_rx_op |= MTL_OP_MODE_RTC_128;
 219        }
 220
 221        mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK;
 222        mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT;
 223
 224        /* Enable flow control only if each channel gets 4 KiB or more FIFO and
 225         * only if channel is not an AVB channel.
 226         */
 227        if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
 228                unsigned int rfd, rfa;
 229
 230                mtl_rx_op |= MTL_OP_MODE_EHFC;
 231
 232                /* Set Threshold for Activating Flow Control to min 2 frames,
 233                 * i.e. 1500 * 2 = 3000 bytes.
 234                 *
 235                 * Set Threshold for Deactivating Flow Control to min 1 frame,
 236                 * i.e. 1500 bytes.
 237                 */
 238                switch (fifosz) {
 239                case 4096:
 240                        /* This violates the above formula because of FIFO size
 241                         * limit therefore overflow may occur in spite of this.
 242                         */
 243                        rfd = 0x03; /* Full-2.5K */
 244                        rfa = 0x01; /* Full-1.5K */
 245                        break;
 246
 247                case 8192:
 248                        rfd = 0x06; /* Full-4K */
 249                        rfa = 0x0a; /* Full-6K */
 250                        break;
 251
 252                case 16384:
 253                        rfd = 0x06; /* Full-4K */
 254                        rfa = 0x12; /* Full-10K */
 255                        break;
 256
 257                default:
 258                        rfd = 0x06; /* Full-4K */
 259                        rfa = 0x1e; /* Full-16K */
 260                        break;
 261                }
 262
 263                mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK;
 264                mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT;
 265
 266                mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK;
 267                mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT;
 268        }
 269
 270        writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));
 271
 272        /* Enable MTL RX overflow */
 273        mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));
 274        writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN,
 275               ioaddr + MTL_CHAN_INT_CTRL(channel));
 276}
 277
 278static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode,
 279                                       u32 channel, int fifosz, u8 qmode)
 280{
 281        u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
 282        unsigned int tqs = fifosz / 256 - 1;
 283
 284        if (mode == SF_DMA_MODE) {
 285                pr_debug("GMAC: enable TX store and forward mode\n");
 286                /* Transmit COE type 2 cannot be done in cut-through mode. */
 287                mtl_tx_op |= MTL_OP_MODE_TSF;
 288        } else {
 289                pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);
 290                mtl_tx_op &= ~MTL_OP_MODE_TSF;
 291                mtl_tx_op &= MTL_OP_MODE_TTC_MASK;
 292                /* Set the transmit threshold */
 293                if (mode <= 32)
 294                        mtl_tx_op |= MTL_OP_MODE_TTC_32;
 295                else if (mode <= 64)
 296                        mtl_tx_op |= MTL_OP_MODE_TTC_64;
 297                else if (mode <= 96)
 298                        mtl_tx_op |= MTL_OP_MODE_TTC_96;
 299                else if (mode <= 128)
 300                        mtl_tx_op |= MTL_OP_MODE_TTC_128;
 301                else if (mode <= 192)
 302                        mtl_tx_op |= MTL_OP_MODE_TTC_192;
 303                else if (mode <= 256)
 304                        mtl_tx_op |= MTL_OP_MODE_TTC_256;
 305                else if (mode <= 384)
 306                        mtl_tx_op |= MTL_OP_MODE_TTC_384;
 307                else
 308                        mtl_tx_op |= MTL_OP_MODE_TTC_512;
 309        }
 310        /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
 311         * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
 312         * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
 313         * with reset values: TXQEN off, TQS 256 bytes.
 314         *
 315         * TXQEN must be written for multi-channel operation and TQS must
 316         * reflect the available fifo size per queue (total fifo size / number
 317         * of enabled queues).
 318         */
 319        mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
 320        if (qmode != MTL_QUEUE_AVB)
 321                mtl_tx_op |= MTL_OP_MODE_TXQEN;
 322        else
 323                mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;
 324        mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK;
 325        mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT;
 326
 327        writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
 328}
 329
 330static void dwmac4_get_hw_feature(void __iomem *ioaddr,
 331                                  struct dma_features *dma_cap)
 332{
 333        u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
 334
 335        /*  MAC HW feature0 */
 336        dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
 337        dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
 338        dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
 339        dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
 340        dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
 341        dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
 342        dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
 343        dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;
 344        dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;
 345        /* MMC */
 346        dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;
 347        /* IEEE 1588-2008 */
 348        dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;
 349        /* 802.3az - Energy-Efficient Ethernet (EEE) */
 350        dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;
 351        /* TX and RX csum */
 352        dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
 353        dma_cap->rx_coe =  (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
 354
 355        /* MAC HW feature1 */
 356        hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
 357        dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
 358        dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
 359        /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by
 360         * shifting and store the sizes in bytes.
 361         */
 362        dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6);
 363        dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0);
 364        /* MAC HW feature2 */
 365        hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);
 366        /* TX and RX number of channels */
 367        dma_cap->number_rx_channel =
 368                ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
 369        dma_cap->number_tx_channel =
 370                ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
 371        /* TX and RX number of queues */
 372        dma_cap->number_rx_queues =
 373                ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1;
 374        dma_cap->number_tx_queues =
 375                ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1;
 376        /* PPS output */
 377        dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24;
 378
 379        /* IEEE 1588-2002 */
 380        dma_cap->time_stamp = 0;
 381
 382        /* MAC HW feature3 */
 383        hw_cap = readl(ioaddr + GMAC_HW_FEATURE3);
 384
 385        /* 5.10 Features */
 386        dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;
 387        dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;
 388        dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;
 389        dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;
 390}
 391
 392/* Enable/disable TSO feature and set MSS */
 393static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
 394{
 395        u32 value;
 396
 397        if (en) {
 398                /* enable TSO */
 399                value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
 400                writel(value | DMA_CONTROL_TSE,
 401                       ioaddr + DMA_CHAN_TX_CONTROL(chan));
 402        } else {
 403                /* enable TSO */
 404                value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
 405                writel(value & ~DMA_CONTROL_TSE,
 406                       ioaddr + DMA_CHAN_TX_CONTROL(chan));
 407        }
 408}
 409
 410static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
 411{
 412        u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
 413
 414        value &= ~DMA_RBSZ_MASK;
 415        value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK;
 416
 417        writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
 418}
 419
 420const struct stmmac_dma_ops dwmac4_dma_ops = {
 421        .reset = dwmac4_dma_reset,
 422        .init = dwmac4_dma_init,
 423        .init_chan = dwmac4_dma_init_channel,
 424        .init_rx_chan = dwmac4_dma_init_rx_chan,
 425        .init_tx_chan = dwmac4_dma_init_tx_chan,
 426        .axi = dwmac4_dma_axi,
 427        .dump_regs = dwmac4_dump_dma_regs,
 428        .dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
 429        .dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
 430        .enable_dma_irq = dwmac4_enable_dma_irq,
 431        .disable_dma_irq = dwmac4_disable_dma_irq,
 432        .start_tx = dwmac4_dma_start_tx,
 433        .stop_tx = dwmac4_dma_stop_tx,
 434        .start_rx = dwmac4_dma_start_rx,
 435        .stop_rx = dwmac4_dma_stop_rx,
 436        .dma_interrupt = dwmac4_dma_interrupt,
 437        .get_hw_feature = dwmac4_get_hw_feature,
 438        .rx_watchdog = dwmac4_rx_watchdog,
 439        .set_rx_ring_len = dwmac4_set_rx_ring_len,
 440        .set_tx_ring_len = dwmac4_set_tx_ring_len,
 441        .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
 442        .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
 443        .enable_tso = dwmac4_enable_tso,
 444        .set_bfsize = dwmac4_set_bfsize,
 445};
 446
 447const struct stmmac_dma_ops dwmac410_dma_ops = {
 448        .reset = dwmac4_dma_reset,
 449        .init = dwmac4_dma_init,
 450        .init_chan = dwmac4_dma_init_channel,
 451        .init_rx_chan = dwmac4_dma_init_rx_chan,
 452        .init_tx_chan = dwmac4_dma_init_tx_chan,
 453        .axi = dwmac4_dma_axi,
 454        .dump_regs = dwmac4_dump_dma_regs,
 455        .dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
 456        .dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
 457        .enable_dma_irq = dwmac410_enable_dma_irq,
 458        .disable_dma_irq = dwmac4_disable_dma_irq,
 459        .start_tx = dwmac4_dma_start_tx,
 460        .stop_tx = dwmac4_dma_stop_tx,
 461        .start_rx = dwmac4_dma_start_rx,
 462        .stop_rx = dwmac4_dma_stop_rx,
 463        .dma_interrupt = dwmac4_dma_interrupt,
 464        .get_hw_feature = dwmac4_get_hw_feature,
 465        .rx_watchdog = dwmac4_rx_watchdog,
 466        .set_rx_ring_len = dwmac4_set_rx_ring_len,
 467        .set_tx_ring_len = dwmac4_set_tx_ring_len,
 468        .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
 469        .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
 470        .enable_tso = dwmac4_enable_tso,
 471        .set_bfsize = dwmac4_set_bfsize,
 472};
 473