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20#include <linux/clk.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/phy/phy.h>
26#include <linux/reset.h>
27
28#define INNO_PHY_PORT_NUM 2
29#define REF_CLK_STABLE_TIME 100
30#define UTMI_CLK_STABLE_TIME 200
31#define TEST_CLK_STABLE_TIME 2
32#define PHY_CLK_STABLE_TIME 2
33#define UTMI_RST_COMPLETE_TIME 2
34#define POR_RST_COMPLETE_TIME 300
35#define PHY_TEST_DATA GENMASK(7, 0)
36#define PHY_TEST_ADDR GENMASK(15, 8)
37#define PHY_TEST_PORT GENMASK(18, 16)
38#define PHY_TEST_WREN BIT(21)
39#define PHY_TEST_CLK BIT(22)
40#define PHY_TEST_RST BIT(23)
41#define PHY_CLK_ENABLE BIT(2)
42
43struct hisi_inno_phy_port {
44 struct reset_control *utmi_rst;
45 struct hisi_inno_phy_priv *priv;
46};
47
48struct hisi_inno_phy_priv {
49 void __iomem *mmio;
50 struct clk *ref_clk;
51 struct reset_control *por_rst;
52 struct hisi_inno_phy_port ports[INNO_PHY_PORT_NUM];
53};
54
55static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv,
56 u8 port, u32 addr, u32 data)
57{
58 void __iomem *reg = priv->mmio;
59 u32 val;
60
61 val = (data & PHY_TEST_DATA) |
62 ((addr << 8) & PHY_TEST_ADDR) |
63 ((port << 16) & PHY_TEST_PORT) |
64 PHY_TEST_WREN | PHY_TEST_RST;
65 writel(val, reg);
66
67 val |= PHY_TEST_CLK;
68 writel(val, reg);
69
70 val &= ~PHY_TEST_CLK;
71 writel(val, reg);
72}
73
74static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv)
75{
76
77 hisi_inno_phy_write_reg(priv, 0, 0x06, PHY_CLK_ENABLE);
78 msleep(PHY_CLK_STABLE_TIME);
79}
80
81static int hisi_inno_phy_init(struct phy *phy)
82{
83 struct hisi_inno_phy_port *port = phy_get_drvdata(phy);
84 struct hisi_inno_phy_priv *priv = port->priv;
85 int ret;
86
87 ret = clk_prepare_enable(priv->ref_clk);
88 if (ret)
89 return ret;
90 udelay(REF_CLK_STABLE_TIME);
91
92 reset_control_deassert(priv->por_rst);
93 udelay(POR_RST_COMPLETE_TIME);
94
95
96 hisi_inno_phy_setup(priv);
97
98 reset_control_deassert(port->utmi_rst);
99 udelay(UTMI_RST_COMPLETE_TIME);
100
101 return 0;
102}
103
104static int hisi_inno_phy_exit(struct phy *phy)
105{
106 struct hisi_inno_phy_port *port = phy_get_drvdata(phy);
107 struct hisi_inno_phy_priv *priv = port->priv;
108
109 reset_control_assert(port->utmi_rst);
110 reset_control_assert(priv->por_rst);
111 clk_disable_unprepare(priv->ref_clk);
112
113 return 0;
114}
115
116static const struct phy_ops hisi_inno_phy_ops = {
117 .init = hisi_inno_phy_init,
118 .exit = hisi_inno_phy_exit,
119 .owner = THIS_MODULE,
120};
121
122static int hisi_inno_phy_probe(struct platform_device *pdev)
123{
124 struct device *dev = &pdev->dev;
125 struct device_node *np = dev->of_node;
126 struct hisi_inno_phy_priv *priv;
127 struct phy_provider *provider;
128 struct device_node *child;
129 struct resource *res;
130 int i = 0;
131 int ret;
132
133 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
134 if (!priv)
135 return -ENOMEM;
136
137 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
138 priv->mmio = devm_ioremap_resource(dev, res);
139 if (IS_ERR(priv->mmio)) {
140 ret = PTR_ERR(priv->mmio);
141 return ret;
142 }
143
144 priv->ref_clk = devm_clk_get(dev, NULL);
145 if (IS_ERR(priv->ref_clk))
146 return PTR_ERR(priv->ref_clk);
147
148 priv->por_rst = devm_reset_control_get_exclusive(dev, NULL);
149 if (IS_ERR(priv->por_rst))
150 return PTR_ERR(priv->por_rst);
151
152 for_each_child_of_node(np, child) {
153 struct reset_control *rst;
154 struct phy *phy;
155
156 rst = of_reset_control_get_exclusive(child, NULL);
157 if (IS_ERR(rst))
158 return PTR_ERR(rst);
159 priv->ports[i].utmi_rst = rst;
160 priv->ports[i].priv = priv;
161
162 phy = devm_phy_create(dev, child, &hisi_inno_phy_ops);
163 if (IS_ERR(phy))
164 return PTR_ERR(phy);
165
166 phy_set_bus_width(phy, 8);
167 phy_set_drvdata(phy, &priv->ports[i]);
168 i++;
169
170 if (i > INNO_PHY_PORT_NUM) {
171 dev_warn(dev, "Support %d ports in maximum\n", i);
172 break;
173 }
174 }
175
176 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
177 return PTR_ERR_OR_ZERO(provider);
178}
179
180static const struct of_device_id hisi_inno_phy_of_match[] = {
181 { .compatible = "hisilicon,inno-usb2-phy", },
182 { .compatible = "hisilicon,hi3798cv200-usb2-phy", },
183 { },
184};
185MODULE_DEVICE_TABLE(of, hisi_inno_phy_of_match);
186
187static struct platform_driver hisi_inno_phy_driver = {
188 .probe = hisi_inno_phy_probe,
189 .driver = {
190 .name = "hisi-inno-phy",
191 .of_match_table = hisi_inno_phy_of_match,
192 }
193};
194module_platform_driver(hisi_inno_phy_driver);
195
196MODULE_DESCRIPTION("HiSilicon INNO USB2 PHY Driver");
197MODULE_LICENSE("GPL v2");
198
