LXR linux/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c

   1/*
   2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 and
   6 * only version 2 as published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 *
  13 * GPIO and pin control functions on this SOC are handled by the "TLMM"
  14 * device.  The driver which controls this device is pinctrl-msm.c.  Each
  15 * SOC with a TLMM is expected to create a client driver that registers
  16 * with pinctrl-msm.c.  This means that all TLMM drivers are pin control
  17 * drivers.
  18 *
  19 * This pin control driver is intended to be used only an ACPI-enabled
  20 * system.  As such, UEFI will handle all pin control configuration, so
  21 * this driver does not provide pin control functions.  It is effectively
  22 * a GPIO-only driver.  The alternative is to duplicate the GPIO code of
  23 * pinctrl-msm.c into another driver.
  24 */
  25
  26#include <linux/module.h>
  27#include <linux/platform_device.h>
  28#include <linux/pinctrl/pinctrl.h>
  29#include <linux/acpi.h>
  30
  31#include "pinctrl-msm.h"
  32
  33/* A maximum of 256 allows us to use a u8 array to hold the GPIO numbers */
  34#define MAX_GPIOS       256
  35
  36/* maximum size of each gpio name (enough room for "gpioXXX" + null) */
  37#define NAME_SIZE       8
  38
  39static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
  40{
  41        struct msm_pinctrl_soc_data *pinctrl;
  42        struct pinctrl_pin_desc *pins;
  43        struct msm_pingroup *groups;
  44        char (*names)[NAME_SIZE];
  45        unsigned int i;
  46        u32 num_gpios;
  47        unsigned int avail_gpios; /* The number of GPIOs we support */
  48        u8 gpios[MAX_GPIOS];      /* An array of supported GPIOs */
  49        int ret;
  50
  51        /* Query the number of GPIOs from ACPI */
  52        ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
  53        if (ret < 0) {
  54                dev_err(&pdev->dev, "missing 'num-gpios' property\n");
  55                return ret;
  56        }
  57        if (!num_gpios || num_gpios > MAX_GPIOS) {
  58                dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
  59                return -ENODEV;
  60        }
  61
  62        /* The number of GPIOs in the approved list */
  63        ret = device_property_read_u8_array(&pdev->dev, "gpios", NULL, 0);
  64        if (ret < 0) {
  65                dev_err(&pdev->dev, "missing 'gpios' property\n");
  66                return ret;
  67        }
  68        /*
  69         * The number of available GPIOs should be non-zero, and no
  70         * more than the total number of GPIOS.
  71         */
  72        if (!ret || ret > num_gpios) {
  73                dev_err(&pdev->dev, "invalid 'gpios' property\n");
  74                return -ENODEV;
  75        }
  76        avail_gpios = ret;
  77
  78        ret = device_property_read_u8_array(&pdev->dev, "gpios", gpios,
  79                                            avail_gpios);
  80        if (ret < 0) {
  81                dev_err(&pdev->dev, "could not read list of GPIOs\n");
  82                return ret;
  83        }
  84
  85        pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
  86        pins = devm_kcalloc(&pdev->dev, num_gpios,
  87                sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
  88        groups = devm_kcalloc(&pdev->dev, num_gpios,
  89                sizeof(struct msm_pingroup), GFP_KERNEL);
  90        names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL);
  91
  92        if (!pinctrl || !pins || !groups || !names)
  93                return -ENOMEM;
  94
  95        /*
  96         * Initialize the array.  GPIOs not listed in the 'gpios' array
  97         * still need a number, but nothing else.
  98         */
  99        for (i = 0; i < num_gpios; i++) {
 100                pins[i].number = i;
 101                groups[i].pins = &pins[i].number;
 102        }
 103
 104        /* Populate the entries that are meant to be exposed as GPIOs. */
 105        for (i = 0; i < avail_gpios; i++) {
 106                unsigned int gpio = gpios[i];
 107
 108                groups[gpio].npins = 1;
 109                snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
 110                pins[gpio].name = names[i];
 111                groups[gpio].name = names[i];
 112
 113                groups[gpio].ctl_reg = 0x10000 * gpio;
 114                groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
 115                groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
 116                groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
 117                groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
 118
 119                groups[gpio].mux_bit = 2;
 120                groups[gpio].pull_bit = 0;
 121                groups[gpio].drv_bit = 6;
 122                groups[gpio].oe_bit = 9;
 123                groups[gpio].in_bit = 0;
 124                groups[gpio].out_bit = 1;
 125                groups[gpio].intr_enable_bit = 0;
 126                groups[gpio].intr_status_bit = 0;
 127                groups[gpio].intr_target_bit = 5;
 128                groups[gpio].intr_target_kpss_val = 1;
 129                groups[gpio].intr_raw_status_bit = 4;
 130                groups[gpio].intr_polarity_bit = 1;
 131                groups[gpio].intr_detection_bit = 2;
 132                groups[gpio].intr_detection_width = 2;
 133        }
 134
 135        pinctrl->pins = pins;
 136        pinctrl->groups = groups;
 137        pinctrl->npins = num_gpios;
 138        pinctrl->ngroups = num_gpios;
 139        pinctrl->ngpios = num_gpios;
 140
 141        return msm_pinctrl_probe(pdev, pinctrl);
 142}
 143
 144static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
 145        {"QCOM8002"},
 146        {},
 147};
 148MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
 149
 150static struct platform_driver qdf2xxx_pinctrl_driver = {
 151        .driver = {
 152                .name = "qdf2xxx-pinctrl",
 153                .acpi_match_table = ACPI_PTR(qdf2xxx_acpi_ids),
 154        },
 155        .probe = qdf2xxx_pinctrl_probe,
 156        .remove = msm_pinctrl_remove,
 157};
 158
 159static int __init qdf2xxx_pinctrl_init(void)
 160{
 161        return platform_driver_register(&qdf2xxx_pinctrl_driver);
 162}
 163arch_initcall(qdf2xxx_pinctrl_init);
 164
 165static void __exit qdf2xxx_pinctrl_exit(void)
 166{
 167        platform_driver_unregister(&qdf2xxx_pinctrl_driver);
 168}
 169module_exit(qdf2xxx_pinctrl_exit);
 170
 171MODULE_DESCRIPTION("Qualcomm Technologies QDF2xxx pin control driver");
 172MODULE_LICENSE("GPL v2");
 173