1/****************************************************************************** 2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 3 * 4 * This program is distributed in the hope that it will be useful, but WITHOUT 5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 7 * more details. 8 * 9 * The full GNU General Public License is included in this distribution in the 10 * file called LICENSE. 11 * 12 * Contact Information: 13 * wlanfae <wlanfae@realtek.com> 14 *****************************************************************************/ 15#ifndef _R819XU_PHYREG_H 16#define _R819XU_PHYREG_H 17 18 19#define RF_DATA 0x1d4 20 21#define rPMAC_Reset 0x100 22#define rPMAC_TxStart 0x104 23#define rPMAC_TxLegacySIG 0x108 24#define rPMAC_TxHTSIG1 0x10c 25#define rPMAC_TxHTSIG2 0x110 26#define rPMAC_PHYDebug 0x114 27#define rPMAC_TxPacketNum 0x118 28#define rPMAC_TxIdle 0x11c 29#define rPMAC_TxMACHeader0 0x120 30#define rPMAC_TxMACHeader1 0x124 31#define rPMAC_TxMACHeader2 0x128 32#define rPMAC_TxMACHeader3 0x12c 33#define rPMAC_TxMACHeader4 0x130 34#define rPMAC_TxMACHeader5 0x134 35#define rPMAC_TxDataType 0x138 36#define rPMAC_TxRandomSeed 0x13c 37#define rPMAC_CCKPLCPPreamble 0x140 38#define rPMAC_CCKPLCPHeader 0x144 39#define rPMAC_CCKCRC16 0x148 40#define rPMAC_OFDMRxCRC32OK 0x170 41#define rPMAC_OFDMRxCRC32Er 0x174 42#define rPMAC_OFDMRxParityEr 0x178 43#define rPMAC_OFDMRxCRC8Er 0x17c 44#define rPMAC_CCKCRxRC16Er 0x180 45#define rPMAC_CCKCRxRC32Er 0x184 46#define rPMAC_CCKCRxRC32OK 0x188 47#define rPMAC_TxStatus 0x18c 48 49#define MCS_TXAGC 0x340 50#define CCK_TXAGC 0x348 51 52/* Mac block on/off control register */ 53#define MacBlkCtrl 0x403 54 55#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ 56#define rFPGA0_TxInfo 0x804 57#define rFPGA0_PSDFunction 0x808 58#define rFPGA0_TxGainStage 0x80c 59#define rFPGA0_RFTiming1 0x810 60#define rFPGA0_RFTiming2 0x814 61#define rFPGA0_XA_HSSIParameter1 0x820 62#define rFPGA0_XA_HSSIParameter2 0x824 63#define rFPGA0_XB_HSSIParameter1 0x828 64#define rFPGA0_XB_HSSIParameter2 0x82c 65#define rFPGA0_XC_HSSIParameter1 0x830 66#define rFPGA0_XC_HSSIParameter2 0x834 67#define rFPGA0_XD_HSSIParameter1 0x838 68#define rFPGA0_XD_HSSIParameter2 0x83c 69#define rFPGA0_XA_LSSIParameter 0x840 70#define rFPGA0_XB_LSSIParameter 0x844 71#define rFPGA0_XC_LSSIParameter 0x848 72#define rFPGA0_XD_LSSIParameter 0x84c 73#define rFPGA0_RFWakeUpParameter 0x850 74#define rFPGA0_RFSleepUpParameter 0x854 75#define rFPGA0_XAB_SwitchControl 0x858 76#define rFPGA0_XCD_SwitchControl 0x85c 77#define rFPGA0_XA_RFInterfaceOE 0x860 78#define rFPGA0_XB_RFInterfaceOE 0x864 79#define rFPGA0_XC_RFInterfaceOE 0x868 80#define rFPGA0_XD_RFInterfaceOE 0x86c 81#define rFPGA0_XAB_RFInterfaceSW 0x870 82#define rFPGA0_XCD_RFInterfaceSW 0x874 83#define rFPGA0_XAB_RFParameter 0x878 84#define rFPGA0_XCD_RFParameter 0x87c 85#define rFPGA0_AnalogParameter1 0x880 86#define rFPGA0_AnalogParameter2 0x884 87#define rFPGA0_AnalogParameter3 0x888 88#define rFPGA0_AnalogParameter4 0x88c 89#define rFPGA0_XA_LSSIReadBack 0x8a0 90#define rFPGA0_XB_LSSIReadBack 0x8a4 91#define rFPGA0_XC_LSSIReadBack 0x8a8 92#define rFPGA0_XD_LSSIReadBack 0x8ac 93#define rFPGA0_PSDReport 0x8b4 94#define rFPGA0_XAB_RFInterfaceRB 0x8e0 95#define rFPGA0_XCD_RFInterfaceRB 0x8e4 96 97/* Page 9 - RF mode & OFDM TxSC */ 98#define rFPGA1_RFMOD 0x900 99#define rFPGA1_TxBlock 0x904 100#define rFPGA1_DebugSelect 0x908 101#define rFPGA1_TxInfo 0x90c 102 103#define rCCK0_System 0xa00 104#define rCCK0_AFESetting 0xa04 105#define rCCK0_CCA 0xa08 106/* AGC default value, saturation level */ 107#define rCCK0_RxAGC1 0xa0c 108#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 109#define rCCK0_RxHP 0xa14 110/* Timing recovery & channel estimation threshold */ 111#define rCCK0_DSPParameter1 0xa18 112#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 113#define rCCK0_TxFilter1 0xa20 114#define rCCK0_TxFilter2 0xa24 115#define rCCK0_DebugPort 0xa28 /* Debug port and TX filter 3 */ 116#define rCCK0_FalseAlarmReport 0xa2c 117#define rCCK0_TRSSIReport 0xa50 118#define rCCK0_RxReport 0xa54 119#define rCCK0_FACounterLower 0xa5c 120#define rCCK0_FACounterUpper 0xa58 121 122#define rOFDM0_LSTF 0xc00 123#define rOFDM0_TRxPathEnable 0xc04 124#define rOFDM0_TRMuxPar 0xc08 125#define rOFDM0_TRSWIsolation 0xc0c 126/* RxIQ DC offset, Rx digital filter, DC notch filter */ 127#define rOFDM0_XARxAFE 0xc10 128#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */ 129#define rOFDM0_XBRxAFE 0xc18 130#define rOFDM0_XBRxIQImbalance 0xc1c 131#define rOFDM0_XCRxAFE 0xc20 132#define rOFDM0_XCRxIQImbalance 0xc24 133#define rOFDM0_XDRxAFE 0xc28 134#define rOFDM0_XDRxIQImbalance 0xc2c 135#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ 136#define rOFDM0_RxDetector2 0xc34 /* SBD */ 137#define rOFDM0_RxDetector3 0xc38 /* Frame Sync */ 138/* PD, SBD, Frame Sync & Short-GI */ 139#define rOFDM0_RxDetector4 0xc3c 140#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 141#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 142#define rOFDM0_CCADropThreshold 0xc48 143#define rOFDM0_ECCAThreshold 0xc4c /* Energy CCA */ 144#define rOFDM0_XAAGCCore1 0xc50 145#define rOFDM0_XAAGCCore2 0xc54 146#define rOFDM0_XBAGCCore1 0xc58 147#define rOFDM0_XBAGCCore2 0xc5c 148#define rOFDM0_XCAGCCore1 0xc60 149#define rOFDM0_XCAGCCore2 0xc64 150#define rOFDM0_XDAGCCore1 0xc68 151#define rOFDM0_XDAGCCore2 0xc6c 152#define rOFDM0_AGCParameter1 0xc70 153#define rOFDM0_AGCParameter2 0xc74 154#define rOFDM0_AGCRSSITable 0xc78 155#define rOFDM0_HTSTFAGC 0xc7c 156#define rOFDM0_XATxIQImbalance 0xc80 157#define rOFDM0_XATxAFE 0xc84 158#define rOFDM0_XBTxIQImbalance 0xc88 159#define rOFDM0_XBTxAFE 0xc8c 160#define rOFDM0_XCTxIQImbalance 0xc90 161#define rOFDM0_XCTxAFE 0xc94 162#define rOFDM0_XDTxIQImbalance 0xc98 163#define rOFDM0_XDTxAFE 0xc9c 164#define rOFDM0_RxHPParameter 0xce0 165#define rOFDM0_TxPseudoNoiseWgt 0xce4 166#define rOFDM0_FrameSync 0xcf0 167#define rOFDM0_DFSReport 0xcf4 168#define rOFDM0_TxCoeff1 0xca4 169#define rOFDM0_TxCoeff2 0xca8 170#define rOFDM0_TxCoeff3 0xcac 171#define rOFDM0_TxCoeff4 0xcb0 172#define rOFDM0_TxCoeff5 0xcb4 173#define rOFDM0_TxCoeff6 0xcb8 174 175 176#define rOFDM1_LSTF 0xd00 177#define rOFDM1_TRxPathEnable 0xd04 178#define rOFDM1_CFO 0xd08 179#define rOFDM1_CSI1 0xd10 180#define rOFDM1_SBD 0xd14 181#define rOFDM1_CSI2 0xd18 182#define rOFDM1_CFOTracking 0xd2c 183#define rOFDM1_TRxMesaure1 0xd34 184#define rOFDM1_IntfDet 0xd3c 185#define rOFDM1_PseudoNoiseStateAB 0xd50 186#define rOFDM1_PseudoNoiseStateCD 0xd54 187#define rOFDM1_RxPseudoNoiseWgt 0xd58 188#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 189#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 190#define rOFDM_PHYCounter3 0xda8 /* MCS not supported */ 191#define rOFDM_ShortCFOAB 0xdac 192#define rOFDM_ShortCFOCD 0xdb0 193#define rOFDM_LongCFOAB 0xdb4 194#define rOFDM_LongCFOCD 0xdb8 195#define rOFDM_TailCFOAB 0xdbc 196#define rOFDM_TailCFOCD 0xdc0 197#define rOFDM_PWMeasure1 0xdc4 198#define rOFDM_PWMeasure2 0xdc8 199#define rOFDM_BWReport 0xdcc 200#define rOFDM_AGCReport 0xdd0 201#define rOFDM_RxSNR 0xdd4 202#define rOFDM_RxEVMCSI 0xdd8 203#define rOFDM_SIGReport 0xddc 204 205#define rTxAGC_Rate18_06 0xe00 206#define rTxAGC_Rate54_24 0xe04 207#define rTxAGC_CCK_Mcs32 0xe08 208#define rTxAGC_Mcs03_Mcs00 0xe10 209#define rTxAGC_Mcs07_Mcs04 0xe14 210#define rTxAGC_Mcs11_Mcs08 0xe18 211#define rTxAGC_Mcs15_Mcs12 0xe1c 212 213 214#define rZebra1_HSSIEnable 0x0 215#define rZebra1_TRxEnable1 0x1 216#define rZebra1_TRxEnable2 0x2 217#define rZebra1_AGC 0x4 218#define rZebra1_ChargePump 0x5 219#define rZebra1_Channel 0x7 220#define rZebra1_TxGain 0x8 221#define rZebra1_TxLPF 0x9 222#define rZebra1_RxLPF 0xb 223#define rZebra1_RxHPFCorner 0xc 224 225/* Zebra 4 */ 226#define rGlobalCtrl 0 227#define rRTL8256_TxLPF 19 228#define rRTL8256_RxLPF 11 229 230/* RTL8258 */ 231#define rRTL8258_TxLPF 0x11 232#define rRTL8258_RxLPF 0x13 233#define rRTL8258_RSSILPF 0xa 234 235/* Bit Mask - Page 1*/ 236#define bBBResetB 0x100 237#define bGlobalResetB 0x200 238#define bOFDMTxStart 0x4 239#define bCCKTxStart 0x8 240#define bCRC32Debug 0x100 241#define bPMACLoopback 0x10 242#define bTxLSIG 0xffffff 243#define bOFDMTxRate 0xf 244#define bOFDMTxReserved 0x10 245#define bOFDMTxLength 0x1ffe0 246#define bOFDMTxParity 0x20000 247#define bTxHTSIG1 0xffffff 248#define bTxHTMCSRate 0x7f 249#define bTxHTBW 0x80 250#define bTxHTLength 0xffff00 251#define bTxHTSIG2 0xffffff 252#define bTxHTSmoothing 0x1 253#define bTxHTSounding 0x2 254#define bTxHTReserved 0x4 255#define bTxHTAggreation 0x8 256#define bTxHTSTBC 0x30 257#define bTxHTAdvanceCoding 0x40 258#define bTxHTShortGI 0x80 259#define bTxHTNumberHT_LTF 0x300 260#define bTxHTCRC8 0x3fc00 261#define bCounterReset 0x10000 262#define bNumOfOFDMTx 0xffff 263#define bNumOfCCKTx 0xffff0000 264#define bTxIdleInterval 0xffff 265#define bOFDMService 0xffff0000 266#define bTxMACHeader 0xffffffff 267#define bTxDataInit 0xff 268#define bTxHTMode 0x100 269#define bTxDataType 0x30000 270#define bTxRandomSeed 0xffffffff 271#define bCCKTxPreamble 0x1 272#define bCCKTxSFD 0xffff0000 273#define bCCKTxSIG 0xff 274#define bCCKTxService 0xff00 275#define bCCKLengthExt 0x8000 276#define bCCKTxLength 0xffff0000 277#define bCCKTxCRC16 0xffff 278#define bCCKTxStatus 0x1 279#define bOFDMTxStatus 0x2 280/* Bit Mask - Page 8 */ 281#define bRFMOD 0x1 282#define bJapanMode 0x2 283#define bCCKTxSC 0x30 284#define bCCKEn 0x1000000 285#define bOFDMEn 0x2000000 286#define bOFDMRxADCPhase 0x10000 287#define bOFDMTxDACPhase 0x40000 288#define bXATxAGC 0x3f 289#define bXBTxAGC 0xf00 290#define bXCTxAGC 0xf000 291#define bXDTxAGC 0xf0000 292#define bPAStart 0xf0000000 293#define bTRStart 0x00f00000 294#define bRFStart 0x0000f000 295#define bBBStart 0x000000f0 296#define bBBCCKStart 0x0000000f 297/* Bit Mask - rFPGA0_RFTiming2 */ 298#define bPAEnd 0xf 299#define bTREnd 0x0f000000 300#define bRFEnd 0x000f0000 301/* T2R */ 302#define bCCAMask 0x000000f0 303#define bR2RCCAMask 0x00000f00 304#define bHSSI_R2TDelay 0xf8000000 305#define bHSSI_T2RDelay 0xf80000 306/* Channel gain at continue TX. */ 307#define bContTxHSSI 0x400 308#define bIGFromCCK 0x200 309#define bAGCAddress 0x3f 310#define bRxHPTx 0x7000 311#define bRxHPT2R 0x38000 312#define bRxHPCCKIni 0xc0000 313#define bAGCTxCode 0xc00000 314#define bAGCRxCode 0x300000 315#define b3WireDataLength 0x800 316#define b3WireAddressLength 0x400 317#define b3WireRFPowerDown 0x1 318/*#define bHWSISelect 0x8 */ 319#define b5GPAPEPolarity 0x40000000 320#define b2GPAPEPolarity 0x80000000 321#define bRFSW_TxDefaultAnt 0x3 322#define bRFSW_TxOptionAnt 0x30 323#define bRFSW_RxDefaultAnt 0x300 324#define bRFSW_RxOptionAnt 0x3000 325#define bRFSI_3WireData 0x1 326#define bRFSI_3WireClock 0x2 327#define bRFSI_3WireLoad 0x4 328#define bRFSI_3WireRW 0x8 329/* 3-wire total control */ 330#define bRFSI_3Wire 0xf 331#define bRFSI_RFENV 0x10 332#define bRFSI_TRSW 0x20 333#define bRFSI_TRSWB 0x40 334#define bRFSI_ANTSW 0x100 335#define bRFSI_ANTSWB 0x200 336#define bRFSI_PAPE 0x400 337#define bRFSI_PAPE5G 0x800 338#define bBandSelect 0x1 339#define bHTSIG2_GI 0x80 340#define bHTSIG2_Smoothing 0x01 341#define bHTSIG2_Sounding 0x02 342#define bHTSIG2_Aggreaton 0x08 343#define bHTSIG2_STBC 0x30 344#define bHTSIG2_AdvCoding 0x40 345#define bHTSIG2_NumOfHTLTF 0x300 346#define bHTSIG2_CRC8 0x3fc 347#define bHTSIG1_MCS 0x7f 348#define bHTSIG1_BandWidth 0x80 349#define bHTSIG1_HTLength 0xffff 350#define bLSIG_Rate 0xf 351#define bLSIG_Reserved 0x10 352#define bLSIG_Length 0x1fffe 353#define bLSIG_Parity 0x20 354#define bCCKRxPhase 0x4 355#define bLSSIReadAddress 0x3f000000 /* LSSI "read" address */ 356#define bLSSIReadEdge 0x80000000 /* LSSI "read" edge signal */ 357#define bLSSIReadBackData 0xfff 358#define bLSSIReadOKFlag 0x1000 359#define bCCKSampleRate 0x8 /* 0: 44 MHz, 1: 88MHz */ 360 361#define bRegulator0Standby 0x1 362#define bRegulatorPLLStandby 0x2 363#define bRegulator1Standby 0x4 364#define bPLLPowerUp 0x8 365#define bDPLLPowerUp 0x10 366#define bDA10PowerUp 0x20 367#define bAD7PowerUp 0x200 368#define bDA6PowerUp 0x2000 369#define bXtalPowerUp 0x4000 370#define b40MDClkPowerUP 0x8000 371#define bDA6DebugMode 0x20000 372#define bDA6Swing 0x380000 373#define bADClkPhase 0x4000000 374#define b80MClkDelay 0x18000000 375#define bAFEWatchDogEnable 0x20000000 376#define bXtalCap 0x0f000000 377#define bXtalCap01 0xc0000000 378#define bXtalCap23 0x3 379#define bXtalCap92x 0x0f000000 380#define bIntDifClkEnable 0x400 381#define bExtSigClkEnable 0x800 382#define bBandgapMbiasPowerUp 0x10000 383#define bAD11SHGain 0xc0000 384#define bAD11InputRange 0x700000 385#define bAD11OPCurrent 0x3800000 386#define bIPathLoopback 0x4000000 387#define bQPathLoopback 0x8000000 388#define bAFELoopback 0x10000000 389#define bDA10Swing 0x7e0 390#define bDA10Reverse 0x800 391#define bDAClkSource 0x1000 392#define bAD7InputRange 0x6000 393#define bAD7Gain 0x38000 394#define bAD7OutputCMMode 0x40000 395#define bAD7InputCMMode 0x380000 396#define bAD7Current 0xc00000 397#define bRegulatorAdjust 0x7000000 398#define bAD11PowerUpAtTx 0x1 399#define bDA10PSAtTx 0x10 400#define bAD11PowerUpAtRx 0x100 401#define bDA10PSAtRx 0x1000 402 403#define bCCKRxAGCFormat 0x200 404 405#define bPSDFFTSamplepPoint 0xc000 406#define bPSDAverageNum 0x3000 407#define bIQPathControl 0xc00 408#define bPSDFreq 0x3ff 409#define bPSDAntennaPath 0x30 410#define bPSDIQSwitch 0x40 411#define bPSDRxTrigger 0x400000 412#define bPSDTxTrigger 0x80000000 413#define bPSDSineToneScale 0x7f000000 414#define bPSDReport 0xffff 415 416/* Page 8 */ 417#define bOFDMTxSC 0x30000000 418#define bCCKTxOn 0x1 419#define bOFDMTxOn 0x2 420/* Reset debug page and also HWord, LWord */ 421#define bDebugPage 0xfff 422/* Reset debug page and LWord */ 423#define bDebugItem 0xff 424#define bAntL 0x10 425#define bAntNonHT 0x100 426#define bAntHT1 0x1000 427#define bAntHT2 0x10000 428#define bAntHT1S1 0x100000 429#define bAntNonHTS1 0x1000000 430 431/* Page a */ 432#define bCCKBBMode 0x3 433#define bCCKTxPowerSaving 0x80 434#define bCCKRxPowerSaving 0x40 435#define bCCKSideBand 0x10 436#define bCCKScramble 0x8 437#define bCCKAntDiversity 0x8000 438#define bCCKCarrierRecovery 0x4000 439#define bCCKTxRate 0x3000 440#define bCCKDCCancel 0x0800 441#define bCCKISICancel 0x0400 442#define bCCKMatchFilter 0x0200 443#define bCCKEqualizer 0x0100 444#define bCCKPreambleDetect 0x800000 445#define bCCKFastFalseCCA 0x400000 446#define bCCKChEstStart 0x300000 447#define bCCKCCACount 0x080000 448#define bCCKcs_lim 0x070000 449#define bCCKBistMode 0x80000000 450#define bCCKCCAMask 0x40000000 451#define bCCKTxDACPhase 0x4 452#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 453#define bCCKr_cp_mode0 0x0100 454#define bCCKTxDCOffset 0xf0 455#define bCCKRxDCOffset 0xf 456#define bCCKCCAMode 0xc000 457#define bCCKFalseCS_lim 0x3f00 458#define bCCKCS_ratio 0xc00000 459#define bCCKCorgBit_sel 0x300000 460#define bCCKPD_lim 0x0f0000 461#define bCCKNewCCA 0x80000000 462#define bCCKRxHPofIG 0x8000 463#define bCCKRxIG 0x7f00 464#define bCCKLNAPolarity 0x800000 465#define bCCKRx1stGain 0x7f0000 466/* CCK Rx Initial gain polarity */ 467#define bCCKRFExtend 0x20000000 468#define bCCKRxAGCSatLevel 0x1f000000 469#define bCCKRxAGCSatCount 0xe0 470/* AGCSAmp_dly */ 471#define bCCKRxRFSettle 0x1f 472#define bCCKFixedRxAGC 0x8000 473/*#define bCCKRxAGCFormat 0x4000 remove to HSSI register 0x824 */ 474#define bCCKAntennaPolarity 0x2000 475#define bCCKTxFilterType 0x0c00 476#define bCCKRxAGCReportType 0x0300 477#define bCCKRxDAGCEn 0x80000000 478#define bCCKRxDAGCPeriod 0x20000000 479#define bCCKRxDAGCSatLevel 0x1f000000 480#define bCCKTimingRecovery 0x800000 481#define bCCKTxC0 0x3f0000 482#define bCCKTxC1 0x3f000000 483#define bCCKTxC2 0x3f 484#define bCCKTxC3 0x3f00 485#define bCCKTxC4 0x3f0000 486#define bCCKTxC5 0x3f000000 487#define bCCKTxC6 0x3f 488#define bCCKTxC7 0x3f00 489#define bCCKDebugPort 0xff0000 490#define bCCKDACDebug 0x0f000000 491#define bCCKFalseAlarmEnable 0x8000 492#define bCCKFalseAlarmRead 0x4000 493#define bCCKTRSSI 0x7f 494#define bCCKRxAGCReport 0xfe 495#define bCCKRxReport_AntSel 0x80000000 496#define bCCKRxReport_MFOff 0x40000000 497#define bCCKRxRxReport_SQLoss 0x20000000 498#define bCCKRxReport_Pktloss 0x10000000 499#define bCCKRxReport_Lockedbit 0x08000000 500#define bCCKRxReport_RateError 0x04000000 501#define bCCKRxReport_RxRate 0x03000000 502#define bCCKRxFACounterLower 0xff 503#define bCCKRxFACounterUpper 0xff000000 504#define bCCKRxHPAGCStart 0xe000 505#define bCCKRxHPAGCFinal 0x1c00 506 507#define bCCKRxFalseAlarmEnable 0x8000 508#define bCCKFACounterFreeze 0x4000 509 510#define bCCKTxPathSel 0x10000000 511#define bCCKDefaultRxPath 0xc000000 512#define bCCKOptionRxPath 0x3000000 513 514/* Page c */ 515#define bNumOfSTF 0x3 516#define bShift_L 0xc0 517#define bGI_TH 0xc 518#define bRxPathA 0x1 519#define bRxPathB 0x2 520#define bRxPathC 0x4 521#define bRxPathD 0x8 522#define bTxPathA 0x1 523#define bTxPathB 0x2 524#define bTxPathC 0x4 525#define bTxPathD 0x8 526#define bTRSSIFreq 0x200 527#define bADCBackoff 0x3000 528#define bDFIRBackoff 0xc000 529#define bTRSSILatchPhase 0x10000 530#define bRxIDCOffset 0xff 531#define bRxQDCOffset 0xff00 532#define bRxDFIRMode 0x1800000 533#define bRxDCNFType 0xe000000 534#define bRXIQImb_A 0x3ff 535#define bRXIQImb_B 0xfc00 536#define bRXIQImb_C 0x3f0000 537#define bRXIQImb_D 0xffc00000 538#define bDC_dc_Notch 0x60000 539#define bRxNBINotch 0x1f000000 540#define bPD_TH 0xf 541#define bPD_TH_Opt2 0xc000 542#define bPWED_TH 0x700 543#define bIfMF_Win_L 0x800 544#define bPD_Option 0x1000 545#define bMF_Win_L 0xe000 546#define bBW_Search_L 0x30000 547#define bwin_enh_L 0xc0000 548#define bBW_TH 0x700000 549#define bED_TH2 0x3800000 550#define bBW_option 0x4000000 551#define bRatio_TH 0x18000000 552#define bWindow_L 0xe0000000 553#define bSBD_Option 0x1 554#define bFrame_TH 0x1c 555#define bFS_Option 0x60 556#define bDC_Slope_check 0x80 557#define bFGuard_Counter_DC_L 0xe00 558#define bFrame_Weight_Short 0x7000 559#define bSub_Tune 0xe00000 560#define bFrame_DC_Length 0xe000000 561#define bSBD_start_offset 0x30000000 562#define bFrame_TH_2 0x7 563#define bFrame_GI2_TH 0x38 564#define bGI2_Sync_en 0x40 565#define bSarch_Short_Early 0x300 566#define bSarch_Short_Late 0xc00 567#define bSarch_GI2_Late 0x70000 568#define bCFOAntSum 0x1 569#define bCFOAcc 0x2 570#define bCFOStartOffset 0xc 571#define bCFOLookBack 0x70 572#define bCFOSumWeight 0x80 573#define bDAGCEnable 0x10000 574#define bTXIQImb_A 0x3ff 575#define bTXIQImb_B 0xfc00 576#define bTXIQImb_C 0x3f0000 577#define bTXIQImb_D 0xffc00000 578#define bTxIDCOffset 0xff 579#define bTxQDCOffset 0xff00 580#define bTxDFIRMode 0x10000 581#define bTxPesudoNoiseOn 0x4000000 582#define bTxPesudoNoise_A 0xff 583#define bTxPesudoNoise_B 0xff00 584#define bTxPesudoNoise_C 0xff0000 585#define bTxPesudoNoise_D 0xff000000 586#define bCCADropOption 0x20000 587#define bCCADropThres 0xfff00000 588#define bEDCCA_H 0xf 589#define bEDCCA_L 0xf0 590#define bLambda_ED 0x300 591#define bRxInitialGain 0x7f 592#define bRxAntDivEn 0x80 593#define bRxAGCAddressForLNA 0x7f00 594#define bRxHighPowerFlow 0x8000 595#define bRxAGCFreezeThres 0xc0000 596#define bRxFreezeStep_AGC1 0x300000 597#define bRxFreezeStep_AGC2 0xc00000 598#define bRxFreezeStep_AGC3 0x3000000 599#define bRxFreezeStep_AGC0 0xc000000 600#define bRxRssi_Cmp_En 0x10000000 601#define bRxQuickAGCEn 0x20000000 602#define bRxAGCFreezeThresMode 0x40000000 603#define bRxOverFlowCheckType 0x80000000 604#define bRxAGCShift 0x7f 605#define bTRSW_Tri_Only 0x80 606#define bPowerThres 0x300 607#define bRxAGCEn 0x1 608#define bRxAGCTogetherEn 0x2 609#define bRxAGCMin 0x4 610#define bRxHP_Ini 0x7 611#define bRxHP_TRLNA 0x70 612#define bRxHP_RSSI 0x700 613#define bRxHP_BBP1 0x7000 614#define bRxHP_BBP2 0x70000 615#define bRxHP_BBP3 0x700000 616/* The threshold for high power */ 617#define bRSSI_H 0x7f0000 618/* The threshold for ant diversity */ 619#define bRSSI_Gen 0x7f000000 620#define bRxSettle_TRSW 0x7 621#define bRxSettle_LNA 0x38 622#define bRxSettle_RSSI 0x1c0 623#define bRxSettle_BBP 0xe00 624#define bRxSettle_RxHP 0x7000 625#define bRxSettle_AntSW_RSSI 0x38000 626#define bRxSettle_AntSW 0xc0000 627#define bRxProcessTime_DAGC 0x300000 628#define bRxSettle_HSSI 0x400000 629#define bRxProcessTime_BBPPW 0x800000 630#define bRxAntennaPowerShift 0x3000000 631#define bRSSITableSelect 0xc000000 632#define bRxHP_Final 0x7000000 633#define bRxHTSettle_BBP 0x7 634#define bRxHTSettle_HSSI 0x8 635#define bRxHTSettle_RxHP 0x70 636#define bRxHTSettle_BBPPW 0x80 637#define bRxHTSettle_Idle 0x300 638#define bRxHTSettle_Reserved 0x1c00 639#define bRxHTRxHPEn 0x8000 640#define bRxHTAGCFreezeThres 0x30000 641#define bRxHTAGCTogetherEn 0x40000 642#define bRxHTAGCMin 0x80000 643#define bRxHTAGCEn 0x100000 644#define bRxHTDAGCEn 0x200000 645#define bRxHTRxHP_BBP 0x1c00000 646#define bRxHTRxHP_Final 0xe0000000 647#define bRxPWRatioTH 0x3 648#define bRxPWRatioEn 0x4 649#define bRxMFHold 0x3800 650#define bRxPD_Delay_TH1 0x38 651#define bRxPD_Delay_TH2 0x1c0 652#define bRxPD_DC_COUNT_MAX 0x600 653/*#define bRxMF_Hold 0x3800*/ 654#define bRxPD_Delay_TH 0x8000 655#define bRxProcess_Delay 0xf0000 656#define bRxSearchrange_GI2_Early 0x700000 657#define bRxFrame_Guard_Counter_L 0x3800000 658#define bRxSGI_Guard_L 0xc000000 659#define bRxSGI_Search_L 0x30000000 660#define bRxSGI_TH 0xc0000000 661#define bDFSCnt0 0xff 662#define bDFSCnt1 0xff00 663#define bDFSFlag 0xf0000 664 665#define bMFWeightSum 0x300000 666#define bMinIdxTH 0x7f000000 667 668#define bDAFormat 0x40000 669 670#define bTxChEmuEnable 0x01000000 671 672#define bTRSWIsolation_A 0x7f 673#define bTRSWIsolation_B 0x7f00 674#define bTRSWIsolation_C 0x7f0000 675#define bTRSWIsolation_D 0x7f000000 676 677#define bExtLNAGain 0x7c00 678 679/* Page d */ 680#define bSTBCEn 0x4 681#define bAntennaMapping 0x10 682#define bNss 0x20 683#define bCFOAntSumD 0x200 684#define bPHYCounterReset 0x8000000 685#define bCFOReportGet 0x4000000 686#define bOFDMContinueTx 0x10000000 687#define bOFDMSingleCarrier 0x20000000 688#define bOFDMSingleTone 0x40000000 689/* #define bRxPath1 0x01 690 * #define bRxPath2 0x02 691 * #define bRxPath3 0x04 692 * #define bRxPath4 0x08 693 * #define bTxPath1 0x10 694 * #define bTxPath2 0x20 695 */ 696#define bHTDetect 0x100 697#define bCFOEn 0x10000 698#define bCFOValue 0xfff00000 699#define bSigTone_Re 0x3f 700#define bSigTone_Im 0x7f00 701#define bCounter_CCA 0xffff 702#define bCounter_ParityFail 0xffff0000 703#define bCounter_RateIllegal 0xffff 704#define bCounter_CRC8Fail 0xffff0000 705#define bCounter_MCSNoSupport 0xffff 706#define bCounter_FastSync 0xffff 707#define bShortCFO 0xfff 708#define bShortCFOTLength 12 /* total */ 709#define bShortCFOFLength 11 /* fraction */ 710#define bLongCFO 0x7ff 711#define bLongCFOTLength 11 712#define bLongCFOFLength 11 713#define bTailCFO 0x1fff 714#define bTailCFOTLength 13 715#define bTailCFOFLength 12 716 717#define bmax_en_pwdB 0xffff 718#define bCC_power_dB 0xffff0000 719#define bnoise_pwdB 0xffff 720#define bPowerMeasTLength 10 721#define bPowerMeasFLength 3 722#define bRx_HT_BW 0x1 723#define bRxSC 0x6 724#define bRx_HT 0x8 725 726#define bNB_intf_det_on 0x1 727#define bIntf_win_len_cfg 0x30 728#define bNB_Intf_TH_cfg 0x1c0 729 730#define bRFGain 0x3f 731#define bTableSel 0x40 732#define bTRSW 0x80 733 734#define bRxSNR_A 0xff 735#define bRxSNR_B 0xff00 736#define bRxSNR_C 0xff0000 737#define bRxSNR_D 0xff000000 738#define bSNREVMTLength 8 739#define bSNREVMFLength 1 740 741#define bCSI1st 0xff 742#define bCSI2nd 0xff00 743#define bRxEVM1st 0xff0000 744#define bRxEVM2nd 0xff000000 745 746#define bSIGEVM 0xff 747#define bPWDB 0xff00 748#define bSGIEN 0x10000 749 750#define bSFactorQAM1 0xf 751#define bSFactorQAM2 0xf0 752#define bSFactorQAM3 0xf00 753#define bSFactorQAM4 0xf000 754#define bSFactorQAM5 0xf0000 755#define bSFactorQAM6 0xf0000 756#define bSFactorQAM7 0xf00000 757#define bSFactorQAM8 0xf000000 758#define bSFactorQAM9 0xf0000000 759#define bCSIScheme 0x100000 760 761#define bNoiseLvlTopSet 0x3 762#define bChSmooth 0x4 763#define bChSmoothCfg1 0x38 764#define bChSmoothCfg2 0x1c0 765#define bChSmoothCfg3 0xe00 766#define bChSmoothCfg4 0x7000 767#define bMRCMode 0x800000 768#define bTHEVMCfg 0x7000000 769 770#define bLoopFitType 0x1 771#define bUpdCFO 0x40 772#define bUpdCFOOffData 0x80 773#define bAdvUpdCFO 0x100 774#define bAdvTimeCtrl 0x800 775#define bUpdClko 0x1000 776#define bFC 0x6000 777#define bTrackingMode 0x8000 778#define bPhCmpEnable 0x10000 779#define bUpdClkoLTF 0x20000 780#define bComChCFO 0x40000 781#define bCSIEstiMode 0x80000 782#define bAdvUpdEqz 0x100000 783#define bUChCfg 0x7000000 784#define bUpdEqz 0x8000000 785 786/* Page e */ 787#define bTxAGCRate18_06 0x7f7f7f7f 788#define bTxAGCRate54_24 0x7f7f7f7f 789#define bTxAGCRateMCS32 0x7f 790#define bTxAGCRateCCK 0x7f00 791#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f 792#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f 793#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f 794#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f 795 796#define bRxPesudoNoiseOn 0x20000000 /* Rx Pseduo noise */ 797#define bRxPesudoNoise_A 0xff 798#define bRxPesudoNoise_B 0xff00 799#define bRxPesudoNoise_C 0xff0000 800#define bRxPesudoNoise_D 0xff000000 801#define bPesudoNoiseState_A 0xffff 802#define bPesudoNoiseState_B 0xffff0000 803#define bPesudoNoiseState_C 0xffff 804#define bPesudoNoiseState_D 0xffff0000 805 806/* RF Zebra 1 */ 807#define bZebra1_HSSIEnable 0x8 808#define bZebra1_TRxControl 0xc00 809#define bZebra1_TRxGainSetting 0x07f 810#define bZebra1_RxCorner 0xc00 811#define bZebra1_TxChargePump 0x38 812#define bZebra1_RxChargePump 0x7 813#define bZebra1_ChannelNum 0xf80 814#define bZebra1_TxLPFBW 0x400 815#define bZebra1_RxLPFBW 0x600 816 817/* Zebra4 */ 818#define bRTL8256RegModeCtrl1 0x100 819#define bRTL8256RegModeCtrl0 0x40 820#define bRTL8256_TxLPFBW 0x18 821#define bRTL8256_RxLPFBW 0x600 822 823/* RTL8258 */ 824#define bRTL8258_TxLPFBW 0xc 825#define bRTL8258_RxLPFBW 0xc00 826#define bRTL8258_RSSILPFBW 0xc0 827 828/* byte enable for sb_write */ 829#define bByte0 0x1 830#define bByte1 0x2 831#define bByte2 0x4 832#define bByte3 0x8 833#define bWord0 0x3 834#define bWord1 0xc 835#define bDWord 0xf 836 837/* for PutRegsetting & GetRegSetting BitMask */ 838#define bMaskByte0 0xff 839#define bMaskByte1 0xff00 840#define bMaskByte2 0xff0000 841#define bMaskByte3 0xff000000 842#define bMaskHWord 0xffff0000 843#define bMaskLWord 0x0000ffff 844#define bMaskDWord 0xffffffff 845 846/* for PutRFRegsetting & GetRFRegSetting BitMask */ 847#define bMask12Bits 0xfff 848 849#define bEnable 0x1 850#define bDisable 0x0 851 852#define LeftAntenna 0x0 853#define RightAntenna 0x1 854 855#define tCheckTxStatus 500 /* 500 ms */ 856#define tUpdateRxCounter 100 /* 100 ms */ 857 858#define rateCCK 0 859#define rateOFDM 1 860#define rateHT 2 861 862#define bPMAC_End 0x1ff /* define Register-End */ 863#define bFPGAPHY0_End 0x8ff 864#define bFPGAPHY1_End 0x9ff 865#define bCCKPHY0_End 0xaff 866#define bOFDMPHY0_End 0xcff 867#define bOFDMPHY1_End 0xdff 868 869 870#define bPMACControl 0x0 871#define bWMACControl 0x1 872#define bWNICControl 0x2 873 874#define PathA 0x0 875#define PathB 0x1 876#define PathC 0x2 877#define PathD 0x3 878 879#define rRTL8256RxMixerPole 0xb 880#define bZebraRxMixerPole 0x6 881#define rRTL8256TxBBOPBias 0x9 882#define bRTL8256TxBBOPBias 0x400 883#define rRTL8256TxBBBW 19 884#define bRTL8256TxBBBW 0x18 885 886#endif 887