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12#include <linux/errno.h>
13#include <linux/tty.h>
14#include <linux/tty_flip.h>
15#include <linux/serial.h>
16#include <linux/circ_buf.h>
17#include <linux/serial_reg.h>
18#include <linux/module.h>
19#include <linux/pci.h>
20#include <linux/ioc4.h>
21#include <linux/serial_core.h>
22#include <linux/slab.h>
23
24
25
26
27
28#define IOC4_NUM_SERIAL_PORTS 4
29#define IOC4_NUM_CARDS 8
30
31#define GET_SIO_IR(_n) (_n == 0) ? (IOC4_SIO_IR_S0) : \
32 (_n == 1) ? (IOC4_SIO_IR_S1) : \
33 (_n == 2) ? (IOC4_SIO_IR_S2) : \
34 (IOC4_SIO_IR_S3)
35
36#define GET_OTHER_IR(_n) (_n == 0) ? (IOC4_OTHER_IR_S0_MEMERR) : \
37 (_n == 1) ? (IOC4_OTHER_IR_S1_MEMERR) : \
38 (_n == 2) ? (IOC4_OTHER_IR_S2_MEMERR) : \
39 (IOC4_OTHER_IR_S3_MEMERR)
40
41
42
43
44
45
46
47
48
49#define IOC4_PCI_ERR_ADDR_L 0x000
50#define IOC4_PCI_ERR_ADDR_VLD (0x1 << 0)
51#define IOC4_PCI_ERR_ADDR_MST_ID_MSK (0xf << 1)
52#define IOC4_PCI_ERR_ADDR_MST_NUM_MSK (0xe << 1)
53#define IOC4_PCI_ERR_ADDR_MST_TYP_MSK (0x1 << 1)
54#define IOC4_PCI_ERR_ADDR_MUL_ERR (0x1 << 5)
55#define IOC4_PCI_ERR_ADDR_ADDR_MSK (0x3ffffff << 6)
56
57
58#define IOC4_SIO_INTR_TYPE 0
59#define IOC4_OTHER_INTR_TYPE 1
60#define IOC4_NUM_INTR_TYPES 2
61
62
63#define IOC4_SIO_IR_S0_TX_MT 0x00000001
64#define IOC4_SIO_IR_S0_RX_FULL 0x00000002
65#define IOC4_SIO_IR_S0_RX_HIGH 0x00000004
66#define IOC4_SIO_IR_S0_RX_TIMER 0x00000008
67#define IOC4_SIO_IR_S0_DELTA_DCD 0x00000010
68#define IOC4_SIO_IR_S0_DELTA_CTS 0x00000020
69#define IOC4_SIO_IR_S0_INT 0x00000040
70#define IOC4_SIO_IR_S0_TX_EXPLICIT 0x00000080
71#define IOC4_SIO_IR_S1_TX_MT 0x00000100
72#define IOC4_SIO_IR_S1_RX_FULL 0x00000200
73#define IOC4_SIO_IR_S1_RX_HIGH 0x00000400
74#define IOC4_SIO_IR_S1_RX_TIMER 0x00000800
75#define IOC4_SIO_IR_S1_DELTA_DCD 0x00001000
76#define IOC4_SIO_IR_S1_DELTA_CTS 0x00002000
77#define IOC4_SIO_IR_S1_INT 0x00004000
78#define IOC4_SIO_IR_S1_TX_EXPLICIT 0x00008000
79#define IOC4_SIO_IR_S2_TX_MT 0x00010000
80#define IOC4_SIO_IR_S2_RX_FULL 0x00020000
81#define IOC4_SIO_IR_S2_RX_HIGH 0x00040000
82#define IOC4_SIO_IR_S2_RX_TIMER 0x00080000
83#define IOC4_SIO_IR_S2_DELTA_DCD 0x00100000
84#define IOC4_SIO_IR_S2_DELTA_CTS 0x00200000
85#define IOC4_SIO_IR_S2_INT 0x00400000
86#define IOC4_SIO_IR_S2_TX_EXPLICIT 0x00800000
87#define IOC4_SIO_IR_S3_TX_MT 0x01000000
88#define IOC4_SIO_IR_S3_RX_FULL 0x02000000
89#define IOC4_SIO_IR_S3_RX_HIGH 0x04000000
90#define IOC4_SIO_IR_S3_RX_TIMER 0x08000000
91#define IOC4_SIO_IR_S3_DELTA_DCD 0x10000000
92#define IOC4_SIO_IR_S3_DELTA_CTS 0x20000000
93#define IOC4_SIO_IR_S3_INT 0x40000000
94#define IOC4_SIO_IR_S3_TX_EXPLICIT 0x80000000
95
96
97#define IOC4_SIO_IR_S0 (IOC4_SIO_IR_S0_TX_MT | \
98 IOC4_SIO_IR_S0_RX_FULL | \
99 IOC4_SIO_IR_S0_RX_HIGH | \
100 IOC4_SIO_IR_S0_RX_TIMER | \
101 IOC4_SIO_IR_S0_DELTA_DCD | \
102 IOC4_SIO_IR_S0_DELTA_CTS | \
103 IOC4_SIO_IR_S0_INT | \
104 IOC4_SIO_IR_S0_TX_EXPLICIT)
105#define IOC4_SIO_IR_S1 (IOC4_SIO_IR_S1_TX_MT | \
106 IOC4_SIO_IR_S1_RX_FULL | \
107 IOC4_SIO_IR_S1_RX_HIGH | \
108 IOC4_SIO_IR_S1_RX_TIMER | \
109 IOC4_SIO_IR_S1_DELTA_DCD | \
110 IOC4_SIO_IR_S1_DELTA_CTS | \
111 IOC4_SIO_IR_S1_INT | \
112 IOC4_SIO_IR_S1_TX_EXPLICIT)
113#define IOC4_SIO_IR_S2 (IOC4_SIO_IR_S2_TX_MT | \
114 IOC4_SIO_IR_S2_RX_FULL | \
115 IOC4_SIO_IR_S2_RX_HIGH | \
116 IOC4_SIO_IR_S2_RX_TIMER | \
117 IOC4_SIO_IR_S2_DELTA_DCD | \
118 IOC4_SIO_IR_S2_DELTA_CTS | \
119 IOC4_SIO_IR_S2_INT | \
120 IOC4_SIO_IR_S2_TX_EXPLICIT)
121#define IOC4_SIO_IR_S3 (IOC4_SIO_IR_S3_TX_MT | \
122 IOC4_SIO_IR_S3_RX_FULL | \
123 IOC4_SIO_IR_S3_RX_HIGH | \
124 IOC4_SIO_IR_S3_RX_TIMER | \
125 IOC4_SIO_IR_S3_DELTA_DCD | \
126 IOC4_SIO_IR_S3_DELTA_CTS | \
127 IOC4_SIO_IR_S3_INT | \
128 IOC4_SIO_IR_S3_TX_EXPLICIT)
129
130
131#define IOC4_OTHER_IR_ATA_INT 0x00000001
132#define IOC4_OTHER_IR_ATA_MEMERR 0x00000002
133#define IOC4_OTHER_IR_S0_MEMERR 0x00000004
134#define IOC4_OTHER_IR_S1_MEMERR 0x00000008
135#define IOC4_OTHER_IR_S2_MEMERR 0x00000010
136#define IOC4_OTHER_IR_S3_MEMERR 0x00000020
137#define IOC4_OTHER_IR_KBD_INT 0x00000040
138#define IOC4_OTHER_IR_RESERVED 0x007fff80
139#define IOC4_OTHER_IR_RT_INT 0x00800000
140#define IOC4_OTHER_IR_GEN_INT 0xff000000
141
142#define IOC4_OTHER_IR_SER_MEMERR (IOC4_OTHER_IR_S0_MEMERR | IOC4_OTHER_IR_S1_MEMERR | \
143 IOC4_OTHER_IR_S2_MEMERR | IOC4_OTHER_IR_S3_MEMERR)
144
145
146#define IOC4_SIO_CR_CMD_PULSE_SHIFT 0
147#define IOC4_SIO_CR_ARB_DIAG_TX0 0x00000000
148#define IOC4_SIO_CR_ARB_DIAG_RX0 0x00000010
149#define IOC4_SIO_CR_ARB_DIAG_TX1 0x00000020
150#define IOC4_SIO_CR_ARB_DIAG_RX1 0x00000030
151#define IOC4_SIO_CR_ARB_DIAG_TX2 0x00000040
152#define IOC4_SIO_CR_ARB_DIAG_RX2 0x00000050
153#define IOC4_SIO_CR_ARB_DIAG_TX3 0x00000060
154#define IOC4_SIO_CR_ARB_DIAG_RX3 0x00000070
155#define IOC4_SIO_CR_SIO_DIAG_IDLE 0x00000080
156
157
158#define IOC4_GPCR_UART0_MODESEL 0x10
159
160#define IOC4_GPCR_UART1_MODESEL 0x20
161
162#define IOC4_GPCR_UART2_MODESEL 0x40
163
164#define IOC4_GPCR_UART3_MODESEL 0x80
165
166
167#define IOC4_GPPR_UART0_MODESEL_PIN 4
168
169#define IOC4_GPPR_UART1_MODESEL_PIN 5
170
171#define IOC4_GPPR_UART2_MODESEL_PIN 6
172
173#define IOC4_GPPR_UART3_MODESEL_PIN 7
174
175
176
177#define IOC4_RXSB_OVERRUN 0x01
178#define IOC4_RXSB_PAR_ERR 0x02
179#define IOC4_RXSB_FRAME_ERR 0x04
180#define IOC4_RXSB_BREAK 0x08
181#define IOC4_RXSB_CTS 0x10
182#define IOC4_RXSB_DCD 0x20
183#define IOC4_RXSB_MODEM_VALID 0x40
184#define IOC4_RXSB_DATA_VALID 0x80
185
186
187
188#define IOC4_TXCB_INT_WHEN_DONE 0x20
189#define IOC4_TXCB_INVALID 0x00
190#define IOC4_TXCB_VALID 0x40
191#define IOC4_TXCB_MCR 0x80
192#define IOC4_TXCB_DELAY 0xc0
193
194
195#define IOC4_SBBR_L_SIZE 0x00000001
196
197
198#define IOC4_SSCR_RX_THRESHOLD 0x000001ff
199#define IOC4_SSCR_TX_TIMER_BUSY 0x00010000
200#define IOC4_SSCR_HFC_EN 0x00020000
201#define IOC4_SSCR_RX_RING_DCD 0x00040000
202#define IOC4_SSCR_RX_RING_CTS 0x00080000
203#define IOC4_SSCR_DIAG 0x00200000
204#define IOC4_SSCR_RX_DRAIN 0x08000000
205#define IOC4_SSCR_DMA_EN 0x10000000
206#define IOC4_SSCR_DMA_PAUSE 0x20000000
207#define IOC4_SSCR_PAUSE_STATE 0x40000000
208#define IOC4_SSCR_RESET 0x80000000
209
210
211#define IOC4_PROD_CONS_PTR_4K 0x00000ff8
212#define IOC4_PROD_CONS_PTR_1K 0x000003f8
213#define IOC4_PROD_CONS_PTR_OFF 3
214
215
216#define IOC4_SRCIR_ARM 0x80000000
217
218
219#define IOC4_SHADOW_DR 0x00000001
220#define IOC4_SHADOW_OE 0x00000002
221#define IOC4_SHADOW_PE 0x00000004
222#define IOC4_SHADOW_FE 0x00000008
223#define IOC4_SHADOW_BI 0x00000010
224#define IOC4_SHADOW_THRE 0x00000020
225#define IOC4_SHADOW_TEMT 0x00000040
226#define IOC4_SHADOW_RFCE 0x00000080
227#define IOC4_SHADOW_DCTS 0x00010000
228#define IOC4_SHADOW_DDCD 0x00080000
229#define IOC4_SHADOW_CTS 0x00100000
230#define IOC4_SHADOW_DCD 0x00800000
231#define IOC4_SHADOW_DTR 0x01000000
232#define IOC4_SHADOW_RTS 0x02000000
233#define IOC4_SHADOW_OUT1 0x04000000
234#define IOC4_SHADOW_OUT2 0x08000000
235#define IOC4_SHADOW_LOOP 0x10000000
236
237
238#define IOC4_SRTR_CNT 0x00000fff
239#define IOC4_SRTR_CNT_VAL 0x0fff0000
240#define IOC4_SRTR_CNT_VAL_SHIFT 16
241#define IOC4_SRTR_HZ 16000
242
243
244struct ioc4_serialregs {
245 uint32_t sscr;
246 uint32_t stpir;
247 uint32_t stcir;
248 uint32_t srpir;
249 uint32_t srcir;
250 uint32_t srtr;
251 uint32_t shadow;
252};
253
254
255struct ioc4_uartregs {
256 char i4u_lcr;
257 union {
258 char iir;
259 char fcr;
260 } u3;
261 union {
262 char ier;
263 char dlm;
264 } u2;
265 union {
266 char rbr;
267 char thr;
268 char dll;
269 } u1;
270 char i4u_scr;
271 char i4u_msr;
272 char i4u_lsr;
273 char i4u_mcr;
274};
275
276
277#define i4u_dll u1.dll
278#define i4u_ier u2.ier
279#define i4u_dlm u2.dlm
280#define i4u_fcr u3.fcr
281
282
283struct ioc4_serial {
284 uint32_t sbbr01_l;
285 uint32_t sbbr01_h;
286 uint32_t sbbr23_l;
287 uint32_t sbbr23_h;
288
289 struct ioc4_serialregs port_0;
290 struct ioc4_serialregs port_1;
291 struct ioc4_serialregs port_2;
292 struct ioc4_serialregs port_3;
293 struct ioc4_uartregs uart_0;
294 struct ioc4_uartregs uart_1;
295 struct ioc4_uartregs uart_2;
296 struct ioc4_uartregs uart_3;
297};
298
299
300#define IOC4_SER_XIN_CLK_66 66666667
301#define IOC4_SER_XIN_CLK_33 33333333
302
303#define IOC4_W_IES 0
304#define IOC4_W_IEC 1
305
306typedef void ioc4_intr_func_f(void *, uint32_t);
307typedef ioc4_intr_func_f *ioc4_intr_func_t;
308
309static unsigned int Num_of_ioc4_cards;
310
311
312
313#define DPRINT_CONFIG(_x...) ;
314
315
316
317#define WAKEUP_CHARS 256
318
319
320#define IOC4_MAX_CHARS 256
321#define IOC4_FIFO_CHARS 255
322
323
324#define DEVICE_NAME_RS232 "ttyIOC"
325#define DEVICE_NAME_RS422 "ttyAIOC"
326#define DEVICE_MAJOR 204
327#define DEVICE_MINOR_RS232 50
328#define DEVICE_MINOR_RS422 84
329
330
331
332#define IOC4_SERIAL_OFFSET 0x300
333
334
335#define NCS_BREAK 0x1
336#define NCS_PARITY 0x2
337#define NCS_FRAMING 0x4
338#define NCS_OVERRUN 0x8
339
340
341#define MIN_BAUD_SUPPORTED 1200
342#define MAX_BAUD_SUPPORTED 115200
343
344
345#define PROTO_RS232 3
346#define PROTO_RS422 7
347
348
349#define N_DATA_READY 0x01
350#define N_OUTPUT_LOWAT 0x02
351#define N_BREAK 0x04
352#define N_PARITY_ERROR 0x08
353#define N_FRAMING_ERROR 0x10
354#define N_OVERRUN_ERROR 0x20
355#define N_DDCD 0x40
356#define N_DCTS 0x80
357
358#define N_ALL_INPUT (N_DATA_READY | N_BREAK | \
359 N_PARITY_ERROR | N_FRAMING_ERROR | \
360 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
361
362#define N_ALL_OUTPUT N_OUTPUT_LOWAT
363
364#define N_ALL_ERRORS (N_PARITY_ERROR | N_FRAMING_ERROR | N_OVERRUN_ERROR)
365
366#define N_ALL (N_DATA_READY | N_OUTPUT_LOWAT | N_BREAK | \
367 N_PARITY_ERROR | N_FRAMING_ERROR | \
368 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
369
370#define SER_DIVISOR(_x, clk) (((clk) + (_x) * 8) / ((_x) * 16))
371#define DIVISOR_TO_BAUD(div, clk) ((clk) / 16 / (div))
372
373
374#define LCR_MASK_BITS_CHAR (UART_LCR_WLEN5 | UART_LCR_WLEN6 \
375 | UART_LCR_WLEN7 | UART_LCR_WLEN8)
376#define LCR_MASK_STOP_BITS (UART_LCR_STOP)
377
378#define PENDING(_p) (readl(&(_p)->ip_mem->sio_ir.raw) & _p->ip_ienb)
379#define READ_SIO_IR(_p) readl(&(_p)->ip_mem->sio_ir.raw)
380
381
382#ifdef IOC4_1K_BUFFERS
383#define RING_BUF_SIZE 1024
384#define IOC4_BUF_SIZE_BIT 0
385#define PROD_CONS_MASK IOC4_PROD_CONS_PTR_1K
386#else
387#define RING_BUF_SIZE 4096
388#define IOC4_BUF_SIZE_BIT IOC4_SBBR_L_SIZE
389#define PROD_CONS_MASK IOC4_PROD_CONS_PTR_4K
390#endif
391
392#define TOTAL_RING_BUF_SIZE (RING_BUF_SIZE * 4)
393
394
395
396
397
398#define UART_PORT_MIN 0
399#define UART_PORT_RS232 UART_PORT_MIN
400#define UART_PORT_RS422 1
401#define UART_PORT_COUNT 2
402
403struct ioc4_control {
404 int ic_irq;
405 struct {
406
407 struct uart_port icp_uart_port[UART_PORT_COUNT];
408
409 struct ioc4_port *icp_port;
410 } ic_port[IOC4_NUM_SERIAL_PORTS];
411 struct ioc4_soft *ic_soft;
412};
413
414
415
416
417#define MAX_IOC4_INTR_ENTS (8 * sizeof(uint32_t))
418struct ioc4_soft {
419 struct ioc4_misc_regs __iomem *is_ioc4_misc_addr;
420 struct ioc4_serial __iomem *is_ioc4_serial_addr;
421
422
423 struct ioc4_intr_type {
424
425
426
427
428
429
430 struct ioc4_intr_info {
431 uint32_t sd_bits;
432 ioc4_intr_func_f *sd_intr;
433 void *sd_info;
434 } is_intr_info[MAX_IOC4_INTR_ENTS];
435
436
437 atomic_t is_num_intrs;
438 } is_intr_type[IOC4_NUM_INTR_TYPES];
439
440
441
442
443
444
445
446 spinlock_t is_ir_lock;
447};
448
449
450struct ioc4_port {
451 struct uart_port *ip_port;
452
453 struct uart_port *ip_all_ports[UART_PORT_COUNT];
454
455 struct ioc4_control *ip_control;
456 struct pci_dev *ip_pdev;
457 struct ioc4_soft *ip_ioc4_soft;
458
459
460 struct ioc4_misc_regs __iomem *ip_mem;
461 struct ioc4_serial __iomem *ip_serial;
462 struct ioc4_serialregs __iomem *ip_serial_regs;
463 struct ioc4_uartregs __iomem *ip_uart_regs;
464
465
466 dma_addr_t ip_dma_ringbuf;
467
468 struct ring_buffer *ip_cpu_ringbuf;
469
470
471 struct ring *ip_inring;
472 struct ring *ip_outring;
473
474
475 struct hooks *ip_hooks;
476
477 spinlock_t ip_lock;
478
479
480 int ip_baud;
481 int ip_tx_lowat;
482 int ip_rx_timeout;
483
484
485 int ip_notify;
486
487
488
489
490 uint32_t ip_ienb;
491 uint32_t ip_sscr;
492 uint32_t ip_tx_prod;
493 uint32_t ip_rx_cons;
494 int ip_pci_bus_speed;
495 unsigned char ip_flags;
496};
497
498
499
500
501
502
503#define TX_LOWAT_LATENCY 1000
504#define TX_LOWAT_HZ (1000000 / TX_LOWAT_LATENCY)
505#define TX_LOWAT_CHARS(baud) (baud / 10 / TX_LOWAT_HZ)
506
507
508#define INPUT_HIGH 0x01
509#define DCD_ON 0x02
510#define LOWAT_WRITTEN 0x04
511#define READ_ABORTED 0x08
512#define PORT_ACTIVE 0x10
513#define PORT_INACTIVE 0
514
515
516
517
518
519
520struct hooks {
521 uint32_t intr_delta_dcd;
522 uint32_t intr_delta_cts;
523 uint32_t intr_tx_mt;
524 uint32_t intr_rx_timer;
525 uint32_t intr_rx_high;
526 uint32_t intr_tx_explicit;
527 uint32_t intr_dma_error;
528 uint32_t intr_clear;
529 uint32_t intr_all;
530 int rs422_select_pin;
531};
532
533static struct hooks hooks_array[IOC4_NUM_SERIAL_PORTS] = {
534
535 {
536 IOC4_SIO_IR_S0_DELTA_DCD, IOC4_SIO_IR_S0_DELTA_CTS,
537 IOC4_SIO_IR_S0_TX_MT, IOC4_SIO_IR_S0_RX_TIMER,
538 IOC4_SIO_IR_S0_RX_HIGH, IOC4_SIO_IR_S0_TX_EXPLICIT,
539 IOC4_OTHER_IR_S0_MEMERR,
540 (IOC4_SIO_IR_S0_TX_MT | IOC4_SIO_IR_S0_RX_FULL |
541 IOC4_SIO_IR_S0_RX_HIGH | IOC4_SIO_IR_S0_RX_TIMER |
542 IOC4_SIO_IR_S0_DELTA_DCD | IOC4_SIO_IR_S0_DELTA_CTS |
543 IOC4_SIO_IR_S0_INT | IOC4_SIO_IR_S0_TX_EXPLICIT),
544 IOC4_SIO_IR_S0, IOC4_GPPR_UART0_MODESEL_PIN,
545 },
546
547
548 {
549 IOC4_SIO_IR_S1_DELTA_DCD, IOC4_SIO_IR_S1_DELTA_CTS,
550 IOC4_SIO_IR_S1_TX_MT, IOC4_SIO_IR_S1_RX_TIMER,
551 IOC4_SIO_IR_S1_RX_HIGH, IOC4_SIO_IR_S1_TX_EXPLICIT,
552 IOC4_OTHER_IR_S1_MEMERR,
553 (IOC4_SIO_IR_S1_TX_MT | IOC4_SIO_IR_S1_RX_FULL |
554 IOC4_SIO_IR_S1_RX_HIGH | IOC4_SIO_IR_S1_RX_TIMER |
555 IOC4_SIO_IR_S1_DELTA_DCD | IOC4_SIO_IR_S1_DELTA_CTS |
556 IOC4_SIO_IR_S1_INT | IOC4_SIO_IR_S1_TX_EXPLICIT),
557 IOC4_SIO_IR_S1, IOC4_GPPR_UART1_MODESEL_PIN,
558 },
559
560
561 {
562 IOC4_SIO_IR_S2_DELTA_DCD, IOC4_SIO_IR_S2_DELTA_CTS,
563 IOC4_SIO_IR_S2_TX_MT, IOC4_SIO_IR_S2_RX_TIMER,
564 IOC4_SIO_IR_S2_RX_HIGH, IOC4_SIO_IR_S2_TX_EXPLICIT,
565 IOC4_OTHER_IR_S2_MEMERR,
566 (IOC4_SIO_IR_S2_TX_MT | IOC4_SIO_IR_S2_RX_FULL |
567 IOC4_SIO_IR_S2_RX_HIGH | IOC4_SIO_IR_S2_RX_TIMER |
568 IOC4_SIO_IR_S2_DELTA_DCD | IOC4_SIO_IR_S2_DELTA_CTS |
569 IOC4_SIO_IR_S2_INT | IOC4_SIO_IR_S2_TX_EXPLICIT),
570 IOC4_SIO_IR_S2, IOC4_GPPR_UART2_MODESEL_PIN,
571 },
572
573
574 {
575 IOC4_SIO_IR_S3_DELTA_DCD, IOC4_SIO_IR_S3_DELTA_CTS,
576 IOC4_SIO_IR_S3_TX_MT, IOC4_SIO_IR_S3_RX_TIMER,
577 IOC4_SIO_IR_S3_RX_HIGH, IOC4_SIO_IR_S3_TX_EXPLICIT,
578 IOC4_OTHER_IR_S3_MEMERR,
579 (IOC4_SIO_IR_S3_TX_MT | IOC4_SIO_IR_S3_RX_FULL |
580 IOC4_SIO_IR_S3_RX_HIGH | IOC4_SIO_IR_S3_RX_TIMER |
581 IOC4_SIO_IR_S3_DELTA_DCD | IOC4_SIO_IR_S3_DELTA_CTS |
582 IOC4_SIO_IR_S3_INT | IOC4_SIO_IR_S3_TX_EXPLICIT),
583 IOC4_SIO_IR_S3, IOC4_GPPR_UART3_MODESEL_PIN,
584 }
585};
586
587
588struct ring_entry {
589 union {
590 struct {
591 uint32_t alldata;
592 uint32_t allsc;
593 } all;
594 struct {
595 char data[4];
596 char sc[4];
597 } s;
598 } u;
599};
600
601
602#define RING_ANY_VALID \
603 ((uint32_t)(IOC4_RXSB_MODEM_VALID | IOC4_RXSB_DATA_VALID) * 0x01010101)
604
605#define ring_sc u.s.sc
606#define ring_data u.s.data
607#define ring_allsc u.all.allsc
608
609
610#define ENTRIES_PER_RING (RING_BUF_SIZE / (int) sizeof(struct ring_entry))
611
612
613struct ring {
614 struct ring_entry entries[ENTRIES_PER_RING];
615};
616
617
618struct ring_buffer {
619 struct ring TX_0_OR_2;
620 struct ring RX_0_OR_2;
621 struct ring TX_1_OR_3;
622 struct ring RX_1_OR_3;
623};
624
625
626#define RING(_p, _wh) &(((struct ring_buffer *)((_p)->ip_cpu_ringbuf))->_wh)
627
628
629
630#define MAXITER 10000000
631
632
633static void receive_chars(struct uart_port *);
634static void handle_intr(void *arg, uint32_t sio_ir);
635
636
637
638
639
640
641static inline int port_is_active(struct ioc4_port *port,
642 struct uart_port *uart_port)
643{
644 if (port) {
645 if ((port->ip_flags & PORT_ACTIVE)
646 && (port->ip_port == uart_port))
647 return 1;
648 }
649 return 0;
650}
651
652
653
654
655
656
657
658
659
660static inline void
661write_ireg(struct ioc4_soft *ioc4_soft, uint32_t val, int which, int type)
662{
663 struct ioc4_misc_regs __iomem *mem = ioc4_soft->is_ioc4_misc_addr;
664 unsigned long flags;
665
666 spin_lock_irqsave(&ioc4_soft->is_ir_lock, flags);
667
668 switch (type) {
669 case IOC4_SIO_INTR_TYPE:
670 switch (which) {
671 case IOC4_W_IES:
672 writel(val, &mem->sio_ies.raw);
673 break;
674
675 case IOC4_W_IEC:
676 writel(val, &mem->sio_iec.raw);
677 break;
678 }
679 break;
680
681 case IOC4_OTHER_INTR_TYPE:
682 switch (which) {
683 case IOC4_W_IES:
684 writel(val, &mem->other_ies.raw);
685 break;
686
687 case IOC4_W_IEC:
688 writel(val, &mem->other_iec.raw);
689 break;
690 }
691 break;
692
693 default:
694 break;
695 }
696 spin_unlock_irqrestore(&ioc4_soft->is_ir_lock, flags);
697}
698
699
700
701
702
703
704static int set_baud(struct ioc4_port *port, int baud)
705{
706 int actual_baud;
707 int diff;
708 int lcr;
709 unsigned short divisor;
710 struct ioc4_uartregs __iomem *uart;
711
712 divisor = SER_DIVISOR(baud, port->ip_pci_bus_speed);
713 if (!divisor)
714 return 1;
715 actual_baud = DIVISOR_TO_BAUD(divisor, port->ip_pci_bus_speed);
716
717 diff = actual_baud - baud;
718 if (diff < 0)
719 diff = -diff;
720
721
722 if (diff * 100 > actual_baud)
723 return 1;
724
725 uart = port->ip_uart_regs;
726 lcr = readb(&uart->i4u_lcr);
727 writeb(lcr | UART_LCR_DLAB, &uart->i4u_lcr);
728 writeb((unsigned char)divisor, &uart->i4u_dll);
729 writeb((unsigned char)(divisor >> 8), &uart->i4u_dlm);
730 writeb(lcr, &uart->i4u_lcr);
731 return 0;
732}
733
734
735
736
737
738
739
740static struct ioc4_port *get_ioc4_port(struct uart_port *the_port, int set)
741{
742 struct ioc4_driver_data *idd = dev_get_drvdata(the_port->dev);
743 struct ioc4_control *control = idd->idd_serial_data;
744 struct ioc4_port *port;
745 int port_num, port_type;
746
747 if (control) {
748 for ( port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS;
749 port_num++ ) {
750 port = control->ic_port[port_num].icp_port;
751 if (!port)
752 continue;
753 for (port_type = UART_PORT_MIN;
754 port_type < UART_PORT_COUNT;
755 port_type++) {
756 if (the_port == port->ip_all_ports
757 [port_type]) {
758
759 if (set) {
760 port->ip_port = the_port;
761 }
762 return port;
763 }
764 }
765 }
766 }
767 return NULL;
768}
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788static inline uint32_t
789pending_intrs(struct ioc4_soft *soft, int type)
790{
791 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
792 unsigned long flag;
793 uint32_t intrs = 0;
794
795 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
796 || (type == IOC4_OTHER_INTR_TYPE)));
797
798 spin_lock_irqsave(&soft->is_ir_lock, flag);
799
800 switch (type) {
801 case IOC4_SIO_INTR_TYPE:
802 intrs = readl(&mem->sio_ir.raw) & readl(&mem->sio_ies.raw);
803 break;
804
805 case IOC4_OTHER_INTR_TYPE:
806 intrs = readl(&mem->other_ir.raw) & readl(&mem->other_ies.raw);
807
808
809 intrs &= ~(IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
810 break;
811
812 default:
813 break;
814 }
815 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
816 return intrs;
817}
818
819
820
821
822
823
824static inline int port_init(struct ioc4_port *port)
825{
826 uint32_t sio_cr;
827 struct hooks *hooks = port->ip_hooks;
828 struct ioc4_uartregs __iomem *uart;
829
830
831 writel(IOC4_SSCR_RESET, &port->ip_serial_regs->sscr);
832
833
834 do
835 sio_cr = readl(&port->ip_mem->sio_cr.raw);
836 while (!(sio_cr & IOC4_SIO_CR_SIO_DIAG_IDLE));
837
838
839 writel(0, &port->ip_serial_regs->sscr);
840
841
842
843
844 port->ip_tx_prod = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
845 writel(port->ip_tx_prod, &port->ip_serial_regs->stpir);
846 port->ip_rx_cons = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
847 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
848
849
850 uart = port->ip_uart_regs;
851 writeb(0, &uart->i4u_lcr);
852 writeb(0, &uart->i4u_ier);
853
854
855 set_baud(port, port->ip_baud);
856
857
858 writeb(UART_LCR_WLEN8 | 0, &uart->i4u_lcr);
859
860
861
862 writeb(UART_FCR_ENABLE_FIFO, &uart->i4u_fcr);
863
864 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
865 &uart->i4u_fcr);
866
867
868 writeb(0, &uart->i4u_mcr);
869
870
871 readb(&uart->i4u_msr);
872
873
874 if (port->ip_hooks == &hooks_array[0]
875 || port->ip_hooks == &hooks_array[2]) {
876 unsigned long ring_pci_addr;
877 uint32_t __iomem *sbbr_l;
878 uint32_t __iomem *sbbr_h;
879
880 if (port->ip_hooks == &hooks_array[0]) {
881 sbbr_l = &port->ip_serial->sbbr01_l;
882 sbbr_h = &port->ip_serial->sbbr01_h;
883 } else {
884 sbbr_l = &port->ip_serial->sbbr23_l;
885 sbbr_h = &port->ip_serial->sbbr23_h;
886 }
887
888 ring_pci_addr = (unsigned long __iomem)port->ip_dma_ringbuf;
889 DPRINT_CONFIG(("%s: ring_pci_addr 0x%lx\n",
890 __func__, ring_pci_addr));
891
892 writel((unsigned int)((uint64_t)ring_pci_addr >> 32), sbbr_h);
893 writel((unsigned int)ring_pci_addr | IOC4_BUF_SIZE_BIT, sbbr_l);
894 }
895
896
897 writel(IOC4_SRTR_HZ / 100, &port->ip_serial_regs->srtr);
898
899
900
901 port->ip_sscr = (ENTRIES_PER_RING * 3 / 4);
902 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
903
904
905 write_ireg(port->ip_ioc4_soft, hooks->intr_clear,
906 IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
907 port->ip_ienb &= ~hooks->intr_clear;
908 writel(hooks->intr_clear, &port->ip_mem->sio_ir.raw);
909 return 0;
910}
911
912
913
914
915
916
917
918static void handle_dma_error_intr(void *arg, uint32_t other_ir)
919{
920 struct ioc4_port *port = (struct ioc4_port *)arg;
921 struct hooks *hooks = port->ip_hooks;
922 unsigned long flags;
923
924 spin_lock_irqsave(&port->ip_lock, flags);
925
926
927 writel(hooks->intr_dma_error, &port->ip_mem->other_ir.raw);
928
929 if (readl(&port->ip_mem->pci_err_addr_l.raw) & IOC4_PCI_ERR_ADDR_VLD) {
930 printk(KERN_ERR
931 "PCI error address is 0x%llx, "
932 "master is serial port %c %s\n",
933 (((uint64_t)readl(&port->ip_mem->pci_err_addr_h)
934 << 32)
935 | readl(&port->ip_mem->pci_err_addr_l.raw))
936 & IOC4_PCI_ERR_ADDR_ADDR_MSK, '1' +
937 ((char)(readl(&port->ip_mem->pci_err_addr_l.raw) &
938 IOC4_PCI_ERR_ADDR_MST_NUM_MSK) >> 1),
939 (readl(&port->ip_mem->pci_err_addr_l.raw)
940 & IOC4_PCI_ERR_ADDR_MST_TYP_MSK)
941 ? "RX" : "TX");
942
943 if (readl(&port->ip_mem->pci_err_addr_l.raw)
944 & IOC4_PCI_ERR_ADDR_MUL_ERR) {
945 printk(KERN_ERR
946 "Multiple errors occurred\n");
947 }
948 }
949 spin_unlock_irqrestore(&port->ip_lock, flags);
950
951
952 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error, IOC4_W_IES,
953 IOC4_OTHER_INTR_TYPE);
954}
955
956
957
958
959
960
961
962
963
964static void
965intr_connect(struct ioc4_soft *soft, int type,
966 uint32_t intrbits, ioc4_intr_func_f * intr, void *info)
967{
968 int i;
969 struct ioc4_intr_info *intr_ptr;
970
971 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
972 || (type == IOC4_OTHER_INTR_TYPE)));
973
974 i = atomic_inc_return(&soft-> is_intr_type[type].is_num_intrs) - 1;
975 BUG_ON(!(i < MAX_IOC4_INTR_ENTS || (printk("i %d\n", i), 0)));
976
977
978 intr_ptr = &soft->is_intr_type[type].is_intr_info[i];
979 intr_ptr->sd_bits = intrbits;
980 intr_ptr->sd_intr = intr;
981 intr_ptr->sd_info = info;
982}
983
984
985
986
987
988
989
990static irqreturn_t ioc4_intr(int irq, void *arg)
991{
992 struct ioc4_soft *soft;
993 uint32_t this_ir, this_mir;
994 int xx, num_intrs = 0;
995 int intr_type;
996 int handled = 0;
997 struct ioc4_intr_info *intr_info;
998
999 soft = arg;
1000 for (intr_type = 0; intr_type < IOC4_NUM_INTR_TYPES; intr_type++) {
1001 num_intrs = (int)atomic_read(
1002 &soft->is_intr_type[intr_type].is_num_intrs);
1003
1004 this_mir = this_ir = pending_intrs(soft, intr_type);
1005
1006
1007
1008
1009 for (xx = 0; xx < num_intrs; xx++) {
1010 intr_info = &soft->is_intr_type[intr_type].is_intr_info[xx];
1011 this_mir = this_ir & intr_info->sd_bits;
1012 if (this_mir) {
1013
1014 handled++;
1015 write_ireg(soft, intr_info->sd_bits, IOC4_W_IEC,
1016 intr_type);
1017 intr_info->sd_intr(intr_info->sd_info, this_mir);
1018 this_ir &= ~this_mir;
1019 }
1020 }
1021 }
1022#ifdef DEBUG_INTERRUPTS
1023 {
1024 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
1025 unsigned long flag;
1026
1027 spin_lock_irqsave(&soft->is_ir_lock, flag);
1028 printk ("%s : %d : mem 0x%p sio_ir 0x%x sio_ies 0x%x "
1029 "other_ir 0x%x other_ies 0x%x mask 0x%x\n",
1030 __func__, __LINE__,
1031 (void *)mem, readl(&mem->sio_ir.raw),
1032 readl(&mem->sio_ies.raw),
1033 readl(&mem->other_ir.raw),
1034 readl(&mem->other_ies.raw),
1035 IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
1036 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
1037 }
1038#endif
1039 return handled ? IRQ_HANDLED : IRQ_NONE;
1040}
1041
1042
1043
1044
1045
1046
1047
1048static inline int ioc4_attach_local(struct ioc4_driver_data *idd)
1049{
1050 struct ioc4_port *port;
1051 struct ioc4_port *ports[IOC4_NUM_SERIAL_PORTS];
1052 int port_number;
1053 uint16_t ioc4_revid_min = 62;
1054 uint16_t ioc4_revid;
1055 struct pci_dev *pdev = idd->idd_pdev;
1056 struct ioc4_control* control = idd->idd_serial_data;
1057 struct ioc4_soft *soft = control->ic_soft;
1058 void __iomem *ioc4_misc = idd->idd_misc_regs;
1059 void __iomem *ioc4_serial = soft->is_ioc4_serial_addr;
1060
1061
1062 pci_read_config_word(pdev, PCI_COMMAND_SPECIAL, &ioc4_revid);
1063
1064 printk(KERN_INFO "IOC4 firmware revision %d\n", ioc4_revid);
1065 if (ioc4_revid < ioc4_revid_min) {
1066 printk(KERN_WARNING
1067 "IOC4 serial not supported on firmware rev %d, "
1068 "please upgrade to rev %d or higher\n",
1069 ioc4_revid, ioc4_revid_min);
1070 return -EPERM;
1071 }
1072 BUG_ON(ioc4_misc == NULL);
1073 BUG_ON(ioc4_serial == NULL);
1074
1075
1076 for (port_number = 0; port_number < IOC4_NUM_SERIAL_PORTS;
1077 port_number++) {
1078 port = kzalloc(sizeof(struct ioc4_port), GFP_KERNEL);
1079 if (!port) {
1080 printk(KERN_WARNING
1081 "IOC4 serial memory not available for port\n");
1082 goto free;
1083 }
1084 spin_lock_init(&port->ip_lock);
1085
1086
1087
1088
1089 ports[port_number] = port;
1090
1091
1092 control->ic_port[port_number].icp_port = port;
1093 port->ip_ioc4_soft = soft;
1094 port->ip_pdev = pdev;
1095 port->ip_ienb = 0;
1096
1097
1098
1099
1100 if (idd->count_period/IOC4_EXTINT_COUNT_DIVISOR < 20) {
1101 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_66;
1102 } else {
1103 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_33;
1104 }
1105 port->ip_baud = 9600;
1106 port->ip_control = control;
1107 port->ip_mem = ioc4_misc;
1108 port->ip_serial = ioc4_serial;
1109
1110
1111 port->ip_hooks = &hooks_array[port_number];
1112
1113
1114
1115
1116 switch (port_number) {
1117 case 0:
1118 port->ip_serial_regs = &(port->ip_serial->port_0);
1119 port->ip_uart_regs = &(port->ip_serial->uart_0);
1120 break;
1121 case 1:
1122 port->ip_serial_regs = &(port->ip_serial->port_1);
1123 port->ip_uart_regs = &(port->ip_serial->uart_1);
1124 break;
1125 case 2:
1126 port->ip_serial_regs = &(port->ip_serial->port_2);
1127 port->ip_uart_regs = &(port->ip_serial->uart_2);
1128 break;
1129 default:
1130 case 3:
1131 port->ip_serial_regs = &(port->ip_serial->port_3);
1132 port->ip_uart_regs = &(port->ip_serial->uart_3);
1133 break;
1134 }
1135
1136
1137 if (port_number && (port_number & 1)) {
1138
1139 port->ip_dma_ringbuf =
1140 ports[port_number - 1]->ip_dma_ringbuf;
1141 port->ip_cpu_ringbuf =
1142 ports[port_number - 1]->ip_cpu_ringbuf;
1143 port->ip_inring = RING(port, RX_1_OR_3);
1144 port->ip_outring = RING(port, TX_1_OR_3);
1145
1146 } else {
1147 if (port->ip_dma_ringbuf == 0) {
1148 port->ip_cpu_ringbuf = pci_alloc_consistent
1149 (pdev, TOTAL_RING_BUF_SIZE,
1150 &port->ip_dma_ringbuf);
1151
1152 }
1153 BUG_ON(!((((int64_t)port->ip_dma_ringbuf) &
1154 (TOTAL_RING_BUF_SIZE - 1)) == 0));
1155 DPRINT_CONFIG(("%s : ip_cpu_ringbuf 0x%p "
1156 "ip_dma_ringbuf 0x%p\n",
1157 __func__,
1158 (void *)port->ip_cpu_ringbuf,
1159 (void *)port->ip_dma_ringbuf));
1160 port->ip_inring = RING(port, RX_0_OR_2);
1161 port->ip_outring = RING(port, TX_0_OR_2);
1162 }
1163 DPRINT_CONFIG(("%s : port %d [addr 0x%p] control 0x%p",
1164 __func__,
1165 port_number, (void *)port, (void *)control));
1166 DPRINT_CONFIG((" ip_serial_regs 0x%p ip_uart_regs 0x%p\n",
1167 (void *)port->ip_serial_regs,
1168 (void *)port->ip_uart_regs));
1169
1170
1171 port_init(port);
1172
1173 DPRINT_CONFIG(("%s: port_number %d port 0x%p inring 0x%p "
1174 "outring 0x%p\n",
1175 __func__,
1176 port_number, (void *)port,
1177 (void *)port->ip_inring,
1178 (void *)port->ip_outring));
1179
1180
1181 intr_connect(soft, IOC4_SIO_INTR_TYPE,
1182 GET_SIO_IR(port_number),
1183 handle_intr, port);
1184
1185 intr_connect(soft, IOC4_OTHER_INTR_TYPE,
1186 GET_OTHER_IR(port_number),
1187 handle_dma_error_intr, port);
1188 }
1189 return 0;
1190
1191free:
1192 while (port_number)
1193 kfree(ports[--port_number]);
1194 return -ENOMEM;
1195}
1196
1197
1198
1199
1200
1201
1202static void enable_intrs(struct ioc4_port *port, uint32_t mask)
1203{
1204 struct hooks *hooks = port->ip_hooks;
1205
1206 if ((port->ip_ienb & mask) != mask) {
1207 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IES,
1208 IOC4_SIO_INTR_TYPE);
1209 port->ip_ienb |= mask;
1210 }
1211
1212 if (port->ip_ienb)
1213 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1214 IOC4_W_IES, IOC4_OTHER_INTR_TYPE);
1215}
1216
1217
1218
1219
1220
1221static inline int local_open(struct ioc4_port *port)
1222{
1223 int spiniter = 0;
1224
1225 port->ip_flags = PORT_ACTIVE;
1226
1227
1228 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1229 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1230 &port->ip_serial_regs->sscr);
1231 while((readl(&port->ip_serial_regs-> sscr)
1232 & IOC4_SSCR_PAUSE_STATE) == 0) {
1233 spiniter++;
1234 if (spiniter > MAXITER) {
1235 port->ip_flags = PORT_INACTIVE;
1236 return -1;
1237 }
1238 }
1239 }
1240
1241
1242
1243
1244
1245
1246 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1247 &port->ip_uart_regs->i4u_fcr);
1248
1249 writeb(UART_LCR_WLEN8, &port->ip_uart_regs->i4u_lcr);
1250
1251
1252
1253
1254
1255 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1256 port->ip_sscr |= 1;
1257
1258
1259
1260
1261 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1262 port->ip_tx_lowat = 1;
1263 return 0;
1264}
1265
1266
1267
1268
1269
1270
1271static inline int set_rx_timeout(struct ioc4_port *port, int timeout)
1272{
1273 int threshold;
1274
1275 port->ip_rx_timeout = timeout;
1276
1277
1278
1279
1280
1281
1282
1283
1284 threshold = timeout * port->ip_baud / 4000;
1285 if (threshold == 0)
1286 threshold = 1;
1287
1288 if ((unsigned)threshold > (unsigned)IOC4_SSCR_RX_THRESHOLD)
1289 return 1;
1290
1291 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1292 port->ip_sscr |= threshold;
1293
1294 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1295
1296
1297
1298
1299 timeout = timeout * IOC4_SRTR_HZ / 100;
1300 if (timeout > IOC4_SRTR_CNT)
1301 timeout = IOC4_SRTR_CNT;
1302
1303 writel(timeout, &port->ip_serial_regs->srtr);
1304 return 0;
1305}
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316static inline int
1317config_port(struct ioc4_port *port,
1318 int baud, int byte_size, int stop_bits, int parenb, int parodd)
1319{
1320 char lcr, sizebits;
1321 int spiniter = 0;
1322
1323 DPRINT_CONFIG(("%s: baud %d byte_size %d stop %d parenb %d parodd %d\n",
1324 __func__, baud, byte_size, stop_bits, parenb, parodd));
1325
1326 if (set_baud(port, baud))
1327 return 1;
1328
1329 switch (byte_size) {
1330 case 5:
1331 sizebits = UART_LCR_WLEN5;
1332 break;
1333 case 6:
1334 sizebits = UART_LCR_WLEN6;
1335 break;
1336 case 7:
1337 sizebits = UART_LCR_WLEN7;
1338 break;
1339 case 8:
1340 sizebits = UART_LCR_WLEN8;
1341 break;
1342 default:
1343 return 1;
1344 }
1345
1346
1347 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1348 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1349 &port->ip_serial_regs->sscr);
1350 while((readl(&port->ip_serial_regs->sscr)
1351 & IOC4_SSCR_PAUSE_STATE) == 0) {
1352 spiniter++;
1353 if (spiniter > MAXITER)
1354 return -1;
1355 }
1356 }
1357
1358
1359 lcr = readb(&port->ip_uart_regs->i4u_lcr);
1360 lcr &= ~(LCR_MASK_BITS_CHAR | UART_LCR_EPAR |
1361 UART_LCR_PARITY | LCR_MASK_STOP_BITS);
1362
1363
1364 lcr |= sizebits;
1365
1366
1367 if (parenb) {
1368 lcr |= UART_LCR_PARITY;
1369 if (!parodd)
1370 lcr |= UART_LCR_EPAR;
1371 }
1372
1373
1374 if (stop_bits)
1375 lcr |= UART_LCR_STOP ;
1376
1377 writeb(lcr, &port->ip_uart_regs->i4u_lcr);
1378
1379
1380 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1381 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1382 }
1383 port->ip_baud = baud;
1384
1385
1386
1387
1388
1389 port->ip_tx_lowat = (TX_LOWAT_CHARS(baud) + 3) / 4;
1390 if (port->ip_tx_lowat == 0)
1391 port->ip_tx_lowat = 1;
1392
1393 set_rx_timeout(port, 2);
1394
1395 return 0;
1396}
1397
1398
1399
1400
1401
1402
1403
1404
1405static inline int do_write(struct ioc4_port *port, char *buf, int len)
1406{
1407 int prod_ptr, cons_ptr, total = 0;
1408 struct ring *outring;
1409 struct ring_entry *entry;
1410 struct hooks *hooks = port->ip_hooks;
1411
1412 BUG_ON(!(len >= 0));
1413
1414 prod_ptr = port->ip_tx_prod;
1415 cons_ptr = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
1416 outring = port->ip_outring;
1417
1418
1419
1420
1421
1422 cons_ptr = (cons_ptr - (int)sizeof(struct ring_entry)) & PROD_CONS_MASK;
1423
1424
1425 while ((prod_ptr != cons_ptr) && (len > 0)) {
1426 int xx;
1427
1428
1429 entry = (struct ring_entry *)((caddr_t) outring + prod_ptr);
1430
1431
1432 entry->ring_allsc = 0;
1433
1434
1435 for (xx = 0; (xx < 4) && (len > 0); xx++) {
1436 entry->ring_data[xx] = *buf++;
1437 entry->ring_sc[xx] = IOC4_TXCB_VALID;
1438 len--;
1439 total++;
1440 }
1441
1442
1443
1444
1445
1446
1447
1448 if (!(port->ip_flags & LOWAT_WRITTEN) &&
1449 ((cons_ptr - prod_ptr) & PROD_CONS_MASK)
1450 <= port->ip_tx_lowat
1451 * (int)sizeof(struct ring_entry)) {
1452 port->ip_flags |= LOWAT_WRITTEN;
1453 entry->ring_sc[0] |= IOC4_TXCB_INT_WHEN_DONE;
1454 }
1455
1456
1457 prod_ptr += sizeof(struct ring_entry);
1458 prod_ptr &= PROD_CONS_MASK;
1459 }
1460
1461
1462 if (total > 0 && !(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
1463 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1464 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1465 }
1466
1467
1468
1469
1470 if (!uart_tx_stopped(port->ip_port)) {
1471 writel(prod_ptr, &port->ip_serial_regs->stpir);
1472
1473
1474
1475
1476 if (total > 0)
1477 enable_intrs(port, hooks->intr_tx_mt);
1478 }
1479 port->ip_tx_prod = prod_ptr;
1480 return total;
1481}
1482
1483
1484
1485
1486
1487
1488static void disable_intrs(struct ioc4_port *port, uint32_t mask)
1489{
1490 struct hooks *hooks = port->ip_hooks;
1491
1492 if (port->ip_ienb & mask) {
1493 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IEC,
1494 IOC4_SIO_INTR_TYPE);
1495 port->ip_ienb &= ~mask;
1496 }
1497
1498 if (!port->ip_ienb)
1499 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1500 IOC4_W_IEC, IOC4_OTHER_INTR_TYPE);
1501}
1502
1503
1504
1505
1506
1507
1508
1509static int set_notification(struct ioc4_port *port, int mask, int set_on)
1510{
1511 struct hooks *hooks = port->ip_hooks;
1512 uint32_t intrbits, sscrbits;
1513
1514 BUG_ON(!mask);
1515
1516 intrbits = sscrbits = 0;
1517
1518 if (mask & N_DATA_READY)
1519 intrbits |= (hooks->intr_rx_timer | hooks->intr_rx_high);
1520 if (mask & N_OUTPUT_LOWAT)
1521 intrbits |= hooks->intr_tx_explicit;
1522 if (mask & N_DDCD) {
1523 intrbits |= hooks->intr_delta_dcd;
1524 sscrbits |= IOC4_SSCR_RX_RING_DCD;
1525 }
1526 if (mask & N_DCTS)
1527 intrbits |= hooks->intr_delta_cts;
1528
1529 if (set_on) {
1530 enable_intrs(port, intrbits);
1531 port->ip_notify |= mask;
1532 port->ip_sscr |= sscrbits;
1533 } else {
1534 disable_intrs(port, intrbits);
1535 port->ip_notify &= ~mask;
1536 port->ip_sscr &= ~sscrbits;
1537 }
1538
1539
1540
1541
1542
1543 if (port->ip_notify & (N_DATA_READY | N_DDCD))
1544 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1545 else if (!(port->ip_ienb & hooks->intr_tx_mt))
1546 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
1547
1548 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1549 return 0;
1550}
1551
1552
1553
1554
1555
1556
1557
1558static inline int set_mcr(struct uart_port *the_port,
1559 int mask1, int mask2)
1560{
1561 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1562 uint32_t shadow;
1563 int spiniter = 0;
1564 char mcr;
1565
1566 if (!port)
1567 return -1;
1568
1569
1570 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1571 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1572 &port->ip_serial_regs->sscr);
1573 while ((readl(&port->ip_serial_regs->sscr)
1574 & IOC4_SSCR_PAUSE_STATE) == 0) {
1575 spiniter++;
1576 if (spiniter > MAXITER)
1577 return -1;
1578 }
1579 }
1580 shadow = readl(&port->ip_serial_regs->shadow);
1581 mcr = (shadow & 0xff000000) >> 24;
1582
1583
1584 mcr |= mask1;
1585 shadow |= mask2;
1586
1587 writeb(mcr, &port->ip_uart_regs->i4u_mcr);
1588 writel(shadow, &port->ip_serial_regs->shadow);
1589
1590
1591 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1592 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1593 }
1594 return 0;
1595}
1596
1597
1598
1599
1600
1601
1602static int ioc4_set_proto(struct ioc4_port *port, int proto)
1603{
1604 struct hooks *hooks = port->ip_hooks;
1605
1606 switch (proto) {
1607 case PROTO_RS232:
1608
1609 writel(0, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1610 break;
1611
1612 case PROTO_RS422:
1613
1614 writel(1, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1615 break;
1616
1617 default:
1618 return 1;
1619 }
1620 return 0;
1621}
1622
1623
1624
1625
1626
1627static void transmit_chars(struct uart_port *the_port)
1628{
1629 int xmit_count, tail, head;
1630 int result;
1631 char *start;
1632 struct tty_struct *tty;
1633 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1634 struct uart_state *state;
1635
1636 if (!the_port)
1637 return;
1638 if (!port)
1639 return;
1640
1641 state = the_port->state;
1642 tty = state->port.tty;
1643
1644 if (uart_circ_empty(&state->xmit) || uart_tx_stopped(the_port)) {
1645
1646 set_notification(port, N_ALL_OUTPUT, 0);
1647 return;
1648 }
1649
1650 head = state->xmit.head;
1651 tail = state->xmit.tail;
1652 start = (char *)&state->xmit.buf[tail];
1653
1654
1655 xmit_count = (head < tail) ? (UART_XMIT_SIZE - tail) : (head - tail);
1656 if (xmit_count > 0) {
1657 result = do_write(port, start, xmit_count);
1658 if (result > 0) {
1659
1660 xmit_count -= result;
1661 the_port->icount.tx += result;
1662
1663 tail += result;
1664 tail &= UART_XMIT_SIZE - 1;
1665 state->xmit.tail = tail;
1666 start = (char *)&state->xmit.buf[tail];
1667 }
1668 }
1669 if (uart_circ_chars_pending(&state->xmit) < WAKEUP_CHARS)
1670 uart_write_wakeup(the_port);
1671
1672 if (uart_circ_empty(&state->xmit)) {
1673 set_notification(port, N_OUTPUT_LOWAT, 0);
1674 } else {
1675 set_notification(port, N_OUTPUT_LOWAT, 1);
1676 }
1677}
1678
1679
1680
1681
1682
1683
1684
1685static void
1686ioc4_change_speed(struct uart_port *the_port,
1687 struct ktermios *new_termios, struct ktermios *old_termios)
1688{
1689 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1690 int baud, bits;
1691 unsigned cflag, iflag;
1692 int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8;
1693 struct uart_state *state = the_port->state;
1694
1695 cflag = new_termios->c_cflag;
1696 iflag = new_termios->c_iflag;
1697
1698 switch (cflag & CSIZE) {
1699 case CS5:
1700 new_data = 5;
1701 bits = 7;
1702 break;
1703 case CS6:
1704 new_data = 6;
1705 bits = 8;
1706 break;
1707 case CS7:
1708 new_data = 7;
1709 bits = 9;
1710 break;
1711 case CS8:
1712 new_data = 8;
1713 bits = 10;
1714 break;
1715 default:
1716
1717 new_data = 5;
1718 bits = 7;
1719 break;
1720 }
1721 if (cflag & CSTOPB) {
1722 bits++;
1723 new_stop = 1;
1724 }
1725 if (cflag & PARENB) {
1726 bits++;
1727 new_parity_enable = 1;
1728 if (cflag & PARODD)
1729 new_parity = 1;
1730 }
1731 baud = uart_get_baud_rate(the_port, new_termios, old_termios,
1732 MIN_BAUD_SUPPORTED, MAX_BAUD_SUPPORTED);
1733 DPRINT_CONFIG(("%s: returned baud %d\n", __func__, baud));
1734
1735
1736 if (!baud)
1737 baud = 9600;
1738
1739 if (!the_port->fifosize)
1740 the_port->fifosize = IOC4_FIFO_CHARS;
1741 the_port->timeout = ((the_port->fifosize * HZ * bits) / (baud / 10));
1742 the_port->timeout += HZ / 50;
1743
1744 the_port->ignore_status_mask = N_ALL_INPUT;
1745
1746 state->port.low_latency = 1;
1747
1748 if (iflag & IGNPAR)
1749 the_port->ignore_status_mask &= ~(N_PARITY_ERROR
1750 | N_FRAMING_ERROR);
1751 if (iflag & IGNBRK) {
1752 the_port->ignore_status_mask &= ~N_BREAK;
1753 if (iflag & IGNPAR)
1754 the_port->ignore_status_mask &= ~N_OVERRUN_ERROR;
1755 }
1756 if (!(cflag & CREAD)) {
1757
1758 the_port->ignore_status_mask &= ~N_DATA_READY;
1759 }
1760
1761 if (cflag & CRTSCTS) {
1762 port->ip_sscr |= IOC4_SSCR_HFC_EN;
1763 }
1764 else {
1765 port->ip_sscr &= ~IOC4_SSCR_HFC_EN;
1766 }
1767 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1768
1769
1770 DPRINT_CONFIG(("%s : port 0x%p cflag 0%o "
1771 "config_port(baud %d data %d stop %d p enable %d parity %d),"
1772 " notification 0x%x\n",
1773 __func__, (void *)port, cflag, baud, new_data, new_stop,
1774 new_parity_enable, new_parity, the_port->ignore_status_mask));
1775
1776 if ((config_port(port, baud,
1777 new_data,
1778 new_stop,
1779 new_parity_enable,
1780 new_parity)) >= 0) {
1781 set_notification(port, the_port->ignore_status_mask, 1);
1782 }
1783}
1784
1785
1786
1787
1788
1789static inline int ic4_startup_local(struct uart_port *the_port)
1790{
1791 struct ioc4_port *port;
1792 struct uart_state *state;
1793
1794 if (!the_port)
1795 return -1;
1796
1797 port = get_ioc4_port(the_port, 0);
1798 if (!port)
1799 return -1;
1800
1801 state = the_port->state;
1802
1803 local_open(port);
1804
1805
1806 ioc4_set_proto(port, the_port->mapbase);
1807
1808
1809 ioc4_change_speed(the_port, &state->port.tty->termios,
1810 (struct ktermios *)0);
1811
1812 return 0;
1813}
1814
1815
1816
1817
1818
1819static void ioc4_cb_output_lowat(struct uart_port *the_port)
1820{
1821 unsigned long pflags;
1822
1823
1824 if (the_port) {
1825 spin_lock_irqsave(&the_port->lock, pflags);
1826 transmit_chars(the_port);
1827 spin_unlock_irqrestore(&the_port->lock, pflags);
1828 }
1829}
1830
1831
1832
1833
1834
1835
1836
1837static void handle_intr(void *arg, uint32_t sio_ir)
1838{
1839 struct ioc4_port *port = (struct ioc4_port *)arg;
1840 struct hooks *hooks = port->ip_hooks;
1841 unsigned int rx_high_rd_aborted = 0;
1842 unsigned long flags;
1843 struct uart_port *the_port;
1844 int loop_counter;
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860 sio_ir &= ~(hooks->intr_tx_mt);
1861
1862 spin_lock_irqsave(&port->ip_lock, flags);
1863
1864 loop_counter = MAXITER;
1865
1866 do {
1867 uint32_t shadow;
1868
1869 if ( loop_counter-- <= 0 ) {
1870 printk(KERN_WARNING "IOC4 serial: "
1871 "possible hang condition/"
1872 "port stuck on interrupt.\n");
1873 break;
1874 }
1875
1876
1877 if (sio_ir & hooks->intr_delta_dcd) {
1878
1879 writel(hooks->intr_delta_dcd,
1880 &port->ip_mem->sio_ir.raw);
1881
1882 shadow = readl(&port->ip_serial_regs->shadow);
1883
1884 if ((port->ip_notify & N_DDCD)
1885 && (shadow & IOC4_SHADOW_DCD)
1886 && (port->ip_port)) {
1887 the_port = port->ip_port;
1888 the_port->icount.dcd = 1;
1889 wake_up_interruptible
1890 (&the_port->state->port.delta_msr_wait);
1891 } else if ((port->ip_notify & N_DDCD)
1892 && !(shadow & IOC4_SHADOW_DCD)) {
1893
1894 port->ip_flags |= DCD_ON;
1895 }
1896 }
1897
1898
1899 if (sio_ir & hooks->intr_delta_cts) {
1900
1901 writel(hooks->intr_delta_cts,
1902 &port->ip_mem->sio_ir.raw);
1903
1904 shadow = readl(&port->ip_serial_regs->shadow);
1905
1906 if ((port->ip_notify & N_DCTS)
1907 && (port->ip_port)) {
1908 the_port = port->ip_port;
1909 the_port->icount.cts =
1910 (shadow & IOC4_SHADOW_CTS) ? 1 : 0;
1911 wake_up_interruptible
1912 (&the_port->state->port.delta_msr_wait);
1913 }
1914 }
1915
1916
1917
1918
1919
1920 if (sio_ir & hooks->intr_rx_timer) {
1921
1922 writel(hooks->intr_rx_timer,
1923 &port->ip_mem->sio_ir.raw);
1924
1925 if ((port->ip_notify & N_DATA_READY)
1926 && (port->ip_port)) {
1927
1928 receive_chars(port->ip_port);
1929 }
1930 }
1931
1932
1933 else if (sio_ir & hooks->intr_rx_high) {
1934
1935 if ((port->ip_notify & N_DATA_READY)
1936 && port->ip_port) {
1937
1938 receive_chars(port->ip_port);
1939 }
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950 if ((sio_ir = PENDING(port)) & hooks->intr_rx_high) {
1951 if ((port->ip_flags & READ_ABORTED) == 0) {
1952 port->ip_ienb &= ~hooks->intr_rx_high;
1953 port->ip_flags |= INPUT_HIGH;
1954 } else {
1955 rx_high_rd_aborted++;
1956 }
1957 }
1958 }
1959
1960
1961
1962
1963
1964 if (sio_ir & hooks->intr_tx_explicit) {
1965 port->ip_flags &= ~LOWAT_WRITTEN;
1966
1967
1968 writel(hooks->intr_tx_explicit,
1969 &port->ip_mem->sio_ir.raw);
1970
1971 if (port->ip_notify & N_OUTPUT_LOWAT)
1972 ioc4_cb_output_lowat(port->ip_port);
1973 }
1974
1975
1976 else if (sio_ir & hooks->intr_tx_mt) {
1977
1978
1979
1980
1981
1982
1983
1984 if (port->ip_notify & N_OUTPUT_LOWAT) {
1985 ioc4_cb_output_lowat(port->ip_port);
1986
1987
1988
1989
1990
1991 sio_ir = PENDING(port);
1992 }
1993
1994
1995
1996
1997 if (sio_ir & hooks->intr_tx_mt) {
1998
1999
2000
2001
2002
2003
2004 if (!(port->ip_notify
2005 & (N_DATA_READY | N_DDCD))) {
2006 BUG_ON(!(port->ip_sscr
2007 & IOC4_SSCR_DMA_EN));
2008 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2009 writel(port->ip_sscr,
2010 &port->ip_serial_regs->sscr);
2011 }
2012
2013
2014 port->ip_ienb &= ~hooks->intr_tx_mt;
2015 }
2016 }
2017 sio_ir = PENDING(port);
2018
2019
2020
2021
2022
2023 if (rx_high_rd_aborted && (sio_ir == hooks->intr_rx_high)) {
2024 sio_ir &= ~hooks->intr_rx_high;
2025 }
2026 } while (sio_ir & hooks->intr_all);
2027
2028 spin_unlock_irqrestore(&port->ip_lock, flags);
2029
2030
2031
2032
2033
2034
2035 write_ireg(port->ip_ioc4_soft, port->ip_ienb, IOC4_W_IES,
2036 IOC4_SIO_INTR_TYPE);
2037}
2038
2039
2040
2041
2042
2043
2044static void ioc4_cb_post_ncs(struct uart_port *the_port, int ncs)
2045{
2046 struct uart_icount *icount;
2047
2048 icount = &the_port->icount;
2049
2050 if (ncs & NCS_BREAK)
2051 icount->brk++;
2052 if (ncs & NCS_FRAMING)
2053 icount->frame++;
2054 if (ncs & NCS_OVERRUN)
2055 icount->overrun++;
2056 if (ncs & NCS_PARITY)
2057 icount->parity++;
2058}
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068static inline int do_read(struct uart_port *the_port, unsigned char *buf,
2069 int len)
2070{
2071 int prod_ptr, cons_ptr, total;
2072 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2073 struct ring *inring;
2074 struct ring_entry *entry;
2075 struct hooks *hooks;
2076 int byte_num;
2077 char *sc;
2078 int loop_counter;
2079
2080 BUG_ON(!(len >= 0));
2081 BUG_ON(!port);
2082 hooks = port->ip_hooks;
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
2106
2107 prod_ptr = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
2108 cons_ptr = port->ip_rx_cons;
2109
2110 if (prod_ptr == cons_ptr) {
2111 int reset_dma = 0;
2112
2113
2114
2115
2116 if (!(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
2117 port->ip_sscr |= IOC4_SSCR_DMA_EN;
2118 reset_dma = 1;
2119 }
2120
2121
2122
2123
2124
2125
2126
2127 writel(port->ip_sscr | IOC4_SSCR_RX_DRAIN,
2128 &port->ip_serial_regs->sscr);
2129 prod_ptr = readl(&port->ip_serial_regs->srpir)
2130 & PROD_CONS_MASK;
2131
2132
2133
2134
2135
2136
2137
2138
2139 if (prod_ptr == cons_ptr) {
2140 loop_counter = 0;
2141 while (readl(&port->ip_serial_regs->sscr) &
2142 IOC4_SSCR_RX_DRAIN) {
2143 loop_counter++;
2144 if (loop_counter > MAXITER)
2145 return -1;
2146 }
2147
2148
2149
2150
2151 prod_ptr = readl(&port->ip_serial_regs->srpir)
2152 & PROD_CONS_MASK;
2153 }
2154 if (reset_dma) {
2155 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2156 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
2157 }
2158 }
2159 inring = port->ip_inring;
2160 port->ip_flags &= ~READ_ABORTED;
2161
2162 total = 0;
2163 loop_counter = 0xfffff;
2164
2165
2166 while ((prod_ptr != cons_ptr) && (len > 0)) {
2167 entry = (struct ring_entry *)((caddr_t)inring + cons_ptr);
2168
2169 if ( loop_counter-- <= 0 ) {
2170 printk(KERN_WARNING "IOC4 serial: "
2171 "possible hang condition/"
2172 "port stuck on read.\n");
2173 break;
2174 }
2175
2176
2177
2178
2179
2180
2181 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2182
2183
2184
2185
2186 port->ip_flags |= READ_ABORTED;
2187 len = 0;
2188 break;
2189 }
2190
2191
2192 for (byte_num = 0; byte_num < 4 && len > 0; byte_num++) {
2193 sc = &(entry->ring_sc[byte_num]);
2194
2195
2196 if ((*sc & IOC4_RXSB_MODEM_VALID)
2197 && (port->ip_notify & N_DDCD)) {
2198
2199
2200 if ((port->ip_flags & DCD_ON)
2201 && !(*sc & IOC4_RXSB_DCD)) {
2202
2203
2204
2205
2206
2207
2208
2209
2210 if (total > 0) {
2211 len = 0;
2212 break;
2213 }
2214 port->ip_flags &= ~DCD_ON;
2215
2216
2217
2218
2219
2220 *sc &= ~IOC4_RXSB_MODEM_VALID;
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230 if ((entry->ring_allsc & RING_ANY_VALID)
2231 == 0) {
2232 cons_ptr += (int)sizeof
2233 (struct ring_entry);
2234 cons_ptr &= PROD_CONS_MASK;
2235 }
2236 writel(cons_ptr,
2237 &port->ip_serial_regs->srcir);
2238 port->ip_rx_cons = cons_ptr;
2239
2240
2241 if ((port->ip_notify & N_DDCD)
2242 && port->ip_port) {
2243 the_port->icount.dcd = 0;
2244 wake_up_interruptible
2245 (&the_port->state->
2246 port.delta_msr_wait);
2247 }
2248
2249
2250
2251
2252 return 0;
2253 }
2254 }
2255 if (*sc & IOC4_RXSB_MODEM_VALID) {
2256
2257 if ((*sc & IOC4_RXSB_OVERRUN)
2258 && (port->ip_notify & N_OVERRUN_ERROR)) {
2259 ioc4_cb_post_ncs(the_port, NCS_OVERRUN);
2260 }
2261
2262 *sc &= ~IOC4_RXSB_MODEM_VALID;
2263 }
2264
2265
2266 if ((*sc & IOC4_RXSB_DATA_VALID) &&
2267 ((*sc & (IOC4_RXSB_PAR_ERR
2268 | IOC4_RXSB_FRAME_ERR
2269 | IOC4_RXSB_BREAK))
2270 && (port->ip_notify & (N_PARITY_ERROR
2271 | N_FRAMING_ERROR
2272 | N_BREAK)))) {
2273
2274
2275
2276
2277
2278
2279
2280 if (total > 0) {
2281 len = 0;
2282 break;
2283 } else {
2284 if ((*sc & IOC4_RXSB_PAR_ERR) &&
2285 (port->ip_notify & N_PARITY_ERROR)) {
2286 ioc4_cb_post_ncs(the_port,
2287 NCS_PARITY);
2288 }
2289 if ((*sc & IOC4_RXSB_FRAME_ERR) &&
2290 (port->ip_notify & N_FRAMING_ERROR)){
2291 ioc4_cb_post_ncs(the_port,
2292 NCS_FRAMING);
2293 }
2294 if ((*sc & IOC4_RXSB_BREAK)
2295 && (port->ip_notify & N_BREAK)) {
2296 ioc4_cb_post_ncs
2297 (the_port,
2298 NCS_BREAK);
2299 }
2300 len = 1;
2301 }
2302 }
2303 if (*sc & IOC4_RXSB_DATA_VALID) {
2304 *sc &= ~IOC4_RXSB_DATA_VALID;
2305 *buf = entry->ring_data[byte_num];
2306 buf++;
2307 len--;
2308 total++;
2309 }
2310 }
2311
2312
2313
2314
2315
2316
2317 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2318 cons_ptr += (int)sizeof(struct ring_entry);
2319 cons_ptr &= PROD_CONS_MASK;
2320 }
2321 }
2322
2323
2324 writel(cons_ptr, &port->ip_serial_regs->srcir);
2325 port->ip_rx_cons = cons_ptr;
2326
2327
2328
2329
2330 if ((port->ip_flags & INPUT_HIGH) && (((prod_ptr - cons_ptr)
2331 & PROD_CONS_MASK) < ((port->ip_sscr &
2332 IOC4_SSCR_RX_THRESHOLD)
2333 << IOC4_PROD_CONS_PTR_OFF))) {
2334 port->ip_flags &= ~INPUT_HIGH;
2335 enable_intrs(port, hooks->intr_rx_high);
2336 }
2337 return total;
2338}
2339
2340
2341
2342
2343
2344static void receive_chars(struct uart_port *the_port)
2345{
2346 unsigned char ch[IOC4_MAX_CHARS];
2347 int read_count, request_count = IOC4_MAX_CHARS;
2348 struct uart_icount *icount;
2349 struct uart_state *state = the_port->state;
2350 unsigned long pflags;
2351
2352
2353 if (!state)
2354 return;
2355
2356 spin_lock_irqsave(&the_port->lock, pflags);
2357
2358 request_count = tty_buffer_request_room(&state->port, IOC4_MAX_CHARS);
2359
2360 if (request_count > 0) {
2361 icount = &the_port->icount;
2362 read_count = do_read(the_port, ch, request_count);
2363 if (read_count > 0) {
2364 tty_insert_flip_string(&state->port, ch, read_count);
2365 icount->rx += read_count;
2366 }
2367 }
2368
2369 spin_unlock_irqrestore(&the_port->lock, pflags);
2370
2371 tty_flip_buffer_push(&state->port);
2372}
2373
2374
2375
2376
2377
2378
2379static const char *ic4_type(struct uart_port *the_port)
2380{
2381 if (the_port->mapbase == PROTO_RS232)
2382 return "SGI IOC4 Serial [rs232]";
2383 else
2384 return "SGI IOC4 Serial [rs422]";
2385}
2386
2387
2388
2389
2390
2391
2392static unsigned int ic4_tx_empty(struct uart_port *the_port)
2393{
2394 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2395 unsigned int ret = 0;
2396
2397 if (port_is_active(port, the_port)) {
2398 if (readl(&port->ip_serial_regs->shadow) & IOC4_SHADOW_TEMT)
2399 ret = TIOCSER_TEMT;
2400 }
2401 return ret;
2402}
2403
2404
2405
2406
2407
2408
2409static void ic4_stop_tx(struct uart_port *the_port)
2410{
2411 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2412
2413 if (port_is_active(port, the_port))
2414 set_notification(port, N_OUTPUT_LOWAT, 0);
2415}
2416
2417
2418
2419
2420
2421
2422static void null_void_function(struct uart_port *the_port)
2423{
2424}
2425
2426
2427
2428
2429
2430
2431static void ic4_shutdown(struct uart_port *the_port)
2432{
2433 unsigned long port_flags;
2434 struct ioc4_port *port;
2435 struct uart_state *state;
2436
2437 port = get_ioc4_port(the_port, 0);
2438 if (!port)
2439 return;
2440
2441 state = the_port->state;
2442 port->ip_port = NULL;
2443
2444 wake_up_interruptible(&state->port.delta_msr_wait);
2445
2446 if (state->port.tty)
2447 set_bit(TTY_IO_ERROR, &state->port.tty->flags);
2448
2449 spin_lock_irqsave(&the_port->lock, port_flags);
2450 set_notification(port, N_ALL, 0);
2451 port->ip_flags = PORT_INACTIVE;
2452 spin_unlock_irqrestore(&the_port->lock, port_flags);
2453}
2454
2455
2456
2457
2458
2459
2460
2461static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2462{
2463 unsigned char mcr = 0;
2464 struct ioc4_port *port;
2465
2466 port = get_ioc4_port(the_port, 0);
2467 if (!port_is_active(port, the_port))
2468 return;
2469
2470 if (mctrl & TIOCM_RTS)
2471 mcr |= UART_MCR_RTS;
2472 if (mctrl & TIOCM_DTR)
2473 mcr |= UART_MCR_DTR;
2474 if (mctrl & TIOCM_OUT1)
2475 mcr |= UART_MCR_OUT1;
2476 if (mctrl & TIOCM_OUT2)
2477 mcr |= UART_MCR_OUT2;
2478 if (mctrl & TIOCM_LOOP)
2479 mcr |= UART_MCR_LOOP;
2480
2481 set_mcr(the_port, mcr, IOC4_SHADOW_DTR);
2482}
2483
2484
2485
2486
2487
2488
2489static unsigned int ic4_get_mctrl(struct uart_port *the_port)
2490{
2491 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2492 uint32_t shadow;
2493 unsigned int ret = 0;
2494
2495 if (!port_is_active(port, the_port))
2496 return 0;
2497
2498 shadow = readl(&port->ip_serial_regs->shadow);
2499 if (shadow & IOC4_SHADOW_DCD)
2500 ret |= TIOCM_CAR;
2501 if (shadow & IOC4_SHADOW_DR)
2502 ret |= TIOCM_DSR;
2503 if (shadow & IOC4_SHADOW_CTS)
2504 ret |= TIOCM_CTS;
2505 return ret;
2506}
2507
2508
2509
2510
2511
2512
2513static void ic4_start_tx(struct uart_port *the_port)
2514{
2515 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2516
2517 if (port_is_active(port, the_port)) {
2518 set_notification(port, N_OUTPUT_LOWAT, 1);
2519 enable_intrs(port, port->ip_hooks->intr_tx_mt);
2520 }
2521}
2522
2523
2524
2525
2526
2527
2528
2529static void ic4_break_ctl(struct uart_port *the_port, int break_state)
2530{
2531}
2532
2533
2534
2535
2536
2537
2538static int ic4_startup(struct uart_port *the_port)
2539{
2540 int retval;
2541 struct ioc4_port *port;
2542 struct ioc4_control *control;
2543 struct uart_state *state;
2544 unsigned long port_flags;
2545
2546 if (!the_port)
2547 return -ENODEV;
2548 port = get_ioc4_port(the_port, 1);
2549 if (!port)
2550 return -ENODEV;
2551 state = the_port->state;
2552
2553 control = port->ip_control;
2554 if (!control) {
2555 port->ip_port = NULL;
2556 return -ENODEV;
2557 }
2558
2559
2560 spin_lock_irqsave(&the_port->lock, port_flags);
2561 retval = ic4_startup_local(the_port);
2562 spin_unlock_irqrestore(&the_port->lock, port_flags);
2563 return retval;
2564}
2565
2566
2567
2568
2569
2570
2571
2572
2573static void
2574ic4_set_termios(struct uart_port *the_port,
2575 struct ktermios *termios, struct ktermios *old_termios)
2576{
2577 unsigned long port_flags;
2578
2579 spin_lock_irqsave(&the_port->lock, port_flags);
2580 ioc4_change_speed(the_port, termios, old_termios);
2581 spin_unlock_irqrestore(&the_port->lock, port_flags);
2582}
2583
2584
2585
2586
2587
2588
2589static int ic4_request_port(struct uart_port *port)
2590{
2591 return 0;
2592}
2593
2594
2595
2596static const struct uart_ops ioc4_ops = {
2597 .tx_empty = ic4_tx_empty,
2598 .set_mctrl = ic4_set_mctrl,
2599 .get_mctrl = ic4_get_mctrl,
2600 .stop_tx = ic4_stop_tx,
2601 .start_tx = ic4_start_tx,
2602 .stop_rx = null_void_function,
2603 .break_ctl = ic4_break_ctl,
2604 .startup = ic4_startup,
2605 .shutdown = ic4_shutdown,
2606 .set_termios = ic4_set_termios,
2607 .type = ic4_type,
2608 .release_port = null_void_function,
2609 .request_port = ic4_request_port,
2610};
2611
2612
2613
2614
2615
2616static struct uart_driver ioc4_uart_rs232 = {
2617 .owner = THIS_MODULE,
2618 .driver_name = "ioc4_serial_rs232",
2619 .dev_name = DEVICE_NAME_RS232,
2620 .major = DEVICE_MAJOR,
2621 .minor = DEVICE_MINOR_RS232,
2622 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2623};
2624
2625static struct uart_driver ioc4_uart_rs422 = {
2626 .owner = THIS_MODULE,
2627 .driver_name = "ioc4_serial_rs422",
2628 .dev_name = DEVICE_NAME_RS422,
2629 .major = DEVICE_MAJOR,
2630 .minor = DEVICE_MINOR_RS422,
2631 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2632};
2633
2634
2635
2636
2637
2638
2639
2640
2641static int ioc4_serial_remove_one(struct ioc4_driver_data *idd)
2642{
2643 int port_num, port_type;
2644 struct ioc4_control *control;
2645 struct uart_port *the_port;
2646 struct ioc4_port *port;
2647 struct ioc4_soft *soft;
2648
2649
2650 control = idd->idd_serial_data;
2651 if (!control)
2652 return 0;
2653
2654 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2655 for (port_type = UART_PORT_MIN;
2656 port_type < UART_PORT_COUNT;
2657 port_type++) {
2658 the_port = &control->ic_port[port_num].icp_uart_port
2659 [port_type];
2660 if (the_port) {
2661 switch (port_type) {
2662 case UART_PORT_RS422:
2663 uart_remove_one_port(&ioc4_uart_rs422,
2664 the_port);
2665 break;
2666 default:
2667 case UART_PORT_RS232:
2668 uart_remove_one_port(&ioc4_uart_rs232,
2669 the_port);
2670 break;
2671 }
2672 }
2673 }
2674 port = control->ic_port[port_num].icp_port;
2675
2676 if (!(port_num & 1) && port) {
2677 pci_free_consistent(port->ip_pdev,
2678 TOTAL_RING_BUF_SIZE,
2679 port->ip_cpu_ringbuf,
2680 port->ip_dma_ringbuf);
2681 kfree(port);
2682 }
2683 }
2684 soft = control->ic_soft;
2685 if (soft) {
2686 free_irq(control->ic_irq, soft);
2687 if (soft->is_ioc4_serial_addr) {
2688 iounmap(soft->is_ioc4_serial_addr);
2689 release_mem_region((unsigned long)
2690 soft->is_ioc4_serial_addr,
2691 sizeof(struct ioc4_serial));
2692 }
2693 kfree(soft);
2694 }
2695 kfree(control);
2696 idd->idd_serial_data = NULL;
2697
2698 return 0;
2699}
2700
2701
2702
2703
2704
2705
2706
2707static inline int
2708ioc4_serial_core_attach(struct pci_dev *pdev, int port_type)
2709{
2710 struct ioc4_port *port;
2711 struct uart_port *the_port;
2712 struct ioc4_driver_data *idd = pci_get_drvdata(pdev);
2713 struct ioc4_control *control = idd->idd_serial_data;
2714 int port_num;
2715 int port_type_idx;
2716 struct uart_driver *u_driver;
2717
2718
2719 DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n",
2720 __func__, pdev, (void *)control));
2721
2722 if (!control)
2723 return -ENODEV;
2724
2725 port_type_idx = (port_type == PROTO_RS232) ? UART_PORT_RS232
2726 : UART_PORT_RS422;
2727
2728 u_driver = (port_type == PROTO_RS232) ? &ioc4_uart_rs232
2729 : &ioc4_uart_rs422;
2730
2731
2732 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2733 the_port = &control->ic_port[port_num].icp_uart_port
2734 [port_type_idx];
2735 port = control->ic_port[port_num].icp_port;
2736 port->ip_all_ports[port_type_idx] = the_port;
2737
2738 DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p : type %s\n",
2739 __func__, (void *)the_port,
2740 (void *)port,
2741 port_type == PROTO_RS232 ? "rs232" : "rs422"));
2742
2743
2744 the_port->membase = (unsigned char __iomem *)1;
2745 the_port->iobase = (pdev->bus->number << 16) | port_num;
2746 the_port->line = (Num_of_ioc4_cards << 2) | port_num;
2747 the_port->mapbase = port_type;
2748 the_port->type = PORT_16550A;
2749 the_port->fifosize = IOC4_FIFO_CHARS;
2750 the_port->ops = &ioc4_ops;
2751 the_port->irq = control->ic_irq;
2752 the_port->dev = &pdev->dev;
2753 spin_lock_init(&the_port->lock);
2754 if (uart_add_one_port(u_driver, the_port) < 0) {
2755 printk(KERN_WARNING
2756 "%s: unable to add port %d bus %d\n",
2757 __func__, the_port->line, pdev->bus->number);
2758 } else {
2759 DPRINT_CONFIG(
2760 ("IOC4 serial port %d irq = %d, bus %d\n",
2761 the_port->line, the_port->irq, pdev->bus->number));
2762 }
2763 }
2764 return 0;
2765}
2766
2767
2768
2769
2770
2771
2772static int
2773ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2774{
2775 unsigned long tmp_addr1;
2776 struct ioc4_serial __iomem *serial;
2777 struct ioc4_soft *soft;
2778 struct ioc4_control *control;
2779 int ret = 0;
2780
2781
2782 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __func__, idd->idd_pdev,
2783 idd->idd_pci_id));
2784
2785
2786
2787
2788 if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
2789 return 0;
2790
2791
2792 tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET;
2793
2794 if (!request_mem_region(tmp_addr1, sizeof(struct ioc4_serial),
2795 "sioc4_uart")) {
2796 printk(KERN_WARNING
2797 "ioc4 (%p): unable to get request region for "
2798 "uart space\n", (void *)idd->idd_pdev);
2799 ret = -ENODEV;
2800 goto out1;
2801 }
2802 serial = ioremap(tmp_addr1, sizeof(struct ioc4_serial));
2803 if (!serial) {
2804 printk(KERN_WARNING
2805 "ioc4 (%p) : unable to remap ioc4 serial register\n",
2806 (void *)idd->idd_pdev);
2807 ret = -ENODEV;
2808 goto out2;
2809 }
2810 DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n",
2811 __func__, (void *)idd->idd_misc_regs,
2812 (void *)serial));
2813
2814
2815 control = kzalloc(sizeof(struct ioc4_control), GFP_KERNEL);
2816
2817 if (!control) {
2818 printk(KERN_WARNING "ioc4_attach_one"
2819 ": unable to get memory for the IOC4\n");
2820 ret = -ENOMEM;
2821 goto out2;
2822 }
2823 idd->idd_serial_data = control;
2824
2825
2826 soft = kzalloc(sizeof(struct ioc4_soft), GFP_KERNEL);
2827 if (!soft) {
2828 printk(KERN_WARNING
2829 "ioc4 (%p): unable to get memory for the soft struct\n",
2830 (void *)idd->idd_pdev);
2831 ret = -ENOMEM;
2832 goto out3;
2833 }
2834
2835 spin_lock_init(&soft->is_ir_lock);
2836 soft->is_ioc4_misc_addr = idd->idd_misc_regs;
2837 soft->is_ioc4_serial_addr = serial;
2838
2839
2840 writel(0xf << IOC4_SIO_CR_CMD_PULSE_SHIFT,
2841 &idd->idd_misc_regs->sio_cr.raw);
2842
2843
2844 writel(IOC4_GPCR_UART0_MODESEL | IOC4_GPCR_UART1_MODESEL
2845 | IOC4_GPCR_UART2_MODESEL | IOC4_GPCR_UART3_MODESEL,
2846 &idd->idd_misc_regs->gpcr_s.raw);
2847
2848
2849 write_ireg(soft, ~0, IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
2850 writel(~0, &idd->idd_misc_regs->sio_ir.raw);
2851 write_ireg(soft, IOC4_OTHER_IR_SER_MEMERR, IOC4_W_IEC,
2852 IOC4_OTHER_INTR_TYPE);
2853 writel(IOC4_OTHER_IR_SER_MEMERR, &idd->idd_misc_regs->other_ir.raw);
2854 control->ic_soft = soft;
2855
2856
2857 if (!request_irq(idd->idd_pdev->irq, ioc4_intr, IRQF_SHARED,
2858 "sgi-ioc4serial", soft)) {
2859 control->ic_irq = idd->idd_pdev->irq;
2860 } else {
2861 printk(KERN_WARNING
2862 "%s : request_irq fails for IRQ 0x%x\n ",
2863 __func__, idd->idd_pdev->irq);
2864 }
2865 ret = ioc4_attach_local(idd);
2866 if (ret)
2867 goto out4;
2868
2869
2870
2871 ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS232);
2872 if (ret)
2873 goto out4;
2874
2875 ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS422);
2876 if (ret)
2877 goto out5;
2878
2879 Num_of_ioc4_cards++;
2880
2881 return ret;
2882
2883
2884out5:
2885 ioc4_serial_remove_one(idd);
2886 return ret;
2887out4:
2888 kfree(soft);
2889out3:
2890 kfree(control);
2891out2:
2892 if (serial)
2893 iounmap(serial);
2894 release_mem_region(tmp_addr1, sizeof(struct ioc4_serial));
2895out1:
2896
2897 return ret;
2898}
2899
2900
2901static struct ioc4_submodule ioc4_serial_submodule = {
2902 .is_name = "IOC4_serial",
2903 .is_owner = THIS_MODULE,
2904 .is_probe = ioc4_serial_attach_one,
2905 .is_remove = ioc4_serial_remove_one,
2906};
2907
2908
2909
2910
2911static int __init ioc4_serial_init(void)
2912{
2913 int ret;
2914
2915
2916 if ((ret = uart_register_driver(&ioc4_uart_rs232)) < 0) {
2917 printk(KERN_WARNING
2918 "%s: Couldn't register rs232 IOC4 serial driver\n",
2919 __func__);
2920 goto out;
2921 }
2922 if ((ret = uart_register_driver(&ioc4_uart_rs422)) < 0) {
2923 printk(KERN_WARNING
2924 "%s: Couldn't register rs422 IOC4 serial driver\n",
2925 __func__);
2926 goto out_uart_rs232;
2927 }
2928
2929
2930 ret = ioc4_register_submodule(&ioc4_serial_submodule);
2931 if (ret)
2932 goto out_uart_rs422;
2933 return 0;
2934
2935out_uart_rs422:
2936 uart_unregister_driver(&ioc4_uart_rs422);
2937out_uart_rs232:
2938 uart_unregister_driver(&ioc4_uart_rs232);
2939out:
2940 return ret;
2941}
2942
2943static void __exit ioc4_serial_exit(void)
2944{
2945 ioc4_unregister_submodule(&ioc4_serial_submodule);
2946 uart_unregister_driver(&ioc4_uart_rs232);
2947 uart_unregister_driver(&ioc4_uart_rs422);
2948}
2949
2950late_initcall(ioc4_serial_init);
2951module_exit(ioc4_serial_exit);
2952
2953MODULE_AUTHOR("Pat Gefre - Silicon Graphics Inc. (SGI) <pfg@sgi.com>");
2954MODULE_DESCRIPTION("Serial PCI driver module for SGI IOC4 Base-IO Card");
2955MODULE_LICENSE("GPL");
2956