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11#ifndef __DRIVERS_USB_DWC3_CORE_H
12#define __DRIVERS_USB_DWC3_CORE_H
13
14#include <linux/device.h>
15#include <linux/spinlock.h>
16#include <linux/ioport.h>
17#include <linux/list.h>
18#include <linux/bitops.h>
19#include <linux/dma-mapping.h>
20#include <linux/mm.h>
21#include <linux/debugfs.h>
22#include <linux/wait.h>
23#include <linux/workqueue.h>
24
25#include <linux/usb/ch9.h>
26#include <linux/usb/gadget.h>
27#include <linux/usb/otg.h>
28#include <linux/ulpi/interface.h>
29
30#include <linux/phy/phy.h>
31
32#define DWC3_MSG_MAX 500
33
34
35#define DWC3_PULL_UP_TIMEOUT 500
36#define DWC3_BOUNCE_SIZE 1024
37#define DWC3_EP0_SETUP_SIZE 512
38#define DWC3_ENDPOINTS_NUM 32
39#define DWC3_XHCI_RESOURCES_NUM 2
40
41#define DWC3_SCRATCHBUF_SIZE 4096
42#define DWC3_EVENT_BUFFERS_SIZE 4096
43#define DWC3_EVENT_TYPE_MASK 0xfe
44
45#define DWC3_EVENT_TYPE_DEV 0
46#define DWC3_EVENT_TYPE_CARKIT 3
47#define DWC3_EVENT_TYPE_I2C 4
48
49#define DWC3_DEVICE_EVENT_DISCONNECT 0
50#define DWC3_DEVICE_EVENT_RESET 1
51#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
52#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
53#define DWC3_DEVICE_EVENT_WAKEUP 4
54#define DWC3_DEVICE_EVENT_HIBER_REQ 5
55#define DWC3_DEVICE_EVENT_EOPF 6
56#define DWC3_DEVICE_EVENT_SOF 7
57#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
58#define DWC3_DEVICE_EVENT_CMD_CMPL 10
59#define DWC3_DEVICE_EVENT_OVERFLOW 11
60
61
62#define DWC3_OTG_ROLE_IDLE 0
63#define DWC3_OTG_ROLE_HOST 1
64#define DWC3_OTG_ROLE_DEVICE 2
65
66#define DWC3_GEVNTCOUNT_MASK 0xfffc
67#define DWC3_GEVNTCOUNT_EHB BIT(31)
68#define DWC3_GSNPSID_MASK 0xffff0000
69#define DWC3_GSNPSREV_MASK 0xffff
70
71
72#define DWC3_XHCI_REGS_START 0x0
73#define DWC3_XHCI_REGS_END 0x7fff
74#define DWC3_GLOBALS_REGS_START 0xc100
75#define DWC3_GLOBALS_REGS_END 0xc6ff
76#define DWC3_DEVICE_REGS_START 0xc700
77#define DWC3_DEVICE_REGS_END 0xcbff
78#define DWC3_OTG_REGS_START 0xcc00
79#define DWC3_OTG_REGS_END 0xccff
80
81
82#define DWC3_GSBUSCFG0 0xc100
83#define DWC3_GSBUSCFG1 0xc104
84#define DWC3_GTXTHRCFG 0xc108
85#define DWC3_GRXTHRCFG 0xc10c
86#define DWC3_GCTL 0xc110
87#define DWC3_GEVTEN 0xc114
88#define DWC3_GSTS 0xc118
89#define DWC3_GUCTL1 0xc11c
90#define DWC3_GSNPSID 0xc120
91#define DWC3_GGPIO 0xc124
92#define DWC3_GUID 0xc128
93#define DWC3_GUCTL 0xc12c
94#define DWC3_GBUSERRADDR0 0xc130
95#define DWC3_GBUSERRADDR1 0xc134
96#define DWC3_GPRTBIMAP0 0xc138
97#define DWC3_GPRTBIMAP1 0xc13c
98#define DWC3_GHWPARAMS0 0xc140
99#define DWC3_GHWPARAMS1 0xc144
100#define DWC3_GHWPARAMS2 0xc148
101#define DWC3_GHWPARAMS3 0xc14c
102#define DWC3_GHWPARAMS4 0xc150
103#define DWC3_GHWPARAMS5 0xc154
104#define DWC3_GHWPARAMS6 0xc158
105#define DWC3_GHWPARAMS7 0xc15c
106#define DWC3_GDBGFIFOSPACE 0xc160
107#define DWC3_GDBGLTSSM 0xc164
108#define DWC3_GDBGBMU 0xc16c
109#define DWC3_GDBGLSPMUX 0xc170
110#define DWC3_GDBGLSP 0xc174
111#define DWC3_GDBGEPINFO0 0xc178
112#define DWC3_GDBGEPINFO1 0xc17c
113#define DWC3_GPRTBIMAP_HS0 0xc180
114#define DWC3_GPRTBIMAP_HS1 0xc184
115#define DWC3_GPRTBIMAP_FS0 0xc188
116#define DWC3_GPRTBIMAP_FS1 0xc18c
117#define DWC3_GUCTL2 0xc19c
118
119#define DWC3_VER_NUMBER 0xc1a0
120#define DWC3_VER_TYPE 0xc1a4
121
122#define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
123#define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
124
125#define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
126
127#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
128
129#define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
130#define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
131
132#define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
133#define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
134#define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
135#define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
136
137#define DWC3_GHWPARAMS8 0xc600
138#define DWC3_GFLADJ 0xc630
139
140
141#define DWC3_DCFG 0xc700
142#define DWC3_DCTL 0xc704
143#define DWC3_DEVTEN 0xc708
144#define DWC3_DSTS 0xc70c
145#define DWC3_DGCMDPAR 0xc710
146#define DWC3_DGCMD 0xc714
147#define DWC3_DALEPENA 0xc720
148
149#define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
150#define DWC3_DEPCMDPAR2 0x00
151#define DWC3_DEPCMDPAR1 0x04
152#define DWC3_DEPCMDPAR0 0x08
153#define DWC3_DEPCMD 0x0c
154
155#define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
156
157
158#define DWC3_OCFG 0xcc00
159#define DWC3_OCTL 0xcc04
160#define DWC3_OEVT 0xcc08
161#define DWC3_OEVTEN 0xcc0C
162#define DWC3_OSTS 0xcc10
163
164
165
166
167#define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
168#define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
169#define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
170
171#define DWC3_TXFIFOQ 0
172#define DWC3_RXFIFOQ 1
173#define DWC3_TXREQQ 2
174#define DWC3_RXREQQ 3
175#define DWC3_RXINFOQ 4
176#define DWC3_PSTATQ 5
177#define DWC3_DESCFETCHQ 6
178#define DWC3_EVENTQ 7
179#define DWC3_AUXEVENTQ 8
180
181
182#define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
183#define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
184#define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
185
186
187#define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
188#define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
189#define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
190#define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
191#define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
192#define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
193#define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
194#define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
195
196
197#define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
198#define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
199#define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26)
200#define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15)
201#define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
202#define DWC31_TXTHRNUMPKTSEL_PRD BIT(10)
203#define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
204#define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
205
206
207#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
208#define DWC3_GCTL_U2RSTECN BIT(16)
209#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
210#define DWC3_GCTL_CLK_BUS (0)
211#define DWC3_GCTL_CLK_PIPE (1)
212#define DWC3_GCTL_CLK_PIPEHALF (2)
213#define DWC3_GCTL_CLK_MASK (3)
214
215#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
216#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
217#define DWC3_GCTL_PRTCAP_HOST 1
218#define DWC3_GCTL_PRTCAP_DEVICE 2
219#define DWC3_GCTL_PRTCAP_OTG 3
220
221#define DWC3_GCTL_CORESOFTRESET BIT(11)
222#define DWC3_GCTL_SOFITPSYNC BIT(10)
223#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
224#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
225#define DWC3_GCTL_DISSCRAMBLE BIT(3)
226#define DWC3_GCTL_U2EXIT_LFPS BIT(2)
227#define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
228#define DWC3_GCTL_DSBLCLKGTNG BIT(0)
229
230
231#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
232#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
233
234
235#define DWC3_GSTS_OTG_IP BIT(10)
236#define DWC3_GSTS_BC_IP BIT(9)
237#define DWC3_GSTS_ADP_IP BIT(8)
238#define DWC3_GSTS_HOST_IP BIT(7)
239#define DWC3_GSTS_DEVICE_IP BIT(6)
240#define DWC3_GSTS_CSR_TIMEOUT BIT(5)
241#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
242
243
244#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
245#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
246#define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
247#define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
248#define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
249#define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
250#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
251#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
252#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
253#define USBTRDTIM_UTMI_8_BIT 9
254#define USBTRDTIM_UTMI_16_BIT 5
255#define UTMI_PHYIF_16_BIT 1
256#define UTMI_PHYIF_8_BIT 0
257
258
259#define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
260#define DWC3_GUSB2PHYACC_BUSY BIT(23)
261#define DWC3_GUSB2PHYACC_WRITE BIT(22)
262#define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
263#define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
264#define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
265
266
267#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
268#define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29)
269#define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
270#define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27)
271#define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24)
272#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
273#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
274#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
275#define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18)
276#define DWC3_GUSB3PIPECTL_SUSPHY BIT(17)
277#define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
278#define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8)
279#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
280#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
281
282
283#define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15)
284#define DWC31_GTXFIFOSIZ_TXFDEF(n) ((n) & 0x7fff)
285#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
286#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
287
288
289#define DWC3_GEVNTSIZ_INTMASK BIT(31)
290#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
291
292
293#define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
294#define DWC3_GHWPARAMS0_MODE_GADGET 0
295#define DWC3_GHWPARAMS0_MODE_HOST 1
296#define DWC3_GHWPARAMS0_MODE_DRD 2
297#define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
298#define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
299#define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
300#define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
301#define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
302
303
304#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
305#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
306#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
307#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
308#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
309#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
310
311
312#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
313#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
314#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
315#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2
316#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
317#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
318#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
319#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
320#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
321#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
322#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
323#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
324
325
326#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
327#define DWC3_MAX_HIBER_SCRATCHBUFS 15
328
329
330#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
331#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
332#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
333#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
334#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
335#define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
336
337
338#define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
339#define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
340
341
342#define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
343#define DWC3_GFLADJ_30MHZ_MASK 0x3f
344
345
346#define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
347
348
349#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
350#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
351
352#define DWC3_DCFG_SPEED_MASK (7 << 0)
353#define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0)
354#define DWC3_DCFG_SUPERSPEED (4 << 0)
355#define DWC3_DCFG_HIGHSPEED (0 << 0)
356#define DWC3_DCFG_FULLSPEED BIT(0)
357#define DWC3_DCFG_LOWSPEED (2 << 0)
358
359#define DWC3_DCFG_NUMP_SHIFT 17
360#define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
361#define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
362#define DWC3_DCFG_LPM_CAP BIT(22)
363
364
365#define DWC3_DCTL_RUN_STOP BIT(31)
366#define DWC3_DCTL_CSFTRST BIT(30)
367#define DWC3_DCTL_LSFTRST BIT(29)
368
369#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
370#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
371
372#define DWC3_DCTL_APPL1RES BIT(23)
373
374
375#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
376#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
377#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
378#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
379#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
380#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
381#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
382
383
384#define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
385#define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
386
387#define DWC3_DCTL_KEEP_CONNECT BIT(19)
388#define DWC3_DCTL_L1_HIBER_EN BIT(18)
389#define DWC3_DCTL_CRS BIT(17)
390#define DWC3_DCTL_CSS BIT(16)
391
392#define DWC3_DCTL_INITU2ENA BIT(12)
393#define DWC3_DCTL_ACCEPTU2ENA BIT(11)
394#define DWC3_DCTL_INITU1ENA BIT(10)
395#define DWC3_DCTL_ACCEPTU1ENA BIT(9)
396#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
397
398#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
399#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
400
401#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
402#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
403#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
404#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
405#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
406#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
407#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
408
409
410#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
411#define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
412#define DWC3_DEVTEN_CMDCMPLTEN BIT(10)
413#define DWC3_DEVTEN_ERRTICERREN BIT(9)
414#define DWC3_DEVTEN_SOFEN BIT(7)
415#define DWC3_DEVTEN_EOPFEN BIT(6)
416#define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
417#define DWC3_DEVTEN_WKUPEVTEN BIT(4)
418#define DWC3_DEVTEN_ULSTCNGEN BIT(3)
419#define DWC3_DEVTEN_CONNECTDONEEN BIT(2)
420#define DWC3_DEVTEN_USBRSTEN BIT(1)
421#define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
422
423
424#define DWC3_DSTS_DCNRD BIT(29)
425
426
427#define DWC3_DSTS_PWRUPREQ BIT(24)
428
429
430#define DWC3_DSTS_RSS BIT(25)
431#define DWC3_DSTS_SSS BIT(24)
432
433#define DWC3_DSTS_COREIDLE BIT(23)
434#define DWC3_DSTS_DEVCTRLHLT BIT(22)
435
436#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
437#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
438
439#define DWC3_DSTS_RXFIFOEMPTY BIT(17)
440
441#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
442#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
443
444#define DWC3_DSTS_CONNECTSPD (7 << 0)
445
446#define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0)
447#define DWC3_DSTS_SUPERSPEED (4 << 0)
448#define DWC3_DSTS_HIGHSPEED (0 << 0)
449#define DWC3_DSTS_FULLSPEED BIT(0)
450#define DWC3_DSTS_LOWSPEED (2 << 0)
451
452
453#define DWC3_DGCMD_SET_LMP 0x01
454#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
455#define DWC3_DGCMD_XMIT_FUNCTION 0x03
456
457
458#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
459#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
460
461#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
462#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
463#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
464#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
465
466#define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
467#define DWC3_DGCMD_CMDACT BIT(10)
468#define DWC3_DGCMD_CMDIOC BIT(8)
469
470
471#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
472#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
473#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
474#define DWC3_DGCMDPAR_TX_FIFO BIT(5)
475#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
476#define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
477
478
479#define DWC3_DEPCMD_PARAM_SHIFT 16
480#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
481#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
482#define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
483#define DWC3_DEPCMD_HIPRI_FORCERM BIT(11)
484#define DWC3_DEPCMD_CLEARPENDIN BIT(11)
485#define DWC3_DEPCMD_CMDACT BIT(10)
486#define DWC3_DEPCMD_CMDIOC BIT(8)
487
488#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
489#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
490#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
491#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
492#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
493#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
494
495#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
496
497#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
498#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
499#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
500
501#define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
502
503
504#define DWC3_DALEPENA_EP(n) BIT(n)
505
506#define DWC3_DEPCMD_TYPE_CONTROL 0
507#define DWC3_DEPCMD_TYPE_ISOC 1
508#define DWC3_DEPCMD_TYPE_BULK 2
509#define DWC3_DEPCMD_TYPE_INTR 3
510
511#define DWC3_DEV_IMOD_COUNT_SHIFT 16
512#define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
513#define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
514#define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
515
516
517#define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
518#define DWC3_OCFG_HIBDISMASK BIT(4)
519#define DWC3_OCFG_SFTRSTMASK BIT(3)
520#define DWC3_OCFG_OTGVERSION BIT(2)
521#define DWC3_OCFG_HNPCAP BIT(1)
522#define DWC3_OCFG_SRPCAP BIT(0)
523
524
525#define DWC3_OCTL_OTG3GOERR BIT(7)
526#define DWC3_OCTL_PERIMODE BIT(6)
527#define DWC3_OCTL_PRTPWRCTL BIT(5)
528#define DWC3_OCTL_HNPREQ BIT(4)
529#define DWC3_OCTL_SESREQ BIT(3)
530#define DWC3_OCTL_TERMSELIDPULSE BIT(2)
531#define DWC3_OCTL_DEVSETHNPEN BIT(1)
532#define DWC3_OCTL_HSTSETHNPEN BIT(0)
533
534
535#define DWC3_OEVT_DEVICEMODE BIT(31)
536#define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
537#define DWC3_OEVT_DEVRUNSTPSET BIT(26)
538#define DWC3_OEVT_HIBENTRY BIT(25)
539#define DWC3_OEVT_CONIDSTSCHNG BIT(24)
540#define DWC3_OEVT_HRRCONFNOTIF BIT(23)
541#define DWC3_OEVT_HRRINITNOTIF BIT(22)
542#define DWC3_OEVT_ADEVIDLE BIT(21)
543#define DWC3_OEVT_ADEVBHOSTEND BIT(20)
544#define DWC3_OEVT_ADEVHOST BIT(19)
545#define DWC3_OEVT_ADEVHNPCHNG BIT(18)
546#define DWC3_OEVT_ADEVSRPDET BIT(17)
547#define DWC3_OEVT_ADEVSESSENDDET BIT(16)
548#define DWC3_OEVT_BDEVBHOSTEND BIT(11)
549#define DWC3_OEVT_BDEVHNPCHNG BIT(10)
550#define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
551#define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
552#define DWC3_OEVT_BSESSVLD BIT(3)
553#define DWC3_OEVT_HSTNEGSTS BIT(2)
554#define DWC3_OEVT_SESREQSTS BIT(1)
555#define DWC3_OEVT_ERROR BIT(0)
556
557
558#define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
559#define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
560#define DWC3_OEVTEN_HIBENTRYEN BIT(25)
561#define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
562#define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
563#define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
564#define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
565#define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
566#define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
567#define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
568#define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
569#define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
570#define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
571#define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
572#define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
573#define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
574
575
576#define DWC3_OSTS_DEVRUNSTP BIT(13)
577#define DWC3_OSTS_XHCIRUNSTP BIT(12)
578#define DWC3_OSTS_PERIPHERALSTATE BIT(4)
579#define DWC3_OSTS_XHCIPRTPOWER BIT(3)
580#define DWC3_OSTS_BSESVLD BIT(2)
581#define DWC3_OSTS_VBUSVLD BIT(1)
582#define DWC3_OSTS_CONIDSTS BIT(0)
583
584
585
586struct dwc3_trb;
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599struct dwc3_event_buffer {
600 void *buf;
601 void *cache;
602 unsigned length;
603 unsigned int lpos;
604 unsigned int count;
605 unsigned int flags;
606
607#define DWC3_EVENT_PENDING BIT(0)
608
609 dma_addr_t dma;
610
611 struct dwc3 *dwc;
612};
613
614#define DWC3_EP_FLAG_STALLED BIT(0)
615#define DWC3_EP_FLAG_WEDGED BIT(1)
616
617#define DWC3_EP_DIRECTION_TX true
618#define DWC3_EP_DIRECTION_RX false
619
620#define DWC3_TRB_NUM 256
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646struct dwc3_ep {
647 struct usb_ep endpoint;
648 struct list_head pending_list;
649 struct list_head started_list;
650
651 wait_queue_head_t wait_end_transfer;
652
653 spinlock_t lock;
654 void __iomem *regs;
655
656 struct dwc3_trb *trb_pool;
657 dma_addr_t trb_pool_dma;
658 struct dwc3 *dwc;
659
660 u32 saved_state;
661 unsigned flags;
662#define DWC3_EP_ENABLED BIT(0)
663#define DWC3_EP_STALL BIT(1)
664#define DWC3_EP_WEDGE BIT(2)
665#define DWC3_EP_TRANSFER_STARTED BIT(3)
666#define DWC3_EP_PENDING_REQUEST BIT(5)
667#define DWC3_EP_END_TRANSFER_PENDING BIT(7)
668
669
670#define DWC3_EP0_DIR_IN BIT(31)
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681 u8 trb_enqueue;
682 u8 trb_dequeue;
683
684 u8 number;
685 u8 type;
686 u8 resource_index;
687 u32 frame_number;
688 u32 interval;
689
690 char name[20];
691
692 unsigned direction:1;
693 unsigned stream_capable:1;
694};
695
696enum dwc3_phy {
697 DWC3_PHY_UNKNOWN = 0,
698 DWC3_PHY_USB3,
699 DWC3_PHY_USB2,
700};
701
702enum dwc3_ep0_next {
703 DWC3_EP0_UNKNOWN = 0,
704 DWC3_EP0_COMPLETE,
705 DWC3_EP0_NRDY_DATA,
706 DWC3_EP0_NRDY_STATUS,
707};
708
709enum dwc3_ep0_state {
710 EP0_UNCONNECTED = 0,
711 EP0_SETUP_PHASE,
712 EP0_DATA_PHASE,
713 EP0_STATUS_PHASE,
714};
715
716enum dwc3_link_state {
717
718 DWC3_LINK_STATE_U0 = 0x00,
719 DWC3_LINK_STATE_U1 = 0x01,
720 DWC3_LINK_STATE_U2 = 0x02,
721 DWC3_LINK_STATE_U3 = 0x03,
722 DWC3_LINK_STATE_SS_DIS = 0x04,
723 DWC3_LINK_STATE_RX_DET = 0x05,
724 DWC3_LINK_STATE_SS_INACT = 0x06,
725 DWC3_LINK_STATE_POLL = 0x07,
726 DWC3_LINK_STATE_RECOV = 0x08,
727 DWC3_LINK_STATE_HRESET = 0x09,
728 DWC3_LINK_STATE_CMPLY = 0x0a,
729 DWC3_LINK_STATE_LPBK = 0x0b,
730 DWC3_LINK_STATE_RESET = 0x0e,
731 DWC3_LINK_STATE_RESUME = 0x0f,
732 DWC3_LINK_STATE_MASK = 0x0f,
733};
734
735
736#define DWC3_TRB_SIZE_MASK (0x00ffffff)
737#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
738#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
739#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
740
741#define DWC3_TRBSTS_OK 0
742#define DWC3_TRBSTS_MISSED_ISOC 1
743#define DWC3_TRBSTS_SETUP_PENDING 2
744#define DWC3_TRB_STS_XFER_IN_PROG 4
745
746
747#define DWC3_TRB_CTRL_HWO BIT(0)
748#define DWC3_TRB_CTRL_LST BIT(1)
749#define DWC3_TRB_CTRL_CHN BIT(2)
750#define DWC3_TRB_CTRL_CSP BIT(3)
751#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
752#define DWC3_TRB_CTRL_ISP_IMI BIT(10)
753#define DWC3_TRB_CTRL_IOC BIT(11)
754#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
755
756#define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
757#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
758#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
759#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
760#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
761#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
762#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
763#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
764#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
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773struct dwc3_trb {
774 u32 bpl;
775 u32 bph;
776 u32 size;
777 u32 ctrl;
778} __packed;
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792struct dwc3_hwparams {
793 u32 hwparams0;
794 u32 hwparams1;
795 u32 hwparams2;
796 u32 hwparams3;
797 u32 hwparams4;
798 u32 hwparams5;
799 u32 hwparams6;
800 u32 hwparams7;
801 u32 hwparams8;
802};
803
804
805#define DWC3_MODE(n) ((n) & 0x7)
806
807#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
808
809
810#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
811
812
813#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
814#define DWC3_NUM_EPS_MASK (0x3f << 12)
815#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
816 (DWC3_NUM_EPS_MASK)) >> 12)
817#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
818 (DWC3_NUM_IN_EPS_MASK)) >> 18)
819
820
821#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
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842struct dwc3_request {
843 struct usb_request request;
844 struct list_head list;
845 struct dwc3_ep *dep;
846 struct scatterlist *sg;
847 struct scatterlist *start_sg;
848
849 unsigned num_pending_sgs;
850 unsigned int num_queued_sgs;
851 unsigned remaining;
852 u8 epnum;
853 struct dwc3_trb *trb;
854 dma_addr_t trb_dma;
855
856 unsigned unaligned:1;
857 unsigned direction:1;
858 unsigned mapped:1;
859 unsigned started:1;
860 unsigned zero:1;
861};
862
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865
866
867struct dwc3_scratchpad_array {
868 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
869};
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990struct dwc3 {
991 struct work_struct drd_work;
992 struct dwc3_trb *ep0_trb;
993 void *bounce;
994 void *scratchbuf;
995 u8 *setup_buf;
996 dma_addr_t ep0_trb_addr;
997 dma_addr_t bounce_addr;
998 dma_addr_t scratch_addr;
999 struct dwc3_request ep0_usb_req;
1000 struct completion ep0_in_setup;
1001
1002
1003 spinlock_t lock;
1004
1005 struct device *dev;
1006 struct device *sysdev;
1007
1008 struct platform_device *xhci;
1009 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
1010
1011 struct dwc3_event_buffer *ev_buf;
1012 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
1013
1014 struct usb_gadget gadget;
1015 struct usb_gadget_driver *gadget_driver;
1016
1017 struct clk_bulk_data *clks;
1018 int num_clks;
1019
1020 struct reset_control *reset;
1021
1022 struct usb_phy *usb2_phy;
1023 struct usb_phy *usb3_phy;
1024
1025 struct phy *usb2_generic_phy;
1026 struct phy *usb3_generic_phy;
1027
1028 bool phys_ready;
1029
1030 struct ulpi *ulpi;
1031 bool ulpi_ready;
1032
1033 void __iomem *regs;
1034 size_t regs_size;
1035
1036 enum usb_dr_mode dr_mode;
1037 u32 current_dr_role;
1038 u32 desired_dr_role;
1039 struct extcon_dev *edev;
1040 struct notifier_block edev_nb;
1041 enum usb_phy_interface hsphy_mode;
1042
1043 u32 fladj;
1044 u32 irq_gadget;
1045 u32 otg_irq;
1046 u32 current_otg_role;
1047 u32 desired_otg_role;
1048 bool otg_restart_host;
1049 u32 nr_scratch;
1050 u32 u1u2;
1051 u32 maximum_speed;
1052
1053
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1058
1059
1060 u32 revision;
1061
1062#define DWC3_REVISION_173A 0x5533173a
1063#define DWC3_REVISION_175A 0x5533175a
1064#define DWC3_REVISION_180A 0x5533180a
1065#define DWC3_REVISION_183A 0x5533183a
1066#define DWC3_REVISION_185A 0x5533185a
1067#define DWC3_REVISION_187A 0x5533187a
1068#define DWC3_REVISION_188A 0x5533188a
1069#define DWC3_REVISION_190A 0x5533190a
1070#define DWC3_REVISION_194A 0x5533194a
1071#define DWC3_REVISION_200A 0x5533200a
1072#define DWC3_REVISION_202A 0x5533202a
1073#define DWC3_REVISION_210A 0x5533210a
1074#define DWC3_REVISION_220A 0x5533220a
1075#define DWC3_REVISION_230A 0x5533230a
1076#define DWC3_REVISION_240A 0x5533240a
1077#define DWC3_REVISION_250A 0x5533250a
1078#define DWC3_REVISION_260A 0x5533260a
1079#define DWC3_REVISION_270A 0x5533270a
1080#define DWC3_REVISION_280A 0x5533280a
1081#define DWC3_REVISION_290A 0x5533290a
1082#define DWC3_REVISION_300A 0x5533300a
1083#define DWC3_REVISION_310A 0x5533310a
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1088
1089#define DWC3_REVISION_IS_DWC31 0x80000000
1090#define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31)
1091#define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31)
1092
1093 enum dwc3_ep0_next ep0_next_event;
1094 enum dwc3_ep0_state ep0state;
1095 enum dwc3_link_state link_state;
1096
1097 u16 u2sel;
1098 u16 u2pel;
1099 u8 u1sel;
1100 u8 u1pel;
1101
1102 u8 speed;
1103
1104 u8 num_eps;
1105
1106 struct dwc3_hwparams hwparams;
1107 struct dentry *root;
1108 struct debugfs_regset32 *regset;
1109
1110 u8 test_mode;
1111 u8 test_mode_nr;
1112 u8 lpm_nyet_threshold;
1113 u8 hird_threshold;
1114 u8 rx_thr_num_pkt_prd;
1115 u8 rx_max_burst_prd;
1116 u8 tx_thr_num_pkt_prd;
1117 u8 tx_max_burst_prd;
1118
1119 const char *hsphy_interface;
1120
1121 unsigned connected:1;
1122 unsigned delayed_status:1;
1123 unsigned ep0_bounced:1;
1124 unsigned ep0_expect_in:1;
1125 unsigned has_hibernation:1;
1126 unsigned sysdev_is_parent:1;
1127 unsigned has_lpm_erratum:1;
1128 unsigned is_utmi_l1_suspend:1;
1129 unsigned is_fpga:1;
1130 unsigned pending_events:1;
1131 unsigned pullups_connected:1;
1132 unsigned setup_packet_pending:1;
1133 unsigned three_stage_setup:1;
1134 unsigned usb3_lpm_capable:1;
1135
1136 unsigned disable_scramble_quirk:1;
1137 unsigned u2exit_lfps_quirk:1;
1138 unsigned u2ss_inp3_quirk:1;
1139 unsigned req_p1p2p3_quirk:1;
1140 unsigned del_p1p2p3_quirk:1;
1141 unsigned del_phy_power_chg_quirk:1;
1142 unsigned lfps_filter_quirk:1;
1143 unsigned rx_detect_poll_quirk:1;
1144 unsigned dis_u3_susphy_quirk:1;
1145 unsigned dis_u2_susphy_quirk:1;
1146 unsigned dis_enblslpm_quirk:1;
1147 unsigned dis_rxdet_inp3_quirk:1;
1148 unsigned dis_u2_freeclk_exists_quirk:1;
1149 unsigned dis_del_phy_power_chg_quirk:1;
1150 unsigned dis_tx_ipgap_linecheck_quirk:1;
1151
1152 unsigned tx_de_emphasis_quirk:1;
1153 unsigned tx_de_emphasis:2;
1154
1155 unsigned dis_metastability_quirk:1;
1156
1157 u16 imod_interval;
1158};
1159
1160#define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
1161
1162
1163
1164struct dwc3_event_type {
1165 u32 is_devspec:1;
1166 u32 type:7;
1167 u32 reserved8_31:24;
1168} __packed;
1169
1170#define DWC3_DEPEVT_XFERCOMPLETE 0x01
1171#define DWC3_DEPEVT_XFERINPROGRESS 0x02
1172#define DWC3_DEPEVT_XFERNOTREADY 0x03
1173#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1174#define DWC3_DEPEVT_STREAMEVT 0x06
1175#define DWC3_DEPEVT_EPCMDCMPLT 0x07
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1196struct dwc3_event_depevt {
1197 u32 one_bit:1;
1198 u32 endpoint_number:5;
1199 u32 endpoint_event:4;
1200 u32 reserved11_10:2;
1201 u32 status:4;
1202
1203
1204#define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3)
1205
1206
1207#define DEPEVT_STATUS_BUSERR BIT(0)
1208#define DEPEVT_STATUS_SHORT BIT(1)
1209#define DEPEVT_STATUS_IOC BIT(2)
1210#define DEPEVT_STATUS_LST BIT(3)
1211#define DEPEVT_STATUS_MISSED_ISOC BIT(3)
1212
1213
1214#define DEPEVT_STREAMEVT_FOUND 1
1215#define DEPEVT_STREAMEVT_NOTFOUND 2
1216
1217
1218#define DEPEVT_STATUS_CONTROL_DATA 1
1219#define DEPEVT_STATUS_CONTROL_STATUS 2
1220#define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3)
1221
1222
1223#define DEPEVT_TRANSFER_NO_RESOURCE 1
1224#define DEPEVT_TRANSFER_BUS_EXPIRY 2
1225
1226 u32 parameters:16;
1227
1228
1229#define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1230} __packed;
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254struct dwc3_event_devt {
1255 u32 one_bit:1;
1256 u32 device_event:7;
1257 u32 type:4;
1258 u32 reserved15_12:4;
1259 u32 event_info:9;
1260 u32 reserved31_25:7;
1261} __packed;
1262
1263
1264
1265
1266
1267
1268
1269
1270struct dwc3_event_gevt {
1271 u32 one_bit:1;
1272 u32 device_event:7;
1273 u32 phy_port_number:4;
1274 u32 reserved31_12:20;
1275} __packed;
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285union dwc3_event {
1286 u32 raw;
1287 struct dwc3_event_type type;
1288 struct dwc3_event_depevt depevt;
1289 struct dwc3_event_devt devt;
1290 struct dwc3_event_gevt gevt;
1291};
1292
1293
1294
1295
1296
1297
1298
1299
1300struct dwc3_gadget_ep_cmd_params {
1301 u32 param2;
1302 u32 param1;
1303 u32 param0;
1304};
1305
1306
1307
1308
1309
1310#define DWC3_HAS_PERIPHERAL BIT(0)
1311#define DWC3_HAS_XHCI BIT(1)
1312#define DWC3_HAS_OTG BIT(3)
1313
1314
1315void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode);
1316void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1317u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1318
1319
1320static inline bool dwc3_is_usb3(struct dwc3 *dwc)
1321{
1322 return !(dwc->revision & DWC3_REVISION_IS_DWC31);
1323}
1324
1325
1326static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1327{
1328 return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1329}
1330
1331bool dwc3_has_imod(struct dwc3 *dwc);
1332
1333int dwc3_event_buffers_setup(struct dwc3 *dwc);
1334void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1335
1336#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1337int dwc3_host_init(struct dwc3 *dwc);
1338void dwc3_host_exit(struct dwc3 *dwc);
1339#else
1340static inline int dwc3_host_init(struct dwc3 *dwc)
1341{ return 0; }
1342static inline void dwc3_host_exit(struct dwc3 *dwc)
1343{ }
1344#endif
1345
1346#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1347int dwc3_gadget_init(struct dwc3 *dwc);
1348void dwc3_gadget_exit(struct dwc3 *dwc);
1349int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1350int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1351int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1352int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1353 struct dwc3_gadget_ep_cmd_params *params);
1354int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1355#else
1356static inline int dwc3_gadget_init(struct dwc3 *dwc)
1357{ return 0; }
1358static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1359{ }
1360static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1361{ return 0; }
1362static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1363{ return 0; }
1364static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1365 enum dwc3_link_state state)
1366{ return 0; }
1367
1368static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1369 struct dwc3_gadget_ep_cmd_params *params)
1370{ return 0; }
1371static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1372 int cmd, u32 param)
1373{ return 0; }
1374#endif
1375
1376#if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1377int dwc3_drd_init(struct dwc3 *dwc);
1378void dwc3_drd_exit(struct dwc3 *dwc);
1379void dwc3_otg_init(struct dwc3 *dwc);
1380void dwc3_otg_exit(struct dwc3 *dwc);
1381void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus);
1382void dwc3_otg_host_init(struct dwc3 *dwc);
1383#else
1384static inline int dwc3_drd_init(struct dwc3 *dwc)
1385{ return 0; }
1386static inline void dwc3_drd_exit(struct dwc3 *dwc)
1387{ }
1388static inline void dwc3_otg_init(struct dwc3 *dwc)
1389{ }
1390static inline void dwc3_otg_exit(struct dwc3 *dwc)
1391{ }
1392static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
1393{ }
1394static inline void dwc3_otg_host_init(struct dwc3 *dwc)
1395{ }
1396#endif
1397
1398
1399#if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1400int dwc3_gadget_suspend(struct dwc3 *dwc);
1401int dwc3_gadget_resume(struct dwc3 *dwc);
1402void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1403#else
1404static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1405{
1406 return 0;
1407}
1408
1409static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1410{
1411 return 0;
1412}
1413
1414static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1415{
1416}
1417#endif
1418
1419#if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1420int dwc3_ulpi_init(struct dwc3 *dwc);
1421void dwc3_ulpi_exit(struct dwc3 *dwc);
1422#else
1423static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1424{ return 0; }
1425static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1426{ }
1427#endif
1428
1429#endif
1430