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9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/dma-mapping.h>
12#include <linux/firmware.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of_device.h>
17#include <linux/phy/phy.h>
18#include <linux/phy/tegra/xusb.h>
19#include <linux/platform_device.h>
20#include <linux/pm.h>
21#include <linux/pm_runtime.h>
22#include <linux/regulator/consumer.h>
23#include <linux/reset.h>
24#include <linux/slab.h>
25#include <soc/tegra/pmc.h>
26
27#include "xhci.h"
28
29#define TEGRA_XHCI_SS_HIGH_SPEED 120000000
30#define TEGRA_XHCI_SS_LOW_SPEED 12000000
31
32
33#define XUSB_CFG_1 0x004
34#define XUSB_IO_SPACE_EN BIT(0)
35#define XUSB_MEM_SPACE_EN BIT(1)
36#define XUSB_BUS_MASTER_EN BIT(2)
37#define XUSB_CFG_4 0x010
38#define XUSB_BASE_ADDR_SHIFT 15
39#define XUSB_BASE_ADDR_MASK 0x1ffff
40#define XUSB_CFG_ARU_C11_CSBRANGE 0x41c
41#define XUSB_CFG_CSB_BASE_ADDR 0x800
42
43
44#define XUSB_CFG_ARU_MBOX_CMD 0x0e4
45#define MBOX_DEST_FALC BIT(27)
46#define MBOX_DEST_PME BIT(28)
47#define MBOX_DEST_SMI BIT(29)
48#define MBOX_DEST_XHCI BIT(30)
49#define MBOX_INT_EN BIT(31)
50#define XUSB_CFG_ARU_MBOX_DATA_IN 0x0e8
51#define CMD_DATA_SHIFT 0
52#define CMD_DATA_MASK 0xffffff
53#define CMD_TYPE_SHIFT 24
54#define CMD_TYPE_MASK 0xff
55#define XUSB_CFG_ARU_MBOX_DATA_OUT 0x0ec
56#define XUSB_CFG_ARU_MBOX_OWNER 0x0f0
57#define MBOX_OWNER_NONE 0
58#define MBOX_OWNER_FW 1
59#define MBOX_OWNER_SW 2
60#define XUSB_CFG_ARU_SMI_INTR 0x428
61#define MBOX_SMI_INTR_FW_HANG BIT(1)
62#define MBOX_SMI_INTR_EN BIT(3)
63
64
65#define IPFS_XUSB_HOST_CONFIGURATION_0 0x180
66#define IPFS_EN_FPCI BIT(0)
67#define IPFS_XUSB_HOST_INTR_MASK_0 0x188
68#define IPFS_IP_INT_MASK BIT(16)
69#define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc
70
71#define CSB_PAGE_SELECT_MASK 0x7fffff
72#define CSB_PAGE_SELECT_SHIFT 9
73#define CSB_PAGE_OFFSET_MASK 0x1ff
74#define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \
75 CSB_PAGE_SELECT_MASK)
76#define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK)
77
78
79#define XUSB_FALC_CPUCTL 0x100
80#define CPUCTL_STARTCPU BIT(1)
81#define CPUCTL_STATE_HALTED BIT(4)
82#define CPUCTL_STATE_STOPPED BIT(5)
83#define XUSB_FALC_BOOTVEC 0x104
84#define XUSB_FALC_DMACTL 0x10c
85#define XUSB_FALC_IMFILLRNG1 0x154
86#define IMFILLRNG1_TAG_MASK 0xffff
87#define IMFILLRNG1_TAG_LO_SHIFT 0
88#define IMFILLRNG1_TAG_HI_SHIFT 16
89#define XUSB_FALC_IMFILLCTL 0x158
90
91
92#define XUSB_CSB_MP_ILOAD_ATTR 0x101a00
93#define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04
94#define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08
95#define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10
96#define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8
97#define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff
98#define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24
99#define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff
100#define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14
101#define L2IMEMOP_ACTION_SHIFT 24
102#define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT)
103#define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT)
104#define XUSB_CSB_MP_APMAP 0x10181c
105#define APMAP_BOOTPATH BIT(31)
106
107#define IMEM_BLOCK_SIZE 256
108
109struct tegra_xusb_fw_header {
110 u32 boot_loadaddr_in_imem;
111 u32 boot_codedfi_offset;
112 u32 boot_codetag;
113 u32 boot_codesize;
114 u32 phys_memaddr;
115 u16 reqphys_memsize;
116 u16 alloc_phys_memsize;
117 u32 rodata_img_offset;
118 u32 rodata_section_start;
119 u32 rodata_section_end;
120 u32 main_fnaddr;
121 u32 fwimg_cksum;
122 u32 fwimg_created_time;
123 u32 imem_resident_start;
124 u32 imem_resident_end;
125 u32 idirect_start;
126 u32 idirect_end;
127 u32 l2_imem_start;
128 u32 l2_imem_end;
129 u32 version_id;
130 u8 init_ddirect;
131 u8 reserved[3];
132 u32 phys_addr_log_buffer;
133 u32 total_log_entries;
134 u32 dequeue_ptr;
135 u32 dummy_var[2];
136 u32 fwimg_len;
137 u8 magic[8];
138 u32 ss_low_power_entry_timeout;
139 u8 num_hsic_port;
140 u8 padding[139];
141};
142
143struct tegra_xusb_phy_type {
144 const char *name;
145 unsigned int num;
146};
147
148struct tegra_xusb_soc {
149 const char *firmware;
150 const char * const *supply_names;
151 unsigned int num_supplies;
152 const struct tegra_xusb_phy_type *phy_types;
153 unsigned int num_types;
154
155 struct {
156 struct {
157 unsigned int offset;
158 unsigned int count;
159 } usb2, ulpi, hsic, usb3;
160 } ports;
161
162 bool scale_ss_clock;
163};
164
165struct tegra_xusb {
166 struct device *dev;
167 void __iomem *regs;
168 struct usb_hcd *hcd;
169
170 struct mutex lock;
171
172 int xhci_irq;
173 int mbox_irq;
174
175 void __iomem *ipfs_base;
176 void __iomem *fpci_base;
177
178 const struct tegra_xusb_soc *soc;
179
180 struct regulator_bulk_data *supplies;
181
182 struct tegra_xusb_padctl *padctl;
183
184 struct clk *host_clk;
185 struct clk *falcon_clk;
186 struct clk *ss_clk;
187 struct clk *ss_src_clk;
188 struct clk *hs_src_clk;
189 struct clk *fs_src_clk;
190 struct clk *pll_u_480m;
191 struct clk *clk_m;
192 struct clk *pll_e;
193
194 struct reset_control *host_rst;
195 struct reset_control *ss_rst;
196
197 struct phy **phys;
198 unsigned int num_phys;
199
200
201 struct {
202 size_t size;
203 void *virt;
204 dma_addr_t phys;
205 } fw;
206};
207
208static struct hc_driver __read_mostly tegra_xhci_hc_driver;
209
210static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
211{
212 return readl(tegra->fpci_base + offset);
213}
214
215static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
216 unsigned int offset)
217{
218 writel(value, tegra->fpci_base + offset);
219}
220
221static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
222{
223 return readl(tegra->ipfs_base + offset);
224}
225
226static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
227 unsigned int offset)
228{
229 writel(value, tegra->ipfs_base + offset);
230}
231
232static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
233{
234 u32 page = CSB_PAGE_SELECT(offset);
235 u32 ofs = CSB_PAGE_OFFSET(offset);
236
237 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
238
239 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
240}
241
242static void csb_writel(struct tegra_xusb *tegra, u32 value,
243 unsigned int offset)
244{
245 u32 page = CSB_PAGE_SELECT(offset);
246 u32 ofs = CSB_PAGE_OFFSET(offset);
247
248 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
249 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
250}
251
252static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
253 unsigned long rate)
254{
255 unsigned long new_parent_rate, old_parent_rate;
256 struct clk *clk = tegra->ss_src_clk;
257 unsigned int div;
258 int err;
259
260 if (clk_get_rate(clk) == rate)
261 return 0;
262
263 switch (rate) {
264 case TEGRA_XHCI_SS_HIGH_SPEED:
265
266
267
268
269 old_parent_rate = clk_get_rate(clk_get_parent(clk));
270 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
271 div = new_parent_rate / rate;
272
273 err = clk_set_rate(clk, old_parent_rate / div);
274 if (err)
275 return err;
276
277 err = clk_set_parent(clk, tegra->pll_u_480m);
278 if (err)
279 return err;
280
281
282
283
284
285 err = clk_set_rate(clk, rate);
286 if (err)
287 return err;
288
289 break;
290
291 case TEGRA_XHCI_SS_LOW_SPEED:
292
293 err = clk_set_parent(clk, tegra->clk_m);
294 if (err)
295 return err;
296
297 err = clk_set_rate(clk, rate);
298 if (err)
299 return err;
300
301 break;
302
303 default:
304 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
305 return -EINVAL;
306 }
307
308 if (clk_get_rate(clk) != rate) {
309 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
310 return -EINVAL;
311 }
312
313 return 0;
314}
315
316static unsigned long extract_field(u32 value, unsigned int start,
317 unsigned int count)
318{
319 return (value >> start) & ((1 << count) - 1);
320}
321
322
323enum tegra_xusb_mbox_cmd {
324 MBOX_CMD_MSG_ENABLED = 1,
325 MBOX_CMD_INC_FALC_CLOCK,
326 MBOX_CMD_DEC_FALC_CLOCK,
327 MBOX_CMD_INC_SSPI_CLOCK,
328 MBOX_CMD_DEC_SSPI_CLOCK,
329 MBOX_CMD_SET_BW,
330 MBOX_CMD_SET_SS_PWR_GATING,
331 MBOX_CMD_SET_SS_PWR_UNGATING,
332 MBOX_CMD_SAVE_DFE_CTLE_CTX,
333 MBOX_CMD_AIRPLANE_MODE_ENABLED,
334 MBOX_CMD_AIRPLANE_MODE_DISABLED,
335 MBOX_CMD_START_HSIC_IDLE,
336 MBOX_CMD_STOP_HSIC_IDLE,
337 MBOX_CMD_DBC_WAKE_STACK,
338 MBOX_CMD_HSIC_PRETEND_CONNECT,
339 MBOX_CMD_RESET_SSPI,
340 MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
341 MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
342
343 MBOX_CMD_MAX,
344
345
346 MBOX_CMD_ACK = 128,
347 MBOX_CMD_NAK
348};
349
350static const char * const mbox_cmd_name[] = {
351 [ 1] = "MSG_ENABLE",
352 [ 2] = "INC_FALCON_CLOCK",
353 [ 3] = "DEC_FALCON_CLOCK",
354 [ 4] = "INC_SSPI_CLOCK",
355 [ 5] = "DEC_SSPI_CLOCK",
356 [ 6] = "SET_BW",
357 [ 7] = "SET_SS_PWR_GATING",
358 [ 8] = "SET_SS_PWR_UNGATING",
359 [ 9] = "SAVE_DFE_CTLE_CTX",
360 [ 10] = "AIRPLANE_MODE_ENABLED",
361 [ 11] = "AIRPLANE_MODE_DISABLED",
362 [ 12] = "START_HSIC_IDLE",
363 [ 13] = "STOP_HSIC_IDLE",
364 [ 14] = "DBC_WAKE_STACK",
365 [ 15] = "HSIC_PRETEND_CONNECT",
366 [ 16] = "RESET_SSPI",
367 [ 17] = "DISABLE_SS_LFPS_DETECTION",
368 [ 18] = "ENABLE_SS_LFPS_DETECTION",
369 [128] = "ACK",
370 [129] = "NAK",
371};
372
373struct tegra_xusb_mbox_msg {
374 u32 cmd;
375 u32 data;
376};
377
378static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
379{
380 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
381 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
382}
383static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
384 u32 value)
385{
386 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
387 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
388}
389
390static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
391{
392 switch (cmd) {
393 case MBOX_CMD_SET_BW:
394 case MBOX_CMD_ACK:
395 case MBOX_CMD_NAK:
396 return false;
397
398 default:
399 return true;
400 }
401}
402
403static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
404 const struct tegra_xusb_mbox_msg *msg)
405{
406 bool wait_for_idle = false;
407 u32 value;
408
409
410
411
412
413 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
414 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
415 if (value != MBOX_OWNER_NONE) {
416 dev_err(tegra->dev, "mailbox is busy\n");
417 return -EBUSY;
418 }
419
420 fpci_writel(tegra, MBOX_OWNER_SW, XUSB_CFG_ARU_MBOX_OWNER);
421
422 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
423 if (value != MBOX_OWNER_SW) {
424 dev_err(tegra->dev, "failed to acquire mailbox\n");
425 return -EBUSY;
426 }
427
428 wait_for_idle = true;
429 }
430
431 value = tegra_xusb_mbox_pack(msg);
432 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_DATA_IN);
433
434 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
435 value |= MBOX_INT_EN | MBOX_DEST_FALC;
436 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
437
438 if (wait_for_idle) {
439 unsigned long timeout = jiffies + msecs_to_jiffies(250);
440
441 while (time_before(jiffies, timeout)) {
442 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
443 if (value == MBOX_OWNER_NONE)
444 break;
445
446 usleep_range(10, 20);
447 }
448
449 if (time_after(jiffies, timeout))
450 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
451
452 if (value != MBOX_OWNER_NONE)
453 return -ETIMEDOUT;
454 }
455
456 return 0;
457}
458
459static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
460{
461 struct tegra_xusb *tegra = data;
462 u32 value;
463
464
465 value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
466 fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
467
468 if (value & MBOX_SMI_INTR_FW_HANG)
469 dev_err(tegra->dev, "controller firmware hang\n");
470
471 return IRQ_WAKE_THREAD;
472}
473
474static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
475 const struct tegra_xusb_mbox_msg *msg)
476{
477 struct tegra_xusb_padctl *padctl = tegra->padctl;
478 const struct tegra_xusb_soc *soc = tegra->soc;
479 struct device *dev = tegra->dev;
480 struct tegra_xusb_mbox_msg rsp;
481 unsigned long mask;
482 unsigned int port;
483 bool idle, enable;
484 int err = 0;
485
486 memset(&rsp, 0, sizeof(rsp));
487
488 switch (msg->cmd) {
489 case MBOX_CMD_INC_FALC_CLOCK:
490 case MBOX_CMD_DEC_FALC_CLOCK:
491 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
492 if (rsp.data != msg->data)
493 rsp.cmd = MBOX_CMD_NAK;
494 else
495 rsp.cmd = MBOX_CMD_ACK;
496
497 break;
498
499 case MBOX_CMD_INC_SSPI_CLOCK:
500 case MBOX_CMD_DEC_SSPI_CLOCK:
501 if (tegra->soc->scale_ss_clock) {
502 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
503 if (err < 0)
504 rsp.cmd = MBOX_CMD_NAK;
505 else
506 rsp.cmd = MBOX_CMD_ACK;
507
508 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
509 } else {
510 rsp.cmd = MBOX_CMD_ACK;
511 rsp.data = msg->data;
512 }
513
514 break;
515
516 case MBOX_CMD_SET_BW:
517
518
519
520
521
522 break;
523
524 case MBOX_CMD_SAVE_DFE_CTLE_CTX:
525 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
526 if (err < 0) {
527 dev_err(dev, "failed to save context for USB3#%u: %d\n",
528 msg->data, err);
529 rsp.cmd = MBOX_CMD_NAK;
530 } else {
531 rsp.cmd = MBOX_CMD_ACK;
532 }
533
534 rsp.data = msg->data;
535 break;
536
537 case MBOX_CMD_START_HSIC_IDLE:
538 case MBOX_CMD_STOP_HSIC_IDLE:
539 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
540 idle = false;
541 else
542 idle = true;
543
544 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
545 soc->ports.hsic.count);
546
547 for_each_set_bit(port, &mask, 32) {
548 err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
549 idle);
550 if (err < 0)
551 break;
552 }
553
554 if (err < 0) {
555 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
556 idle ? "idle" : "busy", err);
557 rsp.cmd = MBOX_CMD_NAK;
558 } else {
559 rsp.cmd = MBOX_CMD_ACK;
560 }
561
562 rsp.data = msg->data;
563 break;
564
565 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
566 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
567 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
568 enable = false;
569 else
570 enable = true;
571
572 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
573 soc->ports.usb3.count);
574
575 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
576 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
577 port,
578 enable);
579 if (err < 0)
580 break;
581 }
582
583 if (err < 0) {
584 dev_err(dev,
585 "failed to %s LFPS detection on USB3#%u: %d\n",
586 enable ? "enable" : "disable", port, err);
587 rsp.cmd = MBOX_CMD_NAK;
588 } else {
589 rsp.cmd = MBOX_CMD_ACK;
590 }
591
592 rsp.data = msg->data;
593 break;
594
595 default:
596 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
597 break;
598 }
599
600 if (rsp.cmd) {
601 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
602
603 err = tegra_xusb_mbox_send(tegra, &rsp);
604 if (err < 0)
605 dev_err(dev, "failed to send %s: %d\n", cmd, err);
606 }
607}
608
609static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
610{
611 struct tegra_xusb *tegra = data;
612 struct tegra_xusb_mbox_msg msg;
613 u32 value;
614
615 mutex_lock(&tegra->lock);
616
617 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_DATA_OUT);
618 tegra_xusb_mbox_unpack(&msg, value);
619
620 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
621 value &= ~MBOX_DEST_SMI;
622 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
623
624
625 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
626 fpci_writel(tegra, MBOX_OWNER_NONE, XUSB_CFG_ARU_MBOX_OWNER);
627
628 tegra_xusb_mbox_handle(tegra, &msg);
629
630 mutex_unlock(&tegra->lock);
631 return IRQ_HANDLED;
632}
633
634static void tegra_xusb_ipfs_config(struct tegra_xusb *tegra,
635 struct resource *regs)
636{
637 u32 value;
638
639 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
640 value |= IPFS_EN_FPCI;
641 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
642
643 usleep_range(10, 20);
644
645
646 value = fpci_readl(tegra, XUSB_CFG_4);
647 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
648 value |= regs->start & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
649 fpci_writel(tegra, value, XUSB_CFG_4);
650
651 usleep_range(100, 200);
652
653
654 value = fpci_readl(tegra, XUSB_CFG_1);
655 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
656 fpci_writel(tegra, value, XUSB_CFG_1);
657
658
659 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
660 value |= IPFS_IP_INT_MASK;
661 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
662
663
664 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
665}
666
667static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
668{
669 int err;
670
671 err = clk_prepare_enable(tegra->pll_e);
672 if (err < 0)
673 return err;
674
675 err = clk_prepare_enable(tegra->host_clk);
676 if (err < 0)
677 goto disable_plle;
678
679 err = clk_prepare_enable(tegra->ss_clk);
680 if (err < 0)
681 goto disable_host;
682
683 err = clk_prepare_enable(tegra->falcon_clk);
684 if (err < 0)
685 goto disable_ss;
686
687 err = clk_prepare_enable(tegra->fs_src_clk);
688 if (err < 0)
689 goto disable_falc;
690
691 err = clk_prepare_enable(tegra->hs_src_clk);
692 if (err < 0)
693 goto disable_fs_src;
694
695 if (tegra->soc->scale_ss_clock) {
696 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
697 if (err < 0)
698 goto disable_hs_src;
699 }
700
701 return 0;
702
703disable_hs_src:
704 clk_disable_unprepare(tegra->hs_src_clk);
705disable_fs_src:
706 clk_disable_unprepare(tegra->fs_src_clk);
707disable_falc:
708 clk_disable_unprepare(tegra->falcon_clk);
709disable_ss:
710 clk_disable_unprepare(tegra->ss_clk);
711disable_host:
712 clk_disable_unprepare(tegra->host_clk);
713disable_plle:
714 clk_disable_unprepare(tegra->pll_e);
715 return err;
716}
717
718static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
719{
720 clk_disable_unprepare(tegra->pll_e);
721 clk_disable_unprepare(tegra->host_clk);
722 clk_disable_unprepare(tegra->ss_clk);
723 clk_disable_unprepare(tegra->falcon_clk);
724 clk_disable_unprepare(tegra->fs_src_clk);
725 clk_disable_unprepare(tegra->hs_src_clk);
726}
727
728static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
729{
730 unsigned int i;
731 int err;
732
733 for (i = 0; i < tegra->num_phys; i++) {
734 err = phy_init(tegra->phys[i]);
735 if (err)
736 goto disable_phy;
737
738 err = phy_power_on(tegra->phys[i]);
739 if (err) {
740 phy_exit(tegra->phys[i]);
741 goto disable_phy;
742 }
743 }
744
745 return 0;
746
747disable_phy:
748 while (i--) {
749 phy_power_off(tegra->phys[i]);
750 phy_exit(tegra->phys[i]);
751 }
752
753 return err;
754}
755
756static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
757{
758 unsigned int i;
759
760 for (i = 0; i < tegra->num_phys; i++) {
761 phy_power_off(tegra->phys[i]);
762 phy_exit(tegra->phys[i]);
763 }
764}
765
766static int tegra_xusb_runtime_suspend(struct device *dev)
767{
768 struct tegra_xusb *tegra = dev_get_drvdata(dev);
769
770 tegra_xusb_phy_disable(tegra);
771 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
772 tegra_xusb_clk_disable(tegra);
773
774 return 0;
775}
776
777static int tegra_xusb_runtime_resume(struct device *dev)
778{
779 struct tegra_xusb *tegra = dev_get_drvdata(dev);
780 int err;
781
782 err = tegra_xusb_clk_enable(tegra);
783 if (err) {
784 dev_err(dev, "failed to enable clocks: %d\n", err);
785 return err;
786 }
787
788 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
789 if (err) {
790 dev_err(dev, "failed to enable regulators: %d\n", err);
791 goto disable_clk;
792 }
793
794 err = tegra_xusb_phy_enable(tegra);
795 if (err < 0) {
796 dev_err(dev, "failed to enable PHYs: %d\n", err);
797 goto disable_regulator;
798 }
799
800 return 0;
801
802disable_regulator:
803 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
804disable_clk:
805 tegra_xusb_clk_disable(tegra);
806 return err;
807}
808
809static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
810{
811 unsigned int code_tag_blocks, code_size_blocks, code_blocks;
812 struct tegra_xusb_fw_header *header;
813 struct device *dev = tegra->dev;
814 const struct firmware *fw;
815 unsigned long timeout;
816 time64_t timestamp;
817 struct tm time;
818 u64 address;
819 u32 value;
820 int err;
821
822 err = request_firmware(&fw, tegra->soc->firmware, tegra->dev);
823 if (err < 0) {
824 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
825 return err;
826 }
827
828
829 header = (struct tegra_xusb_fw_header *)fw->data;
830 tegra->fw.size = le32_to_cpu(header->fwimg_len);
831
832 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
833 &tegra->fw.phys, GFP_KERNEL);
834 if (!tegra->fw.virt) {
835 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
836 release_firmware(fw);
837 return -ENOMEM;
838 }
839
840 header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
841 memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
842 release_firmware(fw);
843
844 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
845 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
846 csb_readl(tegra, XUSB_FALC_CPUCTL));
847 return 0;
848 }
849
850
851 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
852
853
854
855
856
857 address = tegra->fw.phys + sizeof(*header);
858 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
859 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
860
861
862 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
863
864
865 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
866
867
868
869
870
871 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
872 IMEM_BLOCK_SIZE);
873 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
874 IMEM_BLOCK_SIZE);
875 code_blocks = code_tag_blocks + code_size_blocks;
876
877 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
878 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
879 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
880 L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
881 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
882
883
884 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
885 XUSB_CSB_MP_L2IMEMOP_TRIG);
886
887
888 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
889
890 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
891 IMFILLRNG1_TAG_LO_SHIFT) |
892 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
893 IMFILLRNG1_TAG_HI_SHIFT);
894 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
895
896 csb_writel(tegra, 0, XUSB_FALC_DMACTL);
897
898 msleep(50);
899
900 csb_writel(tegra, le32_to_cpu(header->boot_codetag),
901 XUSB_FALC_BOOTVEC);
902
903
904 timeout = jiffies + msecs_to_jiffies(5);
905
906 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
907
908 while (time_before(jiffies, timeout)) {
909 if (csb_readl(tegra, XUSB_FALC_CPUCTL) == CPUCTL_STATE_STOPPED)
910 break;
911
912 usleep_range(100, 200);
913 }
914
915 if (csb_readl(tegra, XUSB_FALC_CPUCTL) != CPUCTL_STATE_STOPPED) {
916 dev_err(dev, "Falcon failed to start, state: %#x\n",
917 csb_readl(tegra, XUSB_FALC_CPUCTL));
918 return -EIO;
919 }
920
921 timestamp = le32_to_cpu(header->fwimg_created_time);
922 time64_to_tm(timestamp, 0, &time);
923
924 dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n",
925 time.tm_year + 1900, time.tm_mon + 1, time.tm_mday,
926 time.tm_hour, time.tm_min, time.tm_sec);
927
928 return 0;
929}
930
931static int tegra_xusb_probe(struct platform_device *pdev)
932{
933 struct tegra_xusb_mbox_msg msg;
934 struct resource *res, *regs;
935 struct tegra_xusb *tegra;
936 struct xhci_hcd *xhci;
937 unsigned int i, j, k;
938 struct phy *phy;
939 int err;
940
941 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
942
943 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
944 if (!tegra)
945 return -ENOMEM;
946
947 tegra->soc = of_device_get_match_data(&pdev->dev);
948 mutex_init(&tegra->lock);
949 tegra->dev = &pdev->dev;
950
951 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
952 tegra->regs = devm_ioremap_resource(&pdev->dev, regs);
953 if (IS_ERR(tegra->regs))
954 return PTR_ERR(tegra->regs);
955
956 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
957 tegra->fpci_base = devm_ioremap_resource(&pdev->dev, res);
958 if (IS_ERR(tegra->fpci_base))
959 return PTR_ERR(tegra->fpci_base);
960
961 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
962 tegra->ipfs_base = devm_ioremap_resource(&pdev->dev, res);
963 if (IS_ERR(tegra->ipfs_base))
964 return PTR_ERR(tegra->ipfs_base);
965
966 tegra->xhci_irq = platform_get_irq(pdev, 0);
967 if (tegra->xhci_irq < 0)
968 return tegra->xhci_irq;
969
970 tegra->mbox_irq = platform_get_irq(pdev, 1);
971 if (tegra->mbox_irq < 0)
972 return tegra->mbox_irq;
973
974 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
975 if (IS_ERR(tegra->padctl))
976 return PTR_ERR(tegra->padctl);
977
978 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
979 if (IS_ERR(tegra->host_clk)) {
980 err = PTR_ERR(tegra->host_clk);
981 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
982 goto put_padctl;
983 }
984
985 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
986 if (IS_ERR(tegra->falcon_clk)) {
987 err = PTR_ERR(tegra->falcon_clk);
988 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
989 goto put_padctl;
990 }
991
992 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
993 if (IS_ERR(tegra->ss_clk)) {
994 err = PTR_ERR(tegra->ss_clk);
995 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
996 goto put_padctl;
997 }
998
999 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
1000 if (IS_ERR(tegra->ss_src_clk)) {
1001 err = PTR_ERR(tegra->ss_src_clk);
1002 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
1003 goto put_padctl;
1004 }
1005
1006 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
1007 if (IS_ERR(tegra->hs_src_clk)) {
1008 err = PTR_ERR(tegra->hs_src_clk);
1009 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
1010 goto put_padctl;
1011 }
1012
1013 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
1014 if (IS_ERR(tegra->fs_src_clk)) {
1015 err = PTR_ERR(tegra->fs_src_clk);
1016 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
1017 goto put_padctl;
1018 }
1019
1020 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
1021 if (IS_ERR(tegra->pll_u_480m)) {
1022 err = PTR_ERR(tegra->pll_u_480m);
1023 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
1024 goto put_padctl;
1025 }
1026
1027 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1028 if (IS_ERR(tegra->clk_m)) {
1029 err = PTR_ERR(tegra->clk_m);
1030 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1031 goto put_padctl;
1032 }
1033
1034 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1035 if (IS_ERR(tegra->pll_e)) {
1036 err = PTR_ERR(tegra->pll_e);
1037 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1038 goto put_padctl;
1039 }
1040
1041 if (!pdev->dev.pm_domain) {
1042 tegra->host_rst = devm_reset_control_get(&pdev->dev,
1043 "xusb_host");
1044 if (IS_ERR(tegra->host_rst)) {
1045 err = PTR_ERR(tegra->host_rst);
1046 dev_err(&pdev->dev,
1047 "failed to get xusb_host reset: %d\n", err);
1048 goto put_padctl;
1049 }
1050
1051 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
1052 if (IS_ERR(tegra->ss_rst)) {
1053 err = PTR_ERR(tegra->ss_rst);
1054 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n",
1055 err);
1056 goto put_padctl;
1057 }
1058
1059 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
1060 tegra->ss_clk,
1061 tegra->ss_rst);
1062 if (err) {
1063 dev_err(&pdev->dev,
1064 "failed to enable XUSBA domain: %d\n", err);
1065 goto put_padctl;
1066 }
1067
1068 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1069 tegra->host_clk,
1070 tegra->host_rst);
1071 if (err) {
1072 dev_err(&pdev->dev,
1073 "failed to enable XUSBC domain: %d\n", err);
1074 goto disable_xusba;
1075 }
1076 }
1077
1078 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1079 sizeof(*tegra->supplies), GFP_KERNEL);
1080 if (!tegra->supplies) {
1081 err = -ENOMEM;
1082 goto disable_xusbc;
1083 }
1084
1085 for (i = 0; i < tegra->soc->num_supplies; i++)
1086 tegra->supplies[i].supply = tegra->soc->supply_names[i];
1087
1088 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1089 tegra->supplies);
1090 if (err) {
1091 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1092 goto disable_xusbc;
1093 }
1094
1095 for (i = 0; i < tegra->soc->num_types; i++)
1096 tegra->num_phys += tegra->soc->phy_types[i].num;
1097
1098 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1099 sizeof(*tegra->phys), GFP_KERNEL);
1100 if (!tegra->phys) {
1101 err = -ENOMEM;
1102 goto disable_xusbc;
1103 }
1104
1105 for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1106 char prop[8];
1107
1108 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1109 snprintf(prop, sizeof(prop), "%s-%d",
1110 tegra->soc->phy_types[i].name, j);
1111
1112 phy = devm_phy_optional_get(&pdev->dev, prop);
1113 if (IS_ERR(phy)) {
1114 dev_err(&pdev->dev,
1115 "failed to get PHY %s: %ld\n", prop,
1116 PTR_ERR(phy));
1117 err = PTR_ERR(phy);
1118 goto disable_xusbc;
1119 }
1120
1121 tegra->phys[k++] = phy;
1122 }
1123 }
1124
1125 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1126 dev_name(&pdev->dev));
1127 if (!tegra->hcd) {
1128 err = -ENOMEM;
1129 goto disable_xusbc;
1130 }
1131
1132
1133
1134
1135
1136 platform_set_drvdata(pdev, tegra);
1137
1138 pm_runtime_enable(&pdev->dev);
1139 if (pm_runtime_enabled(&pdev->dev))
1140 err = pm_runtime_get_sync(&pdev->dev);
1141 else
1142 err = tegra_xusb_runtime_resume(&pdev->dev);
1143
1144 if (err < 0) {
1145 dev_err(&pdev->dev, "failed to enable device: %d\n", err);
1146 goto disable_rpm;
1147 }
1148
1149 tegra_xusb_ipfs_config(tegra, regs);
1150
1151 err = tegra_xusb_load_firmware(tegra);
1152 if (err < 0) {
1153 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1154 goto put_rpm;
1155 }
1156
1157 tegra->hcd->regs = tegra->regs;
1158 tegra->hcd->rsrc_start = regs->start;
1159 tegra->hcd->rsrc_len = resource_size(regs);
1160
1161 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1162 if (err < 0) {
1163 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1164 goto put_rpm;
1165 }
1166
1167 device_wakeup_enable(tegra->hcd->self.controller);
1168
1169 xhci = hcd_to_xhci(tegra->hcd);
1170
1171 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1172 &pdev->dev,
1173 dev_name(&pdev->dev),
1174 tegra->hcd);
1175 if (!xhci->shared_hcd) {
1176 dev_err(&pdev->dev, "failed to create shared HCD\n");
1177 err = -ENOMEM;
1178 goto remove_usb2;
1179 }
1180
1181 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1182 if (err < 0) {
1183 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1184 goto put_usb3;
1185 }
1186
1187 mutex_lock(&tegra->lock);
1188
1189
1190 msg.cmd = MBOX_CMD_MSG_ENABLED;
1191 msg.data = 0;
1192
1193 err = tegra_xusb_mbox_send(tegra, &msg);
1194 if (err < 0) {
1195 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1196 mutex_unlock(&tegra->lock);
1197 goto remove_usb3;
1198 }
1199
1200 mutex_unlock(&tegra->lock);
1201
1202 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1203 tegra_xusb_mbox_irq,
1204 tegra_xusb_mbox_thread, 0,
1205 dev_name(&pdev->dev), tegra);
1206 if (err < 0) {
1207 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1208 goto remove_usb3;
1209 }
1210
1211 return 0;
1212
1213remove_usb3:
1214 usb_remove_hcd(xhci->shared_hcd);
1215put_usb3:
1216 usb_put_hcd(xhci->shared_hcd);
1217remove_usb2:
1218 usb_remove_hcd(tegra->hcd);
1219put_rpm:
1220 if (!pm_runtime_status_suspended(&pdev->dev))
1221 tegra_xusb_runtime_suspend(&pdev->dev);
1222disable_rpm:
1223 pm_runtime_disable(&pdev->dev);
1224 usb_put_hcd(tegra->hcd);
1225disable_xusbc:
1226 if (!pdev->dev.pm_domain)
1227 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1228disable_xusba:
1229 if (!pdev->dev.pm_domain)
1230 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1231put_padctl:
1232 tegra_xusb_padctl_put(tegra->padctl);
1233 return err;
1234}
1235
1236static int tegra_xusb_remove(struct platform_device *pdev)
1237{
1238 struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1239 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1240
1241 usb_remove_hcd(xhci->shared_hcd);
1242 usb_put_hcd(xhci->shared_hcd);
1243 usb_remove_hcd(tegra->hcd);
1244 usb_put_hcd(tegra->hcd);
1245
1246 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1247 tegra->fw.phys);
1248
1249 pm_runtime_put_sync(&pdev->dev);
1250 pm_runtime_disable(&pdev->dev);
1251
1252 tegra_xusb_padctl_put(tegra->padctl);
1253
1254 return 0;
1255}
1256
1257#ifdef CONFIG_PM_SLEEP
1258static int tegra_xusb_suspend(struct device *dev)
1259{
1260 struct tegra_xusb *tegra = dev_get_drvdata(dev);
1261 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1262 bool wakeup = device_may_wakeup(dev);
1263
1264
1265 return xhci_suspend(xhci, wakeup);
1266}
1267
1268static int tegra_xusb_resume(struct device *dev)
1269{
1270 struct tegra_xusb *tegra = dev_get_drvdata(dev);
1271 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1272
1273 return xhci_resume(xhci, 0);
1274}
1275#endif
1276
1277static const struct dev_pm_ops tegra_xusb_pm_ops = {
1278 SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend,
1279 tegra_xusb_runtime_resume, NULL)
1280 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
1281};
1282
1283static const char * const tegra124_supply_names[] = {
1284 "avddio-pex",
1285 "dvddio-pex",
1286 "avdd-usb",
1287 "avdd-pll-utmip",
1288 "avdd-pll-erefe",
1289 "avdd-usb-ss-pll",
1290 "hvdd-usb-ss",
1291 "hvdd-usb-ss-pll-e",
1292};
1293
1294static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
1295 { .name = "usb3", .num = 2, },
1296 { .name = "usb2", .num = 3, },
1297 { .name = "hsic", .num = 2, },
1298};
1299
1300static const struct tegra_xusb_soc tegra124_soc = {
1301 .firmware = "nvidia/tegra124/xusb.bin",
1302 .supply_names = tegra124_supply_names,
1303 .num_supplies = ARRAY_SIZE(tegra124_supply_names),
1304 .phy_types = tegra124_phy_types,
1305 .num_types = ARRAY_SIZE(tegra124_phy_types),
1306 .ports = {
1307 .usb2 = { .offset = 4, .count = 4, },
1308 .hsic = { .offset = 6, .count = 2, },
1309 .usb3 = { .offset = 0, .count = 2, },
1310 },
1311 .scale_ss_clock = true,
1312};
1313MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
1314
1315static const char * const tegra210_supply_names[] = {
1316 "dvddio-pex",
1317 "hvddio-pex",
1318 "avdd-usb",
1319 "avdd-pll-utmip",
1320 "avdd-pll-uerefe",
1321 "dvdd-pex-pll",
1322 "hvdd-pex-pll-e",
1323};
1324
1325static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
1326 { .name = "usb3", .num = 4, },
1327 { .name = "usb2", .num = 4, },
1328 { .name = "hsic", .num = 1, },
1329};
1330
1331static const struct tegra_xusb_soc tegra210_soc = {
1332 .firmware = "nvidia/tegra210/xusb.bin",
1333 .supply_names = tegra210_supply_names,
1334 .num_supplies = ARRAY_SIZE(tegra210_supply_names),
1335 .phy_types = tegra210_phy_types,
1336 .num_types = ARRAY_SIZE(tegra210_phy_types),
1337 .ports = {
1338 .usb2 = { .offset = 4, .count = 4, },
1339 .hsic = { .offset = 8, .count = 1, },
1340 .usb3 = { .offset = 0, .count = 4, },
1341 },
1342 .scale_ss_clock = false,
1343};
1344MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
1345
1346static const struct of_device_id tegra_xusb_of_match[] = {
1347 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
1348 { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
1349 { },
1350};
1351MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
1352
1353static struct platform_driver tegra_xusb_driver = {
1354 .probe = tegra_xusb_probe,
1355 .remove = tegra_xusb_remove,
1356 .driver = {
1357 .name = "tegra-xusb",
1358 .pm = &tegra_xusb_pm_ops,
1359 .of_match_table = tegra_xusb_of_match,
1360 },
1361};
1362
1363static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
1364{
1365 xhci->quirks |= XHCI_PLAT;
1366}
1367
1368static int tegra_xhci_setup(struct usb_hcd *hcd)
1369{
1370 return xhci_gen_setup(hcd, tegra_xhci_quirks);
1371}
1372
1373static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
1374 .reset = tegra_xhci_setup,
1375};
1376
1377static int __init tegra_xusb_init(void)
1378{
1379 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
1380
1381 return platform_driver_register(&tegra_xusb_driver);
1382}
1383module_init(tegra_xusb_init);
1384
1385static void __exit tegra_xusb_exit(void)
1386{
1387 platform_driver_unregister(&tegra_xusb_driver);
1388}
1389module_exit(tegra_xusb_exit);
1390
1391MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
1392MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
1393MODULE_LICENSE("GPL v2");
1394
