LXR linux/include/linux/mfd/tmio.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef MFD_TMIO_H
   3#define MFD_TMIO_H
   4
   5#include <linux/device.h>
   6#include <linux/fb.h>
   7#include <linux/io.h>
   8#include <linux/jiffies.h>
   9#include <linux/mmc/card.h>
  10#include <linux/platform_device.h>
  11#include <linux/pm_runtime.h>
  12
  13#define tmio_ioread8(addr) readb(addr)
  14#define tmio_ioread16(addr) readw(addr)
  15#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
  16#define tmio_ioread32(addr) \
  17        (((u32)readw((addr))) | (((u32)readw((addr) + 2)) << 16))
  18
  19#define tmio_iowrite8(val, addr) writeb((val), (addr))
  20#define tmio_iowrite16(val, addr) writew((val), (addr))
  21#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
  22#define tmio_iowrite32(val, addr) \
  23        do { \
  24                writew((val),       (addr)); \
  25                writew((val) >> 16, (addr) + 2); \
  26        } while (0)
  27
  28#define sd_config_write8(base, shift, reg, val) \
  29        tmio_iowrite8((val), (base) + ((reg) << (shift)))
  30#define sd_config_write16(base, shift, reg, val) \
  31        tmio_iowrite16((val), (base) + ((reg) << (shift)))
  32#define sd_config_write32(base, shift, reg, val) \
  33        do { \
  34                tmio_iowrite16((val), (base) + ((reg) << (shift)));   \
  35                tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
  36        } while (0)
  37
  38/* tmio MMC platform flags */
  39/*
  40 * Some controllers can support a 2-byte block size when the bus width
  41 * is configured in 4-bit mode.
  42 */
  43#define TMIO_MMC_BLKSZ_2BYTES           BIT(1)
  44/*
  45 * Some controllers can support SDIO IRQ signalling.
  46 */
  47#define TMIO_MMC_SDIO_IRQ               BIT(2)
  48
  49/* Some features are only available or tested on R-Car Gen2 or later */
  50#define TMIO_MMC_MIN_RCAR2              BIT(3)
  51
  52/*
  53 * Some controllers require waiting for the SD bus to become
  54 * idle before writing to some registers.
  55 */
  56#define TMIO_MMC_HAS_IDLE_WAIT          BIT(4)
  57/*
  58 * A GPIO is used for card hotplug detection. We need an extra flag for this,
  59 * because 0 is a valid GPIO number too, and requiring users to specify
  60 * cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
  61 */
  62#define TMIO_MMC_USE_GPIO_CD            BIT(5)
  63
  64/*
  65 * Some controllers doesn't have over 0x100 register.
  66 * it is used to checking accessibility of
  67 * CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL
  68 */
  69#define TMIO_MMC_HAVE_HIGH_REG          BIT(6)
  70
  71/*
  72 * Some controllers have CMD12 automatically
  73 * issue/non-issue register
  74 */
  75#define TMIO_MMC_HAVE_CMD12_CTRL        BIT(7)
  76
  77/* Controller has some SDIO status bits which must be 1 */
  78#define TMIO_MMC_SDIO_STATUS_SETBITS    BIT(8)
  79
  80/*
  81 * Some controllers have a 32-bit wide data port register
  82 */
  83#define TMIO_MMC_32BIT_DATA_PORT        BIT(9)
  84
  85/*
  86 * Some controllers allows to set SDx actual clock
  87 */
  88#define TMIO_MMC_CLK_ACTUAL             BIT(10)
  89
  90/* Some controllers have a CBSY bit */
  91#define TMIO_MMC_HAVE_CBSY              BIT(11)
  92
  93int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
  94int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
  95void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
  96void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
  97
  98struct dma_chan;
  99
 100/*
 101 * data for the MMC controller
 102 */
 103struct tmio_mmc_data {
 104        void                            *chan_priv_tx;
 105        void                            *chan_priv_rx;
 106        unsigned int                    hclk;
 107        unsigned long                   capabilities;
 108        unsigned long                   capabilities2;
 109        unsigned long                   flags;
 110        u32                             ocr_mask;       /* available voltages */
 111        unsigned int                    cd_gpio;
 112        int                             alignment_shift;
 113        dma_addr_t                      dma_rx_offset;
 114        unsigned int                    max_blk_count;
 115        unsigned short                  max_segs;
 116        void (*set_pwr)(struct platform_device *host, int state);
 117        void (*set_clk_div)(struct platform_device *host, int state);
 118};
 119
 120/*
 121 * data for the NAND controller
 122 */
 123struct tmio_nand_data {
 124        struct nand_bbt_descr   *badblock_pattern;
 125        struct mtd_partition    *partition;
 126        unsigned int            num_partitions;
 127        const char *const       *part_parsers;
 128};
 129
 130#define FBIO_TMIO_ACC_WRITE     0x7C639300
 131#define FBIO_TMIO_ACC_SYNC      0x7C639301
 132
 133struct tmio_fb_data {
 134        int                     (*lcd_set_power)(struct platform_device *fb_dev,
 135                                                 bool on);
 136        int                     (*lcd_mode)(struct platform_device *fb_dev,
 137                                            const struct fb_videomode *mode);
 138        int                     num_modes;
 139        struct fb_videomode     *modes;
 140
 141        /* in mm: size of screen */
 142        int                     height;
 143        int                     width;
 144};
 145
 146#endif
 147