1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 2004 Ralf Baechle 7 * Copyright (C) 2004 Maciej W. Rozycki 8 */ 9#ifndef __ASM_CPU_FEATURES_H 10#define __ASM_CPU_FEATURES_H 11 12#include <asm/cpu.h> 13#include <asm/cpu-info.h> 14#include <asm/isa-rev.h> 15#include <cpu-feature-overrides.h> 16 17/* 18 * SMP assumption: Options of CPU 0 are a superset of all processors. 19 * This is true for all known MIPS systems. 20 */ 21#ifndef cpu_has_tlb 22#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) 23#endif 24#ifndef cpu_has_ftlb 25#define cpu_has_ftlb (cpu_data[0].options & MIPS_CPU_FTLB) 26#endif 27#ifndef cpu_has_tlbinv 28#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV) 29#endif 30#ifndef cpu_has_segments 31#define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS) 32#endif 33#ifndef cpu_has_eva 34#define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA) 35#endif 36#ifndef cpu_has_htw 37#define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW) 38#endif 39#ifndef cpu_has_ldpte 40#define cpu_has_ldpte (cpu_data[0].options & MIPS_CPU_LDPTE) 41#endif 42#ifndef cpu_has_rixiex 43#define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX) 44#endif 45#ifndef cpu_has_maar 46#define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR) 47#endif 48#ifndef cpu_has_rw_llb 49#define cpu_has_rw_llb (cpu_data[0].options & MIPS_CPU_RW_LLB) 50#endif 51 52/* 53 * For the moment we don't consider R6000 and R8000 so we can assume that 54 * anything that doesn't support R4000-style exceptions and interrupts is 55 * R3000-like. Users should still treat these two macro definitions as 56 * opaque. 57 */ 58#ifndef cpu_has_3kex 59#define cpu_has_3kex (!cpu_has_4kex) 60#endif 61#ifndef cpu_has_4kex 62#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) 63#endif 64#ifndef cpu_has_3k_cache 65#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE) 66#endif 67#define cpu_has_6k_cache 0 68#define cpu_has_8k_cache 0 69#ifndef cpu_has_4k_cache 70#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE) 71#endif 72#ifndef cpu_has_tx39_cache 73#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) 74#endif 75#ifndef cpu_has_octeon_cache 76#define cpu_has_octeon_cache 0 77#endif 78/* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ 79#ifndef cpu_has_fpu 80#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 81#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 82#else 83#define raw_cpu_has_fpu cpu_has_fpu 84#endif 85#ifndef cpu_has_32fpr 86#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) 87#endif 88#ifndef cpu_has_counter 89#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) 90#endif 91#ifndef cpu_has_watch 92#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) 93#endif 94#ifndef cpu_has_divec 95#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) 96#endif 97#ifndef cpu_has_vce 98#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) 99#endif 100#ifndef cpu_has_cache_cdex_p 101#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P) 102#endif 103#ifndef cpu_has_cache_cdex_s 104#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S) 105#endif 106#ifndef cpu_has_prefetch 107#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH) 108#endif 109#ifndef cpu_has_mcheck 110#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) 111#endif 112#ifndef cpu_has_ejtag 113#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) 114#endif 115#ifndef cpu_has_llsc 116#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) 117#endif 118#ifndef cpu_has_bp_ghist 119#define cpu_has_bp_ghist (cpu_data[0].options & MIPS_CPU_BP_GHIST) 120#endif 121#ifndef kernel_uses_llsc 122#define kernel_uses_llsc cpu_has_llsc 123#endif 124#ifndef cpu_has_guestctl0ext 125#define cpu_has_guestctl0ext (cpu_data[0].options & MIPS_CPU_GUESTCTL0EXT) 126#endif 127#ifndef cpu_has_guestctl1 128#define cpu_has_guestctl1 (cpu_data[0].options & MIPS_CPU_GUESTCTL1) 129#endif 130#ifndef cpu_has_guestctl2 131#define cpu_has_guestctl2 (cpu_data[0].options & MIPS_CPU_GUESTCTL2) 132#endif 133#ifndef cpu_has_guestid 134#define cpu_has_guestid (cpu_data[0].options & MIPS_CPU_GUESTID) 135#endif 136#ifndef cpu_has_drg 137#define cpu_has_drg (cpu_data[0].options & MIPS_CPU_DRG) 138#endif 139#ifndef cpu_has_mips16 140#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) 141#endif 142#ifndef cpu_has_mips16e2 143#define cpu_has_mips16e2 (cpu_data[0].ases & MIPS_ASE_MIPS16E2) 144#endif 145#ifndef cpu_has_mdmx 146#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) 147#endif 148#ifndef cpu_has_mips3d 149#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) 150#endif 151#ifndef cpu_has_smartmips 152#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) 153#endif 154 155#ifndef cpu_has_rixi 156#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) 157#endif 158 159#ifndef cpu_has_mmips 160# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS 161# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) 162# else 163# define cpu_has_mmips 0 164# endif 165#endif 166 167#ifndef cpu_has_lpa 168#define cpu_has_lpa (cpu_data[0].options & MIPS_CPU_LPA) 169#endif 170#ifndef cpu_has_mvh 171#define cpu_has_mvh (cpu_data[0].options & MIPS_CPU_MVH) 172#endif 173#ifndef cpu_has_xpa 174#define cpu_has_xpa (cpu_has_lpa && cpu_has_mvh) 175#endif 176#ifndef cpu_has_vtag_icache 177#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 178#endif 179#ifndef cpu_has_dc_aliases 180#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) 181#endif 182#ifndef cpu_has_ic_fills_f_dc 183#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 184#endif 185#ifndef cpu_has_pindexed_dcache 186#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 187#endif 188#ifndef cpu_has_local_ebase 189#define cpu_has_local_ebase 1 190#endif 191 192/* 193 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 194 * such as the R10000 have I-Caches that snoop local stores; the embedded ones 195 * don't. For maintaining I-cache coherency this means we need to flush the 196 * D-cache all the way back to whever the I-cache does refills from, so the 197 * I-cache has a chance to see the new data at all. Then we have to flush the 198 * I-cache also. 199 * Note we may have been rescheduled and may no longer be running on the CPU 200 * that did the store so we can't optimize this into only doing the flush on 201 * the local CPU. 202 */ 203#ifndef cpu_icache_snoops_remote_store 204#ifdef CONFIG_SMP 205#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) 206#else 207#define cpu_icache_snoops_remote_store 1 208#endif 209#endif 210 211/* __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r */ 212#if !((defined(cpu_has_mips32r1) && cpu_has_mips32r1) || \ 213 (defined(cpu_has_mips32r2) && cpu_has_mips32r2) || \ 214 (defined(cpu_has_mips32r6) && cpu_has_mips32r6) || \ 215 (defined(cpu_has_mips64r1) && cpu_has_mips64r1) || \ 216 (defined(cpu_has_mips64r2) && cpu_has_mips64r2) || \ 217 (defined(cpu_has_mips64r6) && cpu_has_mips64r6)) 218#define CPU_NO_EFFICIENT_FFS 1 219#endif 220 221#ifndef cpu_has_mips_1 222# define cpu_has_mips_1 (!cpu_has_mips_r6) 223#endif 224#ifndef cpu_has_mips_2 225# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) 226#endif 227#ifndef cpu_has_mips_3 228# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III) 229#endif 230#ifndef cpu_has_mips_4 231# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV) 232#endif 233#ifndef cpu_has_mips_5 234# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) 235#endif 236#ifndef cpu_has_mips32r1 237# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) 238#endif 239#ifndef cpu_has_mips32r2 240# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 241#endif 242#ifndef cpu_has_mips32r6 243# define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6) 244#endif 245#ifndef cpu_has_mips64r1 246# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 247#endif 248#ifndef cpu_has_mips64r2 249# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 250#endif 251#ifndef cpu_has_mips64r6 252# define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6) 253#endif 254 255/* 256 * Shortcuts ... 257 */ 258#define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5) 259#define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5) 260#define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5) 261 262#define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r) 263#define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r) 264#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r) 265#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r) 266 267#define cpu_has_mips_3_4_5_64_r2_r6 \ 268 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6) 269#define cpu_has_mips_4_5_64_r2_r6 \ 270 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \ 271 cpu_has_mips_r2 | cpu_has_mips_r6) 272 273#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6) 274#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6) 275#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 276#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 277#define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6) 278#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 279 cpu_has_mips32r6 | cpu_has_mips64r1 | \ 280 cpu_has_mips64r2 | cpu_has_mips64r6) 281 282/* MIPSR2 and MIPSR6 have a lot of similarities */ 283#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6) 284 285/* 286 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor 287 * 288 * Returns non-zero value if the current processor implementation requires 289 * an IHB instruction to deal with an instruction hazard as per MIPS R2 290 * architecture specification, zero otherwise. 291 */ 292#ifndef cpu_has_mips_r2_exec_hazard 293#define cpu_has_mips_r2_exec_hazard \ 294({ \ 295 int __res; \ 296 \ 297 switch (current_cpu_type()) { \ 298 case CPU_M14KC: \ 299 case CPU_74K: \ 300 case CPU_1074K: \ 301 case CPU_PROAPTIV: \ 302 case CPU_P5600: \ 303 case CPU_M5150: \ 304 case CPU_QEMU_GENERIC: \ 305 case CPU_CAVIUM_OCTEON: \ 306 case CPU_CAVIUM_OCTEON_PLUS: \ 307 case CPU_CAVIUM_OCTEON2: \ 308 case CPU_CAVIUM_OCTEON3: \ 309 __res = 0; \ 310 break; \ 311 \ 312 default: \ 313 __res = 1; \ 314 } \ 315 \ 316 __res; \ 317}) 318#endif 319 320/* 321 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 322 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and 323 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 324 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 325 */ 326#ifndef cpu_has_clo_clz 327#define cpu_has_clo_clz cpu_has_mips_r 328#endif 329 330/* 331 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH. 332 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD. 333 * This indicates the availability of WSBH and in case of 64 bit CPUs also 334 * DSBH and DSHD. 335 */ 336#ifndef cpu_has_wsbh 337#define cpu_has_wsbh cpu_has_mips_r2 338#endif 339 340#ifndef cpu_has_dsp 341#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 342#endif 343 344#ifndef cpu_has_dsp2 345#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P) 346#endif 347 348#ifndef cpu_has_dsp3 349#define cpu_has_dsp3 (cpu_data[0].ases & MIPS_ASE_DSP3) 350#endif 351 352#ifndef cpu_has_mipsmt 353#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) 354#endif 355 356#ifndef cpu_has_vp 357#define cpu_has_vp (cpu_data[0].options & MIPS_CPU_VP) 358#endif 359 360#ifndef cpu_has_userlocal 361#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI) 362#endif 363 364#ifdef CONFIG_32BIT 365# ifndef cpu_has_nofpuex 366# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) 367# endif 368# ifndef cpu_has_64bits 369# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 370# endif 371# ifndef cpu_has_64bit_zero_reg 372# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 373# endif 374# ifndef cpu_has_64bit_gp_regs 375# define cpu_has_64bit_gp_regs 0 376# endif 377# ifndef cpu_has_64bit_addresses 378# define cpu_has_64bit_addresses 0 379# endif 380# ifndef cpu_vmbits 381# define cpu_vmbits 31 382# endif 383#endif 384 385#ifdef CONFIG_64BIT 386# ifndef cpu_has_nofpuex 387# define cpu_has_nofpuex 0 388# endif 389# ifndef cpu_has_64bits 390# define cpu_has_64bits 1 391# endif 392# ifndef cpu_has_64bit_zero_reg 393# define cpu_has_64bit_zero_reg 1 394# endif 395# ifndef cpu_has_64bit_gp_regs 396# define cpu_has_64bit_gp_regs 1 397# endif 398# ifndef cpu_has_64bit_addresses 399# define cpu_has_64bit_addresses 1 400# endif 401# ifndef cpu_vmbits 402# define cpu_vmbits cpu_data[0].vmbits 403# define __NEED_VMBITS_PROBE 404# endif 405#endif 406 407#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 408# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) 409#elif !defined(cpu_has_vint) 410# define cpu_has_vint 0 411#endif 412 413#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 414# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) 415#elif !defined(cpu_has_veic) 416# define cpu_has_veic 0 417#endif 418 419#ifndef cpu_has_inclusive_pcaches 420#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES) 421#endif 422 423#ifndef cpu_dcache_line_size 424#define cpu_dcache_line_size() cpu_data[0].dcache.linesz 425#endif 426#ifndef cpu_icache_line_size 427#define cpu_icache_line_size() cpu_data[0].icache.linesz 428#endif 429#ifndef cpu_scache_line_size 430#define cpu_scache_line_size() cpu_data[0].scache.linesz 431#endif 432#ifndef cpu_tcache_line_size 433#define cpu_tcache_line_size() cpu_data[0].tcache.linesz 434#endif 435 436#ifndef cpu_hwrena_impl_bits 437#define cpu_hwrena_impl_bits 0 438#endif 439 440#ifndef cpu_has_perf_cntr_intr_bit 441#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI) 442#endif 443 444#ifndef cpu_has_vz 445#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ) 446#endif 447 448#if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa) 449# define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA) 450#elif !defined(cpu_has_msa) 451# define cpu_has_msa 0 452#endif 453 454#ifndef cpu_has_ufr 455# define cpu_has_ufr (cpu_data[0].options & MIPS_CPU_UFR) 456#endif 457 458#ifndef cpu_has_fre 459# define cpu_has_fre (cpu_data[0].options & MIPS_CPU_FRE) 460#endif 461 462#ifndef cpu_has_cdmm 463# define cpu_has_cdmm (cpu_data[0].options & MIPS_CPU_CDMM) 464#endif 465 466#ifndef cpu_has_small_pages 467# define cpu_has_small_pages (cpu_data[0].options & MIPS_CPU_SP) 468#endif 469 470#ifndef cpu_has_nan_legacy 471#define cpu_has_nan_legacy (cpu_data[0].options & MIPS_CPU_NAN_LEGACY) 472#endif 473#ifndef cpu_has_nan_2008 474#define cpu_has_nan_2008 (cpu_data[0].options & MIPS_CPU_NAN_2008) 475#endif 476 477#ifndef cpu_has_ebase_wg 478# define cpu_has_ebase_wg (cpu_data[0].options & MIPS_CPU_EBASE_WG) 479#endif 480 481#ifndef cpu_has_badinstr 482# define cpu_has_badinstr (cpu_data[0].options & MIPS_CPU_BADINSTR) 483#endif 484 485#ifndef cpu_has_badinstrp 486# define cpu_has_badinstrp (cpu_data[0].options & MIPS_CPU_BADINSTRP) 487#endif 488 489#ifndef cpu_has_contextconfig 490# define cpu_has_contextconfig (cpu_data[0].options & MIPS_CPU_CTXTC) 491#endif 492 493#ifndef cpu_has_perf 494# define cpu_has_perf (cpu_data[0].options & MIPS_CPU_PERF) 495#endif 496 497#if defined(CONFIG_SMP) && (MIPS_ISA_REV >= 6) 498/* 499 * Some systems share FTLB RAMs between threads within a core (siblings in 500 * kernel parlance). This means that FTLB entries may become invalid at almost 501 * any point when an entry is evicted due to a sibling thread writing an entry 502 * to the shared FTLB RAM. 503 * 504 * This is only relevant to SMP systems, and the only systems that exhibit this 505 * property implement MIPSr6 or higher so we constrain support for this to 506 * kernels that will run on such systems. 507 */ 508# ifndef cpu_has_shared_ftlb_ram 509# define cpu_has_shared_ftlb_ram \ 510 (current_cpu_data.options & MIPS_CPU_SHARED_FTLB_RAM) 511# endif 512 513/* 514 * Some systems take this a step further & share FTLB entries between siblings. 515 * This is implemented as TLB writes happening as usual, but if an entry 516 * written by a sibling exists in the shared FTLB for a translation which would 517 * otherwise cause a TLB refill exception then the CPU will use the entry 518 * written by its sibling rather than triggering a refill & writing a matching 519 * TLB entry for itself. 520 * 521 * This is naturally only valid if a TLB entry is known to be suitable for use 522 * on all siblings in a CPU, and so it only takes effect when MMIDs are in use 523 * rather than ASIDs or when a TLB entry is marked global. 524 */ 525# ifndef cpu_has_shared_ftlb_entries 526# define cpu_has_shared_ftlb_entries \ 527 (current_cpu_data.options & MIPS_CPU_SHARED_FTLB_ENTRIES) 528# endif 529#endif /* SMP && MIPS_ISA_REV >= 6 */ 530 531#ifndef cpu_has_shared_ftlb_ram 532# define cpu_has_shared_ftlb_ram 0 533#endif 534#ifndef cpu_has_shared_ftlb_entries 535# define cpu_has_shared_ftlb_entries 0 536#endif 537 538#ifdef CONFIG_MIPS_MT_SMP 539# define cpu_has_mipsmt_pertccounters \ 540 (cpu_data[0].options & MIPS_CPU_MT_PER_TC_PERF_COUNTERS) 541#else 542# define cpu_has_mipsmt_pertccounters 0 543#endif /* CONFIG_MIPS_MT_SMP */ 544 545/* 546 * Guest capabilities 547 */ 548#ifndef cpu_guest_has_conf1 549#define cpu_guest_has_conf1 (cpu_data[0].guest.conf & (1 << 1)) 550#endif 551#ifndef cpu_guest_has_conf2 552#define cpu_guest_has_conf2 (cpu_data[0].guest.conf & (1 << 2)) 553#endif 554#ifndef cpu_guest_has_conf3 555#define cpu_guest_has_conf3 (cpu_data[0].guest.conf & (1 << 3)) 556#endif 557#ifndef cpu_guest_has_conf4 558#define cpu_guest_has_conf4 (cpu_data[0].guest.conf & (1 << 4)) 559#endif 560#ifndef cpu_guest_has_conf5 561#define cpu_guest_has_conf5 (cpu_data[0].guest.conf & (1 << 5)) 562#endif 563#ifndef cpu_guest_has_conf6 564#define cpu_guest_has_conf6 (cpu_data[0].guest.conf & (1 << 6)) 565#endif 566#ifndef cpu_guest_has_conf7 567#define cpu_guest_has_conf7 (cpu_data[0].guest.conf & (1 << 7)) 568#endif 569#ifndef cpu_guest_has_fpu 570#define cpu_guest_has_fpu (cpu_data[0].guest.options & MIPS_CPU_FPU) 571#endif 572#ifndef cpu_guest_has_watch 573#define cpu_guest_has_watch (cpu_data[0].guest.options & MIPS_CPU_WATCH) 574#endif 575#ifndef cpu_guest_has_contextconfig 576#define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC) 577#endif 578#ifndef cpu_guest_has_segments 579#define cpu_guest_has_segments (cpu_data[0].guest.options & MIPS_CPU_SEGMENTS) 580#endif 581#ifndef cpu_guest_has_badinstr 582#define cpu_guest_has_badinstr (cpu_data[0].guest.options & MIPS_CPU_BADINSTR) 583#endif 584#ifndef cpu_guest_has_badinstrp 585#define cpu_guest_has_badinstrp (cpu_data[0].guest.options & MIPS_CPU_BADINSTRP) 586#endif 587#ifndef cpu_guest_has_htw 588#define cpu_guest_has_htw (cpu_data[0].guest.options & MIPS_CPU_HTW) 589#endif 590#ifndef cpu_guest_has_mvh 591#define cpu_guest_has_mvh (cpu_data[0].guest.options & MIPS_CPU_MVH) 592#endif 593#ifndef cpu_guest_has_msa 594#define cpu_guest_has_msa (cpu_data[0].guest.ases & MIPS_ASE_MSA) 595#endif 596#ifndef cpu_guest_has_kscr 597#define cpu_guest_has_kscr(n) (cpu_data[0].guest.kscratch_mask & (1u << (n))) 598#endif 599#ifndef cpu_guest_has_rw_llb 600#define cpu_guest_has_rw_llb (cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB)) 601#endif 602#ifndef cpu_guest_has_perf 603#define cpu_guest_has_perf (cpu_data[0].guest.options & MIPS_CPU_PERF) 604#endif 605#ifndef cpu_guest_has_maar 606#define cpu_guest_has_maar (cpu_data[0].guest.options & MIPS_CPU_MAAR) 607#endif 608#ifndef cpu_guest_has_userlocal 609#define cpu_guest_has_userlocal (cpu_data[0].guest.options & MIPS_CPU_ULRI) 610#endif 611 612/* 613 * Guest dynamic capabilities 614 */ 615#ifndef cpu_guest_has_dyn_fpu 616#define cpu_guest_has_dyn_fpu (cpu_data[0].guest.options_dyn & MIPS_CPU_FPU) 617#endif 618#ifndef cpu_guest_has_dyn_watch 619#define cpu_guest_has_dyn_watch (cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH) 620#endif 621#ifndef cpu_guest_has_dyn_contextconfig 622#define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC) 623#endif 624#ifndef cpu_guest_has_dyn_perf 625#define cpu_guest_has_dyn_perf (cpu_data[0].guest.options_dyn & MIPS_CPU_PERF) 626#endif 627#ifndef cpu_guest_has_dyn_msa 628#define cpu_guest_has_dyn_msa (cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA) 629#endif 630#ifndef cpu_guest_has_dyn_maar 631#define cpu_guest_has_dyn_maar (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR) 632#endif 633 634#endif /* __ASM_CPU_FEATURES_H */ 635