LXR linux/arch/x86/include/asm/io.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef _ASM_X86_IO_H
   3#define _ASM_X86_IO_H
   4
   5/*
   6 * This file contains the definitions for the x86 IO instructions
   7 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
   8 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
   9 * versions of the single-IO instructions (inb_p/inw_p/..).
  10 *
  11 * This file is not meant to be obfuscating: it's just complicated
  12 * to (a) handle it all in a way that makes gcc able to optimize it
  13 * as well as possible and (b) trying to avoid writing the same thing
  14 * over and over again with slight variations and possibly making a
  15 * mistake somewhere.
  16 */
  17
  18/*
  19 * Thanks to James van Artsdalen for a better timing-fix than
  20 * the two short jumps: using outb's to a nonexistent port seems
  21 * to guarantee better timings even on fast machines.
  22 *
  23 * On the other hand, I'd like to be sure of a non-existent port:
  24 * I feel a bit unsafe about using 0x80 (should be safe, though)
  25 *
  26 *              Linus
  27 */
  28
  29 /*
  30  *  Bit simplified and optimized by Jan Hubicka
  31  *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
  32  *
  33  *  isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
  34  *  isa_read[wl] and isa_write[wl] fixed
  35  *  - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
  36  */
  37
  38#define ARCH_HAS_IOREMAP_WC
  39#define ARCH_HAS_IOREMAP_WT
  40
  41#include <linux/string.h>
  42#include <linux/compiler.h>
  43#include <asm/page.h>
  44#include <asm/early_ioremap.h>
  45#include <asm/pgtable_types.h>
  46
  47#define build_mmio_read(name, size, type, reg, barrier) \
  48static inline type name(const volatile void __iomem *addr) \
  49{ type ret; asm volatile("mov" size " %1,%0":reg (ret) \
  50:"m" (*(volatile type __force *)addr) barrier); return ret; }
  51
  52#define build_mmio_write(name, size, type, reg, barrier) \
  53static inline void name(type val, volatile void __iomem *addr) \
  54{ asm volatile("mov" size " %0,%1": :reg (val), \
  55"m" (*(volatile type __force *)addr) barrier); }
  56
  57build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
  58build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
  59build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
  60
  61build_mmio_read(__readb, "b", unsigned char, "=q", )
  62build_mmio_read(__readw, "w", unsigned short, "=r", )
  63build_mmio_read(__readl, "l", unsigned int, "=r", )
  64
  65build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
  66build_mmio_write(writew, "w", unsigned short, "r", :"memory")
  67build_mmio_write(writel, "l", unsigned int, "r", :"memory")
  68
  69build_mmio_write(__writeb, "b", unsigned char, "q", )
  70build_mmio_write(__writew, "w", unsigned short, "r", )
  71build_mmio_write(__writel, "l", unsigned int, "r", )
  72
  73#define readb readb
  74#define readw readw
  75#define readl readl
  76#define readb_relaxed(a) __readb(a)
  77#define readw_relaxed(a) __readw(a)
  78#define readl_relaxed(a) __readl(a)
  79#define __raw_readb __readb
  80#define __raw_readw __readw
  81#define __raw_readl __readl
  82
  83#define writeb writeb
  84#define writew writew
  85#define writel writel
  86#define writeb_relaxed(v, a) __writeb(v, a)
  87#define writew_relaxed(v, a) __writew(v, a)
  88#define writel_relaxed(v, a) __writel(v, a)
  89#define __raw_writeb __writeb
  90#define __raw_writew __writew
  91#define __raw_writel __writel
  92
  93#ifdef CONFIG_X86_64
  94
  95build_mmio_read(readq, "q", u64, "=r", :"memory")
  96build_mmio_read(__readq, "q", u64, "=r", )
  97build_mmio_write(writeq, "q", u64, "r", :"memory")
  98build_mmio_write(__writeq, "q", u64, "r", )
  99
 100#define readq_relaxed(a)        __readq(a)
 101#define writeq_relaxed(v, a)    __writeq(v, a)
 102
 103#define __raw_readq             __readq
 104#define __raw_writeq            __writeq
 105
 106/* Let people know that we have them */
 107#define readq                   readq
 108#define writeq                  writeq
 109
 110#endif
 111
 112#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 113extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
 114extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
 115
 116/**
 117 *      virt_to_phys    -       map virtual addresses to physical
 118 *      @address: address to remap
 119 *
 120 *      The returned physical address is the physical (CPU) mapping for
 121 *      the memory address given. It is only valid to use this function on
 122 *      addresses directly mapped or allocated via kmalloc.
 123 *
 124 *      This function does not give bus mappings for DMA transfers. In
 125 *      almost all conceivable cases a device driver should not be using
 126 *      this function
 127 */
 128
 129static inline phys_addr_t virt_to_phys(volatile void *address)
 130{
 131        return __pa(address);
 132}
 133#define virt_to_phys virt_to_phys
 134
 135/**
 136 *      phys_to_virt    -       map physical address to virtual
 137 *      @address: address to remap
 138 *
 139 *      The returned virtual address is a current CPU mapping for
 140 *      the memory address given. It is only valid to use this function on
 141 *      addresses that have a kernel mapping
 142 *
 143 *      This function does not handle bus mappings for DMA transfers. In
 144 *      almost all conceivable cases a device driver should not be using
 145 *      this function
 146 */
 147
 148static inline void *phys_to_virt(phys_addr_t address)
 149{
 150        return __va(address);
 151}
 152#define phys_to_virt phys_to_virt
 153
 154/*
 155 * Change "struct page" to physical address.
 156 */
 157#define page_to_phys(page)    ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 158
 159/*
 160 * ISA I/O bus memory addresses are 1:1 with the physical address.
 161 * However, we truncate the address to unsigned int to avoid undesirable
 162 * promitions in legacy drivers.
 163 */
 164static inline unsigned int isa_virt_to_bus(volatile void *address)
 165{
 166        return (unsigned int)virt_to_phys(address);
 167}
 168#define isa_page_to_bus(page)   ((unsigned int)page_to_phys(page))
 169#define isa_bus_to_virt         phys_to_virt
 170
 171/*
 172 * However PCI ones are not necessarily 1:1 and therefore these interfaces
 173 * are forbidden in portable PCI drivers.
 174 *
 175 * Allow them on x86 for legacy drivers, though.
 176 */
 177#define virt_to_bus virt_to_phys
 178#define bus_to_virt phys_to_virt
 179
 180/*
 181 * The default ioremap() behavior is non-cached; if you need something
 182 * else, you probably want one of the following.
 183 */
 184extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size);
 185#define ioremap_nocache ioremap_nocache
 186extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size);
 187#define ioremap_uc ioremap_uc
 188extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
 189#define ioremap_cache ioremap_cache
 190extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, unsigned long prot_val);
 191#define ioremap_prot ioremap_prot
 192extern void __iomem *ioremap_encrypted(resource_size_t phys_addr, unsigned long size);
 193#define ioremap_encrypted ioremap_encrypted
 194
 195/**
 196 * ioremap     -   map bus memory into CPU space
 197 * @offset:    bus address of the memory
 198 * @size:      size of the resource to map
 199 *
 200 * ioremap performs a platform specific sequence of operations to
 201 * make bus memory CPU accessible via the readb/readw/readl/writeb/
 202 * writew/writel functions and the other mmio helpers. The returned
 203 * address is not guaranteed to be usable directly as a virtual
 204 * address.
 205 *
 206 * If the area you are trying to map is a PCI BAR you should have a
 207 * look at pci_iomap().
 208 */
 209static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
 210{
 211        return ioremap_nocache(offset, size);
 212}
 213#define ioremap ioremap
 214
 215extern void iounmap(volatile void __iomem *addr);
 216#define iounmap iounmap
 217
 218extern void set_iounmap_nonlazy(void);
 219
 220#ifdef __KERNEL__
 221
 222#include <asm-generic/iomap.h>
 223
 224/*
 225 * ISA space is 'always mapped' on a typical x86 system, no need to
 226 * explicitly ioremap() it. The fact that the ISA IO space is mapped
 227 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
 228 * are physical addresses. The following constant pointer can be
 229 * used as the IO-area pointer (it can be iounmapped as well, so the
 230 * analogy with PCI is quite large):
 231 */
 232#define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
 233
 234#endif /* __KERNEL__ */
 235
 236extern void native_io_delay(void);
 237
 238extern int io_delay_type;
 239extern void io_delay_init(void);
 240
 241#if defined(CONFIG_PARAVIRT)
 242#include <asm/paravirt.h>
 243#else
 244
 245static inline void slow_down_io(void)
 246{
 247        native_io_delay();
 248#ifdef REALLY_SLOW_IO
 249        native_io_delay();
 250        native_io_delay();
 251        native_io_delay();
 252#endif
 253}
 254
 255#endif
 256
 257#ifdef CONFIG_AMD_MEM_ENCRYPT
 258#include <linux/jump_label.h>
 259
 260extern struct static_key_false sev_enable_key;
 261static inline bool sev_key_active(void)
 262{
 263        return static_branch_unlikely(&sev_enable_key);
 264}
 265
 266#else /* !CONFIG_AMD_MEM_ENCRYPT */
 267
 268static inline bool sev_key_active(void) { return false; }
 269
 270#endif /* CONFIG_AMD_MEM_ENCRYPT */
 271
 272#define BUILDIO(bwl, bw, type)                                          \
 273static inline void out##bwl(unsigned type value, int port)              \
 274{                                                                       \
 275        asm volatile("out" #bwl " %" #bw "0, %w1"                       \
 276                     : : "a"(value), "Nd"(port));                       \
 277}                                                                       \
 278                                                                        \
 279static inline unsigned type in##bwl(int port)                           \
 280{                                                                       \
 281        unsigned type value;                                            \
 282        asm volatile("in" #bwl " %w1, %" #bw "0"                        \
 283                     : "=a"(value) : "Nd"(port));                       \
 284        return value;                                                   \
 285}                                                                       \
 286                                                                        \
 287static inline void out##bwl##_p(unsigned type value, int port)          \
 288{                                                                       \
 289        out##bwl(value, port);                                          \
 290        slow_down_io();                                                 \
 291}                                                                       \
 292                                                                        \
 293static inline unsigned type in##bwl##_p(int port)                       \
 294{                                                                       \
 295        unsigned type value = in##bwl(port);                            \
 296        slow_down_io();                                                 \
 297        return value;                                                   \
 298}                                                                       \
 299                                                                        \
 300static inline void outs##bwl(int port, const void *addr, unsigned long count) \
 301{                                                                       \
 302        if (sev_key_active()) {                                         \
 303                unsigned type *value = (unsigned type *)addr;           \
 304                while (count) {                                         \
 305                        out##bwl(*value, port);                         \
 306                        value++;                                        \
 307                        count--;                                        \
 308                }                                                       \
 309        } else {                                                        \
 310                asm volatile("rep; outs" #bwl                           \
 311                             : "+S"(addr), "+c"(count)                  \
 312                             : "d"(port) : "memory");                   \
 313        }                                                               \
 314}                                                                       \
 315                                                                        \
 316static inline void ins##bwl(int port, void *addr, unsigned long count)  \
 317{                                                                       \
 318        if (sev_key_active()) {                                         \
 319                unsigned type *value = (unsigned type *)addr;           \
 320                while (count) {                                         \
 321                        *value = in##bwl(port);                         \
 322                        value++;                                        \
 323                        count--;                                        \
 324                }                                                       \
 325        } else {                                                        \
 326                asm volatile("rep; ins" #bwl                            \
 327                             : "+D"(addr), "+c"(count)                  \
 328                             : "d"(port) : "memory");                   \
 329        }                                                               \
 330}
 331
 332BUILDIO(b, b, char)
 333BUILDIO(w, w, short)
 334BUILDIO(l, , int)
 335
 336#define inb inb
 337#define inw inw
 338#define inl inl
 339#define inb_p inb_p
 340#define inw_p inw_p
 341#define inl_p inl_p
 342#define insb insb
 343#define insw insw
 344#define insl insl
 345
 346#define outb outb
 347#define outw outw
 348#define outl outl
 349#define outb_p outb_p
 350#define outw_p outw_p
 351#define outl_p outl_p
 352#define outsb outsb
 353#define outsw outsw
 354#define outsl outsl
 355
 356extern void *xlate_dev_mem_ptr(phys_addr_t phys);
 357extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);
 358
 359#define xlate_dev_mem_ptr xlate_dev_mem_ptr
 360#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
 361
 362extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
 363                                enum page_cache_mode pcm);
 364extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size);
 365#define ioremap_wc ioremap_wc
 366extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size);
 367#define ioremap_wt ioremap_wt
 368
 369extern bool is_early_ioremap_ptep(pte_t *ptep);
 370
 371#define IO_SPACE_LIMIT 0xffff
 372
 373#include <asm-generic/io.h>
 374#undef PCI_IOBASE
 375
 376#ifdef CONFIG_MTRR
 377extern int __must_check arch_phys_wc_index(int handle);
 378#define arch_phys_wc_index arch_phys_wc_index
 379
 380extern int __must_check arch_phys_wc_add(unsigned long base,
 381                                         unsigned long size);
 382extern void arch_phys_wc_del(int handle);
 383#define arch_phys_wc_add arch_phys_wc_add
 384#endif
 385
 386#ifdef CONFIG_X86_PAT
 387extern int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size);
 388extern void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size);
 389#define arch_io_reserve_memtype_wc arch_io_reserve_memtype_wc
 390#endif
 391
 392extern bool arch_memremap_can_ram_remap(resource_size_t offset,
 393                                        unsigned long size,
 394                                        unsigned long flags);
 395#define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
 396
 397extern bool phys_mem_access_encrypted(unsigned long phys_addr,
 398                                      unsigned long size);
 399
 400#endif /* _ASM_X86_IO_H */
 401