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15#include <linux/cpu.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/smp.h>
19#include <linux/preempt.h>
20#include <linux/hardirq.h>
21#include <linux/percpu.h>
22#include <linux/delay.h>
23#include <linux/start_kernel.h>
24#include <linux/sched.h>
25#include <linux/kprobes.h>
26#include <linux/memblock.h>
27#include <linux/export.h>
28#include <linux/mm.h>
29#include <linux/page-flags.h>
30#include <linux/highmem.h>
31#include <linux/console.h>
32#include <linux/pci.h>
33#include <linux/gfp.h>
34#include <linux/edd.h>
35#include <linux/frame.h>
36
37#include <xen/xen.h>
38#include <xen/events.h>
39#include <xen/interface/xen.h>
40#include <xen/interface/version.h>
41#include <xen/interface/physdev.h>
42#include <xen/interface/vcpu.h>
43#include <xen/interface/memory.h>
44#include <xen/interface/nmi.h>
45#include <xen/interface/xen-mca.h>
46#include <xen/features.h>
47#include <xen/page.h>
48#include <xen/hvc-console.h>
49#include <xen/acpi.h>
50
51#include <asm/paravirt.h>
52#include <asm/apic.h>
53#include <asm/page.h>
54#include <asm/xen/pci.h>
55#include <asm/xen/hypercall.h>
56#include <asm/xen/hypervisor.h>
57#include <asm/xen/cpuid.h>
58#include <asm/fixmap.h>
59#include <asm/processor.h>
60#include <asm/proto.h>
61#include <asm/msr-index.h>
62#include <asm/traps.h>
63#include <asm/setup.h>
64#include <asm/desc.h>
65#include <asm/pgalloc.h>
66#include <asm/pgtable.h>
67#include <asm/tlbflush.h>
68#include <asm/reboot.h>
69#include <asm/stackprotector.h>
70#include <asm/hypervisor.h>
71#include <asm/mach_traps.h>
72#include <asm/mwait.h>
73#include <asm/pci_x86.h>
74#include <asm/cpu.h>
75
76#ifdef CONFIG_ACPI
77#include <linux/acpi.h>
78#include <asm/acpi.h>
79#include <acpi/pdc_intel.h>
80#include <acpi/processor.h>
81#include <xen/interface/platform.h>
82#endif
83
84#include "xen-ops.h"
85#include "mmu.h"
86#include "smp.h"
87#include "multicalls.h"
88#include "pmu.h"
89
90#include "../kernel/cpu/cpu.h"
91
92void *xen_initial_gdt;
93
94static int xen_cpu_up_prepare_pv(unsigned int cpu);
95static int xen_cpu_dead_pv(unsigned int cpu);
96
97struct tls_descs {
98 struct desc_struct desc[3];
99};
100
101
102
103
104
105
106
107
108static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc);
109
110static void __init xen_banner(void)
111{
112 unsigned version = HYPERVISOR_xen_version(XENVER_version, NULL);
113 struct xen_extraversion extra;
114 HYPERVISOR_xen_version(XENVER_extraversion, &extra);
115
116 pr_info("Booting paravirtualized kernel on %s\n", pv_info.name);
117 printk(KERN_INFO "Xen version: %d.%d%s%s\n",
118 version >> 16, version & 0xffff, extra.extraversion,
119 xen_feature(XENFEAT_mmu_pt_update_preserve_ad) ? " (preserve-AD)" : "");
120}
121
122bool
123xen_running_on_version_or_later(unsigned int major, unsigned int minor)
124{
125 unsigned int version;
126
127 if (!xen_domain())
128 return false;
129
130 version = HYPERVISOR_xen_version(XENVER_version, NULL);
131 if ((((version >> 16) == major) && ((version & 0xffff) >= minor)) ||
132 ((version >> 16) > major))
133 return true;
134 return false;
135}
136
137static __read_mostly unsigned int cpuid_leaf5_ecx_val;
138static __read_mostly unsigned int cpuid_leaf5_edx_val;
139
140static void xen_cpuid(unsigned int *ax, unsigned int *bx,
141 unsigned int *cx, unsigned int *dx)
142{
143 unsigned maskebx = ~0;
144
145
146
147
148
149 switch (*ax) {
150 case CPUID_MWAIT_LEAF:
151
152 *ax = 0;
153 *bx = 0;
154 *cx = cpuid_leaf5_ecx_val;
155 *dx = cpuid_leaf5_edx_val;
156 return;
157
158 case 0xb:
159
160 maskebx = 0;
161 break;
162 }
163
164 asm(XEN_EMULATE_PREFIX "cpuid"
165 : "=a" (*ax),
166 "=b" (*bx),
167 "=c" (*cx),
168 "=d" (*dx)
169 : "0" (*ax), "2" (*cx));
170
171 *bx &= maskebx;
172}
173STACK_FRAME_NON_STANDARD(xen_cpuid);
174
175static bool __init xen_check_mwait(void)
176{
177#ifdef CONFIG_ACPI
178 struct xen_platform_op op = {
179 .cmd = XENPF_set_processor_pminfo,
180 .u.set_pminfo.id = -1,
181 .u.set_pminfo.type = XEN_PM_PDC,
182 };
183 uint32_t buf[3];
184 unsigned int ax, bx, cx, dx;
185 unsigned int mwait_mask;
186
187
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189
190
191
192
193
194
195 if (!xen_initial_domain())
196 return false;
197
198
199
200
201
202 if (!xen_running_on_version_or_later(4, 2))
203 return false;
204
205 ax = 1;
206 cx = 0;
207
208 native_cpuid(&ax, &bx, &cx, &dx);
209
210 mwait_mask = (1 << (X86_FEATURE_EST % 32)) |
211 (1 << (X86_FEATURE_MWAIT % 32));
212
213 if ((cx & mwait_mask) != mwait_mask)
214 return false;
215
216
217
218
219
220 ax = CPUID_MWAIT_LEAF;
221 bx = 0;
222 cx = 0;
223 dx = 0;
224
225 native_cpuid(&ax, &bx, &cx, &dx);
226
227
228
229
230 buf[0] = ACPI_PDC_REVISION_ID;
231 buf[1] = 1;
232 buf[2] = (ACPI_PDC_C_CAPABILITY_SMP | ACPI_PDC_EST_CAPABILITY_SWSMP);
233
234 set_xen_guest_handle(op.u.set_pminfo.pdc, buf);
235
236 if ((HYPERVISOR_platform_op(&op) == 0) &&
237 (buf[2] & (ACPI_PDC_C_C1_FFH | ACPI_PDC_C_C2C3_FFH))) {
238 cpuid_leaf5_ecx_val = cx;
239 cpuid_leaf5_edx_val = dx;
240 }
241 return true;
242#else
243 return false;
244#endif
245}
246
247static bool __init xen_check_xsave(void)
248{
249 unsigned int cx, xsave_mask;
250
251 cx = cpuid_ecx(1);
252
253 xsave_mask = (1 << (X86_FEATURE_XSAVE % 32)) |
254 (1 << (X86_FEATURE_OSXSAVE % 32));
255
256
257 return (cx & xsave_mask) == xsave_mask;
258}
259
260static void __init xen_init_capabilities(void)
261{
262 setup_force_cpu_cap(X86_FEATURE_XENPV);
263 setup_clear_cpu_cap(X86_FEATURE_DCA);
264 setup_clear_cpu_cap(X86_FEATURE_APERFMPERF);
265 setup_clear_cpu_cap(X86_FEATURE_MTRR);
266 setup_clear_cpu_cap(X86_FEATURE_ACC);
267 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
268 setup_clear_cpu_cap(X86_FEATURE_SME);
269
270
271
272
273
274 setup_clear_cpu_cap(X86_FEATURE_PCID);
275
276 if (!xen_initial_domain())
277 setup_clear_cpu_cap(X86_FEATURE_ACPI);
278
279 if (xen_check_mwait())
280 setup_force_cpu_cap(X86_FEATURE_MWAIT);
281 else
282 setup_clear_cpu_cap(X86_FEATURE_MWAIT);
283
284 if (!xen_check_xsave()) {
285 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
286 setup_clear_cpu_cap(X86_FEATURE_OSXSAVE);
287 }
288}
289
290static void xen_set_debugreg(int reg, unsigned long val)
291{
292 HYPERVISOR_set_debugreg(reg, val);
293}
294
295static unsigned long xen_get_debugreg(int reg)
296{
297 return HYPERVISOR_get_debugreg(reg);
298}
299
300static void xen_end_context_switch(struct task_struct *next)
301{
302 xen_mc_flush();
303 paravirt_end_context_switch(next);
304}
305
306static unsigned long xen_store_tr(void)
307{
308 return 0;
309}
310
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312
313
314
315
316
317static void set_aliased_prot(void *v, pgprot_t prot)
318{
319 int level;
320 pte_t *ptep;
321 pte_t pte;
322 unsigned long pfn;
323 struct page *page;
324 unsigned char dummy;
325
326 ptep = lookup_address((unsigned long)v, &level);
327 BUG_ON(ptep == NULL);
328
329 pfn = pte_pfn(*ptep);
330 page = pfn_to_page(pfn);
331
332 pte = pfn_pte(pfn, prot);
333
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353
354 preempt_disable();
355
356 probe_kernel_read(&dummy, v, 1);
357
358 if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0))
359 BUG();
360
361 if (!PageHighMem(page)) {
362 void *av = __va(PFN_PHYS(pfn));
363
364 if (av != v)
365 if (HYPERVISOR_update_va_mapping((unsigned long)av, pte, 0))
366 BUG();
367 } else
368 kmap_flush_unused();
369
370 preempt_enable();
371}
372
373static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries)
374{
375 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE;
376 int i;
377
378
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380
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387
388
389 for (i = 0; i < entries; i += entries_per_page)
390 set_aliased_prot(ldt + i, PAGE_KERNEL_RO);
391}
392
393static void xen_free_ldt(struct desc_struct *ldt, unsigned entries)
394{
395 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE;
396 int i;
397
398 for (i = 0; i < entries; i += entries_per_page)
399 set_aliased_prot(ldt + i, PAGE_KERNEL);
400}
401
402static void xen_set_ldt(const void *addr, unsigned entries)
403{
404 struct mmuext_op *op;
405 struct multicall_space mcs = xen_mc_entry(sizeof(*op));
406
407 trace_xen_cpu_set_ldt(addr, entries);
408
409 op = mcs.args;
410 op->cmd = MMUEXT_SET_LDT;
411 op->arg1.linear_addr = (unsigned long)addr;
412 op->arg2.nr_ents = entries;
413
414 MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF);
415
416 xen_mc_issue(PARAVIRT_LAZY_CPU);
417}
418
419static void xen_load_gdt(const struct desc_ptr *dtr)
420{
421 unsigned long va = dtr->address;
422 unsigned int size = dtr->size + 1;
423 unsigned long pfn, mfn;
424 int level;
425 pte_t *ptep;
426 void *virt;
427
428
429 BUG_ON(size > PAGE_SIZE);
430 BUG_ON(va & ~PAGE_MASK);
431
432
433
434
435
436
437
438
439 ptep = lookup_address(va, &level);
440 BUG_ON(ptep == NULL);
441
442 pfn = pte_pfn(*ptep);
443 mfn = pfn_to_mfn(pfn);
444 virt = __va(PFN_PHYS(pfn));
445
446 make_lowmem_page_readonly((void *)va);
447 make_lowmem_page_readonly(virt);
448
449 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct)))
450 BUG();
451}
452
453
454
455
456static void __init xen_load_gdt_boot(const struct desc_ptr *dtr)
457{
458 unsigned long va = dtr->address;
459 unsigned int size = dtr->size + 1;
460 unsigned long pfn, mfn;
461 pte_t pte;
462
463
464 BUG_ON(size > PAGE_SIZE);
465 BUG_ON(va & ~PAGE_MASK);
466
467 pfn = virt_to_pfn(va);
468 mfn = pfn_to_mfn(pfn);
469
470 pte = pfn_pte(pfn, PAGE_KERNEL_RO);
471
472 if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0))
473 BUG();
474
475 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct)))
476 BUG();
477}
478
479static inline bool desc_equal(const struct desc_struct *d1,
480 const struct desc_struct *d2)
481{
482 return !memcmp(d1, d2, sizeof(*d1));
483}
484
485static void load_TLS_descriptor(struct thread_struct *t,
486 unsigned int cpu, unsigned int i)
487{
488 struct desc_struct *shadow = &per_cpu(shadow_tls_desc, cpu).desc[i];
489 struct desc_struct *gdt;
490 xmaddr_t maddr;
491 struct multicall_space mc;
492
493 if (desc_equal(shadow, &t->tls_array[i]))
494 return;
495
496 *shadow = t->tls_array[i];
497
498 gdt = get_cpu_gdt_rw(cpu);
499 maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]);
500 mc = __xen_mc_entry(0);
501
502 MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]);
503}
504
505static void xen_load_tls(struct thread_struct *t, unsigned int cpu)
506{
507
508
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519
520
521
522
523
524
525 if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU) {
526#ifdef CONFIG_X86_32
527 lazy_load_gs(0);
528#else
529 loadsegment(fs, 0);
530#endif
531 }
532
533 xen_mc_batch();
534
535 load_TLS_descriptor(t, cpu, 0);
536 load_TLS_descriptor(t, cpu, 1);
537 load_TLS_descriptor(t, cpu, 2);
538
539 xen_mc_issue(PARAVIRT_LAZY_CPU);
540}
541
542#ifdef CONFIG_X86_64
543static void xen_load_gs_index(unsigned int idx)
544{
545 if (HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, idx))
546 BUG();
547}
548#endif
549
550static void xen_write_ldt_entry(struct desc_struct *dt, int entrynum,
551 const void *ptr)
552{
553 xmaddr_t mach_lp = arbitrary_virt_to_machine(&dt[entrynum]);
554 u64 entry = *(u64 *)ptr;
555
556 trace_xen_cpu_write_ldt_entry(dt, entrynum, entry);
557
558 preempt_disable();
559
560 xen_mc_flush();
561 if (HYPERVISOR_update_descriptor(mach_lp.maddr, entry))
562 BUG();
563
564 preempt_enable();
565}
566
567#ifdef CONFIG_X86_64
568struct trap_array_entry {
569 void (*orig)(void);
570 void (*xen)(void);
571 bool ist_okay;
572};
573
574static struct trap_array_entry trap_array[] = {
575 { debug, xen_xendebug, true },
576 { int3, xen_xenint3, true },
577 { double_fault, xen_double_fault, true },
578#ifdef CONFIG_X86_MCE
579 { machine_check, xen_machine_check, true },
580#endif
581 { nmi, xen_xennmi, true },
582 { overflow, xen_overflow, false },
583#ifdef CONFIG_IA32_EMULATION
584 { entry_INT80_compat, xen_entry_INT80_compat, false },
585#endif
586 { page_fault, xen_page_fault, false },
587 { divide_error, xen_divide_error, false },
588 { bounds, xen_bounds, false },
589 { invalid_op, xen_invalid_op, false },
590 { device_not_available, xen_device_not_available, false },
591 { coprocessor_segment_overrun, xen_coprocessor_segment_overrun, false },
592 { invalid_TSS, xen_invalid_TSS, false },
593 { segment_not_present, xen_segment_not_present, false },
594 { stack_segment, xen_stack_segment, false },
595 { general_protection, xen_general_protection, false },
596 { spurious_interrupt_bug, xen_spurious_interrupt_bug, false },
597 { coprocessor_error, xen_coprocessor_error, false },
598 { alignment_check, xen_alignment_check, false },
599 { simd_coprocessor_error, xen_simd_coprocessor_error, false },
600};
601
602static bool __ref get_trap_addr(void **addr, unsigned int ist)
603{
604 unsigned int nr;
605 bool ist_okay = false;
606
607
608
609
610
611
612
613
614 for (nr = 0; nr < ARRAY_SIZE(trap_array); nr++) {
615 struct trap_array_entry *entry = trap_array + nr;
616
617 if (*addr == entry->orig) {
618 *addr = entry->xen;
619 ist_okay = entry->ist_okay;
620 break;
621 }
622 }
623
624 if (nr == ARRAY_SIZE(trap_array) &&
625 *addr >= (void *)early_idt_handler_array[0] &&
626 *addr < (void *)early_idt_handler_array[NUM_EXCEPTION_VECTORS]) {
627 nr = (*addr - (void *)early_idt_handler_array[0]) /
628 EARLY_IDT_HANDLER_SIZE;
629 *addr = (void *)xen_early_idt_handler_array[nr];
630 }
631
632 if (WARN_ON(ist != 0 && !ist_okay))
633 return false;
634
635 return true;
636}
637#endif
638
639static int cvt_gate_to_trap(int vector, const gate_desc *val,
640 struct trap_info *info)
641{
642 unsigned long addr;
643
644 if (val->bits.type != GATE_TRAP && val->bits.type != GATE_INTERRUPT)
645 return 0;
646
647 info->vector = vector;
648
649 addr = gate_offset(val);
650#ifdef CONFIG_X86_64
651 if (!get_trap_addr((void **)&addr, val->bits.ist))
652 return 0;
653#endif
654 info->address = addr;
655
656 info->cs = gate_segment(val);
657 info->flags = val->bits.dpl;
658
659 if (val->bits.type == GATE_INTERRUPT)
660 info->flags |= 1 << 2;
661
662 return 1;
663}
664
665
666static DEFINE_PER_CPU(struct desc_ptr, idt_desc);
667
668
669
670static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g)
671{
672 unsigned long p = (unsigned long)&dt[entrynum];
673 unsigned long start, end;
674
675 trace_xen_cpu_write_idt_entry(dt, entrynum, g);
676
677 preempt_disable();
678
679 start = __this_cpu_read(idt_desc.address);
680 end = start + __this_cpu_read(idt_desc.size) + 1;
681
682 xen_mc_flush();
683
684 native_write_idt_entry(dt, entrynum, g);
685
686 if (p >= start && (p + 8) <= end) {
687 struct trap_info info[2];
688
689 info[1].address = 0;
690
691 if (cvt_gate_to_trap(entrynum, g, &info[0]))
692 if (HYPERVISOR_set_trap_table(info))
693 BUG();
694 }
695
696 preempt_enable();
697}
698
699static void xen_convert_trap_info(const struct desc_ptr *desc,
700 struct trap_info *traps)
701{
702 unsigned in, out, count;
703
704 count = (desc->size+1) / sizeof(gate_desc);
705 BUG_ON(count > 256);
706
707 for (in = out = 0; in < count; in++) {
708 gate_desc *entry = (gate_desc *)(desc->address) + in;
709
710 if (cvt_gate_to_trap(in, entry, &traps[out]))
711 out++;
712 }
713 traps[out].address = 0;
714}
715
716void xen_copy_trap_info(struct trap_info *traps)
717{
718 const struct desc_ptr *desc = this_cpu_ptr(&idt_desc);
719
720 xen_convert_trap_info(desc, traps);
721}
722
723
724
725
726static void xen_load_idt(const struct desc_ptr *desc)
727{
728 static DEFINE_SPINLOCK(lock);
729 static struct trap_info traps[257];
730
731 trace_xen_cpu_load_idt(desc);
732
733 spin_lock(&lock);
734
735 memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc));
736
737 xen_convert_trap_info(desc, traps);
738
739 xen_mc_flush();
740 if (HYPERVISOR_set_trap_table(traps))
741 BUG();
742
743 spin_unlock(&lock);
744}
745
746
747
748static void xen_write_gdt_entry(struct desc_struct *dt, int entry,
749 const void *desc, int type)
750{
751 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type);
752
753 preempt_disable();
754
755 switch (type) {
756 case DESC_LDT:
757 case DESC_TSS:
758
759 break;
760
761 default: {
762 xmaddr_t maddr = arbitrary_virt_to_machine(&dt[entry]);
763
764 xen_mc_flush();
765 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc))
766 BUG();
767 }
768
769 }
770
771 preempt_enable();
772}
773
774
775
776
777
778static void __init xen_write_gdt_entry_boot(struct desc_struct *dt, int entry,
779 const void *desc, int type)
780{
781 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type);
782
783 switch (type) {
784 case DESC_LDT:
785 case DESC_TSS:
786
787 break;
788
789 default: {
790 xmaddr_t maddr = virt_to_machine(&dt[entry]);
791
792 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc))
793 dt[entry] = *(struct desc_struct *)desc;
794 }
795
796 }
797}
798
799static void xen_load_sp0(unsigned long sp0)
800{
801 struct multicall_space mcs;
802
803 mcs = xen_mc_entry(0);
804 MULTI_stack_switch(mcs.mc, __KERNEL_DS, sp0);
805 xen_mc_issue(PARAVIRT_LAZY_CPU);
806 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
807}
808
809void xen_set_iopl_mask(unsigned mask)
810{
811 struct physdev_set_iopl set_iopl;
812
813
814 set_iopl.iopl = (mask == 0) ? 1 : (mask >> 12) & 3;
815 HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl);
816}
817
818static void xen_io_delay(void)
819{
820}
821
822static DEFINE_PER_CPU(unsigned long, xen_cr0_value);
823
824static unsigned long xen_read_cr0(void)
825{
826 unsigned long cr0 = this_cpu_read(xen_cr0_value);
827
828 if (unlikely(cr0 == 0)) {
829 cr0 = native_read_cr0();
830 this_cpu_write(xen_cr0_value, cr0);
831 }
832
833 return cr0;
834}
835
836static void xen_write_cr0(unsigned long cr0)
837{
838 struct multicall_space mcs;
839
840 this_cpu_write(xen_cr0_value, cr0);
841
842
843
844 mcs = xen_mc_entry(0);
845
846 MULTI_fpu_taskswitch(mcs.mc, (cr0 & X86_CR0_TS) != 0);
847
848 xen_mc_issue(PARAVIRT_LAZY_CPU);
849}
850
851static void xen_write_cr4(unsigned long cr4)
852{
853 cr4 &= ~(X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PCE);
854
855 native_write_cr4(cr4);
856}
857#ifdef CONFIG_X86_64
858static inline unsigned long xen_read_cr8(void)
859{
860 return 0;
861}
862static inline void xen_write_cr8(unsigned long val)
863{
864 BUG_ON(val);
865}
866#endif
867
868static u64 xen_read_msr_safe(unsigned int msr, int *err)
869{
870 u64 val;
871
872 if (pmu_msr_read(msr, &val, err))
873 return val;
874
875 val = native_read_msr_safe(msr, err);
876 switch (msr) {
877 case MSR_IA32_APICBASE:
878#ifdef CONFIG_X86_X2APIC
879 if (!(cpuid_ecx(1) & (1 << (X86_FEATURE_X2APIC & 31))))
880#endif
881 val &= ~X2APIC_ENABLE;
882 break;
883 }
884 return val;
885}
886
887static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high)
888{
889 int ret;
890
891 ret = 0;
892
893 switch (msr) {
894#ifdef CONFIG_X86_64
895 unsigned which;
896 u64 base;
897
898 case MSR_FS_BASE: which = SEGBASE_FS; goto set;
899 case MSR_KERNEL_GS_BASE: which = SEGBASE_GS_USER; goto set;
900 case MSR_GS_BASE: which = SEGBASE_GS_KERNEL; goto set;
901
902 set:
903 base = ((u64)high << 32) | low;
904 if (HYPERVISOR_set_segment_base(which, base) != 0)
905 ret = -EIO;
906 break;
907#endif
908
909 case MSR_STAR:
910 case MSR_CSTAR:
911 case MSR_LSTAR:
912 case MSR_SYSCALL_MASK:
913 case MSR_IA32_SYSENTER_CS:
914 case MSR_IA32_SYSENTER_ESP:
915 case MSR_IA32_SYSENTER_EIP:
916
917
918
919 break;
920
921 default:
922 if (!pmu_msr_write(msr, low, high, &ret))
923 ret = native_write_msr_safe(msr, low, high);
924 }
925
926 return ret;
927}
928
929static u64 xen_read_msr(unsigned int msr)
930{
931
932
933
934
935 int err;
936
937 return xen_read_msr_safe(msr, &err);
938}
939
940static void xen_write_msr(unsigned int msr, unsigned low, unsigned high)
941{
942
943
944
945
946 xen_write_msr_safe(msr, low, high);
947}
948
949void xen_setup_shared_info(void)
950{
951 set_fixmap(FIX_PARAVIRT_BOOTMAP, xen_start_info->shared_info);
952
953 HYPERVISOR_shared_info =
954 (struct shared_info *)fix_to_virt(FIX_PARAVIRT_BOOTMAP);
955
956 xen_setup_mfn_list_list();
957
958 if (system_state == SYSTEM_BOOTING) {
959#ifndef CONFIG_SMP
960
961
962
963
964
965 xen_setup_vcpu_info_placement();
966#endif
967
968
969
970
971 xen_init_time_ops();
972 }
973}
974
975
976void __ref xen_setup_vcpu_info_placement(void)
977{
978 int cpu;
979
980 for_each_possible_cpu(cpu) {
981
982 per_cpu(xen_vcpu_id, cpu) = cpu;
983
984
985
986
987
988
989
990
991
992 (void) xen_vcpu_setup(cpu);
993 }
994
995
996
997
998
999 if (xen_have_vcpu_info_placement) {
1000 pv_irq_ops.save_fl = __PV_IS_CALLEE_SAVE(xen_save_fl_direct);
1001 pv_irq_ops.restore_fl = __PV_IS_CALLEE_SAVE(xen_restore_fl_direct);
1002 pv_irq_ops.irq_disable = __PV_IS_CALLEE_SAVE(xen_irq_disable_direct);
1003 pv_irq_ops.irq_enable = __PV_IS_CALLEE_SAVE(xen_irq_enable_direct);
1004 pv_mmu_ops.read_cr2 = xen_read_cr2_direct;
1005 }
1006}
1007
1008static const struct pv_info xen_info __initconst = {
1009 .shared_kernel_pmd = 0,
1010
1011#ifdef CONFIG_X86_64
1012 .extra_user_64bit_cs = FLAT_USER_CS64,
1013#endif
1014 .name = "Xen",
1015};
1016
1017static const struct pv_cpu_ops xen_cpu_ops __initconst = {
1018 .cpuid = xen_cpuid,
1019
1020 .set_debugreg = xen_set_debugreg,
1021 .get_debugreg = xen_get_debugreg,
1022
1023 .read_cr0 = xen_read_cr0,
1024 .write_cr0 = xen_write_cr0,
1025
1026 .write_cr4 = xen_write_cr4,
1027
1028#ifdef CONFIG_X86_64
1029 .read_cr8 = xen_read_cr8,
1030 .write_cr8 = xen_write_cr8,
1031#endif
1032
1033 .wbinvd = native_wbinvd,
1034
1035 .read_msr = xen_read_msr,
1036 .write_msr = xen_write_msr,
1037
1038 .read_msr_safe = xen_read_msr_safe,
1039 .write_msr_safe = xen_write_msr_safe,
1040
1041 .read_pmc = xen_read_pmc,
1042
1043 .iret = xen_iret,
1044#ifdef CONFIG_X86_64
1045 .usergs_sysret64 = xen_sysret64,
1046#endif
1047
1048 .load_tr_desc = paravirt_nop,
1049 .set_ldt = xen_set_ldt,
1050 .load_gdt = xen_load_gdt,
1051 .load_idt = xen_load_idt,
1052 .load_tls = xen_load_tls,
1053#ifdef CONFIG_X86_64
1054 .load_gs_index = xen_load_gs_index,
1055#endif
1056
1057 .alloc_ldt = xen_alloc_ldt,
1058 .free_ldt = xen_free_ldt,
1059
1060 .store_tr = xen_store_tr,
1061
1062 .write_ldt_entry = xen_write_ldt_entry,
1063 .write_gdt_entry = xen_write_gdt_entry,
1064 .write_idt_entry = xen_write_idt_entry,
1065 .load_sp0 = xen_load_sp0,
1066
1067 .set_iopl_mask = xen_set_iopl_mask,
1068 .io_delay = xen_io_delay,
1069
1070
1071 .swapgs = paravirt_nop,
1072
1073 .start_context_switch = paravirt_start_context_switch,
1074 .end_context_switch = xen_end_context_switch,
1075};
1076
1077static void xen_restart(char *msg)
1078{
1079 xen_reboot(SHUTDOWN_reboot);
1080}
1081
1082static void xen_machine_halt(void)
1083{
1084 xen_reboot(SHUTDOWN_poweroff);
1085}
1086
1087static void xen_machine_power_off(void)
1088{
1089 if (pm_power_off)
1090 pm_power_off();
1091 xen_reboot(SHUTDOWN_poweroff);
1092}
1093
1094static void xen_crash_shutdown(struct pt_regs *regs)
1095{
1096 xen_reboot(SHUTDOWN_crash);
1097}
1098
1099static const struct machine_ops xen_machine_ops __initconst = {
1100 .restart = xen_restart,
1101 .halt = xen_machine_halt,
1102 .power_off = xen_machine_power_off,
1103 .shutdown = xen_machine_halt,
1104 .crash_shutdown = xen_crash_shutdown,
1105 .emergency_restart = xen_emergency_restart,
1106};
1107
1108static unsigned char xen_get_nmi_reason(void)
1109{
1110 unsigned char reason = 0;
1111
1112
1113 if (test_bit(_XEN_NMIREASON_io_error,
1114 &HYPERVISOR_shared_info->arch.nmi_reason))
1115 reason |= NMI_REASON_IOCHK;
1116 if (test_bit(_XEN_NMIREASON_pci_serr,
1117 &HYPERVISOR_shared_info->arch.nmi_reason))
1118 reason |= NMI_REASON_SERR;
1119
1120 return reason;
1121}
1122
1123static void __init xen_boot_params_init_edd(void)
1124{
1125#if IS_ENABLED(CONFIG_EDD)
1126 struct xen_platform_op op;
1127 struct edd_info *edd_info;
1128 u32 *mbr_signature;
1129 unsigned nr;
1130 int ret;
1131
1132 edd_info = boot_params.eddbuf;
1133 mbr_signature = boot_params.edd_mbr_sig_buffer;
1134
1135 op.cmd = XENPF_firmware_info;
1136
1137 op.u.firmware_info.type = XEN_FW_DISK_INFO;
1138 for (nr = 0; nr < EDDMAXNR; nr++) {
1139 struct edd_info *info = edd_info + nr;
1140
1141 op.u.firmware_info.index = nr;
1142 info->params.length = sizeof(info->params);
1143 set_xen_guest_handle(op.u.firmware_info.u.disk_info.edd_params,
1144 &info->params);
1145 ret = HYPERVISOR_platform_op(&op);
1146 if (ret)
1147 break;
1148
1149#define C(x) info->x = op.u.firmware_info.u.disk_info.x
1150 C(device);
1151 C(version);
1152 C(interface_support);
1153 C(legacy_max_cylinder);
1154 C(legacy_max_head);
1155 C(legacy_sectors_per_track);
1156#undef C
1157 }
1158 boot_params.eddbuf_entries = nr;
1159
1160 op.u.firmware_info.type = XEN_FW_DISK_MBR_SIGNATURE;
1161 for (nr = 0; nr < EDD_MBR_SIG_MAX; nr++) {
1162 op.u.firmware_info.index = nr;
1163 ret = HYPERVISOR_platform_op(&op);
1164 if (ret)
1165 break;
1166 mbr_signature[nr] = op.u.firmware_info.u.disk_mbr_signature.mbr_signature;
1167 }
1168 boot_params.edd_mbr_sig_buf_entries = nr;
1169#endif
1170}
1171
1172
1173
1174
1175
1176
1177static void xen_setup_gdt(int cpu)
1178{
1179 pv_cpu_ops.write_gdt_entry = xen_write_gdt_entry_boot;
1180 pv_cpu_ops.load_gdt = xen_load_gdt_boot;
1181
1182 setup_stack_canary_segment(0);
1183 switch_to_new_gdt(0);
1184
1185 pv_cpu_ops.write_gdt_entry = xen_write_gdt_entry;
1186 pv_cpu_ops.load_gdt = xen_load_gdt;
1187}
1188
1189static void __init xen_dom0_set_legacy_features(void)
1190{
1191 x86_platform.legacy.rtc = 1;
1192}
1193
1194
1195asmlinkage __visible void __init xen_start_kernel(void)
1196{
1197 struct physdev_set_iopl set_iopl;
1198 unsigned long initrd_start = 0;
1199 int rc;
1200
1201 if (!xen_start_info)
1202 return;
1203
1204 xen_domain_type = XEN_PV_DOMAIN;
1205 xen_start_flags = xen_start_info->flags;
1206
1207 xen_setup_features();
1208
1209
1210 pv_info = xen_info;
1211 pv_init_ops.patch = paravirt_patch_default;
1212 pv_cpu_ops = xen_cpu_ops;
1213 xen_init_irq_ops();
1214
1215
1216
1217
1218
1219
1220
1221
1222 xen_vcpu_info_reset(0);
1223
1224 x86_platform.get_nmi_reason = xen_get_nmi_reason;
1225
1226 x86_init.resources.memory_setup = xen_memory_setup;
1227 x86_init.irqs.intr_mode_select = x86_init_noop;
1228 x86_init.irqs.intr_mode_init = x86_init_noop;
1229 x86_init.oem.arch_setup = xen_arch_setup;
1230 x86_init.oem.banner = xen_banner;
1231
1232
1233
1234
1235
1236 xen_setup_machphys_mapping();
1237 xen_init_mmu_ops();
1238
1239
1240 __supported_pte_mask &= ~_PAGE_GLOBAL;
1241 __default_kernel_pte_mask &= ~_PAGE_GLOBAL;
1242
1243
1244
1245
1246
1247 __userpte_alloc_gfp &= ~__GFP_HIGHMEM;
1248
1249
1250 xen_build_dynamic_phys_to_machine();
1251
1252
1253
1254
1255
1256 xen_setup_gdt(0);
1257
1258
1259 get_cpu_cap(&boot_cpu_data);
1260 x86_configure_nx();
1261
1262
1263 per_cpu(xen_vcpu_id, 0) = 0;
1264
1265 idt_setup_early_handler();
1266
1267 xen_init_capabilities();
1268
1269#ifdef CONFIG_X86_LOCAL_APIC
1270
1271
1272
1273 xen_init_apic();
1274#endif
1275
1276 if (xen_feature(XENFEAT_mmu_pt_update_preserve_ad)) {
1277 pv_mmu_ops.ptep_modify_prot_start = xen_ptep_modify_prot_start;
1278 pv_mmu_ops.ptep_modify_prot_commit = xen_ptep_modify_prot_commit;
1279 }
1280
1281 machine_ops = xen_machine_ops;
1282
1283
1284
1285
1286
1287
1288 xen_initial_gdt = &per_cpu(gdt_page, 0);
1289
1290 xen_smp_init();
1291
1292#ifdef CONFIG_ACPI_NUMA
1293
1294
1295
1296
1297
1298 acpi_numa = -1;
1299#endif
1300 WARN_ON(xen_cpuhp_setup(xen_cpu_up_prepare_pv, xen_cpu_dead_pv));
1301
1302 local_irq_disable();
1303 early_boot_irqs_disabled = true;
1304
1305 xen_raw_console_write("mapping kernel into physical memory\n");
1306 xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base,
1307 xen_start_info->nr_pages);
1308 xen_reserve_special_pages();
1309
1310
1311
1312#ifdef CONFIG_X86_32
1313 pv_info.kernel_rpl = 1;
1314 if (xen_feature(XENFEAT_supervisor_mode_kernel))
1315 pv_info.kernel_rpl = 0;
1316#else
1317 pv_info.kernel_rpl = 0;
1318#endif
1319
1320 xen_reserve_top();
1321
1322
1323
1324
1325
1326
1327 set_iopl.iopl = 1;
1328 rc = HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl);
1329 if (rc != 0)
1330 xen_raw_printk("physdev_op failed %d\n", rc);
1331
1332#ifdef CONFIG_X86_32
1333
1334 cpu_detect(&new_cpu_data);
1335 set_cpu_cap(&new_cpu_data, X86_FEATURE_FPU);
1336 new_cpu_data.x86_capability[CPUID_1_EDX] = cpuid_edx(1);
1337#endif
1338
1339 if (xen_start_info->mod_start) {
1340 if (xen_start_info->flags & SIF_MOD_START_PFN)
1341 initrd_start = PFN_PHYS(xen_start_info->mod_start);
1342 else
1343 initrd_start = __pa(xen_start_info->mod_start);
1344 }
1345
1346
1347 boot_params.hdr.type_of_loader = (9 << 4) | 0;
1348 boot_params.hdr.ramdisk_image = initrd_start;
1349 boot_params.hdr.ramdisk_size = xen_start_info->mod_len;
1350 boot_params.hdr.cmd_line_ptr = __pa(xen_start_info->cmd_line);
1351 boot_params.hdr.hardware_subarch = X86_SUBARCH_XEN;
1352
1353 if (!xen_initial_domain()) {
1354 add_preferred_console("xenboot", 0, NULL);
1355 if (pci_xen)
1356 x86_init.pci.arch_init = pci_xen_init;
1357 } else {
1358 const struct dom0_vga_console_info *info =
1359 (void *)((char *)xen_start_info +
1360 xen_start_info->console.dom0.info_off);
1361 struct xen_platform_op op = {
1362 .cmd = XENPF_firmware_info,
1363 .interface_version = XENPF_INTERFACE_VERSION,
1364 .u.firmware_info.type = XEN_FW_KBD_SHIFT_FLAGS,
1365 };
1366
1367 x86_platform.set_legacy_features =
1368 xen_dom0_set_legacy_features;
1369 xen_init_vga(info, xen_start_info->console.dom0.info_size);
1370 xen_start_info->console.domU.mfn = 0;
1371 xen_start_info->console.domU.evtchn = 0;
1372
1373 if (HYPERVISOR_platform_op(&op) == 0)
1374 boot_params.kbd_status = op.u.firmware_info.u.kbd_shift_flags;
1375
1376
1377 pci_request_acs();
1378
1379 xen_acpi_sleep_register();
1380
1381
1382 x86_init.mpparse.find_smp_config = x86_init_noop;
1383 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
1384
1385 xen_boot_params_init_edd();
1386 }
1387
1388 add_preferred_console("tty", 0, NULL);
1389 add_preferred_console("hvc", 0, NULL);
1390
1391#ifdef CONFIG_PCI
1392
1393 pci_probe &= ~PCI_PROBE_BIOS;
1394#endif
1395 xen_raw_console_write("about to get started...\n");
1396
1397
1398 xen_setup_runstate_info(0);
1399
1400 xen_efi_init();
1401
1402
1403#ifdef CONFIG_X86_32
1404 i386_start_kernel();
1405#else
1406 cr4_init_shadow();
1407 x86_64_start_reservations((char *)__pa_symbol(&boot_params));
1408#endif
1409}
1410
1411static int xen_cpu_up_prepare_pv(unsigned int cpu)
1412{
1413 int rc;
1414
1415 if (per_cpu(xen_vcpu, cpu) == NULL)
1416 return -ENODEV;
1417
1418 xen_setup_timer(cpu);
1419
1420 rc = xen_smp_intr_init(cpu);
1421 if (rc) {
1422 WARN(1, "xen_smp_intr_init() for CPU %d failed: %d\n",
1423 cpu, rc);
1424 return rc;
1425 }
1426
1427 rc = xen_smp_intr_init_pv(cpu);
1428 if (rc) {
1429 WARN(1, "xen_smp_intr_init_pv() for CPU %d failed: %d\n",
1430 cpu, rc);
1431 return rc;
1432 }
1433
1434 return 0;
1435}
1436
1437static int xen_cpu_dead_pv(unsigned int cpu)
1438{
1439 xen_smp_intr_free(cpu);
1440 xen_smp_intr_free_pv(cpu);
1441
1442 xen_teardown_timer(cpu);
1443
1444 return 0;
1445}
1446
1447static uint32_t __init xen_platform_pv(void)
1448{
1449 if (xen_pv_domain())
1450 return xen_cpuid_base();
1451
1452 return 0;
1453}
1454
1455const __initconst struct hypervisor_x86 x86_hyper_xen_pv = {
1456 .name = "Xen PV",
1457 .detect = xen_platform_pv,
1458 .type = X86_HYPER_XEN_PV,
1459 .runtime.pin_vcpu = xen_pin_vcpu,
1460 .ignore_nopv = true,
1461};
1462